2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#42 $"
44 PATCH_ARG_LIST = "struct ahd_softc *ahd"
46 #include "aic79xx.reg"
47 #include "scsi_message.h"
50 SET_MODE(M_SCSI, M_SCSI);
51 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
52 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
53 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
55 * ENSELO is cleared by a SELDO, so we must test for SELDO
59 test SSTAT0, SELDO jnz select_out;
64 test SSTAT0, SELDO jnz select_out;
66 test SSTAT0, SELDI jnz select_in;
67 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
68 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
69 call unexpected_nonpkt_phase_find_ctxt;
70 idle_loop_check_nonpackreq:
71 test SSTAT2, NONPACKREQ jz idle_loop_scsi;
72 call unexpected_nonpkt_phase_find_ctxt;
75 test LQISTAT2, LQIGSAVAIL jz idle_loop_service_fifos;
77 * We have received good status for this transaction. There may
78 * still be data in our FIFOs draining to the host. Setup
79 * monitoring of the draining process or complete the SCB.
82 bmov SCBPTR, GSFIFO, 2;
84 or SCB_CONTROL, STATUS_RCVD;
87 * Since this status did not consume a FIFO, we have to
88 * be a bit more dilligent in how we check for FIFOs pertaining
89 * to this transaction. There are three states that a FIFO still
90 * transferring data may be in.
92 * 1) Configured and draining to the host, with a pending CLRCHN.
93 * 2) Configured and draining to the host, no pending CLRCHN.
94 * 3) Pending cfg4data, fifo not empty.
96 * For case 1, we assume that our DMA post of the completed command
97 * will occur after the FIFO finishes draining due to the higher
98 * priority of data FIFO transfers relative to command channel
101 * Case 2 can be detected by noticing that a longjmp is active for the
102 * FIFO and LONGJMP_SCB matches our SCB. In this case, we allow
103 * the routine servicing the FIFO to complete the SCB.
105 * Case 3 implies either a pending or yet to occur save data
106 * pointers for this same context in the other FIFO. So, if
107 * we detect case 2, we will properly defer the post of the SCB
108 * and achieve the desired result. The pending cfg4data will
109 * notice that status has been received and complete the SCB.
111 test SCB_SGPTR, SG_LIST_NULL jz good_status_check_fifos;
113 * All segments have been loaded (or no data transfer), so
114 * it is safe to complete the command. Since this was a
115 * cheap command to check for completion, loop to see if
116 * more entries can be removed from the GSFIFO.
122 good_status_check_fifos:
124 bmov ARG_1, SCBPTR, 2;
125 SET_MODE(M_DFF0, M_DFF0);
127 jc idle_loop_service_fifos;
128 SET_MODE(M_DFF1, M_DFF1);
130 jc idle_loop_service_fifos;
131 SET_MODE(M_SCSI, M_SCSI);
132 call queue_scb_completion;
134 idle_loop_service_fifos:
135 SET_MODE(M_DFF0, M_DFF0);
136 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
139 SET_MODE(M_DFF1, M_DFF1);
140 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_last_fifo_done;
142 idle_loop_last_fifo_done:
143 call idle_loop_cchan;
147 SET_MODE(M_CCHAN, M_CCHAN);
148 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
149 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
150 test CCSCBCTL, CCSCBDONE jz return;
153 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
155 * A complete SCB upload requires no intervention.
156 * The SCB is already on the COMPLETE_SCB list
157 * and its completion notification will now be
158 * handled just like any other SCB.
160 and CCSCBCTL, ~(CCARREN|CCSCBEN) ret;
161 fill_qoutfifo_dmadone:
162 and CCSCBCTL, ~(CCARREN|CCSCBEN);
163 mvi INTSTAT, CMDCMPLT;
164 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
165 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
166 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
167 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4 ret;
169 fetch_new_scb_inprog:
170 test CCSCBCTL, ARRDONE jz return;
172 and CCSCBCTL, ~(CCARREN|CCSCBEN);
173 bmov REG0, SCBPTR, 2;
174 /* Update the next SCB address to download. */
175 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
176 mvi SCB_NEXT[1], SCB_LIST_NULL;
177 mvi SCB_NEXT2[1], SCB_LIST_NULL;
179 * SCBs that want to send messages are always
180 * queued independently. This ensures that they
181 * are at the head of the SCB list to select out
182 * to a target and we will see the MK_MESSAGE flag.
184 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
185 shr SINDEX, 3, SCB_SCSIID;
187 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
188 bmov DINDEX, SINDEX, 2;
189 bmov SCBPTR, SINDIR, 2;
190 bmov DINDIR, REG0, 2;
191 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
192 bmov SCB_NEXT, REG0, 2;
194 /* Increment our position in the QINFIFO. */
195 mov NONE, SNSCB_QOFF ret;
196 first_new_target_scb:
197 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
198 bmov SCBPTR, WAITING_TID_TAIL, 2;
199 bmov SCB_NEXT2, REG0, 2;
200 bmov WAITING_TID_TAIL, REG0, 2;
201 /* Increment our position in the QINFIFO. */
202 mov NONE, SNSCB_QOFF ret;
204 bmov WAITING_TID_HEAD, REG0, 2;
205 bmov WAITING_TID_TAIL, REG0, 2;
206 /* Increment our position in the QINFIFO. */
207 mov NONE, SNSCB_QOFF ret;
211 * Give precedence to downloading new SCBs to execute
212 * unless select-outs are currently frozen.
213 * XXX Use a timer to prevent completion starvation.
215 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
217 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
218 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
219 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
223 * Keep track of the SCBs we are dmaing just
224 * in case the DMA fails or is aborted.
226 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
227 mvi CCSCBCTL, CCSCBRESET;
228 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
229 bmov CCSCBRAM, COMPLETE_SCB_HEAD, 2;
230 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
231 jmp fill_qoutfifo_first_entry;
233 bmov CCSCBRAM, SCB_NEXT_COMPLETE, 2;
234 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
235 fill_qoutfifo_first_entry:
236 mov NONE, SDSCB_QOFF;
237 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
238 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
239 test QOFF_CTLSTA, SDSCB_ROLLOVR jz fill_qoutfifo_loop;
241 mov SCBHCNT, CCSCBADDR;
242 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
243 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
244 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
247 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
248 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
250 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
251 bmov SCBHADDR, SCB_BUSADDR, 4;
252 mvi CCARREN|CCSCBEN|CCSCBRESET call dma_scb;
254 * Now that we've started the DMA, push us onto
255 * the normal completion queue to have our SCBID
256 * posted to the kernel.
258 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
259 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
260 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
264 * Either post or fetch an SCB from host memory. The caller
265 * is responsible for polling for transfer completion.
267 * Prerequisits: Mode == M_CCHAN
268 * SINDEX contains CCSCBCTL flags
269 * SCBHADDR set to Host SCB address
270 * SCBPTR set to SCB src location on "push" operations
272 SET_SRC_MODE M_CCHAN;
273 SET_DST_MODE M_CCHAN;
275 mvi SCBHCNT, SCB_TRANSFER_SIZE;
276 mov CCSCBCTL, SINDEX;
277 or SEQ_FLAGS2, SCB_DMA ret;
281 bmov LONGJMP_SCB, SCBPTR, 2;
283 bmov LONGJMP_ADDR, STACK, 2 ret;
285 bmov LONGJMP_ADDR, STACK, 2;
287 bmov STACK, LONGJMP_ADDR, 2 ret;
290 /************************ Packetized LongJmp Routines *************************/
292 * Must disable interrupts when setting the mode pointer
293 * register as an interrupt occurring mid update will
294 * fail to store the new mode value for restoration on
297 set_mode_work_around:
298 mvi SEQINTCTL, INTVEC1DSL;
299 mov MODE_PTR, SINDEX;
306 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
309 * Rev A hardware fails to update LAST/CURR/NEXTSCB
310 * correctly after a packetized selection in several
313 * 1) If only one command existed in the the queue, the
314 * LAST/CURR/NEXTSCB are unchanged.
316 * 2) In a non QAS, protocol allowed phase change,
317 * the queue is shifted 1 too far. LASTSCB is
318 * the last SCB that was correctly processed.
320 * 3) In the QAS case, if the full list of commands
321 * was successfully sent, NEXTSCB is NULL and neither
322 * CURRSCB nor LASTSCB can be trusted. We must
323 * manually walk the list counting MAXCMDCNT elements
324 * to find the last SCB that was sent correctly.
326 * To simplify the workaround for this bug in SELDO
327 * handling, we initialize LASTSCB prior to enabling
328 * selection so we can rely on it even for case #1 above.
330 bmov LASTSCB, WAITING_TID_HEAD, 2;
332 bmov CURRSCB, WAITING_TID_HEAD, 2;
333 bmov SCBPTR, WAITING_TID_HEAD, 2;
334 shr SELOID, 4, SCB_SCSIID;
336 * If we want to send a message to the device, ensure
337 * we are selecting with atn irregardless of our packetized
338 * agreement. Since SPI4 only allows target reset or PPR
339 * messages if this is a packetized connection, the change
340 * to our negotiation table entry for this selection will
341 * be cleared when the message is acted on.
343 test SCB_CONTROL, MK_MESSAGE jz . + 3;
344 mov NEGOADDR, SELOID;
345 or NEGCONOPTS, ENAUTOATNO;
346 or SCSISEQ0, ENSELO ret;
350 * Allocate a FIFO for a non-packetized transaction.
351 * For some reason unkown to me, both FIFOs must be free before we
352 * can allocate a FIFO for a non-packetized transaction. This
353 * may be fixed in Rev B.
357 * Do whatever work is required to free a FIFO.
359 SET_MODE(M_DFF0, M_DFF0);
360 test LONGJMP_ADDR[1], INVALID_ADDR jnz . + 2;
362 SET_MODE(M_DFF1, M_DFF1);
363 test LONGJMP_ADDR[1], INVALID_ADDR jnz . + 2;
365 SET_MODE(M_SCSI, M_SCSI);
367 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
368 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
370 bmov ARG_1, SCBPTR, 2;
371 or DFFSTAT, CURRFIFO;
372 SET_MODE(M_DFF1, M_DFF1);
373 bmov SCBPTR, ARG_1, 2 ret;
376 * We have been reselected as an initiator
377 * or selected as a target.
383 and SAVED_SCSIID, SELID_MASK, SELID;
386 mvi CLRSINT0, CLRSELDI;
390 * We have successfully selected out.
393 * Dequeue all SCBs sent from the waiting queue
394 * Requeue all SCBs *not* sent to the tail of the waiting queue
395 * Take Razor #494 into account for above.
397 * In Packetized Mode:
398 * Return to the idle loop. Our interrupt handler will take
399 * care of any incoming L_Qs.
401 * In Non-Packetize Mode:
402 * Continue to our normal state machine.
408 /* Clear out all SCBs that have been successfully sent. */
409 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
411 * For packetized, the LQO manager clears ENSELO on
412 * the assertion of SELDO. If we are non-packetized,
413 * LASTSCB and CURRSCB are acuate.
415 test SCSISEQ0, ENSELO jnz use_lastscb;
418 * The update is correct for LQOSTAT1 errors. All
419 * but LQOBUSFREE are handled by kernel interrupts.
420 * If we see LQOBUSFREE, return to the idle loop.
421 * Once we are out of the select_out critical section,
422 * the kernel will cleanup the LQOBUSFREE and we will
423 * eventually restart the selection if appropriate.
425 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
428 * On a phase change oustside of packet boundaries,
429 * LASTSCB points to the currently active SCB context
432 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
435 * If the hardware has traversed the whole list, NEXTSCB
436 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
437 * but MAXCMDCNT is accurate. If we stop part way through
438 * the list or only had one command to issue, NEXTSCB[1] is
439 * not NULL and LASTSCB is the last command to go out.
441 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
446 bmov SCBPTR, WAITING_TID_HEAD, 2;
447 mvi SEQINTCTL, INTVEC1DSL;
448 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
450 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
454 test A, 0xFF jz found_last_sent_scb;
455 bmov SCBPTR, SCB_NEXT, 2;
456 jmp find_lastscb_loop;
458 bmov SCBPTR, LASTSCB, 2;
460 bmov CURRSCB, SCBPTR, 2;
464 * Untested - Verify with Rev B.
466 bmov SCBPTR, CURRSCB, 2;
469 * Requeue any SCBs not sent, to the tail of the waiting Q.
471 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
474 * We know that neither the per-TID list nor the list of
475 * TIDs is empty. Use this knowledge to our advantage.
477 bmov REG0, SCB_NEXT, 2;
478 bmov SCBPTR, WAITING_TID_TAIL, 2;
479 bmov SCB_NEXT2, REG0, 2;
480 bmov WAITING_TID_TAIL, REG0, 2;
481 jmp select_out_inc_tid_q;
483 select_out_list_done:
485 * The whole list made it. Just clear our TID's tail pointer
486 * unless we were queued independently due to our need to
489 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
490 shr DINDEX, 3, SCB_SCSIID;
491 /* XXX When we switch to SCB_SELOID, put +1 in addition below. */
492 or DINDEX, 1; /* Want only the second byte */
493 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
494 mvi DINDIR, SCB_LIST_NULL;
495 select_out_inc_tid_q:
496 bmov SCBPTR, WAITING_TID_HEAD, 2;
497 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
498 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
499 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
500 bmov SCBPTR, CURRSCB, 2;
503 mvi CLRSINT0, CLRSELDO;
505 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
506 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
509 * If this is a packetized connection, return to our
510 * idle_loop and let our interrupt handler deal with
511 * any connection setup/teardown issues. The only
512 * exception is the case of MK_MESSAGE SCBs. In the
513 * A, the LQO manager transitions to LQOSTOP0 even if
514 * we have selected out with ATN asserted and the target
515 * REQs in a non-packet phase.
517 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
518 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
519 test SCSISIGO, ATNO jnz select_out_non_packetized;
520 select_out_no_message:
522 test LQOSTAT2, LQOSTOP0 jnz idle_loop;
524 select_out_non_packetized:
525 /* Non packetized request. */
526 and SCSISEQ0, ~ENSELO;
527 mov SAVED_SCSIID, SCB_SCSIID;
528 mov SAVED_LUN, SCB_LUN;
532 * As soon as we get a successful selection, the target
533 * should go into the message out phase since we have ATN
536 mvi MSG_OUT, MSG_IDENTIFYFLAG;
537 mvi SEQ_FLAGS, NO_CDB_SENT;
540 * Main loop for information transfer phases. Wait for the
541 * target to assert REQ before checking MSG, C/D and I/O for
550 test A, ~P_DATAIN_DT jz p_data;
551 cmp A,P_COMMAND je p_command;
552 cmp A,P_MESGOUT je p_mesgout;
553 cmp A,P_STATUS je p_status;
554 cmp A,P_MESGIN je p_mesgin;
556 mvi SEQINTCODE, BAD_PHASE;
557 jmp ITloop; /* Try reading the bus again. */
560 * Command phase. Set up the DMA registers and let 'er rip.
565 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
566 jnz p_command_allocate_fifo;
568 * Command retry. Free our current FIFO and
569 * re-allocate a FIFO so transfer state is
572 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
573 p_command_allocate_fifo:
575 add NONE, -17, SCB_CDB_LEN;
576 jnc p_command_embedded;
578 bmov HADDR[0], SCB_CDB_PTR, 11;
579 mvi SG_CACHE_PRE, LAST_SEG;
580 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
583 bmov SHCNT[0], SCB_CDB_LEN, 1;
584 bmov SHCNT[1], ALLZEROS, 2;
585 bmov DFDAT, SCB_CDB_STORE, 16;
588 test DFCNTRL, SCSIEN jnz p_command_loop;
590 * DMA Channel automatically disabled.
591 * Don't allow a data phase if the command
592 * was not fully transferred. Make sure that
593 * we clear the IDENTIFY SEEN flag if a retry
596 and SEQ_FLAGS, ~NO_CDB_SENT;
597 test SSTAT2, SDONE jnz ITloop;
598 or SEQ_FLAGS, NO_CDB_SENT;
603 * Status phase. Wait for the data byte to appear, then read it
604 * and store it into the SCB.
609 test SEQ_FLAGS,NOT_IDENTIFIED jz p_status_okay;
610 mvi SEQINTCODE, PROTO_VIOLATION;
613 mov SCB_SCSI_STATUS, SCSIDAT;
614 or SCB_CONTROL, STATUS_RCVD;
618 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
619 * indentify message sequence and send it to the target. The host may
620 * override this behavior by setting the MK_MESSAGE bit in the SCB
621 * control byte. This will cause us to interrupt the host and allow
622 * it to handle the message phase completely on its own. If the bit
623 * associated with this target is set, we will also interrupt the host,
624 * thereby allowing it to send a message on the next selection regardless
625 * of the transaction being sent.
627 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
628 * This is done to allow the host to send messages outside of an identify
629 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
630 * on an SCB that might not be for the current nexus. (For example, a
631 * BDR message in responce to a bad reselection would leave us pointed to
632 * an SCB that doesn't have anything to do with the current target).
634 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
637 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
638 * in case the target decides to put us in this phase for some strange
642 /* Turn on ATN for the retry */
646 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
647 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
649 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
650 test SCB_CONTROL, DISCENB jnz . + 2;
651 and SINDEX, ~DISCENB;
653 * Send a tag message if TAG_ENB is set in the SCB control block.
654 * Use SCB_NONPACKET_TAG as the tag value.
657 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
658 mov SCSIDAT, SINDEX; /* Send the identify message */
660 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
661 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
663 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
664 mov SCB_NONPACKET_TAG jmp p_mesgout_onebyte;
666 * Interrupt the driver, and allow it to handle this message
667 * phase and any required retries.
670 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
671 jmp host_message_loop;
674 mvi CLRSINT1, CLRATNO;
678 * If the next bus phase after ATN drops is message out, it means
679 * that the target is requesting that the last message(s) be resent.
682 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
685 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
686 mov LAST_MSG, MSG_OUT;
687 mvi MSG_OUT, MSG_NOOP; /* No message left */
691 * Message in phase. Bytes are read using Automatic PIO mode.
694 /* read the 1st message byte */
695 mvi ACCUM call inb_first;
697 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
698 cmp A,MSG_DISCONNECT je mesgin_disconnect;
699 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
700 cmp ALLZEROS,A je mesgin_complete;
701 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
702 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
703 cmp A,MSG_NOOP je mesgin_done;
706 * Pushed message loop to allow the kernel to
707 * run it's own message state engine. To avoid an
708 * extra nop instruction after signaling the kernel,
709 * we perform the phase_lock before checking to see
710 * if we should exit the loop and skip the phase_lock
711 * in the ITloop. Performing back to back phase_locks
712 * shouldn't hurt, but why do it twice...
715 call phase_lock; /* Benign the first time through. */
716 mvi SEQINTCODE, HOST_MSG_LOOP;
717 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
718 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
719 mov SCSIDAT, RETURN_2;
720 jmp host_message_loop;
721 /* Must be CONT_MSG_LOOP_READ */
722 mov NONE, SCSIDAT; /* ACK Byte */
723 jmp host_message_loop;
725 mesgin_ign_wide_residue:
726 shr NEGOADDR, 4, SAVED_SCSIID;
727 test NEGCONOPTS, WIDEXFER jz mesgin_reject;
728 /* Pull the residue byte */
729 mvi REG0 call inb_next;
730 cmp REG0, 0x01 jne mesgin_reject;
731 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
732 test DATA_COUNT_ODD, 0x1 jz mesgin_done;
733 mvi SEQINTCODE, IGN_WIDE_RES;
737 mvi MSG_MESSAGE_REJECT call mk_mesg;
739 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
742 #define INDEX_DISC_LIST_SCB(target, lun) \
744 shr SCBPTR[1], 3, target
746 #define INDEX_DISC_LIST(target, lun) \
747 INDEX_DISC_LIST_SCB(target, lun); \
748 and SINDEX, 0x7, target; \
750 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
751 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
755 * Determine whether a target is using tagged or non-tagged
756 * transactions by first looking at the transaction stored in
757 * the per-device, disconnected array. If there is no untagged
758 * transaction for this target this must be an untagged transaction.
760 shr SINDEX, 4, SAVED_SCSIID;
761 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
762 INDEX_DISC_LIST(SINDEX, SAVED_LUN);
763 bmov DINDEX, SINDEX, 2;
764 bmov SCBPTR, SINDIR, 2;
765 cmp SCBPTR[1], SCB_LIST_NULL je snoop_tag;
766 test SCB_CONTROL, TAG_ENB jnz snoop_tag;
767 /* Untagged. Setup the SCB. */
768 bmov REG1, SCB_TAG, 4; /* Save SCB_TAG and SCB_NEXT */
769 jmp dequeue_first_scb;
772 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
773 * If we get one, we use the tag returned to find the proper
774 * SCB. The disconnected list contains any outstanding tagged transactions
775 * where SCB_TAG != SCB_NONPACKET_TAG or SCB_NONPACKET_TAG + 256.
776 * After receiving the tag, look for the SCB at SCB locations tag and
777 * tag + 256. If those SCBs do not match, traverse the disconnected
778 * list until we find the correct SCB.
781 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
784 mov NONE, SCSIDAT; /* ACK Identify MSG */
786 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
789 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
790 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
793 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
795 /* Save diconnected list head. */
796 bmov REG0, SCBPTR, 2;
798 mvi SCBPTR call inb_next; /* tag value */
802 cmp SCB_NONPACKET_TAG, A jne verify_other_scb;
804 cmp SCB_SCSIID, A jne verify_other_scb;
806 cmp SCB_LUN, A je setup_SCB;
809 test SCBPTR[1], 0xFF jnz verify_scb;
812 /* Restore disconnected list head. */
813 bmov SCBPTR, REG0, 2;
814 mvi REG0[1], SCB_LIST_NULL;
816 search_disc_list_loop:
817 cmp SCB_NONPACKET_TAG, A je dequeue_scb;
818 bmov REG0, SCBPTR, 2;
819 bmov SCBPTR, SCB_NEXT, 2;
820 cmp SCBPTR[1], SCB_LIST_NULL jne search_disc_list_loop;
824 bmov REG1, SCB_TAG, 4; /* Save SCB_TAG and SCB_NEXT */
825 cmp REG0[1], SCB_LIST_NULL jne dequeue_intermediate_SCB;
827 shr SINDEX, 4, SAVED_SCSIID;
828 INDEX_DISC_LIST_SCB(SINDEX, SAVED_LUN);
829 /* Update list head. */
830 bmov DINDIR, REG2, 2;
832 dequeue_intermediate_SCB:
833 bmov SCBPTR, REG0, 2;
834 bmov SCB_NEXT, REG2, 2;
836 bmov SCBPTR, REG1, 2;
839 * Ensure that the SCB the tag points to is for
840 * an SCB transaction to the reconnecting target.
843 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
846 test SCB_CONTROL,DISCONNECTED jz not_found;
847 and SCB_CONTROL,~DISCONNECTED;
848 clr SEQ_FLAGS; /* make note of IDENTIFY */
849 test SCB_SGPTR, SG_LIST_NULL jnz . + 2;
851 /* mvi SEQINTCODE, PRINT_RESIDUALS; */
852 /* See if the host wants to send a message upon reconnection */
853 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
854 mvi HOST_MSG call mk_mesg;
858 mvi SEQINTCODE, NO_MATCH;
862 mvi SEQINTCODE, NO_MATCH;
866 * We received a "command complete" message. Put the SCB on the complete
867 * queue and trigger a completion interrupt via the idle loop. Before doing
868 * so, check to see if there
869 * is a residual or the status byte is something other than STATUS_GOOD (0).
870 * In either of these conditions, we upload the SCB back to the host so it can
871 * process this information. In the case of a non zero status byte, we
872 * additionally interrupt the kernel driver synchronously, allowing it to
873 * decide if sense should be retrieved. If the kernel driver wishes to request
874 * sense, it will fill the kernel SCB with a request sense command, requeue
875 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
876 * RETURN_1 to SEND_SENSE.
881 * If ATN is raised, we still want to give the target a message.
882 * Perhaps there was a parity error on this last message byte.
883 * Either way, the target should take us to message out phase
884 * and then attempt to complete the command again. We should use a
885 * critical section here to guard against a timeout triggering
886 * for this command and setting ATN while we are still processing
888 test SCSISIGI, ATNI jnz mesgin_done;
892 * If the target never sent an identify message but instead went
893 * to mesgin to give an invalid message, let the host abort us.
895 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz . + 3;
896 mvi SEQINTCODE, PROTO_VIOLATION;
900 * If the target never gave us status information, have
901 * the host abort the command.
903 test SCB_CONTROL, STATUS_RCVD jz . - 2;
906 * See if we attempted to deliver a message but the target ingnored us.
908 test SCB_CONTROL, MK_MESSAGE jz . + 2;
909 mvi SEQINTCODE, MKMSG_FAILED;
910 call queue_scb_completion;
914 /* Cancel any pending select-out. */
915 test SSTAT0, SELDO jnz . + 2;
916 and SCSISEQ0, ~ENSELO;
919 add QFREEZE_COUNT, 1;
920 adc QFREEZE_COUNT[1], A;
921 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
922 mov A, ACCUM_SAVE ret;
924 queue_arg1_scb_completion:
925 SET_MODE(M_SCSI, M_SCSI);
926 bmov SCBPTR, ARG_1, 2;
927 queue_scb_completion:
928 test SCB_SCSI_STATUS,0xff jnz bad_status;
930 * Check for residuals
932 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
933 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
934 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
936 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
937 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
939 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
942 bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
943 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
944 or SCB_SGPTR, SG_STATUS_VALID ret;
947 * Is it a disconnect message? Set a flag in the SCB to remind us
948 * and await the bus going free. If this is an untagged transaction
949 * store the SCB id for it in our untagged target table for lookup on
954 * If ATN is raised, we still want to give the target a message.
955 * Perhaps there was a parity error on this last message byte
956 * or we want to abort this command. Either way, the target
957 * should take us to message out phase and then attempt to
959 * XXX - Wait for more testing.
960 test SCSISIGI, ATNI jnz mesgin_done;
962 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz disconnect_allowed;
963 mvi SEQINTCODE, PROTO_VIOLATION;
966 or SCB_CONTROL,DISCONNECTED;
967 test SCB_CONTROL, TAG_ENB jz queue_disc_scb;
968 mov A, SCB_NONPACKET_TAG;
969 cmp SCBPTR, A je await_busfree;
971 bmov REG0, SCBPTR, 2;
972 shr SINDEX, 4, SCB_SCSIID;
973 INDEX_DISC_LIST(SINDEX, SCB_LUN);
974 bmov DINDEX, SINDEX, 2;
975 bmov REG1, SINDIR, 2;
976 bmov DINDIR, REG0, 2;
977 bmov SCBPTR, REG0, 2;
978 bmov SCB_NEXT, REG1, 2;
981 and SIMODE1, ~ENBUSFREE;
982 mov NONE, SCSIDAT; /* Ack the last byte */
983 call clear_target_state;
984 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
985 jnz await_busfree_not_m_dff;
988 await_busfree_clrchn:
989 mvi DFFSXFRCTL, CLRCHN;
990 await_busfree_not_m_dff:
991 test SSTAT1,REQINIT|BUSFREE jz .;
992 test SSTAT1, BUSFREE jnz idle_loop;
993 mvi SEQINTCODE, MISSED_BUSFREE;
997 * Save data pointers message:
998 * Copying RAM values back to SCB, for Save Data Pointers message, but
999 * only if we've actually been into a data phase to change them. This
1000 * protects against bogus data in scratch ram and the residual counts
1001 * since they are only initialized when we go into data_in or data_out.
1002 * Ack the message as soon as possible. For chips without S/G pipelining,
1003 * we can only ack the message after SHADDR has been saved. On these
1004 * chips, SHADDR increments with every bus transaction, even PIO.
1006 SET_SRC_MODE M_DFF1;
1007 SET_DST_MODE M_DFF1;
1009 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1010 test SEQ_FLAGS, DPHASE jz ITloop;
1016 * If we are asked to save our position at the end of the
1017 * transfer, just mark us at the end rather than perform a
1020 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1021 or SCB_SGPTR, SG_LIST_NULL ret;
1025 * The SCB_DATAPTR becomes the current SHADDR.
1026 * All other information comes directly from our residual
1029 bmov SCB_DATAPTR, SHADDR, 8;
1030 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1033 * Restore pointers message? Data pointers are recopied from the
1034 * SCB anytime we enter a data phase for the first time, so all
1035 * we need to do is clear the DPHASE flag and let the data phase
1036 * code do the rest. We also reset/reallocate the FIFO to make
1037 * sure we have a clean start for the next data phase.
1040 and SEQ_FLAGS, ~DPHASE;
1041 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1042 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1043 msgin_rdptrs_get_fifo:
1048 mvi LASTPHASE, P_BUSFREE;
1049 /* clear target specific flags */
1050 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
1053 test SCSIPHASE, 0xFF jz .;
1054 phase_lock_latch_phase:
1055 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1058 * Functions to read data in Automatic PIO mode.
1060 * An ACK is not sent on input from the target until SCSIDATL is read from.
1061 * So we wait until SCSIDATL is latched (the usual way), then read the data
1062 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1063 * line, or we just want to acknowledge the byte, then we do a dummy read
1064 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1065 * data byte on the bus until we send our ACK.
1067 * The assumption here is that these are called in a particular sequence,
1068 * and that REQ is already set when inb_first is called. inb_{first,next}
1069 * use the same calling convention as inb.
1072 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1075 * If there is a parity error, wait for the kernel to
1076 * see the interrupt and prepare our message response
1077 * before continuing.
1079 test SCSIPHASE, 0xFF jz .;
1080 inb_next_check_phase:
1081 and LASTPHASE, PHASE_MASK, SCSISIGI;
1082 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1086 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1088 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1092 mov MSG_OUT,SINDEX ret;
1094 SET_SRC_MODE M_DFF1;
1095 SET_DST_MODE M_DFF1;
1097 test SG_STATE, FETCH_INPROG jz return;
1099 disable_ccsgen_fetch_done:
1103 mvi SEQINTCTL, INTVEC1DSL;
1104 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1107 data_group_idle_loop:
1108 mov SAVED_MODE, MODE_PTR;
1109 test SG_STATE, LOADING_NEEDED jz . + 2;
1111 call toggle_dff_mode;
1112 test SG_STATE, LOADING_NEEDED jz . + 2;
1114 call idle_loop_cchan;
1115 mov SAVED_MODE jmp set_mode_work_around;
1119 * Do we have any prefetch left???
1121 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1124 * Can this FIFO have access to the S/G cache yet?
1126 test CCSGCTL, SG_CACHE_AVAIL jz return;
1128 /* Did we just finish fetching segs? */
1129 cmp CCSGCTL, CCSGEN|SG_CACHE_AVAIL|CCSGDONE
1130 je idle_sgfetch_complete;
1132 /* Are we actively fetching segments? */
1133 test CCSGCTL, CCSGEN jnz return;
1136 * We fetch a "cacheline aligned" and sized amount of data
1137 * so we don't end up referencing a non-existant page.
1138 * Cacheline aligned is in quotes because the kernel will
1139 * set the prefetch amount to a reasonable level if the
1140 * cacheline size is unknown.
1142 mvi SGHCNT, SG_PREFETCH_CNT;
1143 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1144 bmov SGHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
1145 mvi CCSGCTL, CCSGEN|SG_CACHE_AVAIL|CCSGRESET;
1146 or SG_STATE, FETCH_INPROG ret;
1147 idle_sgfetch_complete:
1149 * Guard against SG_CACHE_AVAIL activating during sg fetch
1150 * request in the other FIFO.
1152 test SG_STATE, FETCH_INPROG jz return;
1153 call disable_ccsgen_fetch_done;
1154 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1155 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1157 /* Does the hardware have space for another SG entry? */
1158 test DFSTATUS, PRELOAD_AVAIL jz return;
1159 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1160 bmov HADDR, CCSGRAM, 8;
1162 bmov HADDR, CCSGRAM, 4;
1164 bmov HCNT, CCSGRAM, 3;
1165 test HCNT[0], 0x1 jz . + 2;
1166 xor DATA_COUNT_ODD, 0x1;
1167 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1168 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1169 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1171 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1172 /* Skip 4 bytes of pad. */
1176 clr A; /* add sizeof(struct scatter) */
1177 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1178 adc SCB_RESIDUAL_SGPTR[1],A;
1179 adc SCB_RESIDUAL_SGPTR[2],A;
1180 adc SCB_RESIDUAL_SGPTR[3],A;
1181 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1182 test DATA_COUNT_ODD, 0x1 jz . + 2;
1184 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1185 or SINDEX, LAST_SEG;
1187 mov SG_CACHE_PRE, SINDEX;
1189 * Load the segment. Or in HDMAEN here too
1190 * just in case HDMAENACK has not come true
1191 * by the time this segment is loaded. If
1192 * HDMAENACK is not true, this or will disable
1193 * HDMAEN mid-transfer. We do not want to simply
1194 * mvi our original settings as SCSIEN automatically
1195 * de-asserts and we don't want to accidentally
1198 or DFCNTRL, PRELOADEN|HDMAEN;
1200 * Do we have another segment in the cache?
1202 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1204 and SG_STATE, ~SEGS_AVAIL ret;
1207 * Initialize the DMA address and counter from the SCB.
1210 bmov HADDR, SCB_DATAPTR, 11;
1211 and DATA_COUNT_ODD, 0x1, SCB_DATACNT[0];
1212 and REG0, ~SG_FULL_RESID, SCB_SGPTR[0];
1213 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1215 test DATA_COUNT_ODD, 0x1 jz . + 2;
1217 mov SG_CACHE_PRE, REG0;
1218 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1220 * Since we've are entering a data phase, we will
1221 * rely on the SCB_RESID* fields. Initialize the
1222 * residual and clear the full residual flag.
1224 and SCB_SGPTR[0], ~SG_FULL_RESID;
1225 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1226 /* If we need more S/G elements, tell the idle loop */
1227 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1228 mvi SG_STATE, LOADING_NEEDED ret;
1232 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1233 mvi SEQINTCODE, PROTO_VIOLATION;
1236 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1239 * If we re-enter the data phase after going through another
1240 * phase, our transfer location has almost certainly been
1241 * corrupted by the interveining, non-data, transfers. Ask
1242 * the host driver to fix us up based on the transfer residual
1243 * unless we already know that we should be bitbucketing.
1245 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1246 mvi SEQINTCODE, PDATA_REINIT;
1250 * Turn on `Bit Bucket' mode, wait until the target takes
1251 * us to another phase, and then notify the host.
1253 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1254 jnz bitbucket_not_m_dff;
1256 * Ensure that any FIFO contents are cleared out and the
1257 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1258 * doesn't discard data already in the FIFO.
1260 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1261 SET_MODE(M_SCSI, M_SCSI);
1262 bitbucket_not_m_dff:
1263 or SXFRCTL1,BITBUCKET;
1264 test SCSIPHASE, DATA_PHASE_MASK jnz .;
1265 and SXFRCTL1, ~BITBUCKET;
1266 SET_MODE(M_DFF1, M_DFF1);
1267 mvi SEQINTCODE, DATA_OVERRUN;
1270 data_phase_initialize:
1271 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1272 call load_first_seg;
1273 data_phase_inbounds:
1274 /* We have seen a data phase at least once. */
1275 or SEQ_FLAGS, DPHASE;
1276 data_group_dma_loop:
1278 * The transfer is complete if either the last segment
1279 * completes or the target changes phase. Both conditions
1280 * will clear SCSIEN. We test SCSIEN twice during our
1281 * "idle loop" to avoid long delays before we notice the
1282 * SCSIEN transition.
1284 call data_group_idle_loop;
1285 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1287 data_group_dmafinish:
1289 * The transfer has terminated either due to a phase
1290 * change, and/or the completion of the last segment.
1291 * We have two goals here. Do as much other work
1292 * as possible while the data fifo drains on a read
1293 * and respond as quickly as possible to the standard
1294 * messages (save data pointers/disconnect and command
1295 * complete) that usually follow a data phase.
1300 * Go ahead and shut down the DMA engine now.
1302 test DFCNTRL, DIRECTION jnz data_phase_finish;
1303 data_group_fifoflush:
1304 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1305 or DFCNTRL, FIFOFLUSH;
1308 * We have enabled the auto-ack feature. This means
1309 * that the controller may have already transferred
1310 * some overrun bytes into the data FIFO and acked them
1311 * on the bus. The only way to detect this situation is
1312 * to wait for LAST_SEG_DONE to come true on a completed
1313 * transfer and then test to see if the data FIFO is
1314 * non-empty. We know there is more data yet to transfer
1315 * if SG_LIST_NULL is not yet set, thus there cannot be
1318 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1319 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1320 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1325 * If the target has left us in data phase, loop through
1326 * the dma code again. We will only loop if there is a
1329 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1330 test SSTAT0, TARGET jnz data_phase_done;
1332 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1333 test SSTAT1, REQINIT jz .;
1334 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1338 /* Kill off any pending prefetch */
1339 call disable_ccsgen;
1341 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1342 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1344 and SEQ_FLAGS, ~DPHASE_PENDING;
1345 * For data-in phases, wait for any pending acks from the
1346 * initiator before changing phase. We only need to
1347 * send Ignore Wide Residue messages for data-in phases.
1348 test DFCNTRL, DIRECTION jz target_ITloop;
1349 test SSTAT1, REQINIT jnz .;
1350 test DATA_COUNT_ODD, 0x1 jz target_ITloop;
1351 SET_MODE(M_SCSI, M_SCSI);
1352 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1355 * Issue an Ignore Wide Residue Message.
1356 mvi P_MESGIN|BSYO call change_phase;
1357 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1358 mvi 1 call target_outb;
1366 * We assume that, even though data may still be
1367 * transferring to the host, that the SCSI side of
1368 * the DMA engine is now in a static state. This
1369 * allows us to update our notion of where we are
1372 * If, by chance, we stopped before being able
1373 * to fetch additional segments for this transfer,
1374 * yet the last S/G was completely exhausted,
1375 * call our idle loop until it is able to load
1376 * another segment. This will allow us to immediately
1377 * pickup on the next segment on the next data phase.
1379 * If we happened to stop on the last segment, then
1380 * our residual information is still correct from
1381 * the idle loop and there is no need to perform
1385 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1386 /* Record if we've consumed all S/G entries */
1387 test MDFFSTAT, SHVALID jz . + 2;
1388 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1389 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1390 residual_before_last_seg:
1391 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1393 * Can never happen from an interrupt as the packetized
1394 * hardware will only interrupt us once SHVALID or
1397 call data_group_idle_loop;
1402 * Fixup the residual next S/G pointer. The S/G preload
1403 * feature of the chip allows us to load two elements
1404 * in addition to the currently active element. We
1405 * store the bottom byte of the next S/G pointer in
1406 * the SG_CACHE_PTR register so we can restore the
1407 * correct value when the DMA completes. If the next
1408 * sg ptr value has advanced to the point where higher
1409 * bytes in the address have been affected, fix them
1412 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1413 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1414 add SCB_RESIDUAL_SGPTR[1], -1;
1415 adc SCB_RESIDUAL_SGPTR[2], -1;
1416 adc SCB_RESIDUAL_SGPTR[3], -1;
1418 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1420 test SG_CACHE_SHADOW, ODD_SEG jz . + 2;
1421 or DATA_COUNT_ODD, 0x1;
1422 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1423 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1426 nop; /* Jumps in the first ISR instruction fail on Rev A. */
1427 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1428 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1429 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1430 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1431 mvi SEQINTCODE, INVALID_SEQINT;
1434 * There are two types of save pointers interrupts:
1435 * The first is a snapshot save pointers where the current FIFO is not
1436 * active and contains a snapshot of the current poniter information.
1437 * This happens between packets in a stream for a single L_Q. Since we
1438 * are not performing a pointer save, we can safely clear the channel
1439 * so it can be used for other transactions.
1441 * The second case is a save pointers on an active FIFO which occurs
1442 * if the target changes to a new L_Q or busfrees/QAS' and the transfer
1443 * has a residual. This should occur coincident with a ctxtdone. We
1444 * disable the interrupt and allow our active routine to handle the
1448 test DFCNTRL, HDMAENACK jz snapshot_saveptr;
1449 and SEQIMODE, ~ENSAVEPTRS;
1450 or SEQINTCTL, IRET ret;
1452 mvi DFFSXFRCTL, CLRCHN;
1453 or SEQINTCTL, IRET ret;
1456 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun;
1457 call load_first_seg;
1458 call pkt_handle_xfer;
1459 or SEQINTCTL, IRET ret;
1463 add NONE, -13, SCB_CDB_LEN;
1464 jnc cfg4istat_have_sense_addr;
1465 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1467 * Host sets up address/count and enables transfer.
1469 mvi SEQINTCODE, CFG4ISTAT_INTR;
1470 jmp cfg4istat_setup_handler;
1471 cfg4istat_have_sense_addr:
1472 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1473 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1474 mvi SG_CACHE_PRE, LAST_SEG;
1475 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1476 cfg4istat_setup_handler:
1478 * Status pkt is transferring to host.
1479 * Wait in idle loop for transfer to complete.
1481 call pkt_handle_status;
1482 or SEQINTCTL, IRET ret;
1485 * See if the target has gone on in this context creating an
1486 * overrun condition. For the write case, the hardware cannot
1487 * ack bytes until data is provided. So, if the target begins
1488 * another packet without changing contexts, implying we are
1489 * not sitting on a packet boundary, we are in an overrun
1490 * situation. For the read case, the hardware will continue to
1491 * ack bytes into the FIFO, and may even ack the last overrun packet
1492 * into the FIFO. If the FIFO should become non-empty, we are in
1493 * a read overrun case.
1495 #define check_overrun \
1496 /* Not on a packet boundary. */ \
1497 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1498 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1501 bmov LONGJMP_SCB, SCBPTR, 2;
1502 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1504 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1505 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1506 test SCSISIGO, ATNO jnz . + 2;
1507 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1509 * Defer handling of this NONPACKREQ until we
1510 * can be sure it pertains to this FIFO. SAVEPTRS
1511 * will not be asserted if the NONPACKREQ is for us,
1512 * so we must simulate it if shaddow is valid. If
1513 * shaddow is not valid, keep running this FIFO until we
1514 * have satisfied the transfer by loading segments and
1515 * waiting for either shaddow valid or last_seg_done.
1517 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1519 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1522 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1523 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz last_pkt_done;
1524 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1525 test SCSISIGO, ATNO jnz . + 2;
1526 test SSTAT2, NONPACKREQ jz return;
1527 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1531 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1532 or DFCNTRL, FIFOFLUSH;
1534 test SCB_CONTROL, STATUS_RCVD jz wait_pkt_end;
1536 or SCB_SGPTR, SG_LIST_NULL;
1538 * I think it is safe to skip the FIFO check.
1539 * in this case as LAST_SEG_DONE implies
1540 * the other FIFO, if ever active for this transfer,
1544 or LONGJMP_ADDR[1], INVALID_ADDR;
1545 bmov ARG_1, SCBPTR, 2;
1546 mvi DFFSXFRCTL, CLRCHN;
1547 jmp queue_arg1_scb_completion;
1550 bmov ARG_1, SCBPTR, 2;
1551 mvi DFFSXFRCTL, CLRCHN;
1554 call toggle_dff_mode;
1556 jnc queue_arg1_scb_completion;
1564 test SEQINTSRC, CTXTDONE jnz pkt_end;
1566 test SSTAT2, NONPACKREQ jz return;
1567 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1571 or LONGJMP_ADDR[1], INVALID_ADDR;
1572 or SCB_SGPTR, SG_LIST_NULL;
1573 test SCB_CONTROL, STATUS_RCVD jnz last_pkt_complete;
1574 mvi DFFSXFRCTL, CLRCHN ret;
1578 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1579 * or we have a pending nonpackreq for this FIFO. We differentiate
1580 * between the two by capturing the state of the SAVEPTRS interrupt
1581 * prior to clearing and handling the common code of these two cases.
1585 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1586 or DFCNTRL, FIFOFLUSH;
1588 mov REG0, SEQINTSRC;
1589 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1592 call disable_ccsgen;
1593 or SEQIMODE, ENSAVEPTRS;
1594 or LONGJMP_ADDR[1], INVALID_ADDR;
1595 pkt_saveptrs_check_status:
1596 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1597 test SCB_CONTROL, STATUS_RCVD jz pkt_saveptrs_clrchn;
1598 jmp last_pkt_complete;
1599 pkt_saveptrs_clrchn:
1600 mvi DFFSXFRCTL, CLRCHN ret;
1603 check_status_overrun:
1604 test SHCNT[2], 0xFF jz status_IU_done;
1605 mvi SEQINTCODE, STATUS_OVERRUN;
1609 test MDFFSTAT, LASTSDONE jnz check_status_overrun;
1610 test SEQINTSRC, CTXTDONE jz return;
1613 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1614 or DFCNTRL, FIFOFLUSH;
1616 or LONGJMP_ADDR[1], INVALID_ADDR;
1617 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
1618 or SCB_CONTROL, STATUS_RCVD;
1619 jmp last_pkt_complete;
1622 SET_SRC_MODE M_DFF0;
1623 SET_DST_MODE M_DFF0;
1626 test LONGJMP_ADDR[1], INVALID_ADDR jnz return;
1628 cmp LONGJMP_SCB[1], A jne return;
1630 cmp LONGJMP_SCB[0], A jne return;
1635 * Nonpackreq is a polled status. It can come true in three situations:
1636 * we have received an L_Q, we have sent one or more L_Qs, or there is no
1637 * L_Q context associated with this REQ (REQ occurs immediately after a
1638 * (re)selection). Routines that know that the context responsible for this
1639 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
1640 * top level idle loop, we exhaust all active contexts prior to determining that
1641 * we simply do not have the full I_T_L_Q for this phase.
1643 unexpected_nonpkt_phase_find_ctxt:
1645 * This nonpackreq is most likely associated with one of the tags
1646 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
1647 * nonpackreq if we've cleared out the FIFOs and handled any
1650 SET_SRC_MODE M_SCSI;
1651 SET_DST_MODE M_SCSI;
1652 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
1653 cmp A, FIFO1FREE|FIFO0FREE jne return;
1654 test SSTAT0, SELDO jnz return;
1655 mvi SCBPTR[1], SCB_LIST_NULL;
1656 unexpected_nonpkt_phase:
1657 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz . + 3;
1658 SET_SRC_MODE M_DFF0;
1659 SET_DST_MODE M_DFF0;
1660 or LONGJMP_ADDR[1], INVALID_ADDR;
1661 mvi DFFSXFRCTL, CLRCHN;
1662 mvi CLRSINT2, CLRNONPACKREQ;
1663 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
1664 mvi SEQINTCODE, ENTERING_NONPACK;
1668 mvi SEQINTCODE, ILLEGAL_PHASE;
1672 * We have entered an overrun situation. If we have working
1673 * BITBUCKET, flip that on and let the hardware eat any overrun
1674 * data. Otherwise use an overrun buffer in the host to simulate
1678 mvi SEQINTCODE, CFG4OVERRUN;
1680 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
1681 SET_MODE(M_SCSI, M_SCSI);
1682 or SXFRCTL1,BITBUCKET;
1683 SET_SRC_MODE M_DFF1;
1684 SET_DST_MODE M_DFF1;
1686 call load_overrun_buf;
1687 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
1690 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1691 test DFSTATUS, PKT_PRELOAD_AVAIL jz overrun_load_done;
1692 call load_overrun_buf;
1693 or DFCNTRL, PRELOADEN;
1696 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
1697 test SSTAT2, NONPACKREQ jz return;
1699 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
1700 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1701 test SCB_CONTROL, STATUS_RCVD jnz last_pkt_queue_scb;
1702 mvi DFFSXFRCTL, CLRCHN ret;
1704 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1707 * Load a dummy segment if preload space is available.
1709 mov HADDR[0], SHARED_DATA_ADDR;
1710 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
1713 adc HADDR[2], A, SHARED_DATA_ADDR[2];
1714 adc HADDR[3], A, SHARED_DATA_ADDR[3];
1716 bmov HADDR[4], ALLZEROS, 4;
1717 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
1719 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);