2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#60 $"
44 PATCH_ARG_LIST = "struct ahd_softc *ahd"
47 #include "aic79xx.reg"
48 #include "scsi_message.h"
51 SET_MODE(M_SCSI, M_SCSI)
52 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
53 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz idle_loop_checkbus;
54 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
56 * ENSELO is cleared by a SELDO, so we must test for SELDO
60 test SSTAT0, SELDO jnz select_out;
65 test SSTAT0, SELDO jnz select_out;
67 test SSTAT0, SELDI jnz select_in;
68 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
69 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
70 call unexpected_nonpkt_phase_find_ctxt;
71 idle_loop_check_nonpackreq:
72 test SSTAT2, NONPACKREQ jz idle_loop_scsi;
73 call unexpected_nonpkt_phase_find_ctxt;
76 test LQISTAT2, LQIGSAVAIL jz idle_loop_service_fifos;
78 * We have received good status for this transaction. There may
79 * still be data in our FIFOs draining to the host. Setup
80 * monitoring of the draining process or complete the SCB.
83 bmov SCBPTR, GSFIFO, 2;
85 or SCB_CONTROL, STATUS_RCVD;
88 * Since this status did not consume a FIFO, we have to
89 * be a bit more dilligent in how we check for FIFOs pertaining
90 * to this transaction. There are three states that a FIFO still
91 * transferring data may be in.
93 * 1) Configured and draining to the host, with a pending CLRCHN.
94 * 2) Configured and draining to the host, no pending CLRCHN.
95 * 3) Pending cfg4data, fifo not empty.
97 * Cases 1 and 2 can be detected by noticing that a longjmp is
98 * active for the FIFO and LONGJMP_SCB matches our SCB. In this
99 * case, we allow the routine servicing the FIFO to complete the SCB.
101 * Case 3 implies either a pending or yet to occur save data
102 * pointers for this same context in the other FIFO. So, if
103 * we detect case 2, we will properly defer the post of the SCB
104 * and achieve the desired result. The pending cfg4data will
105 * notice that status has been received and complete the SCB.
107 test SCB_SGPTR, SG_LIST_NULL jz good_status_check_fifos;
109 * All segments have been loaded (or no data transfer), so
110 * it is safe to complete the command. Since this was a
111 * cheap command to check for completion, loop to see if
112 * more entries can be removed from the GSFIFO.
118 good_status_check_fifos:
120 bmov ARG_1, SCBPTR, 2;
121 SET_MODE(M_DFF0, M_DFF0)
123 jc idle_loop_service_fifos;
124 SET_MODE(M_DFF1, M_DFF1)
126 jc idle_loop_service_fifos;
127 SET_MODE(M_SCSI, M_SCSI)
128 call queue_scb_completion;
130 idle_loop_service_fifos:
131 SET_MODE(M_DFF0, M_DFF0)
132 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
135 SET_MODE(M_DFF1, M_DFF1)
136 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_last_fifo_done;
138 idle_loop_last_fifo_done:
139 call idle_loop_cchan;
143 SET_MODE(M_CCHAN, M_CCHAN)
145 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
146 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
147 test CCSCBCTL, CCSCBDONE jz return;
151 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
153 * A complete SCB upload requires no intervention.
154 * The SCB is already on the COMPLETE_SCB list
155 * and its completion notification will now be
156 * handled just like any other SCB.
158 and CCSCBCTL, ~(CCARREN|CCSCBEN) ret;
159 fill_qoutfifo_dmadone:
160 and CCSCBCTL, ~(CCARREN|CCSCBEN);
161 mvi INTSTAT, CMDCMPLT;
162 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
163 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
164 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
165 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
166 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
169 fetch_new_scb_inprog:
170 test CCSCBCTL, ARRDONE jz return;
172 and CCSCBCTL, ~(CCARREN|CCSCBEN);
173 bmov REG0, SCBPTR, 2;
174 /* Update the next SCB address to download. */
175 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
176 mvi SCB_NEXT[1], SCB_LIST_NULL;
177 mvi SCB_NEXT2[1], SCB_LIST_NULL;
179 * SCBs that want to send messages are always
180 * queued independently. This ensures that they
181 * are at the head of the SCB list to select out
182 * to a target and we will see the MK_MESSAGE flag.
184 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
185 shr SINDEX, 3, SCB_SCSIID;
187 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
188 bmov DINDEX, SINDEX, 2;
189 bmov SCBPTR, SINDIR, 2;
190 bmov DINDIR, REG0, 2;
191 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
192 bmov SCB_NEXT, REG0, 2;
194 /* Increment our position in the QINFIFO. */
195 mov NONE, SNSCB_QOFF ret;
196 first_new_target_scb:
197 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
198 bmov SCBPTR, WAITING_TID_TAIL, 2;
199 bmov SCB_NEXT2, REG0, 2;
200 bmov WAITING_TID_TAIL, REG0, 2;
201 /* Increment our position in the QINFIFO. */
202 mov NONE, SNSCB_QOFF ret;
204 bmov WAITING_TID_HEAD, REG0, 2;
205 bmov WAITING_TID_TAIL, REG0, 2;
206 /* Increment our position in the QINFIFO. */
207 mov NONE, SNSCB_QOFF ret;
212 * Give precedence to downloading new SCBs to execute
213 * unless select-outs are currently frozen.
214 * XXX Use a timer to prevent completion starvation.
216 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
218 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
219 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
220 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
224 * Keep track of the SCBs we are dmaing just
225 * in case the DMA fails or is aborted.
227 mov A, QOUTFIFO_ENTRY_VALID_TAG;
228 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
229 mvi CCSCBCTL, CCSCBRESET;
230 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
231 mov CCSCBRAM, COMPLETE_SCB_HEAD;
232 or CCSCBRAM, A, COMPLETE_SCB_HEAD[1];
233 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
234 jmp fill_qoutfifo_first_entry;
236 mov CCSCBRAM, SCB_NEXT_COMPLETE;
237 or CCSCBRAM, A, SCB_NEXT_COMPLETE[1];
238 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
239 fill_qoutfifo_first_entry:
240 mov NONE, SDSCB_QOFF;
241 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
242 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
243 test QOFF_CTLSTA, SDSCB_ROLLOVR jz fill_qoutfifo_loop;
245 mov SCBHCNT, CCSCBADDR;
246 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
247 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
248 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
251 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
252 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
254 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
255 bmov SCBHADDR, SCB_BUSADDR, 4;
256 mvi CCARREN|CCSCBEN|CCSCBRESET call dma_scb;
258 * Now that we've started the DMA, push us onto
259 * the normal completion queue to have our SCBID
260 * posted to the kernel.
262 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
263 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
264 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
268 * Either post or fetch an SCB from host memory. The caller
269 * is responsible for polling for transfer completion.
271 * Prerequisits: Mode == M_CCHAN
272 * SINDEX contains CCSCBCTL flags
273 * SCBHADDR set to Host SCB address
274 * SCBPTR set to SCB src location on "push" operations
276 SET_SRC_MODE M_CCHAN;
277 SET_DST_MODE M_CCHAN;
279 mvi SCBHCNT, SCB_TRANSFER_SIZE;
280 mov CCSCBCTL, SINDEX ret;
284 bmov LONGJMP_SCB, SCBPTR, 2;
286 bmov LONGJMP_ADDR, STACK, 2 ret;
288 bmov LONGJMP_ADDR, STACK, 2;
290 bmov STACK, LONGJMP_ADDR, 2 ret;
293 /************************ Packetized LongJmp Routines *************************/
295 * Must disable interrupts when setting the mode pointer
296 * register as an interrupt occurring mid update will
297 * fail to store the new mode value for restoration on
300 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
301 set_mode_work_around:
302 mvi SEQINTCTL, INTVEC1DSL;
303 mov MODE_PTR, SINDEX;
306 toggle_dff_mode_work_around:
307 mvi SEQINTCTL, INTVEC1DSL;
308 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
316 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
319 * Rev A hardware fails to update LAST/CURR/NEXTSCB
320 * correctly after a packetized selection in several
323 * 1) If only one command existed in the queue, the
324 * LAST/CURR/NEXTSCB are unchanged.
326 * 2) In a non QAS, protocol allowed phase change,
327 * the queue is shifted 1 too far. LASTSCB is
328 * the last SCB that was correctly processed.
330 * 3) In the QAS case, if the full list of commands
331 * was successfully sent, NEXTSCB is NULL and neither
332 * CURRSCB nor LASTSCB can be trusted. We must
333 * manually walk the list counting MAXCMDCNT elements
334 * to find the last SCB that was sent correctly.
336 * To simplify the workaround for this bug in SELDO
337 * handling, we initialize LASTSCB prior to enabling
338 * selection so we can rely on it even for case #1 above.
340 bmov LASTSCB, WAITING_TID_HEAD, 2;
342 bmov CURRSCB, WAITING_TID_HEAD, 2;
343 bmov SCBPTR, WAITING_TID_HEAD, 2;
344 shr SELOID, 4, SCB_SCSIID;
346 * If we want to send a message to the device, ensure
347 * we are selecting with atn irregardless of our packetized
348 * agreement. Since SPI4 only allows target reset or PPR
349 * messages if this is a packetized connection, the change
350 * to our negotiation table entry for this selection will
351 * be cleared when the message is acted on.
353 test SCB_CONTROL, MK_MESSAGE jz . + 3;
354 mov NEGOADDR, SELOID;
355 or NEGCONOPTS, ENAUTOATNO;
356 or SCSISEQ0, ENSELO ret;
360 * Allocate a FIFO for a non-packetized transaction.
361 * For some reason unkown to me, both FIFOs must be free before we
362 * can allocate a FIFO for a non-packetized transaction. This
363 * may be fixed in Rev B.
367 * Do whatever work is required to free a FIFO.
369 SET_MODE(M_DFF0, M_DFF0)
370 test LONGJMP_ADDR[1], INVALID_ADDR jnz . + 2;
372 SET_MODE(M_DFF1, M_DFF1)
373 test LONGJMP_ADDR[1], INVALID_ADDR jnz . + 2;
375 SET_MODE(M_SCSI, M_SCSI)
377 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
378 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
380 or DFFSTAT, CURRFIFO;
381 SET_MODE(M_DFF1, M_DFF1)
382 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
385 * We have been reselected as an initiator
386 * or selected as a target.
391 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
393 * This exposes a window whereby a
394 * busfree just after a selection will
395 * be missed, but there is not other safe
396 * way to enable busfree detection if
397 * the busfreerev function is broken.
399 mvi CLRSINT1,CLRBUSFREE;
400 or SIMODE1, ENBUSFREE;
403 and SAVED_SCSIID, SELID_MASK, SELID;
406 mvi CLRSINT0, CLRSELDI;
410 * We have successfully selected out.
413 * Dequeue all SCBs sent from the waiting queue
414 * Requeue all SCBs *not* sent to the tail of the waiting queue
415 * Take Razor #494 into account for above.
417 * In Packetized Mode:
418 * Return to the idle loop. Our interrupt handler will take
419 * care of any incoming L_Qs.
421 * In Non-Packetize Mode:
422 * Continue to our normal state machine.
428 /* Clear out all SCBs that have been successfully sent. */
429 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
431 * For packetized, the LQO manager clears ENSELO on
432 * the assertion of SELDO. If we are non-packetized,
433 * LASTSCB and CURRSCB are acuate.
435 test SCSISEQ0, ENSELO jnz use_lastscb;
438 * The update is correct for LQOSTAT1 errors. All
439 * but LQOBUSFREE are handled by kernel interrupts.
440 * If we see LQOBUSFREE, return to the idle loop.
441 * Once we are out of the select_out critical section,
442 * the kernel will cleanup the LQOBUSFREE and we will
443 * eventually restart the selection if appropriate.
445 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
448 * On a phase change oustside of packet boundaries,
449 * LASTSCB points to the currently active SCB context
452 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
455 * If the hardware has traversed the whole list, NEXTSCB
456 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
457 * but MAXCMDCNT is accurate. If we stop part way through
458 * the list or only had one command to issue, NEXTSCB[1] is
459 * not NULL and LASTSCB is the last command to go out.
461 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
466 bmov SCBPTR, WAITING_TID_HEAD, 2;
467 mvi SEQINTCTL, INTVEC1DSL;
468 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
470 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
474 test A, 0xFF jz found_last_sent_scb;
475 bmov SCBPTR, SCB_NEXT, 2;
476 jmp find_lastscb_loop;
478 bmov SCBPTR, LASTSCB, 2;
480 bmov CURRSCB, SCBPTR, 2;
484 * Untested - Verify with Rev B.
486 bmov SCBPTR, CURRSCB, 2;
489 * Requeue any SCBs not sent, to the tail of the waiting Q.
491 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
494 * We know that neither the per-TID list nor the list of
495 * TIDs is empty. Use this knowledge to our advantage.
497 bmov REG0, SCB_NEXT, 2;
498 bmov SCBPTR, WAITING_TID_TAIL, 2;
499 bmov SCB_NEXT2, REG0, 2;
500 bmov WAITING_TID_TAIL, REG0, 2;
501 jmp select_out_inc_tid_q;
503 select_out_list_done:
505 * The whole list made it. Just clear our TID's tail pointer
506 * unless we were queued independently due to our need to
509 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
510 shr DINDEX, 3, SCB_SCSIID;
511 or DINDEX, 1; /* Want only the second byte */
512 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
513 mvi DINDIR, SCB_LIST_NULL;
514 select_out_inc_tid_q:
515 bmov SCBPTR, WAITING_TID_HEAD, 2;
516 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
517 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
518 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
519 bmov SCBPTR, CURRSCB, 2;
522 mvi CLRSINT0, CLRSELDO;
524 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
525 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
528 * If this is a packetized connection, return to our
529 * idle_loop and let our interrupt handler deal with
530 * any connection setup/teardown issues. The only
531 * exception is the case of MK_MESSAGE SCBs. In the
532 * A, the LQO manager transitions to LQOSTOP0 even if
533 * we have selected out with ATN asserted and the target
534 * REQs in a non-packet phase.
536 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
537 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
538 test SCSISIGO, ATNO jnz select_out_non_packetized;
539 select_out_no_message:
541 test LQOSTAT2, LQOSTOP0 jnz idle_loop;
543 select_out_non_packetized:
544 /* Non packetized request. */
545 and SCSISEQ0, ~ENSELO;
546 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
548 * This exposes a window whereby a
549 * busfree just after a selection will
550 * be missed, but there is not other safe
551 * way to enable busfree detection if
552 * the busfreerev function is broken.
554 mvi CLRSINT1,CLRBUSFREE;
555 or SIMODE1, ENBUSFREE;
557 mov SAVED_SCSIID, SCB_SCSIID;
558 mov SAVED_LUN, SCB_LUN;
562 * As soon as we get a successful selection, the target
563 * should go into the message out phase since we have ATN
566 mvi MSG_OUT, MSG_IDENTIFYFLAG;
567 mvi SEQ_FLAGS, NO_CDB_SENT;
570 * Main loop for information transfer phases. Wait for the
571 * target to assert REQ before checking MSG, C/D and I/O for
580 test A, ~P_DATAIN_DT jz p_data;
581 cmp A,P_COMMAND je p_command;
582 cmp A,P_MESGOUT je p_mesgout;
583 cmp A,P_STATUS je p_status;
584 cmp A,P_MESGIN je p_mesgin;
586 mvi SEQINTCODE, BAD_PHASE;
587 jmp ITloop; /* Try reading the bus again. */
590 * Command phase. Set up the DMA registers and let 'er rip.
595 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
596 jnz p_command_allocate_fifo;
598 * Command retry. Free our current FIFO and
599 * re-allocate a FIFO so transfer state is
602 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
603 p_command_allocate_fifo:
604 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
606 add NONE, -17, SCB_CDB_LEN;
607 jnc p_command_embedded;
609 bmov HADDR[0], SCB_CDB_PTR, 11;
610 mvi SG_CACHE_PRE, LAST_SEG;
611 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
614 bmov SHCNT[0], SCB_CDB_LEN, 1;
615 bmov SHCNT[1], ALLZEROS, 2;
616 bmov DFDAT, SCB_CDB_STORE, 16;
619 test DFCNTRL, SCSIEN jnz p_command_loop;
621 * DMA Channel automatically disabled.
622 * Don't allow a data phase if the command
623 * was not fully transferred. Make sure that
624 * we clear the IDENTIFY SEEN flag if a retry
627 and SEQ_FLAGS, ~NO_CDB_SENT;
628 test SSTAT2, SDONE jnz ITloop;
629 or SEQ_FLAGS, NO_CDB_SENT;
634 * Status phase. Wait for the data byte to appear, then read it
635 * and store it into the SCB.
640 test SEQ_FLAGS,NOT_IDENTIFIED jz p_status_okay;
641 mvi SEQINTCODE, PROTO_VIOLATION;
644 mov SCB_SCSI_STATUS, SCSIDAT;
645 or SCB_CONTROL, STATUS_RCVD;
649 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
650 * indentify message sequence and send it to the target. The host may
651 * override this behavior by setting the MK_MESSAGE bit in the SCB
652 * control byte. This will cause us to interrupt the host and allow
653 * it to handle the message phase completely on its own. If the bit
654 * associated with this target is set, we will also interrupt the host,
655 * thereby allowing it to send a message on the next selection regardless
656 * of the transaction being sent.
658 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
659 * This is done to allow the host to send messages outside of an identify
660 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
661 * on an SCB that might not be for the current nexus. (For example, a
662 * BDR message in responce to a bad reselection would leave us pointed to
663 * an SCB that doesn't have anything to do with the current target).
665 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
668 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
669 * in case the target decides to put us in this phase for some strange
673 /* Turn on ATN for the retry */
677 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
678 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
680 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
681 test SCB_CONTROL, DISCENB jnz . + 2;
682 and SINDEX, ~DISCENB;
684 * Send a tag message if TAG_ENB is set in the SCB control block.
685 * Use SCB_NONPACKET_TAG as the tag value.
688 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
689 mov SCSIDAT, SINDEX; /* Send the identify message */
691 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
692 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
694 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
695 mov SCBPTR jmp p_mesgout_onebyte;
697 * Interrupt the driver, and allow it to handle this message
698 * phase and any required retries.
701 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
702 jmp host_message_loop;
705 mvi CLRSINT1, CLRATNO;
709 * If the next bus phase after ATN drops is message out, it means
710 * that the target is requesting that the last message(s) be resent.
713 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
716 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
717 mov LAST_MSG, MSG_OUT;
718 mvi MSG_OUT, MSG_NOOP; /* No message left */
722 * Message in phase. Bytes are read using Automatic PIO mode.
725 /* read the 1st message byte */
726 mvi ACCUM call inb_first;
728 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
729 cmp A,MSG_DISCONNECT je mesgin_disconnect;
730 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
731 cmp ALLZEROS,A je mesgin_complete;
732 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
733 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
734 cmp A,MSG_NOOP je mesgin_done;
737 * Pushed message loop to allow the kernel to
738 * run it's own message state engine. To avoid an
739 * extra nop instruction after signaling the kernel,
740 * we perform the phase_lock before checking to see
741 * if we should exit the loop and skip the phase_lock
742 * in the ITloop. Performing back to back phase_locks
743 * shouldn't hurt, but why do it twice...
746 call phase_lock; /* Benign the first time through. */
747 mvi SEQINTCODE, HOST_MSG_LOOP;
748 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
749 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
750 mov SCSIDAT, RETURN_2;
751 jmp host_message_loop;
752 /* Must be CONT_MSG_LOOP_READ */
753 mov NONE, SCSIDAT; /* ACK Byte */
754 jmp host_message_loop;
756 mesgin_ign_wide_residue:
757 shr NEGOADDR, 4, SAVED_SCSIID;
758 test NEGCONOPTS, WIDEXFER jz mesgin_reject;
759 /* Pull the residue byte */
760 mvi REG0 call inb_next;
761 cmp REG0, 0x01 jne mesgin_reject;
762 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
763 test DATA_COUNT_ODD, 0x1 jz mesgin_done;
764 mvi SEQINTCODE, IGN_WIDE_RES;
768 mvi MSG_MESSAGE_REJECT call mk_mesg;
770 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
773 #define INDEX_DISC_LIST(scsiid, lun) \
774 and A, 0xC0, scsiid; \
777 and SINDEX, 0x30, scsiid; \
778 shr SINDEX, 3; /* Multiply by 2 */ \
779 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
780 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
784 * Determine whether a target is using tagged or non-tagged
785 * transactions by first looking at the transaction stored in
786 * the per-device, disconnected array. If there is no untagged
787 * transaction for this target, this must be a tagged transaction.
789 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
790 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
791 bmov DINDEX, SINDEX, 2;
792 bmov REG0, SINDIR, 2;
793 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
794 /* Untagged. Clear the busy table entry and setup the SCB. */
795 bmov DINDIR, ALLONES, 2;
796 bmov SCBPTR, REG0, 2;
800 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
801 * If we get one, we use the tag returned to find the proper
802 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
806 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
809 mov NONE, SCSIDAT; /* ACK Identify MSG */
811 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
814 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
815 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
818 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
821 mvi SCBPTR call inb_next; /* tag value */
823 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
825 cmp SCB_SCSIID, A jne verify_other_scb;
827 cmp SCB_LUN, A je setup_SCB_disconnected;
830 test SCBPTR[1], 0xFF jnz verify_scb;
834 * Ensure that the SCB the tag points to is for
835 * an SCB transaction to the reconnecting target.
838 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
841 test SCB_CONTROL,DISCONNECTED jz not_found;
842 setup_SCB_disconnected:
843 and SCB_CONTROL,~DISCONNECTED;
844 clr SEQ_FLAGS; /* make note of IDENTIFY */
845 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
846 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
848 /* See if the host wants to send a message upon reconnection */
849 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
850 mvi HOST_MSG call mk_mesg;
854 mvi SEQINTCODE, NO_MATCH;
858 mvi SEQINTCODE, NO_MATCH;
862 * We received a "command complete" message. Put the SCB on the complete
863 * queue and trigger a completion interrupt via the idle loop. Before doing
864 * so, check to see if there
865 * is a residual or the status byte is something other than STATUS_GOOD (0).
866 * In either of these conditions, we upload the SCB back to the host so it can
867 * process this information. In the case of a non zero status byte, we
868 * additionally interrupt the kernel driver synchronously, allowing it to
869 * decide if sense should be retrieved. If the kernel driver wishes to request
870 * sense, it will fill the kernel SCB with a request sense command, requeue
871 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
872 * RETURN_1 to SEND_SENSE.
874 mesgin_complete_proto_violation:
875 mvi SEQINTCODE, PROTO_VIOLATION;
880 * If ATN is raised, we still want to give the target a message.
881 * Perhaps there was a parity error on this last message byte.
882 * Either way, the target should take us to message out phase
883 * and then attempt to complete the command again. We should use a
884 * critical section here to guard against a timeout triggering
885 * for this command and setting ATN while we are still processing
887 test SCSISIGI, ATNI jnz mesgin_done;
891 * If we are identified and have successfully sent the CDB,
892 * any status will do. Optimize this fast path.
894 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jnz . + 2;
895 test SCB_CONTROL, STATUS_RCVD jnz complete_accepted;
898 * If the target never sent an identify message but instead went
899 * to mesgin to give an invalid message, let the host abort us.
901 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_complete_proto_violation;
904 * If the target never gave us status information, have
905 * the host abort the command.
907 test SCB_CONTROL, STATUS_RCVD jz mesgin_complete_proto_violation;
910 * If we recevied good status but never successfully sent the
911 * cdb, abort the command.
913 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
914 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_complete_proto_violation;
918 * See if we attempted to deliver a message but the target ingnored us.
920 test SCB_CONTROL, MK_MESSAGE jz . + 2;
921 mvi SEQINTCODE, MKMSG_FAILED;
922 call queue_scb_completion;
926 /* Cancel any pending select-out. */
927 test SSTAT0, SELDO jnz . + 2;
928 and SCSISEQ0, ~ENSELO;
931 add QFREEZE_COUNT, 1;
932 adc QFREEZE_COUNT[1], A;
933 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
934 mov A, ACCUM_SAVE ret;
936 queue_arg1_scb_completion:
937 SET_MODE(M_SCSI, M_SCSI)
938 bmov SCBPTR, ARG_1, 2;
939 queue_scb_completion:
940 test SCB_SCSI_STATUS,0xff jnz bad_status;
942 * Check for residuals
944 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
945 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
946 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
948 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
949 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
951 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
954 bmov SCB_NEXT_COMPLETE, COMPLETE_DMA_SCB_HEAD, 2;
955 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
956 or SCB_SGPTR, SG_STATUS_VALID ret;
959 * Is it a disconnect message? Set a flag in the SCB to remind us
960 * and await the bus going free. If this is an untagged transaction
961 * store the SCB id for it in our untagged target table for lookup on
966 * If ATN is raised, we still want to give the target a message.
967 * Perhaps there was a parity error on this last message byte
968 * or we want to abort this command. Either way, the target
969 * should take us to message out phase and then attempt to
971 * XXX - Wait for more testing.
972 test SCSISIGI, ATNI jnz mesgin_done;
974 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz disconnect_allowed;
975 mvi SEQINTCODE, PROTO_VIOLATION;
978 or SCB_CONTROL,DISCONNECTED;
979 test SCB_CONTROL, TAG_ENB jnz await_busfree;
981 bmov REG0, SCBPTR, 2;
982 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
983 bmov DINDEX, SINDEX, 2;
984 bmov DINDIR, REG0, 2;
985 bmov SCBPTR, REG0, 2;
988 and SIMODE1, ~ENBUSFREE;
989 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
991 * In the BUSFREEREV_BUG case, the
992 * busfree status was cleared at the
993 * beginning of the connection.
995 mvi CLRSINT1,CLRBUSFREE;
997 mov NONE, SCSIDAT; /* Ack the last byte */
998 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
999 jnz await_busfree_not_m_dff;
1000 SET_SRC_MODE M_DFF1;
1001 SET_DST_MODE M_DFF1;
1002 await_busfree_clrchn:
1003 mvi DFFSXFRCTL, CLRCHN;
1004 await_busfree_not_m_dff:
1005 call clear_target_state;
1006 test SSTAT1,REQINIT|BUSFREE jz .;
1007 test SSTAT1, BUSFREE jnz idle_loop;
1008 mvi SEQINTCODE, MISSED_BUSFREE;
1012 * Save data pointers message:
1013 * Copying RAM values back to SCB, for Save Data Pointers message, but
1014 * only if we've actually been into a data phase to change them. This
1015 * protects against bogus data in scratch ram and the residual counts
1016 * since they are only initialized when we go into data_in or data_out.
1017 * Ack the message as soon as possible.
1019 SET_SRC_MODE M_DFF1;
1020 SET_DST_MODE M_DFF1;
1022 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1023 test SEQ_FLAGS, DPHASE jz ITloop;
1029 * If we are asked to save our position at the end of the
1030 * transfer, just mark us at the end rather than perform a
1033 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1034 or SCB_SGPTR, SG_LIST_NULL ret;
1038 * The SCB_DATAPTR becomes the current SHADDR.
1039 * All other information comes directly from our residual
1042 bmov SCB_DATAPTR, SHADDR, 8;
1043 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1046 * Restore pointers message? Data pointers are recopied from the
1047 * SCB anytime we enter a data phase for the first time, so all
1048 * we need to do is clear the DPHASE flag and let the data phase
1049 * code do the rest. We also reset/reallocate the FIFO to make
1050 * sure we have a clean start for the next data phase.
1053 and SEQ_FLAGS, ~DPHASE;
1054 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1055 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1056 msgin_rdptrs_get_fifo:
1061 mvi LASTPHASE, P_BUSFREE;
1062 /* clear target specific flags */
1063 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
1066 test SCSIPHASE, 0xFF jz .;
1067 phase_lock_latch_phase:
1068 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1071 * Functions to read data in Automatic PIO mode.
1073 * An ACK is not sent on input from the target until SCSIDATL is read from.
1074 * So we wait until SCSIDATL is latched (the usual way), then read the data
1075 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1076 * line, or we just want to acknowledge the byte, then we do a dummy read
1077 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1078 * data byte on the bus until we send our ACK.
1080 * The assumption here is that these are called in a particular sequence,
1081 * and that REQ is already set when inb_first is called. inb_{first,next}
1082 * use the same calling convention as inb.
1085 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1088 * If there is a parity error, wait for the kernel to
1089 * see the interrupt and prepare our message response
1090 * before continuing.
1092 test SCSIPHASE, 0xFF jz .;
1093 inb_next_check_phase:
1094 and LASTPHASE, PHASE_MASK, SCSISIGI;
1095 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1099 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1101 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1105 mov MSG_OUT,SINDEX ret;
1107 SET_SRC_MODE M_DFF1;
1108 SET_DST_MODE M_DFF1;
1110 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1112 disable_ccsgen_fetch_done:
1115 data_group_idle_loop:
1116 mov SAVED_MODE, MODE_PTR;
1117 test SG_STATE, LOADING_NEEDED jz . + 2;
1120 test SG_STATE, LOADING_NEEDED jz . + 2;
1122 call idle_loop_cchan;
1123 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1124 mov SAVED_MODE jmp set_mode_work_around;
1126 mov MODE_PTR, SAVED_MODE ret;
1131 * Do we have any prefetch left???
1133 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1136 * Can this FIFO have access to the S/G cache yet?
1138 test CCSGCTL, SG_CACHE_AVAIL jz return;
1140 /* Did we just finish fetching segs? */
1141 cmp CCSGCTL, CCSGEN|SG_CACHE_AVAIL|CCSGDONE
1142 je idle_sgfetch_complete;
1144 /* Are we actively fetching segments? */
1145 test CCSGCTL, CCSGEN jnz return;
1148 * We fetch a "cacheline aligned" and sized amount of data
1149 * so we don't end up referencing a non-existant page.
1150 * Cacheline aligned is in quotes because the kernel will
1151 * set the prefetch amount to a reasonable level if the
1152 * cacheline size is unknown.
1154 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1155 mvi SGHCNT, SG_PREFETCH_CNT;
1156 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1158 * Need two instruction between "touches" of SGHADDR.
1159 * Note the setting of SGHCNT counts as one of
1160 * these two instructions.
1164 bmov SGHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
1165 mvi CCSGCTL, CCSGEN|SG_CACHE_AVAIL|CCSGRESET;
1166 or SG_STATE, FETCH_INPROG ret;
1167 idle_sgfetch_complete:
1169 * Guard against SG_CACHE_AVAIL activating during sg fetch
1170 * request in the other FIFO.
1172 test SG_STATE, FETCH_INPROG jz return;
1174 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1175 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1177 /* Does the hardware have space for another SG entry? */
1178 test DFSTATUS, PRELOAD_AVAIL jz return;
1179 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1180 bmov HADDR, CCSGRAM, 8;
1182 bmov HADDR, CCSGRAM, 4;
1184 bmov HCNT, CCSGRAM, 3;
1185 test HCNT[0], 0x1 jz . + 2;
1186 xor DATA_COUNT_ODD, 0x1;
1187 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1188 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1189 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1191 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1192 /* Skip 4 bytes of pad. */
1196 clr A; /* add sizeof(struct scatter) */
1197 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1198 adc SCB_RESIDUAL_SGPTR[1],A;
1199 adc SCB_RESIDUAL_SGPTR[2],A;
1200 adc SCB_RESIDUAL_SGPTR[3],A;
1201 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1202 test DATA_COUNT_ODD, 0x1 jz . + 2;
1204 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1205 or SINDEX, LAST_SEG;
1207 mov SG_CACHE_PRE, SINDEX;
1209 * Load the segment. Or in HDMAEN here too
1210 * just in case HDMAENACK has not come true
1211 * by the time this segment is loaded. If
1212 * HDMAENACK is not true, this or will disable
1213 * HDMAEN mid-transfer. We do not want to simply
1214 * mvi our original settings as SCSIEN automatically
1215 * de-asserts and we don't want to accidentally
1218 or DFCNTRL, PRELOADEN|HDMAEN;
1220 * Do we have another segment in the cache?
1222 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1224 and SG_STATE, ~SEGS_AVAIL ret;
1227 * Initialize the DMA address and counter from the SCB.
1230 bmov HADDR, SCB_DATAPTR, 11;
1231 and DATA_COUNT_ODD, 0x1, SCB_DATACNT[0];
1232 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1233 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1234 or REG_ISR, LAST_SEG;
1235 test DATA_COUNT_ODD, 0x1 jz . + 2;
1236 or REG_ISR, ODD_SEG;
1237 mov SG_CACHE_PRE, REG_ISR;
1238 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1240 * Since we've are entering a data phase, we will
1241 * rely on the SCB_RESID* fields. Initialize the
1242 * residual and clear the full residual flag.
1244 and SCB_SGPTR[0], ~SG_FULL_RESID;
1245 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1246 /* If we need more S/G elements, tell the idle loop */
1247 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1248 mvi SG_STATE, LOADING_NEEDED ret;
1252 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1253 mvi SEQINTCODE, PROTO_VIOLATION;
1256 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1259 * If we re-enter the data phase after going through another
1260 * phase, our transfer location has almost certainly been
1261 * corrupted by the interveining, non-data, transfers. Ask
1262 * the host driver to fix us up based on the transfer residual
1263 * unless we already know that we should be bitbucketing.
1265 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1266 mvi SEQINTCODE, PDATA_REINIT;
1267 jmp data_group_dma_loop;
1271 * Turn on `Bit Bucket' mode, wait until the target takes
1272 * us to another phase, and then notify the host.
1274 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1275 jnz bitbucket_not_m_dff;
1277 * Ensure that any FIFO contents are cleared out and the
1278 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1279 * doesn't discard data already in the FIFO.
1281 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1282 SET_MODE(M_SCSI, M_SCSI)
1283 bitbucket_not_m_dff:
1284 or SXFRCTL1,BITBUCKET;
1285 /* Wait for non-data phase. */
1286 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1287 and SXFRCTL1, ~BITBUCKET;
1288 SET_MODE(M_DFF1, M_DFF1)
1289 mvi SEQINTCODE, DATA_OVERRUN;
1292 data_phase_initialize:
1293 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1294 call load_first_seg;
1295 data_phase_inbounds:
1296 /* We have seen a data phase at least once. */
1297 or SEQ_FLAGS, DPHASE;
1298 data_group_dma_loop:
1300 * The transfer is complete if either the last segment
1301 * completes or the target changes phase. Both conditions
1302 * will clear SCSIEN.
1304 call data_group_idle_loop;
1305 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1307 data_group_dmafinish:
1309 * The transfer has terminated either due to a phase
1310 * change, and/or the completion of the last segment.
1311 * We have two goals here. Do as much other work
1312 * as possible while the data fifo drains on a read
1313 * and respond as quickly as possible to the standard
1314 * messages (save data pointers/disconnect and command
1315 * complete) that usually follow a data phase.
1320 * Go ahead and shut down the DMA engine now.
1322 test DFCNTRL, DIRECTION jnz data_phase_finish;
1323 data_group_fifoflush:
1324 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1325 or DFCNTRL, FIFOFLUSH;
1328 * We have enabled the auto-ack feature. This means
1329 * that the controller may have already transferred
1330 * some overrun bytes into the data FIFO and acked them
1331 * on the bus. The only way to detect this situation is
1332 * to wait for LAST_SEG_DONE to come true on a completed
1333 * transfer and then test to see if the data FIFO is
1334 * non-empty. We know there is more data yet to transfer
1335 * if SG_LIST_NULL is not yet set, thus there cannot be
1338 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1339 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1340 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1345 * If the target has left us in data phase, loop through
1346 * the dma code again. We will only loop if there is a
1349 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1350 test SSTAT0, TARGET jnz data_phase_done;
1352 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1353 test SSTAT1, REQINIT jz .;
1354 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1358 /* Kill off any pending prefetch */
1359 call disable_ccsgen;
1361 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1362 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1364 and SEQ_FLAGS, ~DPHASE_PENDING;
1365 * For data-in phases, wait for any pending acks from the
1366 * initiator before changing phase. We only need to
1367 * send Ignore Wide Residue messages for data-in phases.
1368 test DFCNTRL, DIRECTION jz target_ITloop;
1369 test SSTAT1, REQINIT jnz .;
1370 test DATA_COUNT_ODD, 0x1 jz target_ITloop;
1371 SET_MODE(M_SCSI, M_SCSI)
1372 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1375 * Issue an Ignore Wide Residue Message.
1376 mvi P_MESGIN|BSYO call change_phase;
1377 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1378 mvi 1 call target_outb;
1386 * We assume that, even though data may still be
1387 * transferring to the host, that the SCSI side of
1388 * the DMA engine is now in a static state. This
1389 * allows us to update our notion of where we are
1392 * If, by chance, we stopped before being able
1393 * to fetch additional segments for this transfer,
1394 * yet the last S/G was completely exhausted,
1395 * call our idle loop until it is able to load
1396 * another segment. This will allow us to immediately
1397 * pickup on the next segment on the next data phase.
1399 * If we happened to stop on the last segment, then
1400 * our residual information is still correct from
1401 * the idle loop and there is no need to perform
1405 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1406 /* Record if we've consumed all S/G entries */
1407 test MDFFSTAT, SHVALID jz . + 2;
1408 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1409 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1410 residual_before_last_seg:
1411 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1413 * Can never happen from an interrupt as the packetized
1414 * hardware will only interrupt us once SHVALID or
1417 call data_group_idle_loop;
1422 * Fixup the residual next S/G pointer. The S/G preload
1423 * feature of the chip allows us to load two elements
1424 * in addition to the currently active element. We
1425 * store the bottom byte of the next S/G pointer in
1426 * the SG_CACHE_PTR register so we can restore the
1427 * correct value when the DMA completes. If the next
1428 * sg ptr value has advanced to the point where higher
1429 * bytes in the address have been affected, fix them
1432 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1433 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1434 add SCB_RESIDUAL_SGPTR[1], -1;
1435 adc SCB_RESIDUAL_SGPTR[2], -1;
1436 adc SCB_RESIDUAL_SGPTR[3], -1;
1438 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1440 test SG_CACHE_SHADOW, ODD_SEG jz . + 2;
1441 or DATA_COUNT_ODD, 0x1;
1442 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1443 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1446 nop; /* Jumps in the first ISR instruction fail on Rev A. */
1447 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1448 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1449 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1450 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1451 mvi SEQINTCODE, INVALID_SEQINT;
1454 * There are two types of save pointers interrupts:
1455 * The first is a snapshot save pointers where the current FIFO is not
1456 * active and contains a snapshot of the current poniter information.
1457 * This happens between packets in a stream for a single L_Q. Since we
1458 * are not performing a pointer save, we can safely clear the channel
1459 * so it can be used for other transactions.
1461 * The second case is a save pointers on an active FIFO which occurs
1462 * if the target changes to a new L_Q or busfrees/QAS' and the transfer
1463 * has a residual. This should occur coincident with a ctxtdone. We
1464 * disable the interrupt and allow our active routine to handle the
1468 test DFCNTRL, HDMAENACK jz snapshot_saveptr;
1469 and SEQIMODE, ~ENSAVEPTRS;
1470 or SEQINTCTL, IRET ret;
1472 mvi DFFSXFRCTL, CLRCHN;
1473 or SEQINTCTL, IRET ret;
1476 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun;
1477 call load_first_seg;
1478 call pkt_handle_xfer;
1479 or SEQINTCTL, IRET ret;
1483 add NONE, -13, SCB_CDB_LEN;
1484 jnc cfg4istat_have_sense_addr;
1485 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1487 * Host sets up address/count and enables transfer.
1489 mvi SEQINTCODE, CFG4ISTAT_INTR;
1490 jmp cfg4istat_setup_handler;
1491 cfg4istat_have_sense_addr:
1492 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1493 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1494 mvi SG_CACHE_PRE, LAST_SEG;
1495 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1496 cfg4istat_setup_handler:
1498 * Status pkt is transferring to host.
1499 * Wait in idle loop for transfer to complete.
1501 call pkt_handle_status;
1502 or SEQINTCTL, IRET ret;
1505 * See if the target has gone on in this context creating an
1506 * overrun condition. For the write case, the hardware cannot
1507 * ack bytes until data are provided. So, if the target begins
1508 * another packet without changing contexts, implying we are
1509 * not sitting on a packet boundary, we are in an overrun
1510 * situation. For the read case, the hardware will continue to
1511 * ack bytes into the FIFO, and may even ack the last overrun packet
1512 * into the FIFO. If the FIFO should become non-empty, we are in
1513 * a read overrun case.
1515 #define check_overrun \
1516 /* Not on a packet boundary. */ \
1517 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1518 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1521 bmov LONGJMP_SCB, SCBPTR, 2;
1522 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1524 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1525 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1526 test SCSISIGO, ATNO jnz . + 2;
1527 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1529 * Defer handling of this NONPACKREQ until we
1530 * can be sure it pertains to this FIFO. SAVEPTRS
1531 * will not be asserted if the NONPACKREQ is for us,
1532 * so we must simulate it if shaddow is valid. If
1533 * shaddow is not valid, keep running this FIFO until we
1534 * have satisfied the transfer by loading segments and
1535 * waiting for either shaddow valid or last_seg_done.
1537 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1539 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1542 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1543 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz last_pkt_done;
1544 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1545 test SCSISIGO, ATNO jnz . + 2;
1546 test SSTAT2, NONPACKREQ jz return;
1547 test MDFFSTAT, SHVALID jz return;
1551 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1552 * or we have a pending nonpackreq for this FIFO. We differentiate
1553 * between the two by capturing the state of the SAVEPTRS interrupt
1554 * prior to clearing this status and executing the common code for
1559 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1560 or DFCNTRL, FIFOFLUSH;
1562 mov REG0, SEQINTSRC;
1565 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1566 call disable_ccsgen;
1567 or SEQIMODE, ENSAVEPTRS;
1568 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1569 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1571 * Keep a handler around for this FIFO until it drains
1572 * to the host to guarantee that we don't complete the
1573 * command to the host before the data arrives.
1575 pkt_saveptrs_wait_fifoemp:
1577 test DFSTATUS, FIFOEMP jz return;
1578 pkt_saveptrs_check_status:
1579 or LONGJMP_ADDR[1], INVALID_ADDR;
1580 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1581 test SCB_CONTROL, STATUS_RCVD jz pkt_saveptrs_clrchn;
1582 jmp last_pkt_complete;
1583 pkt_saveptrs_clrchn:
1584 mvi DFFSXFRCTL, CLRCHN ret;
1589 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1590 or DFCNTRL, FIFOFLUSH;
1592 test SCB_CONTROL, STATUS_RCVD jz wait_pkt_end;
1594 or SCB_SGPTR, SG_LIST_NULL;
1596 * It is safe to skip the other FIFO check since
1597 * we defer CLRCHN on SAVEPTRS until all data in
1598 * the FIFO are seen by the host and a CFG4DATA
1599 * in this FIFO for the same context is held off
1603 or LONGJMP_ADDR[1], INVALID_ADDR;
1604 bmov ARG_1, SCBPTR, 2;
1605 mvi DFFSXFRCTL, CLRCHN;
1606 jmp queue_arg1_scb_completion;
1609 bmov ARG_1, SCBPTR, 2;
1610 mvi DFFSXFRCTL, CLRCHN;
1615 jnc queue_arg1_scb_completion;
1623 test SEQINTSRC, CTXTDONE jnz pkt_end;
1625 test SSTAT2, NONPACKREQ jz return;
1626 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1630 or LONGJMP_ADDR[1], INVALID_ADDR;
1631 or SCB_SGPTR, SG_LIST_NULL;
1632 test SCB_CONTROL, STATUS_RCVD jnz last_pkt_complete;
1633 mvi DFFSXFRCTL, CLRCHN ret;
1636 check_status_overrun:
1637 test SHCNT[2], 0xFF jz status_IU_done;
1638 mvi SEQINTCODE, STATUS_OVERRUN;
1642 test MDFFSTAT, LASTSDONE jnz check_status_overrun;
1643 test SEQINTSRC, CTXTDONE jz return;
1646 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1647 or DFCNTRL, FIFOFLUSH;
1649 or LONGJMP_ADDR[1], INVALID_ADDR;
1650 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
1651 or SCB_CONTROL, STATUS_RCVD;
1652 jmp last_pkt_complete;
1655 SET_SRC_MODE M_DFF0;
1656 SET_DST_MODE M_DFF0;
1659 test LONGJMP_ADDR[1], INVALID_ADDR jnz return;
1661 cmp LONGJMP_SCB[1], A jne return;
1663 cmp LONGJMP_SCB[0], A jne return;
1668 * Nonpackreq is a polled status. It can come true in three situations:
1669 * we have received an L_Q, we have sent one or more L_Qs, or there is no
1670 * L_Q context associated with this REQ (REQ occurs immediately after a
1671 * (re)selection). Routines that know that the context responsible for this
1672 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
1673 * top level idle loop, we exhaust all active contexts prior to determining that
1674 * we simply do not have the full I_T_L_Q for this phase.
1676 unexpected_nonpkt_phase_find_ctxt:
1678 * This nonpackreq is most likely associated with one of the tags
1679 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
1680 * nonpackreq if we've cleared out the FIFOs and handled any
1683 SET_SRC_MODE M_SCSI;
1684 SET_DST_MODE M_SCSI;
1685 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
1686 cmp A, FIFO1FREE|FIFO0FREE jne return;
1687 test SSTAT0, SELDO jnz return;
1688 mvi SCBPTR[1], SCB_LIST_NULL;
1689 unexpected_nonpkt_phase:
1690 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz . + 3;
1691 SET_SRC_MODE M_DFF0;
1692 SET_DST_MODE M_DFF0;
1693 or LONGJMP_ADDR[1], INVALID_ADDR;
1694 mvi DFFSXFRCTL, CLRCHN;
1695 mvi CLRSINT2, CLRNONPACKREQ;
1696 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
1697 mvi SEQINTCODE, ENTERING_NONPACK;
1701 mvi SEQINTCODE, ILLEGAL_PHASE;
1705 * We have entered an overrun situation. If we have working
1706 * BITBUCKET, flip that on and let the hardware eat any overrun
1707 * data. Otherwise use an overrun buffer in the host to simulate
1711 mvi SEQINTCODE, CFG4OVERRUN;
1713 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
1714 SET_MODE(M_SCSI, M_SCSI)
1715 or SXFRCTL1,BITBUCKET;
1716 SET_SRC_MODE M_DFF1;
1717 SET_DST_MODE M_DFF1;
1719 call load_overrun_buf;
1720 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
1723 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1724 test DFSTATUS, PKT_PRELOAD_AVAIL jz overrun_load_done;
1725 call load_overrun_buf;
1726 or DFCNTRL, PRELOADEN;
1729 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
1730 test SSTAT2, NONPACKREQ jz return;
1732 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
1733 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1734 test SCB_CONTROL, STATUS_RCVD jnz last_pkt_queue_scb;
1735 mvi DFFSXFRCTL, CLRCHN ret;
1737 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
1740 * Load a dummy segment if preload space is available.
1742 mov HADDR[0], SHARED_DATA_ADDR;
1743 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
1746 adc HADDR[2], A, SHARED_DATA_ADDR[2];
1747 adc HADDR[3], A, SHARED_DATA_ADDR[3];
1749 bmov HADDR[4], ALLZEROS, 4;
1750 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
1752 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);