2 * DO NOT EDIT - This file is automatically generated
3 * from the following source files:
5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $
10 typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
11 typedef struct ahd_reg_parse_entry {
15 } ahd_reg_parse_entry_t;
17 #if AIC_DEBUG_REGISTERS
18 ahd_reg_print_t ahd_mode_ptr_print;
20 #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \
21 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap)
24 #if AIC_DEBUG_REGISTERS
25 ahd_reg_print_t ahd_intstat_print;
27 #define ahd_intstat_print(regvalue, cur_col, wrap) \
28 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
31 #if AIC_DEBUG_REGISTERS
32 ahd_reg_print_t ahd_seqintcode_print;
34 #define ahd_seqintcode_print(regvalue, cur_col, wrap) \
35 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap)
38 #if AIC_DEBUG_REGISTERS
39 ahd_reg_print_t ahd_clrint_print;
41 #define ahd_clrint_print(regvalue, cur_col, wrap) \
42 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
45 #if AIC_DEBUG_REGISTERS
46 ahd_reg_print_t ahd_error_print;
48 #define ahd_error_print(regvalue, cur_col, wrap) \
49 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap)
52 #if AIC_DEBUG_REGISTERS
53 ahd_reg_print_t ahd_clrerr_print;
55 #define ahd_clrerr_print(regvalue, cur_col, wrap) \
56 ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
59 #if AIC_DEBUG_REGISTERS
60 ahd_reg_print_t ahd_hcntrl_print;
62 #define ahd_hcntrl_print(regvalue, cur_col, wrap) \
63 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
66 #if AIC_DEBUG_REGISTERS
67 ahd_reg_print_t ahd_hnscb_qoff_print;
69 #define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
70 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
73 #if AIC_DEBUG_REGISTERS
74 ahd_reg_print_t ahd_hescb_qoff_print;
76 #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
77 ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap)
80 #if AIC_DEBUG_REGISTERS
81 ahd_reg_print_t ahd_hs_mailbox_print;
83 #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
84 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
87 #if AIC_DEBUG_REGISTERS
88 ahd_reg_print_t ahd_seqintstat_print;
90 #define ahd_seqintstat_print(regvalue, cur_col, wrap) \
91 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
94 #if AIC_DEBUG_REGISTERS
95 ahd_reg_print_t ahd_clrseqintstat_print;
97 #define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \
98 ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
101 #if AIC_DEBUG_REGISTERS
102 ahd_reg_print_t ahd_swtimer_print;
104 #define ahd_swtimer_print(regvalue, cur_col, wrap) \
105 ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap)
108 #if AIC_DEBUG_REGISTERS
109 ahd_reg_print_t ahd_snscb_qoff_print;
111 #define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
112 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
115 #if AIC_DEBUG_REGISTERS
116 ahd_reg_print_t ahd_sescb_qoff_print;
118 #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
119 ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap)
122 #if AIC_DEBUG_REGISTERS
123 ahd_reg_print_t ahd_sdscb_qoff_print;
125 #define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
126 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
129 #if AIC_DEBUG_REGISTERS
130 ahd_reg_print_t ahd_qoff_ctlsta_print;
132 #define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
133 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
136 #if AIC_DEBUG_REGISTERS
137 ahd_reg_print_t ahd_intctl_print;
139 #define ahd_intctl_print(regvalue, cur_col, wrap) \
140 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
143 #if AIC_DEBUG_REGISTERS
144 ahd_reg_print_t ahd_dfcntrl_print;
146 #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
147 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
150 #if AIC_DEBUG_REGISTERS
151 ahd_reg_print_t ahd_dscommand0_print;
153 #define ahd_dscommand0_print(regvalue, cur_col, wrap) \
154 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
157 #if AIC_DEBUG_REGISTERS
158 ahd_reg_print_t ahd_dfstatus_print;
160 #define ahd_dfstatus_print(regvalue, cur_col, wrap) \
161 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
164 #if AIC_DEBUG_REGISTERS
165 ahd_reg_print_t ahd_sg_cache_shadow_print;
167 #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
168 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
171 #if AIC_DEBUG_REGISTERS
172 ahd_reg_print_t ahd_sg_cache_pre_print;
174 #define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
175 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
178 #if AIC_DEBUG_REGISTERS
179 ahd_reg_print_t ahd_arbctl_print;
181 #define ahd_arbctl_print(regvalue, cur_col, wrap) \
182 ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
185 #if AIC_DEBUG_REGISTERS
186 ahd_reg_print_t ahd_lqin_print;
188 #define ahd_lqin_print(regvalue, cur_col, wrap) \
189 ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap)
192 #if AIC_DEBUG_REGISTERS
193 ahd_reg_print_t ahd_typeptr_print;
195 #define ahd_typeptr_print(regvalue, cur_col, wrap) \
196 ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
199 #if AIC_DEBUG_REGISTERS
200 ahd_reg_print_t ahd_tagptr_print;
202 #define ahd_tagptr_print(regvalue, cur_col, wrap) \
203 ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
206 #if AIC_DEBUG_REGISTERS
207 ahd_reg_print_t ahd_lunptr_print;
209 #define ahd_lunptr_print(regvalue, cur_col, wrap) \
210 ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap)
213 #if AIC_DEBUG_REGISTERS
214 ahd_reg_print_t ahd_datalenptr_print;
216 #define ahd_datalenptr_print(regvalue, cur_col, wrap) \
217 ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
220 #if AIC_DEBUG_REGISTERS
221 ahd_reg_print_t ahd_statlenptr_print;
223 #define ahd_statlenptr_print(regvalue, cur_col, wrap) \
224 ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
227 #if AIC_DEBUG_REGISTERS
228 ahd_reg_print_t ahd_cmdlenptr_print;
230 #define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
231 ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap)
234 #if AIC_DEBUG_REGISTERS
235 ahd_reg_print_t ahd_attrptr_print;
237 #define ahd_attrptr_print(regvalue, cur_col, wrap) \
238 ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap)
241 #if AIC_DEBUG_REGISTERS
242 ahd_reg_print_t ahd_flagptr_print;
244 #define ahd_flagptr_print(regvalue, cur_col, wrap) \
245 ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap)
248 #if AIC_DEBUG_REGISTERS
249 ahd_reg_print_t ahd_cmdptr_print;
251 #define ahd_cmdptr_print(regvalue, cur_col, wrap) \
252 ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap)
255 #if AIC_DEBUG_REGISTERS
256 ahd_reg_print_t ahd_qnextptr_print;
258 #define ahd_qnextptr_print(regvalue, cur_col, wrap) \
259 ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap)
262 #if AIC_DEBUG_REGISTERS
263 ahd_reg_print_t ahd_idptr_print;
265 #define ahd_idptr_print(regvalue, cur_col, wrap) \
266 ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
269 #if AIC_DEBUG_REGISTERS
270 ahd_reg_print_t ahd_abrtbyteptr_print;
272 #define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
273 ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap)
276 #if AIC_DEBUG_REGISTERS
277 ahd_reg_print_t ahd_abrtbitptr_print;
279 #define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \
280 ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap)
283 #if AIC_DEBUG_REGISTERS
284 ahd_reg_print_t ahd_maxcmdbytes_print;
286 #define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
287 ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
290 #if AIC_DEBUG_REGISTERS
291 ahd_reg_print_t ahd_maxcmd2rcv_print;
293 #define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
294 ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
297 #if AIC_DEBUG_REGISTERS
298 ahd_reg_print_t ahd_shortthresh_print;
300 #define ahd_shortthresh_print(regvalue, cur_col, wrap) \
301 ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
304 #if AIC_DEBUG_REGISTERS
305 ahd_reg_print_t ahd_lunlen_print;
307 #define ahd_lunlen_print(regvalue, cur_col, wrap) \
308 ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap)
311 #if AIC_DEBUG_REGISTERS
312 ahd_reg_print_t ahd_cdblimit_print;
314 #define ahd_cdblimit_print(regvalue, cur_col, wrap) \
315 ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap)
318 #if AIC_DEBUG_REGISTERS
319 ahd_reg_print_t ahd_maxcmd_print;
321 #define ahd_maxcmd_print(regvalue, cur_col, wrap) \
322 ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap)
325 #if AIC_DEBUG_REGISTERS
326 ahd_reg_print_t ahd_maxcmdcnt_print;
328 #define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \
329 ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap)
332 #if AIC_DEBUG_REGISTERS
333 ahd_reg_print_t ahd_lqrsvd01_print;
335 #define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
336 ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
339 #if AIC_DEBUG_REGISTERS
340 ahd_reg_print_t ahd_lqrsvd16_print;
342 #define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
343 ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
346 #if AIC_DEBUG_REGISTERS
347 ahd_reg_print_t ahd_lqrsvd17_print;
349 #define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
350 ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
353 #if AIC_DEBUG_REGISTERS
354 ahd_reg_print_t ahd_cmdrsvd0_print;
356 #define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
357 ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
360 #if AIC_DEBUG_REGISTERS
361 ahd_reg_print_t ahd_lqctl0_print;
363 #define ahd_lqctl0_print(regvalue, cur_col, wrap) \
364 ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
367 #if AIC_DEBUG_REGISTERS
368 ahd_reg_print_t ahd_lqctl1_print;
370 #define ahd_lqctl1_print(regvalue, cur_col, wrap) \
371 ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap)
374 #if AIC_DEBUG_REGISTERS
375 ahd_reg_print_t ahd_lqctl2_print;
377 #define ahd_lqctl2_print(regvalue, cur_col, wrap) \
378 ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap)
381 #if AIC_DEBUG_REGISTERS
382 ahd_reg_print_t ahd_scsbist0_print;
384 #define ahd_scsbist0_print(regvalue, cur_col, wrap) \
385 ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
388 #if AIC_DEBUG_REGISTERS
389 ahd_reg_print_t ahd_scsiseq0_print;
391 #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
392 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
395 #if AIC_DEBUG_REGISTERS
396 ahd_reg_print_t ahd_scsbist1_print;
398 #define ahd_scsbist1_print(regvalue, cur_col, wrap) \
399 ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
402 #if AIC_DEBUG_REGISTERS
403 ahd_reg_print_t ahd_scsiseq1_print;
405 #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
406 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
409 #if AIC_DEBUG_REGISTERS
410 ahd_reg_print_t ahd_businitid_print;
412 #define ahd_businitid_print(regvalue, cur_col, wrap) \
413 ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
416 #if AIC_DEBUG_REGISTERS
417 ahd_reg_print_t ahd_sxfrctl0_print;
419 #define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \
420 ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap)
423 #if AIC_DEBUG_REGISTERS
424 ahd_reg_print_t ahd_dlcount_print;
426 #define ahd_dlcount_print(regvalue, cur_col, wrap) \
427 ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
430 #if AIC_DEBUG_REGISTERS
431 ahd_reg_print_t ahd_sxfrctl1_print;
433 #define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
434 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
437 #if AIC_DEBUG_REGISTERS
438 ahd_reg_print_t ahd_bustargid_print;
440 #define ahd_bustargid_print(regvalue, cur_col, wrap) \
441 ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
444 #if AIC_DEBUG_REGISTERS
445 ahd_reg_print_t ahd_sxfrctl2_print;
447 #define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
448 ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
451 #if AIC_DEBUG_REGISTERS
452 ahd_reg_print_t ahd_dffstat_print;
454 #define ahd_dffstat_print(regvalue, cur_col, wrap) \
455 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
458 #if AIC_DEBUG_REGISTERS
459 ahd_reg_print_t ahd_scsisigo_print;
461 #define ahd_scsisigo_print(regvalue, cur_col, wrap) \
462 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
465 #if AIC_DEBUG_REGISTERS
466 ahd_reg_print_t ahd_multargid_print;
468 #define ahd_multargid_print(regvalue, cur_col, wrap) \
469 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
472 #if AIC_DEBUG_REGISTERS
473 ahd_reg_print_t ahd_scsisigi_print;
475 #define ahd_scsisigi_print(regvalue, cur_col, wrap) \
476 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
479 #if AIC_DEBUG_REGISTERS
480 ahd_reg_print_t ahd_scsiphase_print;
482 #define ahd_scsiphase_print(regvalue, cur_col, wrap) \
483 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
486 #if AIC_DEBUG_REGISTERS
487 ahd_reg_print_t ahd_scsidat0_img_print;
489 #define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
490 ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
493 #if AIC_DEBUG_REGISTERS
494 ahd_reg_print_t ahd_scsidat_print;
496 #define ahd_scsidat_print(regvalue, cur_col, wrap) \
497 ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap)
500 #if AIC_DEBUG_REGISTERS
501 ahd_reg_print_t ahd_scsibus_print;
503 #define ahd_scsibus_print(regvalue, cur_col, wrap) \
504 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
507 #if AIC_DEBUG_REGISTERS
508 ahd_reg_print_t ahd_targidin_print;
510 #define ahd_targidin_print(regvalue, cur_col, wrap) \
511 ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap)
514 #if AIC_DEBUG_REGISTERS
515 ahd_reg_print_t ahd_selid_print;
517 #define ahd_selid_print(regvalue, cur_col, wrap) \
518 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
521 #if AIC_DEBUG_REGISTERS
522 ahd_reg_print_t ahd_optionmode_print;
524 #define ahd_optionmode_print(regvalue, cur_col, wrap) \
525 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
528 #if AIC_DEBUG_REGISTERS
529 ahd_reg_print_t ahd_sblkctl_print;
531 #define ahd_sblkctl_print(regvalue, cur_col, wrap) \
532 ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
535 #if AIC_DEBUG_REGISTERS
536 ahd_reg_print_t ahd_simode0_print;
538 #define ahd_simode0_print(regvalue, cur_col, wrap) \
539 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
542 #if AIC_DEBUG_REGISTERS
543 ahd_reg_print_t ahd_sstat0_print;
545 #define ahd_sstat0_print(regvalue, cur_col, wrap) \
546 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
549 #if AIC_DEBUG_REGISTERS
550 ahd_reg_print_t ahd_clrsint0_print;
552 #define ahd_clrsint0_print(regvalue, cur_col, wrap) \
553 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
556 #if AIC_DEBUG_REGISTERS
557 ahd_reg_print_t ahd_sstat1_print;
559 #define ahd_sstat1_print(regvalue, cur_col, wrap) \
560 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
563 #if AIC_DEBUG_REGISTERS
564 ahd_reg_print_t ahd_clrsint1_print;
566 #define ahd_clrsint1_print(regvalue, cur_col, wrap) \
567 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
570 #if AIC_DEBUG_REGISTERS
571 ahd_reg_print_t ahd_sstat2_print;
573 #define ahd_sstat2_print(regvalue, cur_col, wrap) \
574 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
577 #if AIC_DEBUG_REGISTERS
578 ahd_reg_print_t ahd_clrsint2_print;
580 #define ahd_clrsint2_print(regvalue, cur_col, wrap) \
581 ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap)
584 #if AIC_DEBUG_REGISTERS
585 ahd_reg_print_t ahd_simode2_print;
587 #define ahd_simode2_print(regvalue, cur_col, wrap) \
588 ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap)
591 #if AIC_DEBUG_REGISTERS
592 ahd_reg_print_t ahd_perrdiag_print;
594 #define ahd_perrdiag_print(regvalue, cur_col, wrap) \
595 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
598 #if AIC_DEBUG_REGISTERS
599 ahd_reg_print_t ahd_lqistate_print;
601 #define ahd_lqistate_print(regvalue, cur_col, wrap) \
602 ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
605 #if AIC_DEBUG_REGISTERS
606 ahd_reg_print_t ahd_soffcnt_print;
608 #define ahd_soffcnt_print(regvalue, cur_col, wrap) \
609 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
612 #if AIC_DEBUG_REGISTERS
613 ahd_reg_print_t ahd_lqostate_print;
615 #define ahd_lqostate_print(regvalue, cur_col, wrap) \
616 ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap)
619 #if AIC_DEBUG_REGISTERS
620 ahd_reg_print_t ahd_lqistat0_print;
622 #define ahd_lqistat0_print(regvalue, cur_col, wrap) \
623 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
626 #if AIC_DEBUG_REGISTERS
627 ahd_reg_print_t ahd_clrlqiint0_print;
629 #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
630 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
633 #if AIC_DEBUG_REGISTERS
634 ahd_reg_print_t ahd_lqimode0_print;
636 #define ahd_lqimode0_print(regvalue, cur_col, wrap) \
637 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
640 #if AIC_DEBUG_REGISTERS
641 ahd_reg_print_t ahd_lqistat1_print;
643 #define ahd_lqistat1_print(regvalue, cur_col, wrap) \
644 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
647 #if AIC_DEBUG_REGISTERS
648 ahd_reg_print_t ahd_clrlqiint1_print;
650 #define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \
651 ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap)
654 #if AIC_DEBUG_REGISTERS
655 ahd_reg_print_t ahd_lqimode1_print;
657 #define ahd_lqimode1_print(regvalue, cur_col, wrap) \
658 ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap)
661 #if AIC_DEBUG_REGISTERS
662 ahd_reg_print_t ahd_lqistat2_print;
664 #define ahd_lqistat2_print(regvalue, cur_col, wrap) \
665 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
668 #if AIC_DEBUG_REGISTERS
669 ahd_reg_print_t ahd_sstat3_print;
671 #define ahd_sstat3_print(regvalue, cur_col, wrap) \
672 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
675 #if AIC_DEBUG_REGISTERS
676 ahd_reg_print_t ahd_clrsint3_print;
678 #define ahd_clrsint3_print(regvalue, cur_col, wrap) \
679 ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap)
682 #if AIC_DEBUG_REGISTERS
683 ahd_reg_print_t ahd_simode3_print;
685 #define ahd_simode3_print(regvalue, cur_col, wrap) \
686 ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap)
689 #if AIC_DEBUG_REGISTERS
690 ahd_reg_print_t ahd_lqomode0_print;
692 #define ahd_lqomode0_print(regvalue, cur_col, wrap) \
693 ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
696 #if AIC_DEBUG_REGISTERS
697 ahd_reg_print_t ahd_lqostat0_print;
699 #define ahd_lqostat0_print(regvalue, cur_col, wrap) \
700 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
703 #if AIC_DEBUG_REGISTERS
704 ahd_reg_print_t ahd_clrlqoint0_print;
706 #define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \
707 ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap)
710 #if AIC_DEBUG_REGISTERS
711 ahd_reg_print_t ahd_lqomode1_print;
713 #define ahd_lqomode1_print(regvalue, cur_col, wrap) \
714 ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
717 #if AIC_DEBUG_REGISTERS
718 ahd_reg_print_t ahd_lqostat1_print;
720 #define ahd_lqostat1_print(regvalue, cur_col, wrap) \
721 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
724 #if AIC_DEBUG_REGISTERS
725 ahd_reg_print_t ahd_clrlqoint1_print;
727 #define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \
728 ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap)
731 #if AIC_DEBUG_REGISTERS
732 ahd_reg_print_t ahd_os_space_cnt_print;
734 #define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \
735 ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap)
738 #if AIC_DEBUG_REGISTERS
739 ahd_reg_print_t ahd_lqostat2_print;
741 #define ahd_lqostat2_print(regvalue, cur_col, wrap) \
742 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
745 #if AIC_DEBUG_REGISTERS
746 ahd_reg_print_t ahd_simode1_print;
748 #define ahd_simode1_print(regvalue, cur_col, wrap) \
749 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
752 #if AIC_DEBUG_REGISTERS
753 ahd_reg_print_t ahd_gsfifo_print;
755 #define ahd_gsfifo_print(regvalue, cur_col, wrap) \
756 ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap)
759 #if AIC_DEBUG_REGISTERS
760 ahd_reg_print_t ahd_dffsxfrctl_print;
762 #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
763 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
766 #if AIC_DEBUG_REGISTERS
767 ahd_reg_print_t ahd_nextscb_print;
769 #define ahd_nextscb_print(regvalue, cur_col, wrap) \
770 ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap)
773 #if AIC_DEBUG_REGISTERS
774 ahd_reg_print_t ahd_lqoscsctl_print;
776 #define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
777 ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
780 #if AIC_DEBUG_REGISTERS
781 ahd_reg_print_t ahd_seqintsrc_print;
783 #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
784 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
787 #if AIC_DEBUG_REGISTERS
788 ahd_reg_print_t ahd_clrseqintsrc_print;
790 #define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \
791 ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap)
794 #if AIC_DEBUG_REGISTERS
795 ahd_reg_print_t ahd_currscb_print;
797 #define ahd_currscb_print(regvalue, cur_col, wrap) \
798 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
801 #if AIC_DEBUG_REGISTERS
802 ahd_reg_print_t ahd_seqimode_print;
804 #define ahd_seqimode_print(regvalue, cur_col, wrap) \
805 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
808 #if AIC_DEBUG_REGISTERS
809 ahd_reg_print_t ahd_mdffstat_print;
811 #define ahd_mdffstat_print(regvalue, cur_col, wrap) \
812 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
815 #if AIC_DEBUG_REGISTERS
816 ahd_reg_print_t ahd_crccontrol_print;
818 #define ahd_crccontrol_print(regvalue, cur_col, wrap) \
819 ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap)
822 #if AIC_DEBUG_REGISTERS
823 ahd_reg_print_t ahd_scsitest_print;
825 #define ahd_scsitest_print(regvalue, cur_col, wrap) \
826 ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
829 #if AIC_DEBUG_REGISTERS
830 ahd_reg_print_t ahd_dfftag_print;
832 #define ahd_dfftag_print(regvalue, cur_col, wrap) \
833 ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap)
836 #if AIC_DEBUG_REGISTERS
837 ahd_reg_print_t ahd_lastscb_print;
839 #define ahd_lastscb_print(regvalue, cur_col, wrap) \
840 ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap)
843 #if AIC_DEBUG_REGISTERS
844 ahd_reg_print_t ahd_iopdnctl_print;
846 #define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
847 ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
850 #if AIC_DEBUG_REGISTERS
851 ahd_reg_print_t ahd_negoaddr_print;
853 #define ahd_negoaddr_print(regvalue, cur_col, wrap) \
854 ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap)
857 #if AIC_DEBUG_REGISTERS
858 ahd_reg_print_t ahd_shaddr_print;
860 #define ahd_shaddr_print(regvalue, cur_col, wrap) \
861 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
864 #if AIC_DEBUG_REGISTERS
865 ahd_reg_print_t ahd_dgrpcrci_print;
867 #define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
868 ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
871 #if AIC_DEBUG_REGISTERS
872 ahd_reg_print_t ahd_negperiod_print;
874 #define ahd_negperiod_print(regvalue, cur_col, wrap) \
875 ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap)
878 #if AIC_DEBUG_REGISTERS
879 ahd_reg_print_t ahd_packcrci_print;
881 #define ahd_packcrci_print(regvalue, cur_col, wrap) \
882 ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
885 #if AIC_DEBUG_REGISTERS
886 ahd_reg_print_t ahd_negoffset_print;
888 #define ahd_negoffset_print(regvalue, cur_col, wrap) \
889 ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap)
892 #if AIC_DEBUG_REGISTERS
893 ahd_reg_print_t ahd_negppropts_print;
895 #define ahd_negppropts_print(regvalue, cur_col, wrap) \
896 ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap)
899 #if AIC_DEBUG_REGISTERS
900 ahd_reg_print_t ahd_negconopts_print;
902 #define ahd_negconopts_print(regvalue, cur_col, wrap) \
903 ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap)
906 #if AIC_DEBUG_REGISTERS
907 ahd_reg_print_t ahd_annexcol_print;
909 #define ahd_annexcol_print(regvalue, cur_col, wrap) \
910 ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap)
913 #if AIC_DEBUG_REGISTERS
914 ahd_reg_print_t ahd_annexdat_print;
916 #define ahd_annexdat_print(regvalue, cur_col, wrap) \
917 ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap)
920 #if AIC_DEBUG_REGISTERS
921 ahd_reg_print_t ahd_scschkn_print;
923 #define ahd_scschkn_print(regvalue, cur_col, wrap) \
924 ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap)
927 #if AIC_DEBUG_REGISTERS
928 ahd_reg_print_t ahd_iownid_print;
930 #define ahd_iownid_print(regvalue, cur_col, wrap) \
931 ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap)
934 #if AIC_DEBUG_REGISTERS
935 ahd_reg_print_t ahd_shcnt_print;
937 #define ahd_shcnt_print(regvalue, cur_col, wrap) \
938 ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap)
941 #if AIC_DEBUG_REGISTERS
942 ahd_reg_print_t ahd_pll960ctl0_print;
944 #define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
945 ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
948 #if AIC_DEBUG_REGISTERS
949 ahd_reg_print_t ahd_pll960ctl1_print;
951 #define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
952 ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
955 #if AIC_DEBUG_REGISTERS
956 ahd_reg_print_t ahd_townid_print;
958 #define ahd_townid_print(regvalue, cur_col, wrap) \
959 ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap)
962 #if AIC_DEBUG_REGISTERS
963 ahd_reg_print_t ahd_xsig_print;
965 #define ahd_xsig_print(regvalue, cur_col, wrap) \
966 ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
969 #if AIC_DEBUG_REGISTERS
970 ahd_reg_print_t ahd_pll960cnt0_print;
972 #define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
973 ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
976 #if AIC_DEBUG_REGISTERS
977 ahd_reg_print_t ahd_seloid_print;
979 #define ahd_seloid_print(regvalue, cur_col, wrap) \
980 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
983 #if AIC_DEBUG_REGISTERS
984 ahd_reg_print_t ahd_fairness_print;
986 #define ahd_fairness_print(regvalue, cur_col, wrap) \
987 ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
990 #if AIC_DEBUG_REGISTERS
991 ahd_reg_print_t ahd_pll400ctl0_print;
993 #define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
994 ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
997 #if AIC_DEBUG_REGISTERS
998 ahd_reg_print_t ahd_pll400ctl1_print;
1000 #define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
1001 ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
1004 #if AIC_DEBUG_REGISTERS
1005 ahd_reg_print_t ahd_pll400cnt0_print;
1007 #define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
1008 ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
1011 #if AIC_DEBUG_REGISTERS
1012 ahd_reg_print_t ahd_unfairness_print;
1014 #define ahd_unfairness_print(regvalue, cur_col, wrap) \
1015 ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
1018 #if AIC_DEBUG_REGISTERS
1019 ahd_reg_print_t ahd_hodmaadr_print;
1021 #define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
1022 ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
1025 #if AIC_DEBUG_REGISTERS
1026 ahd_reg_print_t ahd_haddr_print;
1028 #define ahd_haddr_print(regvalue, cur_col, wrap) \
1029 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
1032 #if AIC_DEBUG_REGISTERS
1033 ahd_reg_print_t ahd_plldelay_print;
1035 #define ahd_plldelay_print(regvalue, cur_col, wrap) \
1036 ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
1039 #if AIC_DEBUG_REGISTERS
1040 ahd_reg_print_t ahd_hcnt_print;
1042 #define ahd_hcnt_print(regvalue, cur_col, wrap) \
1043 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
1046 #if AIC_DEBUG_REGISTERS
1047 ahd_reg_print_t ahd_hodmacnt_print;
1049 #define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
1050 ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
1053 #if AIC_DEBUG_REGISTERS
1054 ahd_reg_print_t ahd_hodmaen_print;
1056 #define ahd_hodmaen_print(regvalue, cur_col, wrap) \
1057 ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap)
1060 #if AIC_DEBUG_REGISTERS
1061 ahd_reg_print_t ahd_scbhaddr_print;
1063 #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
1064 ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
1067 #if AIC_DEBUG_REGISTERS
1068 ahd_reg_print_t ahd_sghaddr_print;
1070 #define ahd_sghaddr_print(regvalue, cur_col, wrap) \
1071 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
1074 #if AIC_DEBUG_REGISTERS
1075 ahd_reg_print_t ahd_scbhcnt_print;
1077 #define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
1078 ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
1081 #if AIC_DEBUG_REGISTERS
1082 ahd_reg_print_t ahd_sghcnt_print;
1084 #define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1085 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1088 #if AIC_DEBUG_REGISTERS
1089 ahd_reg_print_t ahd_dff_thrsh_print;
1091 #define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
1092 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap)
1095 #if AIC_DEBUG_REGISTERS
1096 ahd_reg_print_t ahd_romaddr_print;
1098 #define ahd_romaddr_print(regvalue, cur_col, wrap) \
1099 ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
1102 #if AIC_DEBUG_REGISTERS
1103 ahd_reg_print_t ahd_romcntrl_print;
1105 #define ahd_romcntrl_print(regvalue, cur_col, wrap) \
1106 ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
1109 #if AIC_DEBUG_REGISTERS
1110 ahd_reg_print_t ahd_romdata_print;
1112 #define ahd_romdata_print(regvalue, cur_col, wrap) \
1113 ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
1116 #if AIC_DEBUG_REGISTERS
1117 ahd_reg_print_t ahd_dchrxmsg0_print;
1119 #define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
1120 ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
1123 #if AIC_DEBUG_REGISTERS
1124 ahd_reg_print_t ahd_ovlyrxmsg0_print;
1126 #define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
1127 ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
1130 #if AIC_DEBUG_REGISTERS
1131 ahd_reg_print_t ahd_cmcrxmsg0_print;
1133 #define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
1134 ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
1137 #if AIC_DEBUG_REGISTERS
1138 ahd_reg_print_t ahd_roenable_print;
1140 #define ahd_roenable_print(regvalue, cur_col, wrap) \
1141 ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
1144 #if AIC_DEBUG_REGISTERS
1145 ahd_reg_print_t ahd_dchrxmsg1_print;
1147 #define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
1148 ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
1151 #if AIC_DEBUG_REGISTERS
1152 ahd_reg_print_t ahd_ovlyrxmsg1_print;
1154 #define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
1155 ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
1158 #if AIC_DEBUG_REGISTERS
1159 ahd_reg_print_t ahd_cmcrxmsg1_print;
1161 #define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
1162 ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
1165 #if AIC_DEBUG_REGISTERS
1166 ahd_reg_print_t ahd_nsenable_print;
1168 #define ahd_nsenable_print(regvalue, cur_col, wrap) \
1169 ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
1172 #if AIC_DEBUG_REGISTERS
1173 ahd_reg_print_t ahd_dchrxmsg2_print;
1175 #define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
1176 ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
1179 #if AIC_DEBUG_REGISTERS
1180 ahd_reg_print_t ahd_ovlyrxmsg2_print;
1182 #define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
1183 ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
1186 #if AIC_DEBUG_REGISTERS
1187 ahd_reg_print_t ahd_cmcrxmsg2_print;
1189 #define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
1190 ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
1193 #if AIC_DEBUG_REGISTERS
1194 ahd_reg_print_t ahd_ost_print;
1196 #define ahd_ost_print(regvalue, cur_col, wrap) \
1197 ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
1200 #if AIC_DEBUG_REGISTERS
1201 ahd_reg_print_t ahd_dchrxmsg3_print;
1203 #define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
1204 ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
1207 #if AIC_DEBUG_REGISTERS
1208 ahd_reg_print_t ahd_ovlyrxmsg3_print;
1210 #define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
1211 ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
1214 #if AIC_DEBUG_REGISTERS
1215 ahd_reg_print_t ahd_cmcrxmsg3_print;
1217 #define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
1218 ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
1221 #if AIC_DEBUG_REGISTERS
1222 ahd_reg_print_t ahd_pcixctl_print;
1224 #define ahd_pcixctl_print(regvalue, cur_col, wrap) \
1225 ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap)
1228 #if AIC_DEBUG_REGISTERS
1229 ahd_reg_print_t ahd_cmcseqbcnt_print;
1231 #define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
1232 ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
1235 #if AIC_DEBUG_REGISTERS
1236 ahd_reg_print_t ahd_dchseqbcnt_print;
1238 #define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
1239 ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
1242 #if AIC_DEBUG_REGISTERS
1243 ahd_reg_print_t ahd_ovlyseqbcnt_print;
1245 #define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
1246 ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
1249 #if AIC_DEBUG_REGISTERS
1250 ahd_reg_print_t ahd_cmcspltstat0_print;
1252 #define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
1253 ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1256 #if AIC_DEBUG_REGISTERS
1257 ahd_reg_print_t ahd_dchspltstat0_print;
1259 #define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
1260 ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1263 #if AIC_DEBUG_REGISTERS
1264 ahd_reg_print_t ahd_ovlyspltstat0_print;
1266 #define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
1267 ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1270 #if AIC_DEBUG_REGISTERS
1271 ahd_reg_print_t ahd_cmcspltstat1_print;
1273 #define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
1274 ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1277 #if AIC_DEBUG_REGISTERS
1278 ahd_reg_print_t ahd_dchspltstat1_print;
1280 #define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
1281 ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1284 #if AIC_DEBUG_REGISTERS
1285 ahd_reg_print_t ahd_ovlyspltstat1_print;
1287 #define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
1288 ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1291 #if AIC_DEBUG_REGISTERS
1292 ahd_reg_print_t ahd_sgrxmsg0_print;
1294 #define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
1295 ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
1298 #if AIC_DEBUG_REGISTERS
1299 ahd_reg_print_t ahd_slvspltoutadr0_print;
1301 #define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
1302 ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
1305 #if AIC_DEBUG_REGISTERS
1306 ahd_reg_print_t ahd_sgrxmsg1_print;
1308 #define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
1309 ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
1312 #if AIC_DEBUG_REGISTERS
1313 ahd_reg_print_t ahd_slvspltoutadr1_print;
1315 #define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
1316 ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
1319 #if AIC_DEBUG_REGISTERS
1320 ahd_reg_print_t ahd_sgrxmsg2_print;
1322 #define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
1323 ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
1326 #if AIC_DEBUG_REGISTERS
1327 ahd_reg_print_t ahd_slvspltoutadr2_print;
1329 #define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
1330 ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
1333 #if AIC_DEBUG_REGISTERS
1334 ahd_reg_print_t ahd_sgrxmsg3_print;
1336 #define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
1337 ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
1340 #if AIC_DEBUG_REGISTERS
1341 ahd_reg_print_t ahd_slvspltoutadr3_print;
1343 #define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
1344 ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
1347 #if AIC_DEBUG_REGISTERS
1348 ahd_reg_print_t ahd_slvspltoutattr0_print;
1350 #define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
1351 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
1354 #if AIC_DEBUG_REGISTERS
1355 ahd_reg_print_t ahd_sgseqbcnt_print;
1357 #define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
1358 ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
1361 #if AIC_DEBUG_REGISTERS
1362 ahd_reg_print_t ahd_slvspltoutattr1_print;
1364 #define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
1365 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
1368 #if AIC_DEBUG_REGISTERS
1369 ahd_reg_print_t ahd_slvspltoutattr2_print;
1371 #define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
1372 ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
1375 #if AIC_DEBUG_REGISTERS
1376 ahd_reg_print_t ahd_sgspltstat0_print;
1378 #define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
1379 ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
1382 #if AIC_DEBUG_REGISTERS
1383 ahd_reg_print_t ahd_sfunct_print;
1385 #define ahd_sfunct_print(regvalue, cur_col, wrap) \
1386 ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
1389 #if AIC_DEBUG_REGISTERS
1390 ahd_reg_print_t ahd_sgspltstat1_print;
1392 #define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \
1393 ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap)
1396 #if AIC_DEBUG_REGISTERS
1397 ahd_reg_print_t ahd_df0pcistat_print;
1399 #define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
1400 ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap)
1403 #if AIC_DEBUG_REGISTERS
1404 ahd_reg_print_t ahd_reg0_print;
1406 #define ahd_reg0_print(regvalue, cur_col, wrap) \
1407 ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap)
1410 #if AIC_DEBUG_REGISTERS
1411 ahd_reg_print_t ahd_df1pcistat_print;
1413 #define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
1414 ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
1417 #if AIC_DEBUG_REGISTERS
1418 ahd_reg_print_t ahd_sgpcistat_print;
1420 #define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
1421 ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
1424 #if AIC_DEBUG_REGISTERS
1425 ahd_reg_print_t ahd_reg1_print;
1427 #define ahd_reg1_print(regvalue, cur_col, wrap) \
1428 ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
1431 #if AIC_DEBUG_REGISTERS
1432 ahd_reg_print_t ahd_cmcpcistat_print;
1434 #define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
1435 ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
1438 #if AIC_DEBUG_REGISTERS
1439 ahd_reg_print_t ahd_ovlypcistat_print;
1441 #define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
1442 ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
1445 #if AIC_DEBUG_REGISTERS
1446 ahd_reg_print_t ahd_reg_isr_print;
1448 #define ahd_reg_isr_print(regvalue, cur_col, wrap) \
1449 ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap)
1452 #if AIC_DEBUG_REGISTERS
1453 ahd_reg_print_t ahd_msipcistat_print;
1455 #define ahd_msipcistat_print(regvalue, cur_col, wrap) \
1456 ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
1459 #if AIC_DEBUG_REGISTERS
1460 ahd_reg_print_t ahd_sg_state_print;
1462 #define ahd_sg_state_print(regvalue, cur_col, wrap) \
1463 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
1466 #if AIC_DEBUG_REGISTERS
1467 ahd_reg_print_t ahd_targpcistat_print;
1469 #define ahd_targpcistat_print(regvalue, cur_col, wrap) \
1470 ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap)
1473 #if AIC_DEBUG_REGISTERS
1474 ahd_reg_print_t ahd_data_count_odd_print;
1476 #define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
1477 ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
1480 #if AIC_DEBUG_REGISTERS
1481 ahd_reg_print_t ahd_scbptr_print;
1483 #define ahd_scbptr_print(regvalue, cur_col, wrap) \
1484 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
1487 #if AIC_DEBUG_REGISTERS
1488 ahd_reg_print_t ahd_ccscbacnt_print;
1490 #define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
1491 ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
1494 #if AIC_DEBUG_REGISTERS
1495 ahd_reg_print_t ahd_scbautoptr_print;
1497 #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
1498 ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
1501 #if AIC_DEBUG_REGISTERS
1502 ahd_reg_print_t ahd_ccscbadr_bk_print;
1504 #define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
1505 ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
1508 #if AIC_DEBUG_REGISTERS
1509 ahd_reg_print_t ahd_ccsgaddr_print;
1511 #define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
1512 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
1515 #if AIC_DEBUG_REGISTERS
1516 ahd_reg_print_t ahd_ccscbaddr_print;
1518 #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
1519 ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
1522 #if AIC_DEBUG_REGISTERS
1523 ahd_reg_print_t ahd_ccscbctl_print;
1525 #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
1526 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
1529 #if AIC_DEBUG_REGISTERS
1530 ahd_reg_print_t ahd_ccsgctl_print;
1532 #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
1533 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
1536 #if AIC_DEBUG_REGISTERS
1537 ahd_reg_print_t ahd_cmc_rambist_print;
1539 #define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
1540 ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
1543 #if AIC_DEBUG_REGISTERS
1544 ahd_reg_print_t ahd_ccsgram_print;
1546 #define ahd_ccsgram_print(regvalue, cur_col, wrap) \
1547 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
1550 #if AIC_DEBUG_REGISTERS
1551 ahd_reg_print_t ahd_ccscbram_print;
1553 #define ahd_ccscbram_print(regvalue, cur_col, wrap) \
1554 ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap)
1557 #if AIC_DEBUG_REGISTERS
1558 ahd_reg_print_t ahd_flexadr_print;
1560 #define ahd_flexadr_print(regvalue, cur_col, wrap) \
1561 ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
1564 #if AIC_DEBUG_REGISTERS
1565 ahd_reg_print_t ahd_flexcnt_print;
1567 #define ahd_flexcnt_print(regvalue, cur_col, wrap) \
1568 ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
1571 #if AIC_DEBUG_REGISTERS
1572 ahd_reg_print_t ahd_flexdmastat_print;
1574 #define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
1575 ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
1578 #if AIC_DEBUG_REGISTERS
1579 ahd_reg_print_t ahd_flexdata_print;
1581 #define ahd_flexdata_print(regvalue, cur_col, wrap) \
1582 ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
1585 #if AIC_DEBUG_REGISTERS
1586 ahd_reg_print_t ahd_brddat_print;
1588 #define ahd_brddat_print(regvalue, cur_col, wrap) \
1589 ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap)
1592 #if AIC_DEBUG_REGISTERS
1593 ahd_reg_print_t ahd_brdctl_print;
1595 #define ahd_brdctl_print(regvalue, cur_col, wrap) \
1596 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
1599 #if AIC_DEBUG_REGISTERS
1600 ahd_reg_print_t ahd_seeadr_print;
1602 #define ahd_seeadr_print(regvalue, cur_col, wrap) \
1603 ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap)
1606 #if AIC_DEBUG_REGISTERS
1607 ahd_reg_print_t ahd_seedat_print;
1609 #define ahd_seedat_print(regvalue, cur_col, wrap) \
1610 ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap)
1613 #if AIC_DEBUG_REGISTERS
1614 ahd_reg_print_t ahd_seectl_print;
1616 #define ahd_seectl_print(regvalue, cur_col, wrap) \
1617 ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap)
1620 #if AIC_DEBUG_REGISTERS
1621 ahd_reg_print_t ahd_seestat_print;
1623 #define ahd_seestat_print(regvalue, cur_col, wrap) \
1624 ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap)
1627 #if AIC_DEBUG_REGISTERS
1628 ahd_reg_print_t ahd_scbcnt_print;
1630 #define ahd_scbcnt_print(regvalue, cur_col, wrap) \
1631 ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
1634 #if AIC_DEBUG_REGISTERS
1635 ahd_reg_print_t ahd_dspfltrctl_print;
1637 #define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
1638 ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
1641 #if AIC_DEBUG_REGISTERS
1642 ahd_reg_print_t ahd_dfwaddr_print;
1644 #define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
1645 ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
1648 #if AIC_DEBUG_REGISTERS
1649 ahd_reg_print_t ahd_dspdatactl_print;
1651 #define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
1652 ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap)
1655 #if AIC_DEBUG_REGISTERS
1656 ahd_reg_print_t ahd_dspreqctl_print;
1658 #define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
1659 ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
1662 #if AIC_DEBUG_REGISTERS
1663 ahd_reg_print_t ahd_dfraddr_print;
1665 #define ahd_dfraddr_print(regvalue, cur_col, wrap) \
1666 ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
1669 #if AIC_DEBUG_REGISTERS
1670 ahd_reg_print_t ahd_dspackctl_print;
1672 #define ahd_dspackctl_print(regvalue, cur_col, wrap) \
1673 ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
1676 #if AIC_DEBUG_REGISTERS
1677 ahd_reg_print_t ahd_dfdat_print;
1679 #define ahd_dfdat_print(regvalue, cur_col, wrap) \
1680 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
1683 #if AIC_DEBUG_REGISTERS
1684 ahd_reg_print_t ahd_dspselect_print;
1686 #define ahd_dspselect_print(regvalue, cur_col, wrap) \
1687 ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap)
1690 #if AIC_DEBUG_REGISTERS
1691 ahd_reg_print_t ahd_wrtbiasctl_print;
1693 #define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \
1694 ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap)
1697 #if AIC_DEBUG_REGISTERS
1698 ahd_reg_print_t ahd_rcvrbiosctl_print;
1700 #define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
1701 ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
1704 #if AIC_DEBUG_REGISTERS
1705 ahd_reg_print_t ahd_wrtbiascalc_print;
1707 #define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
1708 ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
1711 #if AIC_DEBUG_REGISTERS
1712 ahd_reg_print_t ahd_dfptrs_print;
1714 #define ahd_dfptrs_print(regvalue, cur_col, wrap) \
1715 ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
1718 #if AIC_DEBUG_REGISTERS
1719 ahd_reg_print_t ahd_rcvrbiascalc_print;
1721 #define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
1722 ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
1725 #if AIC_DEBUG_REGISTERS
1726 ahd_reg_print_t ahd_dfbkptr_print;
1728 #define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
1729 ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
1732 #if AIC_DEBUG_REGISTERS
1733 ahd_reg_print_t ahd_skewcalc_print;
1735 #define ahd_skewcalc_print(regvalue, cur_col, wrap) \
1736 ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
1739 #if AIC_DEBUG_REGISTERS
1740 ahd_reg_print_t ahd_dfdbctl_print;
1742 #define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
1743 ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
1746 #if AIC_DEBUG_REGISTERS
1747 ahd_reg_print_t ahd_dfscnt_print;
1749 #define ahd_dfscnt_print(regvalue, cur_col, wrap) \
1750 ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
1753 #if AIC_DEBUG_REGISTERS
1754 ahd_reg_print_t ahd_dfbcnt_print;
1756 #define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
1757 ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
1760 #if AIC_DEBUG_REGISTERS
1761 ahd_reg_print_t ahd_ovlyaddr_print;
1763 #define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
1764 ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
1767 #if AIC_DEBUG_REGISTERS
1768 ahd_reg_print_t ahd_seqctl0_print;
1770 #define ahd_seqctl0_print(regvalue, cur_col, wrap) \
1771 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
1774 #if AIC_DEBUG_REGISTERS
1775 ahd_reg_print_t ahd_seqctl1_print;
1777 #define ahd_seqctl1_print(regvalue, cur_col, wrap) \
1778 ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
1781 #if AIC_DEBUG_REGISTERS
1782 ahd_reg_print_t ahd_flags_print;
1784 #define ahd_flags_print(regvalue, cur_col, wrap) \
1785 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
1788 #if AIC_DEBUG_REGISTERS
1789 ahd_reg_print_t ahd_seqintctl_print;
1791 #define ahd_seqintctl_print(regvalue, cur_col, wrap) \
1792 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
1795 #if AIC_DEBUG_REGISTERS
1796 ahd_reg_print_t ahd_seqram_print;
1798 #define ahd_seqram_print(regvalue, cur_col, wrap) \
1799 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
1802 #if AIC_DEBUG_REGISTERS
1803 ahd_reg_print_t ahd_prgmcnt_print;
1805 #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
1806 ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap)
1809 #if AIC_DEBUG_REGISTERS
1810 ahd_reg_print_t ahd_accum_print;
1812 #define ahd_accum_print(regvalue, cur_col, wrap) \
1813 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
1816 #if AIC_DEBUG_REGISTERS
1817 ahd_reg_print_t ahd_sindex_print;
1819 #define ahd_sindex_print(regvalue, cur_col, wrap) \
1820 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
1823 #if AIC_DEBUG_REGISTERS
1824 ahd_reg_print_t ahd_dindex_print;
1826 #define ahd_dindex_print(regvalue, cur_col, wrap) \
1827 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
1830 #if AIC_DEBUG_REGISTERS
1831 ahd_reg_print_t ahd_brkaddr1_print;
1833 #define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
1834 ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
1837 #if AIC_DEBUG_REGISTERS
1838 ahd_reg_print_t ahd_brkaddr0_print;
1840 #define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
1841 ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
1844 #if AIC_DEBUG_REGISTERS
1845 ahd_reg_print_t ahd_allones_print;
1847 #define ahd_allones_print(regvalue, cur_col, wrap) \
1848 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
1851 #if AIC_DEBUG_REGISTERS
1852 ahd_reg_print_t ahd_none_print;
1854 #define ahd_none_print(regvalue, cur_col, wrap) \
1855 ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap)
1858 #if AIC_DEBUG_REGISTERS
1859 ahd_reg_print_t ahd_allzeros_print;
1861 #define ahd_allzeros_print(regvalue, cur_col, wrap) \
1862 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
1865 #if AIC_DEBUG_REGISTERS
1866 ahd_reg_print_t ahd_sindir_print;
1868 #define ahd_sindir_print(regvalue, cur_col, wrap) \
1869 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
1872 #if AIC_DEBUG_REGISTERS
1873 ahd_reg_print_t ahd_dindir_print;
1875 #define ahd_dindir_print(regvalue, cur_col, wrap) \
1876 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
1879 #if AIC_DEBUG_REGISTERS
1880 ahd_reg_print_t ahd_function1_print;
1882 #define ahd_function1_print(regvalue, cur_col, wrap) \
1883 ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
1886 #if AIC_DEBUG_REGISTERS
1887 ahd_reg_print_t ahd_stack_print;
1889 #define ahd_stack_print(regvalue, cur_col, wrap) \
1890 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
1893 #if AIC_DEBUG_REGISTERS
1894 ahd_reg_print_t ahd_intvec1_addr_print;
1896 #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
1897 ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap)
1900 #if AIC_DEBUG_REGISTERS
1901 ahd_reg_print_t ahd_curaddr_print;
1903 #define ahd_curaddr_print(regvalue, cur_col, wrap) \
1904 ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap)
1907 #if AIC_DEBUG_REGISTERS
1908 ahd_reg_print_t ahd_intvec2_addr_print;
1910 #define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
1911 ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
1914 #if AIC_DEBUG_REGISTERS
1915 ahd_reg_print_t ahd_lastaddr_print;
1917 #define ahd_lastaddr_print(regvalue, cur_col, wrap) \
1918 ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
1921 #if AIC_DEBUG_REGISTERS
1922 ahd_reg_print_t ahd_longjmp_addr_print;
1924 #define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \
1925 ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap)
1928 #if AIC_DEBUG_REGISTERS
1929 ahd_reg_print_t ahd_accum_save_print;
1931 #define ahd_accum_save_print(regvalue, cur_col, wrap) \
1932 ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap)
1935 #if AIC_DEBUG_REGISTERS
1936 ahd_reg_print_t ahd_sram_base_print;
1938 #define ahd_sram_base_print(regvalue, cur_col, wrap) \
1939 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1942 #if AIC_DEBUG_REGISTERS
1943 ahd_reg_print_t ahd_waiting_scb_tails_print;
1945 #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1946 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1949 #if AIC_DEBUG_REGISTERS
1950 ahd_reg_print_t ahd_ahd_pci_config_base_print;
1952 #define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \
1953 ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap)
1956 #if AIC_DEBUG_REGISTERS
1957 ahd_reg_print_t ahd_waiting_tid_head_print;
1959 #define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \
1960 ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap)
1963 #if AIC_DEBUG_REGISTERS
1964 ahd_reg_print_t ahd_waiting_tid_tail_print;
1966 #define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \
1967 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap)
1970 #if AIC_DEBUG_REGISTERS
1971 ahd_reg_print_t ahd_next_queued_scb_addr_print;
1973 #define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \
1974 ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap)
1977 #if AIC_DEBUG_REGISTERS
1978 ahd_reg_print_t ahd_complete_scb_head_print;
1980 #define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \
1981 ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap)
1984 #if AIC_DEBUG_REGISTERS
1985 ahd_reg_print_t ahd_complete_scb_dmainprog_head_print;
1987 #define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \
1988 ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap)
1991 #if AIC_DEBUG_REGISTERS
1992 ahd_reg_print_t ahd_complete_dma_scb_head_print;
1994 #define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \
1995 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap)
1998 #if AIC_DEBUG_REGISTERS
1999 ahd_reg_print_t ahd_complete_dma_scb_tail_print;
2001 #define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \
2002 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap)
2005 #if AIC_DEBUG_REGISTERS
2006 ahd_reg_print_t ahd_complete_on_qfreeze_head_print;
2008 #define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \
2009 ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap)
2012 #if AIC_DEBUG_REGISTERS
2013 ahd_reg_print_t ahd_qfreeze_count_print;
2015 #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
2016 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)
2019 #if AIC_DEBUG_REGISTERS
2020 ahd_reg_print_t ahd_kernel_qfreeze_count_print;
2022 #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \
2023 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)
2026 #if AIC_DEBUG_REGISTERS
2027 ahd_reg_print_t ahd_saved_mode_print;
2029 #define ahd_saved_mode_print(regvalue, cur_col, wrap) \
2030 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)
2033 #if AIC_DEBUG_REGISTERS
2034 ahd_reg_print_t ahd_msg_out_print;
2036 #define ahd_msg_out_print(regvalue, cur_col, wrap) \
2037 ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap)
2040 #if AIC_DEBUG_REGISTERS
2041 ahd_reg_print_t ahd_dmaparams_print;
2043 #define ahd_dmaparams_print(regvalue, cur_col, wrap) \
2044 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap)
2047 #if AIC_DEBUG_REGISTERS
2048 ahd_reg_print_t ahd_seq_flags_print;
2050 #define ahd_seq_flags_print(regvalue, cur_col, wrap) \
2051 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)
2054 #if AIC_DEBUG_REGISTERS
2055 ahd_reg_print_t ahd_saved_scsiid_print;
2057 #define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
2058 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap)
2061 #if AIC_DEBUG_REGISTERS
2062 ahd_reg_print_t ahd_saved_lun_print;
2064 #define ahd_saved_lun_print(regvalue, cur_col, wrap) \
2065 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap)
2068 #if AIC_DEBUG_REGISTERS
2069 ahd_reg_print_t ahd_lastphase_print;
2071 #define ahd_lastphase_print(regvalue, cur_col, wrap) \
2072 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)
2075 #if AIC_DEBUG_REGISTERS
2076 ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print;
2078 #define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \
2079 ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap)
2082 #if AIC_DEBUG_REGISTERS
2083 ahd_reg_print_t ahd_kernel_tqinpos_print;
2085 #define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \
2086 ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap)
2089 #if AIC_DEBUG_REGISTERS
2090 ahd_reg_print_t ahd_tqinpos_print;
2092 #define ahd_tqinpos_print(regvalue, cur_col, wrap) \
2093 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap)
2096 #if AIC_DEBUG_REGISTERS
2097 ahd_reg_print_t ahd_shared_data_addr_print;
2099 #define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
2100 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap)
2103 #if AIC_DEBUG_REGISTERS
2104 ahd_reg_print_t ahd_qoutfifo_next_addr_print;
2106 #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
2107 ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap)
2110 #if AIC_DEBUG_REGISTERS
2111 ahd_reg_print_t ahd_arg_1_print;
2113 #define ahd_arg_1_print(regvalue, cur_col, wrap) \
2114 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap)
2117 #if AIC_DEBUG_REGISTERS
2118 ahd_reg_print_t ahd_arg_2_print;
2120 #define ahd_arg_2_print(regvalue, cur_col, wrap) \
2121 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap)
2124 #if AIC_DEBUG_REGISTERS
2125 ahd_reg_print_t ahd_last_msg_print;
2127 #define ahd_last_msg_print(regvalue, cur_col, wrap) \
2128 ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap)
2131 #if AIC_DEBUG_REGISTERS
2132 ahd_reg_print_t ahd_scsiseq_template_print;
2134 #define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \
2135 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap)
2138 #if AIC_DEBUG_REGISTERS
2139 ahd_reg_print_t ahd_initiator_tag_print;
2141 #define ahd_initiator_tag_print(regvalue, cur_col, wrap) \
2142 ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap)
2145 #if AIC_DEBUG_REGISTERS
2146 ahd_reg_print_t ahd_seq_flags2_print;
2148 #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
2149 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)
2152 #if AIC_DEBUG_REGISTERS
2153 ahd_reg_print_t ahd_allocfifo_scbptr_print;
2155 #define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \
2156 ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap)
2159 #if AIC_DEBUG_REGISTERS
2160 ahd_reg_print_t ahd_int_coalescing_timer_print;
2162 #define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \
2163 ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap)
2166 #if AIC_DEBUG_REGISTERS
2167 ahd_reg_print_t ahd_int_coalescing_maxcmds_print;
2169 #define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \
2170 ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap)
2173 #if AIC_DEBUG_REGISTERS
2174 ahd_reg_print_t ahd_int_coalescing_mincmds_print;
2176 #define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \
2177 ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap)
2180 #if AIC_DEBUG_REGISTERS
2181 ahd_reg_print_t ahd_cmds_pending_print;
2183 #define ahd_cmds_pending_print(regvalue, cur_col, wrap) \
2184 ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap)
2187 #if AIC_DEBUG_REGISTERS
2188 ahd_reg_print_t ahd_int_coalescing_cmdcount_print;
2190 #define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \
2191 ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap)
2194 #if AIC_DEBUG_REGISTERS
2195 ahd_reg_print_t ahd_local_hs_mailbox_print;
2197 #define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \
2198 ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap)
2201 #if AIC_DEBUG_REGISTERS
2202 ahd_reg_print_t ahd_cmdsize_table_print;
2204 #define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \
2205 ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap)
2208 #if AIC_DEBUG_REGISTERS
2209 ahd_reg_print_t ahd_mk_message_scb_print;
2211 #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \
2212 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)
2215 #if AIC_DEBUG_REGISTERS
2216 ahd_reg_print_t ahd_mk_message_scsiid_print;
2218 #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \
2219 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)
2222 #if AIC_DEBUG_REGISTERS
2223 ahd_reg_print_t ahd_scb_base_print;
2225 #define ahd_scb_base_print(regvalue, cur_col, wrap) \
2226 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
2229 #if AIC_DEBUG_REGISTERS
2230 ahd_reg_print_t ahd_scb_residual_datacnt_print;
2232 #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
2233 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
2236 #if AIC_DEBUG_REGISTERS
2237 ahd_reg_print_t ahd_scb_residual_sgptr_print;
2239 #define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
2240 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
2243 #if AIC_DEBUG_REGISTERS
2244 ahd_reg_print_t ahd_scb_scsi_status_print;
2246 #define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \
2247 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap)
2250 #if AIC_DEBUG_REGISTERS
2251 ahd_reg_print_t ahd_scb_target_phases_print;
2253 #define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
2254 ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
2257 #if AIC_DEBUG_REGISTERS
2258 ahd_reg_print_t ahd_scb_target_data_dir_print;
2260 #define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
2261 ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
2264 #if AIC_DEBUG_REGISTERS
2265 ahd_reg_print_t ahd_scb_target_itag_print;
2267 #define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
2268 ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
2271 #if AIC_DEBUG_REGISTERS
2272 ahd_reg_print_t ahd_scb_sense_busaddr_print;
2274 #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
2275 ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap)
2278 #if AIC_DEBUG_REGISTERS
2279 ahd_reg_print_t ahd_scb_tag_print;
2281 #define ahd_scb_tag_print(regvalue, cur_col, wrap) \
2282 ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap)
2285 #if AIC_DEBUG_REGISTERS
2286 ahd_reg_print_t ahd_scb_control_print;
2288 #define ahd_scb_control_print(regvalue, cur_col, wrap) \
2289 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
2292 #if AIC_DEBUG_REGISTERS
2293 ahd_reg_print_t ahd_scb_scsiid_print;
2295 #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
2296 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
2299 #if AIC_DEBUG_REGISTERS
2300 ahd_reg_print_t ahd_scb_lun_print;
2302 #define ahd_scb_lun_print(regvalue, cur_col, wrap) \
2303 ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap)
2306 #if AIC_DEBUG_REGISTERS
2307 ahd_reg_print_t ahd_scb_task_attribute_print;
2309 #define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \
2310 ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap)
2313 #if AIC_DEBUG_REGISTERS
2314 ahd_reg_print_t ahd_scb_cdb_len_print;
2316 #define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
2317 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
2320 #if AIC_DEBUG_REGISTERS
2321 ahd_reg_print_t ahd_scb_task_management_print;
2323 #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
2324 ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap)
2327 #if AIC_DEBUG_REGISTERS
2328 ahd_reg_print_t ahd_scb_dataptr_print;
2330 #define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \
2331 ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap)
2334 #if AIC_DEBUG_REGISTERS
2335 ahd_reg_print_t ahd_scb_datacnt_print;
2337 #define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \
2338 ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap)
2341 #if AIC_DEBUG_REGISTERS
2342 ahd_reg_print_t ahd_scb_sgptr_print;
2344 #define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \
2345 ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap)
2348 #if AIC_DEBUG_REGISTERS
2349 ahd_reg_print_t ahd_scb_busaddr_print;
2351 #define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \
2352 ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap)
2355 #if AIC_DEBUG_REGISTERS
2356 ahd_reg_print_t ahd_scb_next_print;
2358 #define ahd_scb_next_print(regvalue, cur_col, wrap) \
2359 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
2362 #if AIC_DEBUG_REGISTERS
2363 ahd_reg_print_t ahd_scb_next2_print;
2365 #define ahd_scb_next2_print(regvalue, cur_col, wrap) \
2366 ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap)
2369 #if AIC_DEBUG_REGISTERS
2370 ahd_reg_print_t ahd_scb_spare_print;
2372 #define ahd_scb_spare_print(regvalue, cur_col, wrap) \
2373 ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
2376 #if AIC_DEBUG_REGISTERS
2377 ahd_reg_print_t ahd_scb_disconnected_lists_print;
2379 #define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
2380 ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap)
2384 #define MODE_PTR 0x00
2385 #define DST_MODE 0x70
2386 #define SRC_MODE 0x07
2388 #define INTSTAT 0x01
2389 #define INT_PEND 0xff
2390 #define HWERRINT 0x80
2391 #define BRKADRINT 0x40
2392 #define SWTMINT 0x20
2394 #define SCSIINT 0x08
2396 #define CMDCMPLT 0x02
2397 #define SPLTINT 0x01
2399 #define SEQINTCODE 0x02
2400 #define BAD_SCB_STATUS 0x1a
2401 #define SAW_HWERR 0x19
2402 #define TRACEPOINT3 0x18
2403 #define TRACEPOINT2 0x17
2404 #define TRACEPOINT1 0x16
2405 #define TRACEPOINT0 0x15
2406 #define TASKMGMT_CMD_CMPLT_OKAY 0x14
2407 #define TASKMGMT_FUNC_COMPLETE 0x13
2408 #define ENTERING_NONPACK 0x12
2409 #define CFG4OVERRUN 0x11
2410 #define STATUS_OVERRUN 0x10
2411 #define CFG4ISTAT_INTR 0x0f
2412 #define INVALID_SEQINT 0x0e
2413 #define ILLEGAL_PHASE 0x0d
2414 #define DUMP_CARD_STATE 0x0c
2415 #define MISSED_BUSFREE 0x0b
2416 #define MKMSG_FAILED 0x0a
2417 #define DATA_OVERRUN 0x09
2418 #define BAD_STATUS 0x08
2419 #define HOST_MSG_LOOP 0x07
2420 #define PDATA_REINIT 0x06
2421 #define IGN_WIDE_RES 0x05
2422 #define NO_MATCH 0x04
2423 #define PROTO_VIOLATION 0x03
2424 #define SEND_REJECT 0x02
2425 #define BAD_PHASE 0x01
2426 #define NO_SEQINT 0x00
2429 #define CLRHWERRINT 0x80
2430 #define CLRBRKADRINT 0x40
2431 #define CLRSWTMINT 0x20
2432 #define CLRPCIINT 0x10
2433 #define CLRSCSIINT 0x08
2434 #define CLRSEQINT 0x04
2435 #define CLRCMDINT 0x02
2436 #define CLRSPLTINT 0x01
2439 #define CIOPARERR 0x80
2440 #define CIOACCESFAIL 0x40
2441 #define MPARERR 0x20
2442 #define DPARERR 0x10
2443 #define SQPARERR 0x08
2444 #define ILLOPCODE 0x04
2445 #define DSCTMOUT 0x02
2448 #define CLRCIOPARERR 0x80
2449 #define CLRCIOACCESFAIL 0x40
2450 #define CLRMPARERR 0x20
2451 #define CLRDPARERR 0x10
2452 #define CLRSQPARERR 0x08
2453 #define CLRILLOPCODE 0x04
2454 #define CLRDSCTMOUT 0x02
2457 #define SEQ_RESET 0x80
2460 #define SWTIMER_START_B 0x08
2463 #define CHIPRST 0x01
2464 #define CHIPRSTACK 0x01
2466 #define HNSCB_QOFF 0x06
2468 #define HESCB_QOFF 0x08
2470 #define HS_MAILBOX 0x0b
2471 #define HOST_TQINPOS 0x80
2472 #define ENINT_COALESCE 0x40
2474 #define SEQINTSTAT 0x0c
2475 #define SEQ_SWTMRTO 0x10
2476 #define SEQ_SEQINT 0x08
2477 #define SEQ_SCSIINT 0x04
2478 #define SEQ_PCIINT 0x02
2479 #define SEQ_SPLTINT 0x01
2481 #define CLRSEQINTSTAT 0x0c
2482 #define CLRSEQ_SWTMRTO 0x10
2483 #define CLRSEQ_SEQINT 0x08
2484 #define CLRSEQ_SCSIINT 0x04
2485 #define CLRSEQ_PCIINT 0x02
2486 #define CLRSEQ_SPLTINT 0x01
2488 #define SWTIMER 0x0e
2490 #define SNSCB_QOFF 0x10
2492 #define SESCB_QOFF 0x12
2494 #define SDSCB_QOFF 0x14
2496 #define QOFF_CTLSTA 0x16
2497 #define EMPTY_SCB_AVAIL 0x80
2498 #define NEW_SCB_AVAIL 0x40
2499 #define SDSCB_ROLLOVR 0x20
2500 #define HS_MAILBOX_ACT 0x10
2501 #define SCB_QSIZE 0x0f
2502 #define SCB_QSIZE_16384 0x0c
2503 #define SCB_QSIZE_8192 0x0b
2504 #define SCB_QSIZE_4096 0x0a
2505 #define SCB_QSIZE_2048 0x09
2506 #define SCB_QSIZE_1024 0x08
2507 #define SCB_QSIZE_512 0x07
2508 #define SCB_QSIZE_256 0x06
2509 #define SCB_QSIZE_128 0x05
2510 #define SCB_QSIZE_64 0x04
2511 #define SCB_QSIZE_32 0x03
2512 #define SCB_QSIZE_16 0x02
2513 #define SCB_QSIZE_8 0x01
2514 #define SCB_QSIZE_4 0x00
2517 #define SWTMINTMASK 0x80
2518 #define SWTMINTEN 0x40
2519 #define SWTIMER_START 0x20
2520 #define AUTOCLRCMDINT 0x10
2521 #define PCIINTEN 0x08
2522 #define SCSIINTEN 0x04
2523 #define SEQINTEN 0x02
2524 #define SPLTINTEN 0x01
2526 #define DFCNTRL 0x19
2527 #define SCSIENWRDIS 0x40
2528 #define SCSIENACK 0x20
2529 #define DIRECTIONACK 0x04
2530 #define FIFOFLUSHACK 0x02
2531 #define DIRECTIONEN 0x01
2533 #define DSCOMMAND0 0x19
2534 #define CACHETHEN 0x80
2535 #define DPARCKEN 0x40
2536 #define MPARCKEN 0x20
2537 #define EXTREQLCK 0x10
2538 #define DISABLE_TWATE 0x02
2539 #define CIOPARCKEN 0x01
2541 #define DFSTATUS 0x1a
2542 #define PRELOAD_AVAIL 0x80
2543 #define PKT_PRELOAD_AVAIL 0x40
2544 #define MREQPEND 0x10
2546 #define DFTHRESH 0x04
2547 #define FIFOFULL 0x02
2548 #define FIFOEMP 0x01
2550 #define SG_CACHE_SHADOW 0x1b
2551 #define ODD_SEG 0x04
2552 #define LAST_SEG 0x02
2553 #define LAST_SEG_DONE 0x01
2555 #define SG_CACHE_PRE 0x1b
2558 #define RESET_HARB 0x80
2559 #define RETRY_SWEN 0x08
2560 #define USE_TIME 0x07
2564 #define TYPEPTR 0x20
2570 #define DATALENPTR 0x23
2572 #define STATLENPTR 0x24
2574 #define CMDLENPTR 0x25
2576 #define ATTRPTR 0x26
2578 #define FLAGPTR 0x27
2582 #define QNEXTPTR 0x29
2586 #define ABRTBYTEPTR 0x2b
2588 #define ABRTBITPTR 0x2c
2590 #define MAXCMDBYTES 0x2d
2592 #define MAXCMD2RCV 0x2e
2594 #define SHORTTHRESH 0x2f
2597 #define TLUNLEN 0xf0
2598 #define ILUNLEN 0x0f
2600 #define CDBLIMIT 0x31
2604 #define MAXCMDCNT 0x33
2606 #define LQRSVD01 0x34
2608 #define LQRSVD16 0x35
2610 #define LQRSVD17 0x36
2612 #define CMDRSVD0 0x37
2615 #define LQITARGCLT 0xc0
2616 #define LQIINITGCLT 0x30
2617 #define LQ0TARGCLT 0x0c
2618 #define LQ0INITGCLT 0x03
2621 #define PCI2PCI 0x04
2622 #define SINGLECMD 0x02
2623 #define ABORTPENDING 0x01
2626 #define LQIRETRY 0x80
2627 #define LQICONTINUE 0x40
2628 #define LQITOIDLE 0x20
2629 #define LQIPAUSE 0x10
2630 #define LQORETRY 0x08
2631 #define LQOCONTINUE 0x04
2632 #define LQOTOIDLE 0x02
2633 #define LQOPAUSE 0x01
2635 #define SCSBIST0 0x39
2636 #define GSBISTERR 0x40
2637 #define GSBISTDONE 0x20
2638 #define GSBISTRUN 0x10
2639 #define OSBISTERR 0x04
2640 #define OSBISTDONE 0x02
2641 #define OSBISTRUN 0x01
2643 #define SCSISEQ0 0x3a
2644 #define TEMODEO 0x80
2647 #define FORCEBUSFREE 0x10
2648 #define SCSIRSTO 0x01
2650 #define SCSBIST1 0x3a
2651 #define NTBISTERR 0x04
2652 #define NTBISTDONE 0x02
2653 #define NTBISTRUN 0x01
2655 #define SCSISEQ1 0x3b
2657 #define BUSINITID 0x3c
2659 #define SXFRCTL0 0x3c
2662 #define BIOSCANCELEN 0x10
2665 #define DLCOUNT 0x3c
2667 #define SXFRCTL1 0x3d
2668 #define BITBUCKET 0x80
2669 #define ENSACHK 0x40
2670 #define ENSPCHK 0x20
2671 #define STIMESEL 0x18
2672 #define ENSTIMER 0x04
2673 #define ACTNEGEN 0x02
2676 #define BUSTARGID 0x3e
2678 #define SXFRCTL2 0x3e
2679 #define AUTORSTDIS 0x10
2680 #define CMDDMAEN 0x08
2683 #define DFFSTAT 0x3f
2684 #define CURRFIFO 0x03
2685 #define FIFO1FREE 0x20
2686 #define FIFO0FREE 0x10
2687 #define CURRFIFO_NONE 0x03
2688 #define CURRFIFO_1 0x01
2689 #define CURRFIFO_0 0x00
2691 #define SCSISIGO 0x40
2701 #define MULTARGID 0x40
2703 #define SCSISIGI 0x41
2710 #define SCSIPHASE 0x42
2711 #define STATUS_PHASE 0x20
2712 #define COMMAND_PHASE 0x10
2713 #define MSG_IN_PHASE 0x08
2714 #define MSG_OUT_PHASE 0x04
2715 #define DATA_PHASE_MASK 0x03
2716 #define DATA_IN_PHASE 0x02
2717 #define DATA_OUT_PHASE 0x01
2719 #define SCSIDAT0_IMG 0x43
2721 #define SCSIDAT 0x44
2723 #define SCSIBUS 0x46
2725 #define TARGIDIN 0x48
2730 #define SELID_MASK 0xf0
2733 #define OPTIONMODE 0x4a
2734 #define OPTIONMODE_DEFAULTS 0x02
2735 #define BIOSCANCTL 0x80
2736 #define AUTOACKEN 0x40
2737 #define BIASCANCTL 0x20
2738 #define BUSFREEREV 0x10
2739 #define ENDGFORMCHK 0x04
2740 #define AUTO_MSGOUT_DE 0x02
2742 #define SBLKCTL 0x4a
2743 #define DIAGLEDEN 0x80
2744 #define DIAGLEDON 0x40
2747 #define SELWIDE 0x02
2749 #define SIMODE0 0x4b
2750 #define ENSELDO 0x40
2751 #define ENSELDI 0x20
2752 #define ENSELINGO 0x10
2753 #define ENIOERR 0x08
2754 #define ENOVERRUN 0x04
2755 #define ENSPIORDY 0x02
2756 #define ENARBDO 0x01
2762 #define SELINGO 0x10
2764 #define OVERRUN 0x04
2765 #define SPIORDY 0x02
2768 #define CLRSINT0 0x4b
2769 #define CLRSELDO 0x40
2770 #define CLRSELDI 0x20
2771 #define CLRSELINGO 0x10
2772 #define CLRIOERR 0x08
2773 #define CLROVERRUN 0x04
2774 #define CLRSPIORDY 0x02
2775 #define CLRARBDO 0x01
2779 #define ATNTARG 0x40
2780 #define SCSIRSTI 0x20
2781 #define PHASEMIS 0x10
2782 #define BUSFREE 0x08
2783 #define SCSIPERR 0x04
2784 #define STRB2FAST 0x02
2785 #define REQINIT 0x01
2787 #define CLRSINT1 0x4c
2788 #define CLRSELTIMEO 0x80
2789 #define CLRATNO 0x40
2790 #define CLRSCSIRSTI 0x20
2791 #define CLRBUSFREE 0x08
2792 #define CLRSCSIPERR 0x04
2793 #define CLRSTRB2FAST 0x02
2794 #define CLRREQINIT 0x01
2797 #define BUSFREETIME 0xc0
2798 #define NONPACKREQ 0x20
2799 #define EXP_ACTIVE 0x10
2801 #define WIDE_RES 0x04
2803 #define DMADONE 0x01
2804 #define BUSFREE_DFF1 0xc0
2805 #define BUSFREE_DFF0 0x80
2806 #define BUSFREE_LQO 0x40
2808 #define CLRSINT2 0x4d
2809 #define CLRNONPACKREQ 0x20
2810 #define CLRWIDE_RES 0x04
2811 #define CLRSDONE 0x02
2812 #define CLRDMADONE 0x01
2814 #define SIMODE2 0x4d
2815 #define ENWIDE_RES 0x04
2816 #define ENSDONE 0x02
2817 #define ENDMADONE 0x01
2819 #define PERRDIAG 0x4e
2822 #define PREVPHASE 0x20
2823 #define PARITYERR 0x10
2826 #define DGFORMERR 0x02
2829 #define LQISTATE 0x4e
2831 #define SOFFCNT 0x4f
2833 #define LQOSTATE 0x4f
2835 #define LQISTAT0 0x50
2836 #define LQIATNQAS 0x20
2837 #define LQICRCT1 0x10
2838 #define LQICRCT2 0x08
2839 #define LQIBADLQT 0x04
2840 #define LQIATNLQ 0x02
2841 #define LQIATNCMD 0x01
2843 #define CLRLQIINT0 0x50
2844 #define CLRLQIATNQAS 0x20
2845 #define CLRLQICRCT1 0x10
2846 #define CLRLQICRCT2 0x08
2847 #define CLRLQIBADLQT 0x04
2848 #define CLRLQIATNLQ 0x02
2849 #define CLRLQIATNCMD 0x01
2851 #define LQIMODE0 0x50
2852 #define ENLQIATNQASK 0x20
2853 #define ENLQICRCT1 0x10
2854 #define ENLQICRCT2 0x08
2855 #define ENLQIBADLQT 0x04
2856 #define ENLQIATNLQ 0x02
2857 #define ENLQIATNCMD 0x01
2859 #define LQISTAT1 0x51
2860 #define LQIPHASE_LQ 0x80
2861 #define LQIPHASE_NLQ 0x40
2862 #define LQIABORT 0x20
2863 #define LQICRCI_LQ 0x10
2864 #define LQICRCI_NLQ 0x08
2865 #define LQIBADLQI 0x04
2866 #define LQIOVERI_LQ 0x02
2867 #define LQIOVERI_NLQ 0x01
2869 #define CLRLQIINT1 0x51
2870 #define CLRLQIPHASE_LQ 0x80
2871 #define CLRLQIPHASE_NLQ 0x40
2872 #define CLRLIQABORT 0x20
2873 #define CLRLQICRCI_LQ 0x10
2874 #define CLRLQICRCI_NLQ 0x08
2875 #define CLRLQIBADLQI 0x04
2876 #define CLRLQIOVERI_LQ 0x02
2877 #define CLRLQIOVERI_NLQ 0x01
2879 #define LQIMODE1 0x51
2880 #define ENLQIPHASE_LQ 0x80
2881 #define ENLQIPHASE_NLQ 0x40
2882 #define ENLIQABORT 0x20
2883 #define ENLQICRCI_LQ 0x10
2884 #define ENLQICRCI_NLQ 0x08
2885 #define ENLQIBADLQI 0x04
2886 #define ENLQIOVERI_LQ 0x02
2887 #define ENLQIOVERI_NLQ 0x01
2889 #define LQISTAT2 0x52
2890 #define PACKETIZED 0x80
2891 #define LQIPHASE_OUTPKT 0x40
2892 #define LQIWORKONLQ 0x20
2893 #define LQIWAITFIFO 0x10
2894 #define LQISTOPPKT 0x08
2895 #define LQISTOPLQ 0x04
2896 #define LQISTOPCMD 0x02
2897 #define LQIGSAVAIL 0x01
2900 #define NTRAMPERR 0x02
2901 #define OSRAMPERR 0x01
2903 #define CLRSINT3 0x53
2904 #define CLRNTRAMPERR 0x02
2905 #define CLROSRAMPERR 0x01
2907 #define SIMODE3 0x53
2908 #define ENNTRAMPERR 0x02
2909 #define ENOSRAMPERR 0x01
2911 #define LQOMODE0 0x54
2912 #define ENLQOTARGSCBPERR 0x10
2913 #define ENLQOSTOPT2 0x08
2914 #define ENLQOATNLQ 0x04
2915 #define ENLQOATNPKT 0x02
2916 #define ENLQOTCRC 0x01
2918 #define LQOSTAT0 0x54
2919 #define LQOTARGSCBPERR 0x10
2920 #define LQOSTOPT2 0x08
2921 #define LQOATNLQ 0x04
2922 #define LQOATNPKT 0x02
2923 #define LQOTCRC 0x01
2925 #define CLRLQOINT0 0x54
2926 #define CLRLQOTARGSCBPERR 0x10
2927 #define CLRLQOSTOPT2 0x08
2928 #define CLRLQOATNLQ 0x04
2929 #define CLRLQOATNPKT 0x02
2930 #define CLRLQOTCRC 0x01
2932 #define LQOMODE1 0x55
2933 #define ENLQOINITSCBPERR 0x10
2934 #define ENLQOSTOPI2 0x08
2935 #define ENLQOBADQAS 0x04
2936 #define ENLQOBUSFREE 0x02
2937 #define ENLQOPHACHGINPKT 0x01
2939 #define LQOSTAT1 0x55
2940 #define LQOINITSCBPERR 0x10
2941 #define LQOSTOPI2 0x08
2942 #define LQOBADQAS 0x04
2943 #define LQOBUSFREE 0x02
2944 #define LQOPHACHGINPKT 0x01
2946 #define CLRLQOINT1 0x55
2947 #define CLRLQOINITSCBPERR 0x10
2948 #define CLRLQOSTOPI2 0x08
2949 #define CLRLQOBADQAS 0x04
2950 #define CLRLQOBUSFREE 0x02
2951 #define CLRLQOPHACHGINPKT 0x01
2953 #define OS_SPACE_CNT 0x56
2955 #define LQOSTAT2 0x56
2957 #define LQOWAITFIFO 0x10
2958 #define LQOPHACHGOUTPKT 0x02
2959 #define LQOSTOP0 0x01
2961 #define SIMODE1 0x57
2962 #define ENSELTIMO 0x80
2963 #define ENATNTARG 0x40
2964 #define ENSCSIRST 0x20
2965 #define ENPHASEMIS 0x10
2966 #define ENBUSFREE 0x08
2967 #define ENSCSIPERR 0x04
2968 #define ENSTRB2FAST 0x02
2969 #define ENREQINIT 0x01
2973 #define DFFSXFRCTL 0x5a
2974 #define DFFBITBUCKET 0x08
2975 #define CLRSHCNT 0x04
2979 #define NEXTSCB 0x5a
2981 #define LQOSCSCTL 0x5a
2982 #define LQOH2A_VERSION 0x80
2983 #define LQONOCHKOVER 0x01
2985 #define SEQINTSRC 0x5b
2986 #define CTXTDONE 0x40
2987 #define SAVEPTRS 0x20
2988 #define CFG4DATA 0x10
2989 #define CFG4ISTAT 0x08
2990 #define CFG4TSTAT 0x04
2991 #define CFG4ICMD 0x02
2992 #define CFG4TCMD 0x01
2994 #define CLRSEQINTSRC 0x5b
2995 #define CLRCTXTDONE 0x40
2996 #define CLRSAVEPTRS 0x20
2997 #define CLRCFG4DATA 0x10
2998 #define CLRCFG4ISTAT 0x08
2999 #define CLRCFG4TSTAT 0x04
3000 #define CLRCFG4ICMD 0x02
3001 #define CLRCFG4TCMD 0x01
3003 #define CURRSCB 0x5c
3005 #define SEQIMODE 0x5c
3006 #define ENCTXTDONE 0x40
3007 #define ENSAVEPTRS 0x20
3008 #define ENCFG4DATA 0x10
3009 #define ENCFG4ISTAT 0x08
3010 #define ENCFG4TSTAT 0x04
3011 #define ENCFG4ICMD 0x02
3012 #define ENCFG4TCMD 0x01
3014 #define MDFFSTAT 0x5d
3015 #define SHCNTNEGATIVE 0x40
3016 #define SHCNTMINUS1 0x20
3017 #define LASTSDONE 0x10
3018 #define SHVALID 0x08
3020 #define DATAINFIFO 0x02
3021 #define FIFOFREE 0x01
3023 #define CRCCONTROL 0x5d
3024 #define CRCVALCHKEN 0x40
3026 #define SCSITEST 0x5e
3027 #define CNTRTEST 0x08
3028 #define SEL_TXPLL_DEBUG 0x04
3032 #define LASTSCB 0x5e
3034 #define IOPDNCTL 0x5f
3035 #define DISABLE_OE 0x80
3036 #define PDN_IDIST 0x04
3037 #define PDN_DIFFSENSE 0x01
3039 #define NEGOADDR 0x60
3043 #define DGRPCRCI 0x60
3045 #define NEGPERIOD 0x61
3047 #define PACKCRCI 0x62
3049 #define NEGOFFSET 0x62
3051 #define NEGPPROPTS 0x63
3052 #define PPROPT_PACE 0x08
3053 #define PPROPT_QAS 0x04
3054 #define PPROPT_DT 0x02
3055 #define PPROPT_IUT 0x01
3057 #define NEGCONOPTS 0x64
3058 #define ENSNAPSHOT 0x40
3059 #define RTI_WRTDIS 0x20
3060 #define RTI_OVRDTRN 0x10
3061 #define ENSLOWCRC 0x08
3062 #define ENAUTOATNI 0x04
3063 #define ENAUTOATNO 0x02
3064 #define WIDEXFER 0x01
3066 #define ANNEXCOL 0x65
3068 #define ANNEXDAT 0x66
3070 #define SCSCHKN 0x66
3071 #define STSELSKIDDIS 0x40
3072 #define CURRFIFODEF 0x20
3073 #define WIDERESEN 0x10
3074 #define SDONEMSKDIS 0x08
3075 #define DFFACTCLR 0x04
3076 #define SHVALIDSTDIS 0x02
3077 #define LSTSGCLRDIS 0x01
3083 #define PLL960CTL0 0x68
3085 #define PLL960CTL1 0x69
3091 #define PLL960CNT0 0x6a
3095 #define FAIRNESS 0x6c
3097 #define PLL400CTL0 0x6c
3098 #define PLL_VCOSEL 0x80
3099 #define PLL_PWDN 0x40
3101 #define PLL_ENLUD 0x08
3102 #define PLL_ENLPF 0x04
3103 #define PLL_DLPF 0x02
3104 #define PLL_ENFBM 0x01
3106 #define PLL400CTL1 0x6d
3107 #define PLL_CNTEN 0x80
3108 #define PLL_CNTCLR 0x40
3109 #define PLL_RST 0x01
3111 #define PLL400CNT0 0x6e
3113 #define UNFAIRNESS 0x6e
3115 #define HODMAADR 0x70
3119 #define PLLDELAY 0x70
3120 #define SPLIT_DROP_REQ 0x80
3124 #define HODMACNT 0x78
3126 #define HODMAEN 0x7a
3128 #define SCBHADDR 0x7c
3130 #define SGHADDR 0x7c
3132 #define SCBHCNT 0x84
3136 #define DFF_THRSH 0x88
3137 #define WR_DFTHRSH 0x70
3138 #define RD_DFTHRSH 0x07
3139 #define WR_DFTHRSH_MAX 0x70
3140 #define WR_DFTHRSH_90 0x60
3141 #define WR_DFTHRSH_85 0x50
3142 #define WR_DFTHRSH_75 0x40
3143 #define WR_DFTHRSH_63 0x30
3144 #define WR_DFTHRSH_50 0x20
3145 #define WR_DFTHRSH_25 0x10
3146 #define RD_DFTHRSH_MAX 0x07
3147 #define RD_DFTHRSH_90 0x06
3148 #define RD_DFTHRSH_85 0x05
3149 #define RD_DFTHRSH_75 0x04
3150 #define RD_DFTHRSH_63 0x03
3151 #define RD_DFTHRSH_50 0x02
3152 #define RD_DFTHRSH_25 0x01
3153 #define WR_DFTHRSH_MIN 0x00
3154 #define RD_DFTHRSH_MIN 0x00
3156 #define ROMADDR 0x8a
3158 #define ROMCNTRL 0x8d
3164 #define ROMDATA 0x8e
3166 #define DCHRXMSG0 0x90
3168 #define OVLYRXMSG0 0x90
3170 #define CMCRXMSG0 0x90
3172 #define ROENABLE 0x90
3173 #define MSIROEN 0x20
3174 #define OVLYROEN 0x10
3175 #define CMCROEN 0x08
3177 #define DCH1ROEN 0x02
3178 #define DCH0ROEN 0x01
3180 #define DCHRXMSG1 0x91
3182 #define OVLYRXMSG1 0x91
3184 #define CMCRXMSG1 0x91
3186 #define NSENABLE 0x91
3187 #define MSINSEN 0x20
3188 #define OVLYNSEN 0x10
3189 #define CMCNSEN 0x08
3191 #define DCH1NSEN 0x02
3192 #define DCH0NSEN 0x01
3194 #define DCHRXMSG2 0x92
3196 #define OVLYRXMSG2 0x92
3198 #define CMCRXMSG2 0x92
3202 #define DCHRXMSG3 0x93
3204 #define OVLYRXMSG3 0x93
3206 #define CMCRXMSG3 0x93
3208 #define PCIXCTL 0x93
3209 #define SERRPULSE 0x80
3210 #define UNEXPSCIEN 0x20
3211 #define SPLTSMADIS 0x10
3212 #define SPLTSTADIS 0x08
3213 #define SRSPDPEEN 0x04
3214 #define TSCSERREN 0x02
3215 #define CMPABCDIS 0x01
3217 #define CMCSEQBCNT 0x94
3219 #define DCHSEQBCNT 0x94
3221 #define OVLYSEQBCNT 0x94
3223 #define CMCSPLTSTAT0 0x96
3225 #define DCHSPLTSTAT0 0x96
3227 #define OVLYSPLTSTAT0 0x96
3229 #define CMCSPLTSTAT1 0x97
3231 #define DCHSPLTSTAT1 0x97
3233 #define OVLYSPLTSTAT1 0x97
3235 #define SGRXMSG0 0x98
3239 #define SLVSPLTOUTADR0 0x98
3240 #define LOWER_ADDR 0x7f
3242 #define SGRXMSG1 0x99
3245 #define SLVSPLTOUTADR1 0x99
3246 #define REQ_DNUM 0xf8
3247 #define REQ_FNUM 0x07
3249 #define SGRXMSG2 0x9a
3252 #define SLVSPLTOUTADR2 0x9a
3253 #define REQ_BNUM 0xff
3255 #define SGRXMSG3 0x9b
3258 #define SLVSPLTOUTADR3 0x9b
3259 #define TAG_NUM 0x1f
3262 #define SLVSPLTOUTATTR0 0x9c
3263 #define LOWER_BCNT 0xff
3265 #define SGSEQBCNT 0x9c
3267 #define SLVSPLTOUTATTR1 0x9d
3268 #define CMPLT_DNUM 0xf8
3269 #define CMPLT_FNUM 0x07
3271 #define SLVSPLTOUTATTR2 0x9e
3272 #define CMPLT_BNUM 0xff
3274 #define SGSPLTSTAT0 0x9e
3275 #define STAETERM 0x80
3276 #define SCBCERR 0x40
3277 #define SCADERR 0x20
3278 #define SCDATBUCKET 0x10
3279 #define CNTNOTCMPLT 0x08
3280 #define RXOVRUN 0x04
3281 #define RXSCEMSG 0x02
3282 #define RXSPLTRSP 0x01
3285 #define TEST_GROUP 0xf0
3286 #define TEST_NUM 0x0f
3288 #define SGSPLTSTAT1 0x9f
3289 #define RXDATABUCKET 0x01
3291 #define DF0PCISTAT 0xa0
3295 #define DF1PCISTAT 0xa1
3297 #define SGPCISTAT 0xa2
3301 #define CMCPCISTAT 0xa3
3303 #define OVLYPCISTAT 0xa4
3304 #define SCAAPERR 0x08
3307 #define REG_ISR 0xa4
3309 #define MSIPCISTAT 0xa6
3312 #define CLRPENDMSI 0x08
3315 #define SG_STATE 0xa6
3316 #define FETCH_INPROG 0x04
3317 #define LOADING_NEEDED 0x02
3318 #define SEGS_AVAIL 0x01
3320 #define TARGPCISTAT 0xa7
3324 #define TWATERR 0x02
3326 #define DATA_COUNT_ODD 0xa7
3330 #define CCSCBACNT 0xab
3332 #define SCBAUTOPTR 0xab
3333 #define AUSCBPTR_EN 0x80
3334 #define SCBPTR_ADDR 0x38
3335 #define SCBPTR_OFF 0x07
3337 #define CCSCBADR_BK 0xac
3339 #define CCSGADDR 0xac
3341 #define CCSCBADDR 0xac
3343 #define CCSCBCTL 0xad
3344 #define CCSCBDONE 0x80
3345 #define ARRDONE 0x40
3346 #define CCARREN 0x10
3347 #define CCSCBEN 0x08
3348 #define CCSCBDIR 0x04
3349 #define CCSCBRESET 0x01
3351 #define CCSGCTL 0xad
3353 #define CCSGDONE 0x80
3354 #define SG_CACHE_AVAIL 0x10
3355 #define CCSGENACK 0x08
3356 #define SG_FETCH_REQ 0x02
3357 #define CCSGRESET 0x01
3359 #define CMC_RAMBIST 0xad
3360 #define SG_ELEMENT_SIZE 0x80
3361 #define SCBRAMBIST_FAIL 0x40
3362 #define SG_BIST_FAIL 0x20
3363 #define SG_BIST_EN 0x10
3364 #define CMC_BUFFER_BIST_FAIL 0x02
3365 #define CMC_BUFFER_BIST_EN 0x01
3367 #define CCSGRAM 0xb0
3369 #define CCSCBRAM 0xb0
3371 #define FLEXADR 0xb0
3373 #define FLEXCNT 0xb3
3375 #define FLEXDMASTAT 0xb5
3376 #define FLEXDMAERR 0x02
3377 #define FLEXDMADONE 0x01
3379 #define FLEXDATA 0xb6
3384 #define FLXARBACK 0x80
3385 #define FLXARBREQ 0x40
3386 #define BRDADDR 0x38
3396 #define SEEOP_EWEN 0x40
3397 #define SEEOP_EWDS 0x40
3398 #define SEEOP_WALL 0x40
3399 #define SEEOPCODE 0x70
3401 #define SEESTART 0x01
3402 #define SEEOP_ERASE 0x70
3403 #define SEEOP_READ 0x60
3404 #define SEEOP_WRITE 0x50
3405 #define SEEOP_ERAL 0x40
3407 #define SEESTAT 0xbe
3408 #define INIT_DONE 0x80
3409 #define LDALTID_L 0x08
3410 #define SEEARBACK 0x04
3411 #define SEEBUSY 0x02
3415 #define DSPFLTRCTL 0xc0
3416 #define FLTRDISABLE 0x20
3417 #define EDGESENSE 0x10
3418 #define DSPFCNTSEL 0x0f
3420 #define DFWADDR 0xc0
3422 #define DSPDATACTL 0xc1
3423 #define BYPASSENAB 0x80
3424 #define DESQDIS 0x10
3425 #define RCVROFFSTDIS 0x04
3426 #define XMITOFFSTDIS 0x02
3428 #define DSPREQCTL 0xc2
3429 #define MANREQCTL 0xc0
3430 #define MANREQDLY 0x3f
3432 #define DFRADDR 0xc2
3434 #define DSPACKCTL 0xc3
3435 #define MANACKCTL 0xc0
3436 #define MANACKDLY 0x3f
3440 #define DSPSELECT 0xc4
3441 #define AUTOINCEN 0x80
3444 #define WRTBIASCTL 0xc5
3445 #define AUTOXBCDIS 0x80
3446 #define XMITMANVAL 0x3f
3448 #define RCVRBIOSCTL 0xc6
3449 #define AUTORBCDIS 0x80
3450 #define RCVRMANVAL 0x3f
3452 #define WRTBIASCALC 0xc7
3456 #define RCVRBIASCALC 0xc8
3458 #define DFBKPTR 0xc9
3460 #define SKEWCALC 0xc9
3462 #define DFDBCTL 0xcb
3463 #define DFF_CIO_WR_RDY 0x20
3464 #define DFF_CIO_RD_RDY 0x10
3465 #define DFF_DIR_ERR 0x08
3466 #define DFF_RAMBIST_FAIL 0x04
3467 #define DFF_RAMBIST_DONE 0x02
3468 #define DFF_RAMBIST_EN 0x01
3474 #define OVLYADDR 0xd4
3476 #define SEQCTL0 0xd6
3477 #define PERRORDIS 0x80
3478 #define PAUSEDIS 0x40
3479 #define FAILDIS 0x20
3480 #define FASTMODE 0x10
3481 #define BRKADRINTEN 0x08
3483 #define SEQRESET 0x02
3484 #define LOADRAM 0x01
3486 #define SEQCTL1 0xd7
3487 #define OVRLAY_DATA_CHK 0x08
3488 #define RAMBIST_DONE 0x04
3489 #define RAMBIST_FAIL 0x02
3490 #define RAMBIST_EN 0x01
3496 #define SEQINTCTL 0xd9
3497 #define INTVEC1DSL 0x80
3498 #define INT1_CONTEXT 0x20
3499 #define SCS_SEQ_INT1M1 0x10
3500 #define SCS_SEQ_INT1M0 0x08
3501 #define INTMASK2 0x04
3502 #define INTMASK1 0x02
3507 #define PRGMCNT 0xde
3515 #define BRKADDR1 0xe6
3518 #define BRKADDR0 0xe6
3520 #define ALLONES 0xe8
3524 #define ALLZEROS 0xea
3530 #define FUNCTION1 0xf0
3534 #define INTVEC1_ADDR 0xf4
3536 #define CURADDR 0xf4
3538 #define INTVEC2_ADDR 0xf6
3540 #define LASTADDR 0xf6
3542 #define LONGJMP_ADDR 0xf8
3544 #define ACCUM_SAVE 0xfa
3546 #define SRAM_BASE 0x100
3548 #define WAITING_SCB_TAILS 0x100
3550 #define AHD_PCI_CONFIG_BASE 0x100
3552 #define WAITING_TID_HEAD 0x120
3554 #define WAITING_TID_TAIL 0x122
3556 #define NEXT_QUEUED_SCB_ADDR 0x124
3558 #define COMPLETE_SCB_HEAD 0x128
3560 #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a
3562 #define COMPLETE_DMA_SCB_HEAD 0x12c
3564 #define COMPLETE_DMA_SCB_TAIL 0x12e
3566 #define COMPLETE_ON_QFREEZE_HEAD 0x130
3568 #define QFREEZE_COUNT 0x132
3570 #define KERNEL_QFREEZE_COUNT 0x134
3572 #define SAVED_MODE 0x136
3574 #define MSG_OUT 0x137
3576 #define DMAPARAMS 0x138
3577 #define PRELOADEN 0x80
3578 #define WIDEODD 0x40
3581 #define SDMAENACK 0x10
3583 #define HDMAENACK 0x08
3584 #define DIRECTION 0x04
3585 #define FIFOFLUSH 0x02
3586 #define FIFORESET 0x01
3588 #define SEQ_FLAGS 0x139
3589 #define NOT_IDENTIFIED 0x80
3590 #define NO_CDB_SENT 0x40
3591 #define TARGET_CMD_IS_TAGGED 0x40
3593 #define TARG_CMD_PENDING 0x10
3594 #define CMDPHASE_PENDING 0x08
3595 #define DPHASE_PENDING 0x04
3596 #define SPHASE_PENDING 0x02
3597 #define NO_DISCONNECT 0x01
3599 #define SAVED_SCSIID 0x13a
3601 #define SAVED_LUN 0x13b
3603 #define LASTPHASE 0x13c
3604 #define PHASE_MASK 0xe0
3608 #define P_BUSFREE 0x01
3609 #define P_MESGIN 0xe0
3610 #define P_STATUS 0xc0
3611 #define P_MESGOUT 0xa0
3612 #define P_COMMAND 0x80
3613 #define P_DATAIN_DT 0x60
3614 #define P_DATAIN 0x40
3615 #define P_DATAOUT_DT 0x20
3616 #define P_DATAOUT 0x00
3618 #define QOUTFIFO_ENTRY_VALID_TAG 0x13d
3620 #define KERNEL_TQINPOS 0x13e
3622 #define TQINPOS 0x13f
3624 #define SHARED_DATA_ADDR 0x140
3626 #define QOUTFIFO_NEXT_ADDR 0x144
3629 #define RETURN_1 0x148
3630 #define SEND_MSG 0x80
3631 #define SEND_SENSE 0x40
3632 #define SEND_REJ 0x20
3633 #define MSGOUT_PHASEMIS 0x10
3634 #define EXIT_MSG_LOOP 0x08
3635 #define CONT_MSG_LOOP_WRITE 0x04
3636 #define CONT_MSG_LOOP_READ 0x03
3637 #define CONT_MSG_LOOP_TARG 0x02
3640 #define RETURN_2 0x149
3642 #define LAST_MSG 0x14a
3644 #define SCSISEQ_TEMPLATE 0x14b
3645 #define MANUALCTL 0x40
3647 #define ENRSELI 0x10
3648 #define MANUALP 0x0c
3649 #define ENAUTOATNP 0x02
3650 #define ALTSTIM 0x01
3652 #define INITIATOR_TAG 0x14c
3654 #define SEQ_FLAGS2 0x14d
3655 #define SELECTOUT_QFROZEN 0x04
3656 #define TARGET_MSG_PENDING 0x02
3657 #define PENDING_MK_MESSAGE 0x01
3659 #define ALLOCFIFO_SCBPTR 0x14e
3661 #define INT_COALESCING_TIMER 0x150
3663 #define INT_COALESCING_MAXCMDS 0x152
3665 #define INT_COALESCING_MINCMDS 0x153
3667 #define CMDS_PENDING 0x154
3669 #define INT_COALESCING_CMDCOUNT 0x156
3671 #define LOCAL_HS_MAILBOX 0x157
3673 #define CMDSIZE_TABLE 0x158
3675 #define MK_MESSAGE_SCB 0x160
3677 #define MK_MESSAGE_SCSIID 0x162
3679 #define SCB_BASE 0x180
3681 #define SCB_RESIDUAL_DATACNT 0x180
3682 #define SCB_HOST_CDB_PTR 0x180
3683 #define SCB_CDB_STORE 0x180
3685 #define SCB_RESIDUAL_SGPTR 0x184
3686 #define SG_ADDR_MASK 0xf8
3687 #define SG_ADDR_BIT 0x04
3688 #define SG_OVERRUN_RESID 0x02
3690 #define SCB_SCSI_STATUS 0x188
3691 #define SCB_HOST_CDB_LEN 0x188
3693 #define SCB_TARGET_PHASES 0x189
3695 #define SCB_TARGET_DATA_DIR 0x18a
3697 #define SCB_TARGET_ITAG 0x18b
3699 #define SCB_SENSE_BUSADDR 0x18c
3700 #define SCB_NEXT_COMPLETE 0x18c
3702 #define SCB_TAG 0x190
3703 #define SCB_FIFO_USE_COUNT 0x190
3705 #define SCB_CONTROL 0x192
3706 #define TARGET_SCB 0x80
3707 #define DISCENB 0x40
3708 #define TAG_ENB 0x20
3709 #define MK_MESSAGE 0x10
3710 #define STATUS_RCVD 0x08
3711 #define DISCONNECTED 0x04
3712 #define SCB_TAG_TYPE 0x03
3714 #define SCB_SCSIID 0x193
3718 #define SCB_LUN 0x194
3721 #define SCB_TASK_ATTRIBUTE 0x195
3722 #define SCB_XFERLEN_ODD 0x01
3724 #define SCB_CDB_LEN 0x196
3725 #define SCB_CDB_LEN_PTR 0x80
3727 #define SCB_TASK_MANAGEMENT 0x197
3729 #define SCB_DATAPTR 0x198
3731 #define SCB_DATACNT 0x1a0
3732 #define SG_LAST_SEG 0x80
3733 #define SG_HIGH_ADDR_BITS 0x7f
3735 #define SCB_SGPTR 0x1a4
3736 #define SG_STATUS_VALID 0x04
3737 #define SG_FULL_RESID 0x02
3738 #define SG_LIST_NULL 0x01
3740 #define SCB_BUSADDR 0x1a8
3742 #define SCB_NEXT 0x1ac
3743 #define SCB_NEXT_SCB_BUSADDR 0x1ac
3745 #define SCB_NEXT2 0x1ae
3747 #define SCB_SPARE 0x1b0
3748 #define SCB_PKT_LUN 0x1b0
3750 #define SCB_DISCONNECTED_LISTS 0x1b8
3753 #define STATUS_QUEUE_FULL 0x28
3754 #define WRTBIASCTL_HP_DEFAULT 0x00
3755 #define NUMDSPS 0x14
3756 #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04
3757 #define AHD_TIMER_MAX_US 0x18ffe7
3758 #define STIMESEL_MIN 0x18
3759 #define TARGET_CMD_CMPLT 0xfe
3760 #define SEEOP_ERAL_ADDR 0x80
3761 #define SRC_MODE_SHIFT 0x00
3762 #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30
3763 #define MAX_OFFSET_PACED 0xfe
3764 #define SEEOP_EWDS_ADDR 0x00
3765 #define AHD_ANNEXCOL_AMPLITUDE 0x06
3766 #define AHD_PRECOMP_CUTBACK_29 0x06
3767 #define AHD_ANNEXCOL_PER_DEV0 0x04
3768 #define AHD_TIMER_MAX_TICKS 0xffff
3769 #define STATUS_PKT_SENSE 0xff
3770 #define CMD_GROUP_CODE_SHIFT 0x05
3771 #define BUS_8_BIT 0x00
3772 #define CCSGRAM_MAXSEGS 0x10
3773 #define AHD_AMPLITUDE_DEF 0x07
3774 #define AHD_SLEWRATE_DEF_REVB 0x08
3775 #define AHD_PRECOMP_CUTBACK_37 0x07
3776 #define AHD_PRECOMP_SHIFT 0x00
3777 #define PKT_OVERRUN_BUFSIZE 0x200
3778 #define SCB_TRANSFER_SIZE_FULL_LUN 0x38
3779 #define TARGET_DATA_IN 0x01
3780 #define STATUS_BUSY 0x08
3781 #define BUS_16_BIT 0x01
3782 #define CCSCBADDR_MAX 0x80
3783 #define TID_SHIFT 0x04
3784 #define AHD_AMPLITUDE_SHIFT 0x00
3785 #define AHD_SLEWRATE_DEF_REVA 0x08
3786 #define AHD_SLEWRATE_MASK 0x78
3787 #define MAX_OFFSET_PACED_BUG 0x7f
3788 #define AHD_PRECOMP_CUTBACK_17 0x04
3789 #define AHD_PRECOMP_MASK 0x07
3790 #define AHD_TIMER_US_PER_TICK 0x19
3791 #define HOST_MSG 0xff
3792 #define MAX_OFFSET 0xfe
3793 #define BUS_32_BIT 0x02
3794 #define SEEOP_EWEN_ADDR 0xc0
3795 #define AHD_AMPLITUDE_MASK 0x07
3796 #define LUNLEN_SINGLE_LEVEL_LUN 0x0f
3797 #define DST_MODE_SHIFT 0x04
3798 #define STIMESEL_SHIFT 0x03
3799 #define SEEOP_WRAL_ADDR 0x40
3800 #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04
3801 #define MAX_OFFSET_NON_PACED 0x7f
3802 #define NVRAM_SCB_OFFSET 0x2c
3803 #define AHD_SENSE_BUFSIZE 0x100
3804 #define STIMESEL_BUG_ADJ 0x08
3805 #define INVALID_ADDR 0x80
3806 #define CCSGADDR_MAX 0x80
3807 #define MK_MESSAGE_BIT_OFFSET 0x04
3808 #define AHD_SLEWRATE_SHIFT 0x03
3809 #define B_CURRFIFO_0 0x02
3812 /* Downloaded Constant Definitions */
3813 #define SG_SIZEOF 0x04
3814 #define CACHELINE_MASK 0x07
3815 #define SG_PREFETCH_ADDR_MASK 0x03
3816 #define SG_PREFETCH_ALIGN_MASK 0x02
3817 #define SCB_TRANSFER_SIZE 0x06
3818 #define SG_PREFETCH_CNT 0x00
3819 #define SG_PREFETCH_CNT_LIMIT 0x01
3820 #define PKT_OVERRUN_BUFOFFSET 0x05
3821 #define DOWNLOAD_CONST_COUNT 0x08
3824 /* Exported Labels */
3825 #define LABEL_seq_isr 0x28f
3826 #define LABEL_timer_isr 0x28b