2 * Core routines and tables shareable across OS platforms.
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
57 /****************************** Softc Data ************************************/
58 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
60 /***************************** Lookup Tables **********************************/
61 char *ahc_chip_names[] =
80 * Hardware error codes.
82 struct ahc_hard_error_entry {
87 static struct ahc_hard_error_entry ahc_hard_errors[] = {
88 { ILLHADDR, "Illegal Host Access" },
89 { ILLSADDR, "Illegal Sequencer Address referrenced" },
90 { ILLOPCODE, "Illegal Opcode in sequencer program" },
91 { SQPARERR, "Sequencer Parity Error" },
92 { DPARERR, "Data-path Parity Error" },
93 { MPARERR, "Scratch or SCB Memory Parity Error" },
94 { PCIERRSTAT, "PCI Error detected" },
95 { CIOPARERR, "CIOBUS Parity Error" },
97 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
99 static struct ahc_phase_table_entry ahc_phase_table[] =
101 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
102 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
103 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
104 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
105 { P_COMMAND, MSG_NOOP, "in Command phase" },
106 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
107 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
108 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
109 { P_BUSFREE, MSG_NOOP, "while idle" },
110 { 0, MSG_NOOP, "in unknown phase" }
114 * In most cases we only wish to itterate over real phases, so
115 * exclude the last element from the count.
117 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
120 * Valid SCSIRATE values. (p. 3-17)
121 * Provides a mapping of transfer periods in ns to the proper value to
122 * stick in the scsixfer reg.
124 static struct ahc_syncrate ahc_syncrates[] =
126 /* ultra2 fast/ultra period rate */
127 { 0x42, 0x000, 9, "80.0" },
128 { 0x03, 0x000, 10, "40.0" },
129 { 0x04, 0x000, 11, "33.0" },
130 { 0x05, 0x100, 12, "20.0" },
131 { 0x06, 0x110, 15, "16.0" },
132 { 0x07, 0x120, 18, "13.4" },
133 { 0x08, 0x000, 25, "10.0" },
134 { 0x19, 0x010, 31, "8.0" },
135 { 0x1a, 0x020, 37, "6.67" },
136 { 0x1b, 0x030, 43, "5.7" },
137 { 0x1c, 0x040, 50, "5.0" },
138 { 0x00, 0x050, 56, "4.4" },
139 { 0x00, 0x060, 62, "4.0" },
140 { 0x00, 0x070, 68, "3.6" },
141 { 0x00, 0x000, 0, NULL }
144 /* Our Sequencer Program */
145 #include "aic7xxx_seq.h"
147 /**************************** Function Declarations ***************************/
148 static void ahc_force_renegotiation(struct ahc_softc *ahc,
149 struct ahc_devinfo *devinfo);
150 static struct ahc_tmode_tstate*
151 ahc_alloc_tstate(struct ahc_softc *ahc,
152 u_int scsi_id, char channel);
153 #ifdef AHC_TARGET_MODE
154 static void ahc_free_tstate(struct ahc_softc *ahc,
155 u_int scsi_id, char channel, int force);
157 static struct ahc_syncrate*
158 ahc_devlimited_syncrate(struct ahc_softc *ahc,
159 struct ahc_initiator_tinfo *,
163 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
164 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo);
166 static void ahc_scb_devinfo(struct ahc_softc *ahc,
167 struct ahc_devinfo *devinfo,
169 static void ahc_assert_atn(struct ahc_softc *ahc);
170 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
171 struct ahc_devinfo *devinfo,
173 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
174 struct ahc_devinfo *devinfo);
175 static void ahc_construct_sdtr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset);
178 static void ahc_construct_wdtr(struct ahc_softc *ahc,
179 struct ahc_devinfo *devinfo,
181 static void ahc_construct_ppr(struct ahc_softc *ahc,
182 struct ahc_devinfo *devinfo,
183 u_int period, u_int offset,
184 u_int bus_width, u_int ppr_options);
185 static void ahc_clear_msg_state(struct ahc_softc *ahc);
186 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
187 static void ahc_handle_message_phase(struct ahc_softc *ahc);
193 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
194 u_int msgval, int full);
195 static int ahc_parse_msg(struct ahc_softc *ahc,
196 struct ahc_devinfo *devinfo);
197 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
198 struct ahc_devinfo *devinfo);
199 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
200 struct ahc_devinfo *devinfo);
201 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
202 static void ahc_handle_devreset(struct ahc_softc *ahc,
203 struct ahc_devinfo *devinfo,
204 cam_status status, char *message,
206 #ifdef AHC_TARGET_MODE
207 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
208 struct ahc_devinfo *devinfo,
212 static bus_dmamap_callback_t ahc_dmamap_cb;
213 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
214 static int ahc_init_scbdata(struct ahc_softc *ahc);
215 static void ahc_fini_scbdata(struct ahc_softc *ahc);
216 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
217 struct scb *prev_scb,
219 static int ahc_qinfifo_count(struct ahc_softc *ahc);
220 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
221 u_int prev, u_int scbptr);
222 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
223 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
224 u_int scbpos, u_int prev);
225 static void ahc_reset_current_bus(struct ahc_softc *ahc);
227 static void ahc_dumpseq(struct ahc_softc *ahc);
229 static int ahc_loadseq(struct ahc_softc *ahc);
230 static int ahc_check_patch(struct ahc_softc *ahc,
231 struct patch **start_patch,
232 u_int start_instr, u_int *skip_addr);
233 static void ahc_download_instr(struct ahc_softc *ahc,
234 u_int instrptr, uint8_t *dconsts);
235 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
237 struct scb *other_scb);
238 #ifdef AHC_TARGET_MODE
239 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
240 struct ahc_tmode_lstate *lstate,
244 static void ahc_update_scsiid(struct ahc_softc *ahc,
246 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
247 struct target_cmd *cmd);
249 /************************* Sequencer Execution Control ************************/
251 * Restart the sequencer program from address zero
254 ahc_restart(struct ahc_softc *ahc)
259 /* No more pending messages. */
260 ahc_clear_msg_state(ahc);
262 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
263 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
264 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
265 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
266 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
267 ahc_outb(ahc, SAVED_LUN, 0xFF);
270 * Ensure that the sequencer's idea of TQINPOS
271 * matches our own. The sequencer increments TQINPOS
272 * only after it sees a DMA complete and a reset could
273 * occur before the increment leaving the kernel to believe
274 * the command arrived but the sequencer to not.
276 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
278 /* Always allow reselection */
279 ahc_outb(ahc, SCSISEQ,
280 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
281 if ((ahc->features & AHC_CMD_CHAN) != 0) {
282 /* Ensure that no DMA operations are in progress */
283 ahc_outb(ahc, CCSCBCNT, 0);
284 ahc_outb(ahc, CCSGCTL, 0);
285 ahc_outb(ahc, CCSCBCTL, 0);
288 * If we were in the process of DMA'ing SCB data into
289 * an SCB, replace that SCB on the free list. This prevents
292 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
293 ahc_add_curscb_to_free_list(ahc);
294 ahc_outb(ahc, SEQ_FLAGS2,
295 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
299 * Clear any pending sequencer interrupt. It is no
300 * longer relevant since we're resetting the Program
303 ahc_outb(ahc, CLRINT, CLRSEQINT);
305 ahc_outb(ahc, MWI_RESIDUAL, 0);
306 ahc_outb(ahc, SEQCTL, ahc->seqctl);
307 ahc_outb(ahc, SEQADDR0, 0);
308 ahc_outb(ahc, SEQADDR1, 0);
313 /************************* Input/Output Queues ********************************/
315 ahc_run_qoutfifo(struct ahc_softc *ahc)
320 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
321 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
322 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
323 if ((ahc->qoutfifonext & 0x03) == 0x03) {
327 * Clear 32bits of QOUTFIFO at a time
328 * so that we don't clobber an incoming
329 * byte DMA to the array on architectures
330 * that only support 32bit load and store
333 modnext = ahc->qoutfifonext & ~0x3;
334 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
335 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
336 ahc->shared_data_dmamap,
337 /*offset*/modnext, /*len*/4,
338 BUS_DMASYNC_PREREAD);
342 scb = ahc_lookup_scb(ahc, scb_index);
344 printf("%s: WARNING no command for scb %d "
345 "(cmdcmplt)\nQOUTPOS = %d\n",
346 ahc_name(ahc), scb_index,
347 (ahc->qoutfifonext - 1) & 0xFF);
352 * Save off the residual
355 ahc_update_residual(ahc, scb);
361 ahc_run_untagged_queues(struct ahc_softc *ahc)
365 for (i = 0; i < 16; i++)
366 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
370 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
374 if (ahc->untagged_queue_lock != 0)
377 if ((scb = TAILQ_FIRST(queue)) != NULL
378 && (scb->flags & SCB_ACTIVE) == 0) {
379 scb->flags |= SCB_ACTIVE;
381 * Timers are disabled while recovery is in progress.
383 aic_scb_timer_start(scb);
384 ahc_queue_scb(ahc, scb);
388 /************************* Interrupt Handling *********************************/
390 ahc_handle_brkadrint(struct ahc_softc *ahc)
393 * We upset the sequencer :-(
394 * Lookup the error message
399 error = ahc_inb(ahc, ERROR);
400 for (i = 0; error != 1 && i < num_errors; i++)
402 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
403 ahc_name(ahc), ahc_hard_errors[i].errmesg,
404 ahc_inb(ahc, SEQADDR0) |
405 (ahc_inb(ahc, SEQADDR1) << 8));
407 ahc_dump_card_state(ahc);
409 /* Tell everyone that this HBA is no longer available */
410 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
411 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
414 /* Disable all interrupt sources by resetting the controller */
419 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
422 struct ahc_devinfo devinfo;
424 ahc_fetch_devinfo(ahc, &devinfo);
427 * Clear the upper byte that holds SEQINT status
428 * codes and clear the SEQINT bit. We will unpause
429 * the sequencer, if appropriate, after servicing
432 ahc_outb(ahc, CLRINT, CLRSEQINT);
433 switch (intstat & SEQINT_MASK) {
437 struct hardware_scb *hscb;
440 * Set the default return value to 0 (don't
441 * send sense). The sense code will change
444 ahc_outb(ahc, RETURN_1, 0);
447 * The sequencer will notify us when a command
448 * has an error that would be of interest to
449 * the kernel. This allows us to leave the sequencer
450 * running in the common case of command completes
451 * without error. The sequencer will already have
452 * dma'd the SCB back up to us, so we can reference
453 * the in kernel copy directly.
455 scb_index = ahc_inb(ahc, SCB_TAG);
456 scb = ahc_lookup_scb(ahc, scb_index);
458 ahc_print_devinfo(ahc, &devinfo);
459 printf("ahc_intr - referenced scb "
460 "not valid during seqint 0x%x scb(%d)\n",
462 ahc_dump_card_state(ahc);
469 /* Don't want to clobber the original sense code */
470 if ((scb->flags & SCB_SENSE) != 0) {
472 * Clear the SCB_SENSE Flag and have
473 * the sequencer do a normal command
476 scb->flags &= ~SCB_SENSE;
477 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
480 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
481 /* Freeze the queue until the client sees the error. */
482 ahc_freeze_devq(ahc, scb);
484 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
485 switch (hscb->shared_data.status.scsi_status) {
487 printf("%s: Interrupted for staus of 0???\n",
490 case SCSI_STATUS_CMD_TERMINATED:
491 case SCSI_STATUS_CHECK_COND:
493 struct ahc_dma_seg *sg;
494 struct scsi_sense *sc;
495 struct ahc_initiator_tinfo *targ_info;
496 struct ahc_tmode_tstate *tstate;
497 struct ahc_transinfo *tinfo;
499 if (ahc_debug & AHC_SHOW_SENSE) {
500 ahc_print_path(ahc, scb);
501 printf("SCB %d: requests Check Status\n",
506 if (aic_perform_autosense(scb) == 0)
509 targ_info = ahc_fetch_transinfo(ahc,
514 tinfo = &targ_info->curr;
516 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
518 * Save off the residual if there is one.
520 ahc_update_residual(ahc, scb);
522 if (ahc_debug & AHC_SHOW_SENSE) {
523 ahc_print_path(ahc, scb);
524 printf("Sending Sense\n");
527 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
528 sg->len = aic_get_sense_bufsize(ahc, scb);
529 sg->len |= AHC_DMA_LAST_SEG;
531 /* Fixup byte order */
532 sg->addr = aic_htole32(sg->addr);
533 sg->len = aic_htole32(sg->len);
535 sc->opcode = REQUEST_SENSE;
537 if (tinfo->protocol_version <= SCSI_REV_2
538 && SCB_GET_LUN(scb) < 8)
539 sc->byte2 = SCB_GET_LUN(scb) << 5;
542 sc->length = sg->len;
546 * We can't allow the target to disconnect.
547 * This will be an untagged transaction and
548 * having the target disconnect will make this
549 * transaction indestinguishable from outstanding
550 * tagged transactions.
555 * This request sense could be because the
556 * the device lost power or in some other
557 * way has lost our transfer negotiations.
558 * Renegotiate if appropriate. Unit attention
559 * errors will be reported before any data
562 if (aic_get_residual(scb)
563 == aic_get_transfer_length(scb)) {
564 ahc_update_neg_request(ahc, &devinfo,
566 AHC_NEG_IF_NON_ASYNC);
568 if (tstate->auto_negotiate & devinfo.target_mask) {
569 hscb->control |= MK_MESSAGE;
570 scb->flags &= ~SCB_NEGOTIATE;
571 scb->flags |= SCB_AUTO_NEGOTIATE;
573 hscb->cdb_len = sizeof(*sc);
574 hscb->dataptr = sg->addr;
575 hscb->datacnt = sg->len;
576 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
577 hscb->sgptr = aic_htole32(hscb->sgptr);
579 scb->flags |= SCB_SENSE;
580 ahc_qinfifo_requeue_tail(ahc, scb);
581 ahc_outb(ahc, RETURN_1, SEND_SENSE);
583 * Ensure we have enough time to actually
584 * retrieve the sense, but only schedule
585 * the timer if we are not in recovery or
586 * this is a recovery SCB that is allowed
587 * to have an active timer.
589 if (ahc->scb_data->recovery_scbs == 0
590 || (scb->flags & SCB_RECOVERY_SCB) != 0)
591 aic_scb_timer_reset(scb, 5 * 1000);
601 /* Ensure we don't leave the selection hardware on */
602 ahc_outb(ahc, SCSISEQ,
603 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
605 printf("%s:%c:%d: no active SCB for reconnecting "
606 "target - issuing BUS DEVICE RESET\n",
607 ahc_name(ahc), devinfo.channel, devinfo.target);
608 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
609 "ARG_1 == 0x%x ACCUM = 0x%x\n",
610 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
611 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
612 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
614 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
615 ahc_index_busy_tcl(ahc,
616 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
617 ahc_inb(ahc, SAVED_LUN))),
618 ahc_inb(ahc, SINDEX));
619 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
620 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
621 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
622 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
623 ahc_inb(ahc, SCB_CONTROL));
624 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
625 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
626 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
627 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
628 ahc_dump_card_state(ahc);
629 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
631 ahc->msgout_index = 0;
632 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
633 ahc_outb(ahc, MSG_OUT, HOST_MSG);
639 u_int rejbyte = ahc_inb(ahc, ACCUM);
640 printf("%s:%c:%d: Warning - unknown message received from "
641 "target (0x%x). Rejecting\n",
642 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
645 case PROTO_VIOLATION:
647 ahc_handle_proto_violation(ahc);
651 ahc_handle_ign_wide_residue(ahc, &devinfo);
654 ahc_reinitialize_dataptrs(ahc);
660 lastphase = ahc_inb(ahc, LASTPHASE);
661 printf("%s:%c:%d: unknown scsi bus phase %x, "
662 "lastphase = 0x%x. Attempting to continue\n",
663 ahc_name(ahc), devinfo.channel, devinfo.target,
664 lastphase, ahc_inb(ahc, SCSISIGI));
671 lastphase = ahc_inb(ahc, LASTPHASE);
672 printf("%s:%c:%d: Missed busfree. "
673 "Lastphase = 0x%x, Curphase = 0x%x\n",
674 ahc_name(ahc), devinfo.channel, devinfo.target,
675 lastphase, ahc_inb(ahc, SCSISIGI));
682 * The sequencer has encountered a message phase
683 * that requires host assistance for completion.
684 * While handling the message phase(s), we will be
685 * notified by the sequencer after each byte is
686 * transferred so we can track bus phase changes.
688 * If this is the first time we've seen a HOST_MSG_LOOP
689 * interrupt, initialize the state of the host message
692 if (ahc->msg_type == MSG_TYPE_NONE) {
697 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
698 if (bus_phase != P_MESGIN
699 && bus_phase != P_MESGOUT) {
700 printf("ahc_intr: HOST_MSG_LOOP bad "
704 * Probably transitioned to bus free before
705 * we got here. Just punt the message.
707 ahc_clear_intstat(ahc);
712 scb_index = ahc_inb(ahc, SCB_TAG);
713 scb = ahc_lookup_scb(ahc, scb_index);
714 if (devinfo.role == ROLE_INITIATOR) {
716 panic("HOST_MSG_LOOP with "
717 "invalid SCB %x\n", scb_index);
719 if (bus_phase == P_MESGOUT)
720 ahc_setup_initiator_msgout(ahc,
725 MSG_TYPE_INITIATOR_MSGIN;
726 ahc->msgin_index = 0;
729 #ifdef AHC_TARGET_MODE
731 if (bus_phase == P_MESGOUT) {
733 MSG_TYPE_TARGET_MSGOUT;
734 ahc->msgin_index = 0;
737 ahc_setup_target_msgin(ahc,
744 ahc_handle_message_phase(ahc);
750 * If we've cleared the parity error interrupt
751 * but the sequencer still believes that SCSIPERR
752 * is true, it must be that the parity error is
753 * for the currently presented byte on the bus,
754 * and we are not in a phase (data-in) where we will
755 * eventually ack this byte. Ack the byte and
756 * throw it away in the hope that the target will
757 * take us to message out to deliver the appropriate
760 if ((intstat & SCSIINT) == 0
761 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
762 if ((ahc->features & AHC_DT) == 0) {
766 * The hardware will only let you ack bytes
767 * if the expected phase in SCSISIGO matches
768 * the current phase. Make sure this is
769 * currently the case.
771 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
772 ahc_outb(ahc, LASTPHASE, curphase);
773 ahc_outb(ahc, SCSISIGO, curphase);
775 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
779 * In a data phase. Faster to bitbucket
780 * the data than to individually ack each
781 * byte. This is also the only strategy
782 * that will work with AUTOACK enabled.
784 ahc_outb(ahc, SXFRCTL1,
785 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
787 while (--wait != 0) {
788 if ((ahc_inb(ahc, SCSISIGI)
793 ahc_outb(ahc, SXFRCTL1,
794 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
799 ahc_print_devinfo(ahc, &devinfo);
800 printf("Unable to clear parity error. "
802 scb_index = ahc_inb(ahc, SCB_TAG);
803 scb = ahc_lookup_scb(ahc, scb_index);
805 aic_set_transaction_status(scb,
807 ahc_reset_channel(ahc, devinfo.channel,
811 ahc_inb(ahc, SCSIDATL);
819 * When the sequencer detects an overrun, it
820 * places the controller in "BITBUCKET" mode
821 * and allows the target to complete its transfer.
822 * Unfortunately, none of the counters get updated
823 * when the controller is in this mode, so we have
824 * no way of knowing how large the overrun was.
826 u_int scbindex = ahc_inb(ahc, SCB_TAG);
827 u_int lastphase = ahc_inb(ahc, LASTPHASE);
830 scb = ahc_lookup_scb(ahc, scbindex);
831 for (i = 0; i < num_phases; i++) {
832 if (lastphase == ahc_phase_table[i].phase)
835 ahc_print_path(ahc, scb);
836 printf("data overrun detected %s."
838 ahc_phase_table[i].phasemsg,
840 ahc_print_path(ahc, scb);
841 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
842 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
843 aic_get_transfer_length(scb), scb->sg_count);
844 if (scb->sg_count > 0) {
845 for (i = 0; i < scb->sg_count; i++) {
846 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
848 (aic_le32toh(scb->sg_list[i].len) >> 24
849 & SG_HIGH_ADDR_BITS),
850 aic_le32toh(scb->sg_list[i].addr),
851 aic_le32toh(scb->sg_list[i].len)
856 * Set this and it will take effect when the
857 * target does a command complete.
859 ahc_freeze_devq(ahc, scb);
860 if ((scb->flags & SCB_SENSE) == 0) {
861 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
863 scb->flags &= ~SCB_SENSE;
864 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
868 if ((ahc->features & AHC_ULTRA2) != 0) {
870 * Clear the channel in case we return
871 * to data phase later.
873 ahc_outb(ahc, SXFRCTL0,
874 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
875 ahc_outb(ahc, SXFRCTL0,
876 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
878 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
881 /* Ensure HHADDR is 0 for future DMA operations. */
882 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
883 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
884 ahc_outb(ahc, HADDR, 0);
885 ahc_outb(ahc, DSCOMMAND1, dscommand1);
893 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
894 ahc_name(ahc), devinfo.channel, devinfo.target,
896 scbindex = ahc_inb(ahc, SCB_TAG);
897 scb = ahc_lookup_scb(ahc, scbindex);
899 && (scb->flags & SCB_RECOVERY_SCB) != 0)
901 * Ensure that we didn't put a second instance of this
902 * SCB into the QINFIFO.
904 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
905 SCB_GET_CHANNEL(ahc, scb),
906 SCB_GET_LUN(scb), scb->hscb->tag,
907 ROLE_INITIATOR, /*status*/0,
913 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
914 ahc_dump_card_state(ahc);
922 scbptr = ahc_inb(ahc, SCBPTR);
923 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
924 scbptr, ahc_inb(ahc, ARG_1),
925 ahc->scb_data->hscbs[scbptr].tag);
926 ahc_dump_card_state(ahc);
932 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
933 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
934 "ARG_1 == 0x%x ACCUM = 0x%x\n",
935 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
936 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
937 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
938 "SINDEX == 0x%x\n, A == 0x%x\n",
939 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
940 ahc_index_busy_tcl(ahc,
941 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
942 ahc_inb(ahc, SAVED_LUN))),
943 ahc_inb(ahc, SINDEX),
944 ahc_inb(ahc, ACCUM));
945 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
946 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
947 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
948 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
949 ahc_inb(ahc, SCB_CONTROL));
950 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
951 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
952 ahc_dump_card_state(ahc);
957 printf("ahc_intr: seqint, "
958 "intstat == 0x%x, scsisigi = 0x%x\n",
959 intstat, ahc_inb(ahc, SCSISIGI));
964 * The sequencer is paused immediately on
965 * a SEQINT, so we should restart it when
972 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
981 if ((ahc->features & AHC_TWIN) != 0
982 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
986 intr_channel = cur_channel;
988 if ((ahc->features & AHC_ULTRA2) != 0)
989 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
992 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
993 if (status == 0 && status0 == 0) {
994 if ((ahc->features & AHC_TWIN) != 0) {
995 /* Try the other channel */
996 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
997 status = ahc_inb(ahc, SSTAT1)
998 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
999 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1002 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1003 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1009 /* Make sure the sequencer is in a safe location. */
1010 ahc_clear_critical_section(ahc);
1012 scb_index = ahc_inb(ahc, SCB_TAG);
1013 scb = ahc_lookup_scb(ahc, scb_index);
1015 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1018 if ((ahc->features & AHC_ULTRA2) != 0
1019 && (status0 & IOERR) != 0) {
1022 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1023 printf("%s: Transceiver State Has Changed to %s mode\n",
1024 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1025 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1027 * When transitioning to SE mode, the reset line
1028 * glitches, triggering an arbitration bug in some
1029 * Ultra2 controllers. This bug is cleared when we
1030 * assert the reset line. Since a reset glitch has
1031 * already occurred with this transition and a
1032 * transceiver state change is handled just like
1033 * a bus reset anyway, asserting the reset line
1034 * ourselves is safe.
1036 ahc_reset_channel(ahc, intr_channel,
1037 /*Initiate Reset*/now_lvd == 0);
1038 } else if ((status & SCSIRSTI) != 0) {
1039 printf("%s: Someone reset channel %c\n",
1040 ahc_name(ahc), intr_channel);
1041 if (intr_channel != cur_channel)
1042 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1043 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1044 } else if ((status & SCSIPERR) != 0) {
1046 * Determine the bus phase and queue an appropriate message.
1047 * SCSIPERR is latched true as soon as a parity error
1048 * occurs. If the sequencer acked the transfer that
1049 * caused the parity error and the currently presented
1050 * transfer on the bus has correct parity, SCSIPERR will
1051 * be cleared by CLRSCSIPERR. Use this to determine if
1052 * we should look at the last phase the sequencer recorded,
1053 * or the current phase presented on the bus.
1055 struct ahc_devinfo devinfo;
1065 lastphase = ahc_inb(ahc, LASTPHASE);
1066 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1067 sstat2 = ahc_inb(ahc, SSTAT2);
1068 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1070 * For all phases save DATA, the sequencer won't
1071 * automatically ack a byte that has a parity error
1072 * in it. So the only way that the current phase
1073 * could be 'data-in' is if the parity error is for
1074 * an already acked byte in the data phase. During
1075 * synchronous data-in transfers, we may actually
1076 * ack bytes before latching the current phase in
1077 * LASTPHASE, leading to the discrepancy between
1078 * curphase and lastphase.
1080 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1081 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1082 errorphase = curphase;
1084 errorphase = lastphase;
1086 for (i = 0; i < num_phases; i++) {
1087 if (errorphase == ahc_phase_table[i].phase)
1090 mesg_out = ahc_phase_table[i].mesg_out;
1093 if (SCB_IS_SILENT(scb))
1096 ahc_print_path(ahc, scb);
1097 scb->flags |= SCB_TRANSMISSION_ERROR;
1099 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1100 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1101 scsirate = ahc_inb(ahc, SCSIRATE);
1102 if (silent == FALSE) {
1103 printf("parity error detected %s. "
1104 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1105 ahc_phase_table[i].phasemsg,
1106 ahc_inw(ahc, SEQADDR0),
1108 if ((ahc->features & AHC_DT) != 0) {
1109 if ((sstat2 & CRCVALERR) != 0)
1110 printf("\tCRC Value Mismatch\n");
1111 if ((sstat2 & CRCENDERR) != 0)
1112 printf("\tNo terminal CRC packet "
1114 if ((sstat2 & CRCREQERR) != 0)
1115 printf("\tIllegal CRC packet "
1117 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1118 printf("\tUnexpected %sDT Data Phase\n",
1119 (scsirate & SINGLE_EDGE)
1124 if ((ahc->features & AHC_DT) != 0
1125 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1127 * This error applies regardless of
1128 * data direction, so ignore the value
1129 * in the phase table.
1131 mesg_out = MSG_INITIATOR_DET_ERR;
1135 * We've set the hardware to assert ATN if we
1136 * get a parity error on "in" phases, so all we
1137 * need to do is stuff the message buffer with
1138 * the appropriate message. "In" phases have set
1139 * mesg_out to something other than MSG_NOP.
1141 if (mesg_out != MSG_NOOP) {
1142 if (ahc->msg_type != MSG_TYPE_NONE)
1143 ahc->send_msg_perror = TRUE;
1145 ahc_outb(ahc, MSG_OUT, mesg_out);
1148 * Force a renegotiation with this target just in
1149 * case we are out of sync for some external reason
1150 * unknown (or unreported) by the target.
1152 ahc_fetch_devinfo(ahc, &devinfo);
1153 ahc_force_renegotiation(ahc, &devinfo);
1155 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1157 } else if ((status & SELTO) != 0) {
1160 /* Stop the selection */
1161 ahc_outb(ahc, SCSISEQ, 0);
1163 /* No more pending messages */
1164 ahc_clear_msg_state(ahc);
1166 /* Clear interrupt state */
1167 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1168 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1171 * Although the driver does not care about the
1172 * 'Selection in Progress' status bit, the busy
1173 * LED does. SELINGO is only cleared by a successful
1174 * selection, so we must manually clear it to insure
1175 * the LED turns off just incase no future successful
1176 * selections occur (e.g. no devices on the bus).
1178 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1180 scbptr = ahc_inb(ahc, WAITING_SCBH);
1181 ahc_outb(ahc, SCBPTR, scbptr);
1182 scb_index = ahc_inb(ahc, SCB_TAG);
1184 scb = ahc_lookup_scb(ahc, scb_index);
1186 printf("%s: ahc_intr - referenced scb not "
1187 "valid during SELTO scb(%d, %d)\n",
1188 ahc_name(ahc), scbptr, scb_index);
1189 ahc_dump_card_state(ahc);
1191 struct ahc_devinfo devinfo;
1193 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1194 ahc_print_path(ahc, scb);
1195 printf("Saw Selection Timeout for SCB 0x%x\n",
1199 ahc_scb_devinfo(ahc, &devinfo, scb);
1200 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1201 ahc_freeze_devq(ahc, scb);
1204 * Cancel any pending transactions on the device
1205 * now that it seems to be missing. This will
1206 * also revert us to async/narrow transfers until
1207 * we can renegotiate with the device.
1209 ahc_handle_devreset(ahc, &devinfo,
1211 "Selection Timeout",
1212 /*verbose_level*/1);
1214 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1216 } else if ((status & BUSFREE) != 0
1217 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1218 struct ahc_devinfo devinfo;
1223 u_int initiator_role_id;
1228 * Clear our selection hardware as soon as possible.
1229 * We may have an entry in the waiting Q for this target,
1230 * that is affected by this busfree and we don't want to
1231 * go about selecting the target while we handle the event.
1233 ahc_outb(ahc, SCSISEQ,
1234 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1237 * Disable busfree interrupts and clear the busfree
1238 * interrupt status. We do this here so that several
1239 * bus transactions occur prior to clearing the SCSIINT
1240 * latch. It can take a bit for the clearing to take effect.
1242 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1243 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1246 * Look at what phase we were last in.
1247 * If its message out, chances are pretty good
1248 * that the busfree was in response to one of
1249 * our abort requests.
1251 lastphase = ahc_inb(ahc, LASTPHASE);
1252 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1253 saved_lun = ahc_inb(ahc, SAVED_LUN);
1254 target = SCSIID_TARGET(ahc, saved_scsiid);
1255 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1256 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1257 ahc_compile_devinfo(&devinfo, initiator_role_id,
1258 target, saved_lun, channel, ROLE_INITIATOR);
1261 if (lastphase == P_MESGOUT) {
1264 tag = SCB_LIST_NULL;
1265 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1266 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1267 if (ahc->msgout_buf[ahc->msgout_index - 1]
1269 tag = scb->hscb->tag;
1270 ahc_print_path(ahc, scb);
1271 printf("SCB %d - Abort%s Completed.\n",
1272 scb->hscb->tag, tag == SCB_LIST_NULL ?
1274 ahc_abort_scbs(ahc, target, channel,
1279 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1280 MSG_BUS_DEV_RESET, TRUE)) {
1283 * Don't mark the user's request for this BDR
1284 * as completing with CAM_BDR_SENT. CAM3
1285 * specifies CAM_REQ_CMP.
1288 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1289 && ahc_match_scb(ahc, scb, target, channel,
1293 aic_set_transaction_status(scb, CAM_REQ_CMP);
1296 ahc_compile_devinfo(&devinfo,
1302 ahc_handle_devreset(ahc, &devinfo,
1305 /*verbose_level*/0);
1307 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1308 MSG_EXT_PPR, FALSE)) {
1309 struct ahc_initiator_tinfo *tinfo;
1310 struct ahc_tmode_tstate *tstate;
1313 * PPR Rejected. Try non-ppr negotiation
1314 * and retry command.
1316 tinfo = ahc_fetch_transinfo(ahc,
1321 tinfo->curr.transport_version = 2;
1322 tinfo->goal.transport_version = 2;
1323 tinfo->goal.ppr_options = 0;
1324 ahc_qinfifo_requeue_tail(ahc, scb);
1326 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1327 MSG_EXT_WDTR, FALSE)) {
1329 * Negotiation Rejected. Go-narrow and
1332 ahc_set_width(ahc, &devinfo,
1333 MSG_EXT_WDTR_BUS_8_BIT,
1334 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1336 ahc_qinfifo_requeue_tail(ahc, scb);
1338 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1339 MSG_EXT_SDTR, FALSE)) {
1341 * Negotiation Rejected. Go-async and
1344 ahc_set_syncrate(ahc, &devinfo,
1346 /*period*/0, /*offset*/0,
1348 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1350 ahc_qinfifo_requeue_tail(ahc, scb);
1354 if (printerror != 0) {
1360 if ((scb->hscb->control & TAG_ENB) != 0)
1361 tag = scb->hscb->tag;
1363 tag = SCB_LIST_NULL;
1364 ahc_print_path(ahc, scb);
1365 ahc_abort_scbs(ahc, target, channel,
1366 SCB_GET_LUN(scb), tag,
1371 * We had not fully identified this connection,
1372 * so we cannot abort anything.
1374 printf("%s: ", ahc_name(ahc));
1376 for (i = 0; i < num_phases; i++) {
1377 if (lastphase == ahc_phase_table[i].phase)
1380 if (lastphase != P_BUSFREE) {
1382 * Renegotiate with this device at the
1383 * next opportunity just in case this busfree
1384 * is due to a negotiation mismatch with the
1387 ahc_force_renegotiation(ahc, &devinfo);
1389 printf("Unexpected busfree %s\n"
1390 "SEQADDR == 0x%x\n",
1391 ahc_phase_table[i].phasemsg,
1392 ahc_inb(ahc, SEQADDR0)
1393 | (ahc_inb(ahc, SEQADDR1) << 8));
1395 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1398 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1399 ahc_name(ahc), status);
1400 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1405 * Force renegotiation to occur the next time we initiate
1406 * a command to the current device.
1409 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1411 struct ahc_initiator_tinfo *targ_info;
1412 struct ahc_tmode_tstate *tstate;
1414 targ_info = ahc_fetch_transinfo(ahc,
1416 devinfo->our_scsiid,
1419 ahc_update_neg_request(ahc, devinfo, tstate,
1420 targ_info, AHC_NEG_IF_NON_ASYNC);
1423 #define AHC_MAX_STEPS 2000
1425 ahc_clear_critical_section(struct ahc_softc *ahc)
1432 if (ahc->num_critical_sections == 0)
1444 seqaddr = ahc_inb(ahc, SEQADDR0)
1445 | (ahc_inb(ahc, SEQADDR1) << 8);
1448 * Seqaddr represents the next instruction to execute,
1449 * so we are really executing the instruction just
1452 cs = ahc->critical_sections;
1453 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1455 if (cs->begin < seqaddr && cs->end >= seqaddr)
1459 if (i == ahc->num_critical_sections)
1462 if (steps > AHC_MAX_STEPS) {
1463 printf("%s: Infinite loop in critical section\n",
1465 ahc_dump_card_state(ahc);
1466 panic("critical section loop");
1470 if (stepping == FALSE) {
1472 * Disable all interrupt sources so that the
1473 * sequencer will not be stuck by a pausing
1474 * interrupt condition while we attempt to
1475 * leave a critical section.
1477 simode0 = ahc_inb(ahc, SIMODE0);
1478 ahc_outb(ahc, SIMODE0, 0);
1479 simode1 = ahc_inb(ahc, SIMODE1);
1480 if ((ahc->features & AHC_DT) != 0)
1482 * On DT class controllers, we
1483 * use the enhanced busfree logic.
1484 * Unfortunately we cannot re-enable
1485 * busfree detection within the
1486 * current connection, so we must
1487 * leave it on while single stepping.
1489 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1491 ahc_outb(ahc, SIMODE1, 0);
1492 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1493 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1496 if ((ahc->features & AHC_DT) != 0) {
1497 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1498 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1500 ahc_outb(ahc, HCNTRL, ahc->unpause);
1501 while (!ahc_is_paused(ahc))
1505 ahc_outb(ahc, SIMODE0, simode0);
1506 ahc_outb(ahc, SIMODE1, simode1);
1507 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1512 * Clear any pending interrupt status.
1515 ahc_clear_intstat(struct ahc_softc *ahc)
1517 /* Clear any interrupt conditions this may have caused */
1518 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1519 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1521 ahc_flush_device_writes(ahc);
1522 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1523 ahc_flush_device_writes(ahc);
1524 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1525 ahc_flush_device_writes(ahc);
1528 /**************************** Debugging Routines ******************************/
1530 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1534 ahc_print_scb(struct scb *scb)
1538 struct hardware_scb *hscb = scb->hscb;
1540 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1546 printf("Shared Data: ");
1547 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1548 printf("%#02x", hscb->shared_data.cdb[i]);
1549 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1550 aic_le32toh(hscb->dataptr),
1551 aic_le32toh(hscb->datacnt),
1552 aic_le32toh(hscb->sgptr),
1554 if (scb->sg_count > 0) {
1555 for (i = 0; i < scb->sg_count; i++) {
1556 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1558 (aic_le32toh(scb->sg_list[i].len) >> 24
1559 & SG_HIGH_ADDR_BITS),
1560 aic_le32toh(scb->sg_list[i].addr),
1561 aic_le32toh(scb->sg_list[i].len));
1566 /************************* Transfer Negotiation *******************************/
1568 * Allocate per target mode instance (ID we respond to as a target)
1569 * transfer negotiation data structures.
1571 static struct ahc_tmode_tstate *
1572 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1574 struct ahc_tmode_tstate *master_tstate;
1575 struct ahc_tmode_tstate *tstate;
1578 master_tstate = ahc->enabled_targets[ahc->our_id];
1579 if (channel == 'B') {
1581 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1583 if (ahc->enabled_targets[scsi_id] != NULL
1584 && ahc->enabled_targets[scsi_id] != master_tstate)
1585 panic("%s: ahc_alloc_tstate - Target already allocated",
1587 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1588 M_DEVBUF, M_NOWAIT);
1593 * If we have allocated a master tstate, copy user settings from
1594 * the master tstate (taken from SRAM or the EEPROM) for this
1595 * channel, but reset our current and goal settings to async/narrow
1596 * until an initiator talks to us.
1598 if (master_tstate != NULL) {
1599 memcpy(tstate, master_tstate, sizeof(*tstate));
1600 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1601 tstate->ultraenb = 0;
1602 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1603 memset(&tstate->transinfo[i].curr, 0,
1604 sizeof(tstate->transinfo[i].curr));
1605 memset(&tstate->transinfo[i].goal, 0,
1606 sizeof(tstate->transinfo[i].goal));
1609 memset(tstate, 0, sizeof(*tstate));
1610 ahc->enabled_targets[scsi_id] = tstate;
1614 #ifdef AHC_TARGET_MODE
1616 * Free per target mode instance (ID we respond to as a target)
1617 * transfer negotiation data structures.
1620 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1622 struct ahc_tmode_tstate *tstate;
1625 * Don't clean up our "master" tstate.
1626 * It has our default user settings.
1628 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1629 || (channel == 'A' && scsi_id == ahc->our_id))
1635 tstate = ahc->enabled_targets[scsi_id];
1637 free(tstate, M_DEVBUF);
1638 ahc->enabled_targets[scsi_id] = NULL;
1643 * Called when we have an active connection to a target on the bus,
1644 * this function finds the nearest syncrate to the input period limited
1645 * by the capabilities of the bus connectivity of and sync settings for
1648 struct ahc_syncrate *
1649 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1650 struct ahc_initiator_tinfo *tinfo,
1651 u_int *period, u_int *ppr_options, role_t role)
1653 struct ahc_transinfo *transinfo;
1656 if ((ahc->features & AHC_ULTRA2) != 0) {
1657 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1658 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1659 maxsync = AHC_SYNCRATE_DT;
1661 maxsync = AHC_SYNCRATE_ULTRA;
1662 /* Can't do DT on an SE bus */
1663 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1665 } else if ((ahc->features & AHC_ULTRA) != 0) {
1666 maxsync = AHC_SYNCRATE_ULTRA;
1668 maxsync = AHC_SYNCRATE_FAST;
1671 * Never allow a value higher than our current goal
1672 * period otherwise we may allow a target initiated
1673 * negotiation to go above the limit as set by the
1674 * user. In the case of an initiator initiated
1675 * sync negotiation, we limit based on the user
1676 * setting. This allows the system to still accept
1677 * incoming negotiations even if target initiated
1678 * negotiation is not performed.
1680 if (role == ROLE_TARGET)
1681 transinfo = &tinfo->user;
1683 transinfo = &tinfo->goal;
1684 *ppr_options &= transinfo->ppr_options;
1685 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1686 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1687 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1689 if (transinfo->period == 0) {
1694 *period = MAX(*period, transinfo->period);
1695 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1699 * Look up the valid period to SCSIRATE conversion in our table.
1700 * Return the period and offset that should be sent to the target
1701 * if this was the beginning of an SDTR.
1703 struct ahc_syncrate *
1704 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1705 u_int *ppr_options, u_int maxsync)
1707 struct ahc_syncrate *syncrate;
1709 if ((ahc->features & AHC_DT) == 0)
1710 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1712 /* Skip all DT only entries if DT is not available */
1713 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1714 && maxsync < AHC_SYNCRATE_ULTRA2)
1715 maxsync = AHC_SYNCRATE_ULTRA2;
1717 for (syncrate = &ahc_syncrates[maxsync];
1718 syncrate->rate != NULL;
1721 * The Ultra2 table doesn't go as low
1722 * as for the Fast/Ultra cards.
1724 if ((ahc->features & AHC_ULTRA2) != 0
1725 && (syncrate->sxfr_u2 == 0))
1728 if (*period <= syncrate->period) {
1730 * When responding to a target that requests
1731 * sync, the requested rate may fall between
1732 * two rates that we can output, but still be
1733 * a rate that we can receive. Because of this,
1734 * we want to respond to the target with
1735 * the same rate that it sent to us even
1736 * if the period we use to send data to it
1737 * is lower. Only lower the response period
1740 if (syncrate == &ahc_syncrates[maxsync])
1741 *period = syncrate->period;
1744 * At some speeds, we only support
1747 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1748 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1754 || (syncrate->rate == NULL)
1755 || ((ahc->features & AHC_ULTRA2) != 0
1756 && (syncrate->sxfr_u2 == 0))) {
1757 /* Use asynchronous transfers. */
1760 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1766 * Convert from an entry in our syncrate table to the SCSI equivalent
1767 * sync "period" factor.
1770 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1772 struct ahc_syncrate *syncrate;
1774 if ((ahc->features & AHC_ULTRA2) != 0)
1775 scsirate &= SXFR_ULTRA2;
1779 syncrate = &ahc_syncrates[maxsync];
1780 while (syncrate->rate != NULL) {
1781 if ((ahc->features & AHC_ULTRA2) != 0) {
1782 if (syncrate->sxfr_u2 == 0)
1784 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1785 return (syncrate->period);
1786 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1787 return (syncrate->period);
1791 return (0); /* async */
1795 * Truncate the given synchronous offset to a value the
1796 * current adapter type and syncrate are capable of.
1799 ahc_validate_offset(struct ahc_softc *ahc,
1800 struct ahc_initiator_tinfo *tinfo,
1801 struct ahc_syncrate *syncrate,
1802 u_int *offset, int wide, role_t role)
1806 /* Limit offset to what we can do */
1807 if (syncrate == NULL) {
1809 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1810 maxoffset = MAX_OFFSET_ULTRA2;
1813 maxoffset = MAX_OFFSET_16BIT;
1815 maxoffset = MAX_OFFSET_8BIT;
1817 *offset = MIN(*offset, maxoffset);
1818 if (tinfo != NULL) {
1819 if (role == ROLE_TARGET)
1820 *offset = MIN(*offset, tinfo->user.offset);
1822 *offset = MIN(*offset, tinfo->goal.offset);
1827 * Truncate the given transfer width parameter to a value the
1828 * current adapter type is capable of.
1831 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1832 u_int *bus_width, role_t role)
1834 switch (*bus_width) {
1836 if (ahc->features & AHC_WIDE) {
1838 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1842 case MSG_EXT_WDTR_BUS_8_BIT:
1843 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1846 if (tinfo != NULL) {
1847 if (role == ROLE_TARGET)
1848 *bus_width = MIN(tinfo->user.width, *bus_width);
1850 *bus_width = MIN(tinfo->goal.width, *bus_width);
1855 * Update the bitmask of targets for which the controller should
1856 * negotiate with at the next convenient opportunity. This currently
1857 * means the next time we send the initial identify messages for
1858 * a new transaction.
1861 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1862 struct ahc_tmode_tstate *tstate,
1863 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1865 u_int auto_negotiate_orig;
1867 auto_negotiate_orig = tstate->auto_negotiate;
1868 if (neg_type == AHC_NEG_ALWAYS) {
1870 * Force our "current" settings to be
1871 * unknown so that unless a bus reset
1872 * occurs the need to renegotiate is
1873 * recorded persistently.
1875 if ((ahc->features & AHC_WIDE) != 0)
1876 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1877 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1878 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1880 if (tinfo->curr.period != tinfo->goal.period
1881 || tinfo->curr.width != tinfo->goal.width
1882 || tinfo->curr.offset != tinfo->goal.offset
1883 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1884 || (neg_type == AHC_NEG_IF_NON_ASYNC
1885 && (tinfo->goal.offset != 0
1886 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1887 || tinfo->goal.ppr_options != 0)))
1888 tstate->auto_negotiate |= devinfo->target_mask;
1890 tstate->auto_negotiate &= ~devinfo->target_mask;
1892 return (auto_negotiate_orig != tstate->auto_negotiate);
1896 * Update the user/goal/curr tables of synchronous negotiation
1897 * parameters as well as, in the case of a current or active update,
1898 * any data structures on the host controller. In the case of an
1899 * active update, the specified target is currently talking to us on
1900 * the bus, so the transfer parameter update must take effect
1904 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1905 struct ahc_syncrate *syncrate, u_int period,
1906 u_int offset, u_int ppr_options, u_int type, int paused)
1908 struct ahc_initiator_tinfo *tinfo;
1909 struct ahc_tmode_tstate *tstate;
1916 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1919 if (syncrate == NULL) {
1924 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1925 devinfo->target, &tstate);
1927 if ((type & AHC_TRANS_USER) != 0) {
1928 tinfo->user.period = period;
1929 tinfo->user.offset = offset;
1930 tinfo->user.ppr_options = ppr_options;
1933 if ((type & AHC_TRANS_GOAL) != 0) {
1934 tinfo->goal.period = period;
1935 tinfo->goal.offset = offset;
1936 tinfo->goal.ppr_options = ppr_options;
1939 old_period = tinfo->curr.period;
1940 old_offset = tinfo->curr.offset;
1941 old_ppr = tinfo->curr.ppr_options;
1943 if ((type & AHC_TRANS_CUR) != 0
1944 && (old_period != period
1945 || old_offset != offset
1946 || old_ppr != ppr_options)) {
1950 scsirate = tinfo->scsirate;
1951 if ((ahc->features & AHC_ULTRA2) != 0) {
1952 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1953 if (syncrate != NULL) {
1954 scsirate |= syncrate->sxfr_u2;
1955 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1956 scsirate |= ENABLE_CRC;
1958 scsirate |= SINGLE_EDGE;
1961 scsirate &= ~(SXFR|SOFS);
1963 * Ensure Ultra mode is set properly for
1966 tstate->ultraenb &= ~devinfo->target_mask;
1967 if (syncrate != NULL) {
1968 if (syncrate->sxfr & ULTRA_SXFR) {
1970 devinfo->target_mask;
1972 scsirate |= syncrate->sxfr & SXFR;
1973 scsirate |= offset & SOFS;
1978 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1979 sxfrctl0 &= ~FAST20;
1980 if (tstate->ultraenb & devinfo->target_mask)
1982 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1986 ahc_outb(ahc, SCSIRATE, scsirate);
1987 if ((ahc->features & AHC_ULTRA2) != 0)
1988 ahc_outb(ahc, SCSIOFFSET, offset);
1991 tinfo->scsirate = scsirate;
1992 tinfo->curr.period = period;
1993 tinfo->curr.offset = offset;
1994 tinfo->curr.ppr_options = ppr_options;
1996 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1997 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2000 printf("%s: target %d synchronous at %sMHz%s, "
2001 "offset = 0x%x\n", ahc_name(ahc),
2002 devinfo->target, syncrate->rate,
2003 (ppr_options & MSG_EXT_PPR_DT_REQ)
2004 ? " DT" : "", offset);
2006 printf("%s: target %d using "
2007 "asynchronous transfers\n",
2008 ahc_name(ahc), devinfo->target);
2013 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2014 tinfo, AHC_NEG_TO_GOAL);
2017 ahc_update_pending_scbs(ahc);
2021 * Update the user/goal/curr tables of wide negotiation
2022 * parameters as well as, in the case of a current or active update,
2023 * any data structures on the host controller. In the case of an
2024 * active update, the specified target is currently talking to us on
2025 * the bus, so the transfer parameter update must take effect
2029 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2030 u_int width, u_int type, int paused)
2032 struct ahc_initiator_tinfo *tinfo;
2033 struct ahc_tmode_tstate *tstate;
2038 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2040 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2041 devinfo->target, &tstate);
2043 if ((type & AHC_TRANS_USER) != 0)
2044 tinfo->user.width = width;
2046 if ((type & AHC_TRANS_GOAL) != 0)
2047 tinfo->goal.width = width;
2049 oldwidth = tinfo->curr.width;
2050 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2054 scsirate = tinfo->scsirate;
2055 scsirate &= ~WIDEXFER;
2056 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2057 scsirate |= WIDEXFER;
2059 tinfo->scsirate = scsirate;
2062 ahc_outb(ahc, SCSIRATE, scsirate);
2064 tinfo->curr.width = width;
2066 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2067 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2069 printf("%s: target %d using %dbit transfers\n",
2070 ahc_name(ahc), devinfo->target,
2071 8 * (0x01 << width));
2075 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2076 tinfo, AHC_NEG_TO_GOAL);
2078 ahc_update_pending_scbs(ahc);
2082 * Update the current state of tagged queuing for a given target.
2085 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2088 ahc_platform_set_tags(ahc, devinfo, alg);
2089 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2090 devinfo->lun, AC_TRANSFER_NEG, &alg);
2094 * When the transfer settings for a connection change, update any
2095 * in-transit SCBs to contain the new data so the hardware will
2096 * be set correctly during future (re)selections.
2099 ahc_update_pending_scbs(struct ahc_softc *ahc)
2101 struct scb *pending_scb;
2102 int pending_scb_count;
2108 * Traverse the pending SCB list and ensure that all of the
2109 * SCBs there have the proper settings.
2111 pending_scb_count = 0;
2112 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2113 struct ahc_devinfo devinfo;
2114 struct hardware_scb *pending_hscb;
2115 struct ahc_initiator_tinfo *tinfo;
2116 struct ahc_tmode_tstate *tstate;
2118 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2119 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2121 devinfo.target, &tstate);
2122 pending_hscb = pending_scb->hscb;
2123 pending_hscb->control &= ~ULTRAENB;
2124 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2125 pending_hscb->control |= ULTRAENB;
2126 pending_hscb->scsirate = tinfo->scsirate;
2127 pending_hscb->scsioffset = tinfo->curr.offset;
2128 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2129 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2130 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2131 pending_hscb->control &= ~MK_MESSAGE;
2133 ahc_sync_scb(ahc, pending_scb,
2134 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2135 pending_scb_count++;
2138 if (pending_scb_count == 0)
2141 if (ahc_is_paused(ahc)) {
2148 saved_scbptr = ahc_inb(ahc, SCBPTR);
2149 /* Ensure that the hscbs down on the card match the new information */
2150 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2151 struct hardware_scb *pending_hscb;
2155 ahc_outb(ahc, SCBPTR, i);
2156 scb_tag = ahc_inb(ahc, SCB_TAG);
2157 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2158 if (pending_scb == NULL)
2161 pending_hscb = pending_scb->hscb;
2162 control = ahc_inb(ahc, SCB_CONTROL);
2163 control &= ~(ULTRAENB|MK_MESSAGE);
2164 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2165 ahc_outb(ahc, SCB_CONTROL, control);
2166 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2167 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2169 ahc_outb(ahc, SCBPTR, saved_scbptr);
2175 /**************************** Pathing Information *****************************/
2177 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2183 if (ahc_inb(ahc, SSTAT0) & TARGET)
2186 role = ROLE_INITIATOR;
2188 if (role == ROLE_TARGET
2189 && (ahc->features & AHC_MULTI_TID) != 0
2190 && (ahc_inb(ahc, SEQ_FLAGS)
2191 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2192 /* We were selected, so pull our id from TARGIDIN */
2193 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2194 } else if ((ahc->features & AHC_ULTRA2) != 0)
2195 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2197 our_id = ahc_inb(ahc, SCSIID) & OID;
2199 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2200 ahc_compile_devinfo(devinfo,
2202 SCSIID_TARGET(ahc, saved_scsiid),
2203 ahc_inb(ahc, SAVED_LUN),
2204 SCSIID_CHANNEL(ahc, saved_scsiid),
2208 struct ahc_phase_table_entry*
2209 ahc_lookup_phase_entry(int phase)
2211 struct ahc_phase_table_entry *entry;
2212 struct ahc_phase_table_entry *last_entry;
2215 * num_phases doesn't include the default entry which
2216 * will be returned if the phase doesn't match.
2218 last_entry = &ahc_phase_table[num_phases];
2219 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2220 if (phase == entry->phase)
2227 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2228 u_int lun, char channel, role_t role)
2230 devinfo->our_scsiid = our_id;
2231 devinfo->target = target;
2233 devinfo->target_offset = target;
2234 devinfo->channel = channel;
2235 devinfo->role = role;
2237 devinfo->target_offset += 8;
2238 devinfo->target_mask = (0x01 << devinfo->target_offset);
2242 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2244 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2245 devinfo->target, devinfo->lun);
2249 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2255 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2256 role = ROLE_INITIATOR;
2257 if ((scb->flags & SCB_TARGET_SCB) != 0)
2259 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2260 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2263 /************************ Message Phase Processing ****************************/
2265 ahc_assert_atn(struct ahc_softc *ahc)
2270 if ((ahc->features & AHC_DT) == 0)
2271 scsisigo |= ahc_inb(ahc, SCSISIGI);
2272 ahc_outb(ahc, SCSISIGO, scsisigo);
2276 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2277 * or enters the initial message out phase, we are interrupted. Fill our
2278 * outgoing message buffer with the appropriate message and beging handing
2279 * the message phase(s) manually.
2282 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2286 * To facilitate adding multiple messages together,
2287 * each routine should increment the index and len
2288 * variables instead of setting them explicitly.
2290 ahc->msgout_index = 0;
2291 ahc->msgout_len = 0;
2293 if ((scb->flags & SCB_DEVICE_RESET) == 0
2294 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2297 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2298 if ((scb->hscb->control & DISCENB) != 0)
2299 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2300 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2303 if ((scb->hscb->control & TAG_ENB) != 0) {
2304 ahc->msgout_buf[ahc->msgout_index++] =
2305 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2306 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2307 ahc->msgout_len += 2;
2311 if (scb->flags & SCB_DEVICE_RESET) {
2312 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2314 ahc_print_path(ahc, scb);
2315 printf("Bus Device Reset Message Sent\n");
2317 * Clear our selection hardware in advance of
2318 * the busfree. We may have an entry in the waiting
2319 * Q for this target, and we don't want to go about
2320 * selecting while we handle the busfree and blow it
2323 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2324 } else if ((scb->flags & SCB_ABORT) != 0) {
2325 if ((scb->hscb->control & TAG_ENB) != 0)
2326 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2328 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2330 ahc_print_path(ahc, scb);
2331 printf("Abort%s Message Sent\n",
2332 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2334 * Clear our selection hardware in advance of
2335 * the busfree. We may have an entry in the waiting
2336 * Q for this target, and we don't want to go about
2337 * selecting while we handle the busfree and blow it
2340 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2341 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2342 ahc_build_transfer_msg(ahc, devinfo);
2344 printf("ahc_intr: AWAITING_MSG for an SCB that "
2345 "does not have a waiting message\n");
2346 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2347 devinfo->target_mask);
2348 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2349 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2350 ahc_inb(ahc, MSG_OUT), scb->flags);
2354 * Clear the MK_MESSAGE flag from the SCB so we aren't
2355 * asked to send this message again.
2357 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2358 scb->hscb->control &= ~MK_MESSAGE;
2359 ahc->msgout_index = 0;
2360 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2364 * Build an appropriate transfer negotiation message for the
2365 * currently active target.
2368 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2371 * We need to initiate transfer negotiations.
2372 * If our current and goal settings are identical,
2373 * we want to renegotiate due to a check condition.
2375 struct ahc_initiator_tinfo *tinfo;
2376 struct ahc_tmode_tstate *tstate;
2377 struct ahc_syncrate *rate;
2385 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2386 devinfo->target, &tstate);
2388 * Filter our period based on the current connection.
2389 * If we can't perform DT transfers on this segment (not in LVD
2390 * mode for instance), then our decision to issue a PPR message
2393 period = tinfo->goal.period;
2394 offset = tinfo->goal.offset;
2395 ppr_options = tinfo->goal.ppr_options;
2396 /* Target initiated PPR is not allowed in the SCSI spec */
2397 if (devinfo->role == ROLE_TARGET)
2399 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2400 &ppr_options, devinfo->role);
2401 dowide = tinfo->curr.width != tinfo->goal.width;
2402 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2404 * Only use PPR if we have options that need it, even if the device
2405 * claims to support it. There might be an expander in the way
2408 doppr = ppr_options != 0;
2410 if (!dowide && !dosync && !doppr) {
2411 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2412 dosync = tinfo->goal.offset != 0;
2415 if (!dowide && !dosync && !doppr) {
2417 * Force async with a WDTR message if we have a wide bus,
2418 * or just issue an SDTR with a 0 offset.
2420 if ((ahc->features & AHC_WIDE) != 0)
2426 ahc_print_devinfo(ahc, devinfo);
2427 printf("Ensuring async\n");
2431 /* Target initiated PPR is not allowed in the SCSI spec */
2432 if (devinfo->role == ROLE_TARGET)
2436 * Both the PPR message and SDTR message require the
2437 * goal syncrate to be limited to what the target device
2438 * is capable of handling (based on whether an LVD->SE
2439 * expander is on the bus), so combine these two cases.
2440 * Regardless, guarantee that if we are using WDTR and SDTR
2441 * messages that WDTR comes first.
2443 if (doppr || (dosync && !dowide)) {
2444 offset = tinfo->goal.offset;
2445 ahc_validate_offset(ahc, tinfo, rate, &offset,
2446 doppr ? tinfo->goal.width
2447 : tinfo->curr.width,
2450 ahc_construct_ppr(ahc, devinfo, period, offset,
2451 tinfo->goal.width, ppr_options);
2453 ahc_construct_sdtr(ahc, devinfo, period, offset);
2456 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2461 * Build a synchronous negotiation message in our message
2462 * buffer based on the input parameters.
2465 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2466 u_int period, u_int offset)
2469 period = AHC_ASYNC_XFER_PERIOD;
2470 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2471 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2472 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2473 ahc->msgout_buf[ahc->msgout_index++] = period;
2474 ahc->msgout_buf[ahc->msgout_index++] = offset;
2475 ahc->msgout_len += 5;
2477 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2478 ahc_name(ahc), devinfo->channel, devinfo->target,
2479 devinfo->lun, period, offset);
2484 * Build a wide negotiation message in our message
2485 * buffer based on the input parameters.
2488 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2491 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2492 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2493 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2494 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2495 ahc->msgout_len += 4;
2497 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2498 ahc_name(ahc), devinfo->channel, devinfo->target,
2499 devinfo->lun, bus_width);
2504 * Build a parallel protocol request message in our message
2505 * buffer based on the input parameters.
2508 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2509 u_int period, u_int offset, u_int bus_width,
2513 period = AHC_ASYNC_XFER_PERIOD;
2514 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2515 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2516 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2517 ahc->msgout_buf[ahc->msgout_index++] = period;
2518 ahc->msgout_buf[ahc->msgout_index++] = 0;
2519 ahc->msgout_buf[ahc->msgout_index++] = offset;
2520 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2521 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2522 ahc->msgout_len += 8;
2524 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2525 "offset %x, ppr_options %x\n", ahc_name(ahc),
2526 devinfo->channel, devinfo->target, devinfo->lun,
2527 bus_width, period, offset, ppr_options);
2532 * Clear any active message state.
2535 ahc_clear_msg_state(struct ahc_softc *ahc)
2537 ahc->msgout_len = 0;
2538 ahc->msgin_index = 0;
2539 ahc->msg_type = MSG_TYPE_NONE;
2540 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2542 * The target didn't care to respond to our
2543 * message request, so clear ATN.
2545 ahc_outb(ahc, CLRSINT1, CLRATNO);
2547 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2548 ahc_outb(ahc, SEQ_FLAGS2,
2549 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2553 ahc_handle_proto_violation(struct ahc_softc *ahc)
2555 struct ahc_devinfo devinfo;
2563 ahc_fetch_devinfo(ahc, &devinfo);
2564 scbid = ahc_inb(ahc, SCB_TAG);
2565 scb = ahc_lookup_scb(ahc, scbid);
2566 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2567 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2568 lastphase = ahc_inb(ahc, LASTPHASE);
2569 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2571 * The reconnecting target either did not send an
2572 * identify message, or did, but we didn't find an SCB
2575 ahc_print_devinfo(ahc, &devinfo);
2576 printf("Target did not send an IDENTIFY message. "
2577 "LASTPHASE = 0x%x.\n", lastphase);
2579 } else if (scb == NULL) {
2581 * We don't seem to have an SCB active for this
2582 * transaction. Print an error and reset the bus.
2584 ahc_print_devinfo(ahc, &devinfo);
2585 printf("No SCB found during protocol violation\n");
2586 goto proto_violation_reset;
2588 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2589 if ((seq_flags & NO_CDB_SENT) != 0) {
2590 ahc_print_path(ahc, scb);
2591 printf("No or incomplete CDB sent to device.\n");
2592 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2594 * The target never bothered to provide status to
2595 * us prior to completing the command. Since we don't
2596 * know the disposition of this command, we must attempt
2597 * to abort it. Assert ATN and prepare to send an abort
2600 ahc_print_path(ahc, scb);
2601 printf("Completed command without status.\n");
2603 ahc_print_path(ahc, scb);
2604 printf("Unknown protocol violation.\n");
2605 ahc_dump_card_state(ahc);
2608 if ((lastphase & ~P_DATAIN_DT) == 0
2609 || lastphase == P_COMMAND) {
2610 proto_violation_reset:
2612 * Target either went directly to data/command
2613 * phase or didn't respond to our ATN.
2614 * The only safe thing to do is to blow
2615 * it away with a bus reset.
2617 found = ahc_reset_channel(ahc, 'A', TRUE);
2618 printf("%s: Issued Channel %c Bus Reset. "
2619 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2622 * Leave the selection hardware off in case
2623 * this abort attempt will affect yet to
2626 ahc_outb(ahc, SCSISEQ,
2627 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2628 ahc_assert_atn(ahc);
2629 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2631 ahc_print_devinfo(ahc, &devinfo);
2632 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2633 ahc->msgout_len = 1;
2634 ahc->msgout_index = 0;
2635 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2637 ahc_print_path(ahc, scb);
2638 scb->flags |= SCB_ABORT;
2640 printf("Protocol violation %s. Attempting to abort.\n",
2641 ahc_lookup_phase_entry(curphase)->phasemsg);
2646 * Manual message loop handler.
2649 ahc_handle_message_phase(struct ahc_softc *ahc)
2651 struct ahc_devinfo devinfo;
2655 ahc_fetch_devinfo(ahc, &devinfo);
2656 end_session = FALSE;
2657 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2660 switch (ahc->msg_type) {
2661 case MSG_TYPE_INITIATOR_MSGOUT:
2667 if (ahc->msgout_len == 0)
2668 panic("HOST_MSG_LOOP interrupt with no active message");
2671 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2672 ahc_print_devinfo(ahc, &devinfo);
2673 printf("INITIATOR_MSG_OUT");
2676 phasemis = bus_phase != P_MESGOUT;
2679 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2680 printf(" PHASEMIS %s\n",
2681 ahc_lookup_phase_entry(bus_phase)
2685 if (bus_phase == P_MESGIN) {
2687 * Change gears and see if
2688 * this messages is of interest to
2689 * us or should be passed back to
2692 ahc_outb(ahc, CLRSINT1, CLRATNO);
2693 ahc->send_msg_perror = FALSE;
2694 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2695 ahc->msgin_index = 0;
2702 if (ahc->send_msg_perror) {
2703 ahc_outb(ahc, CLRSINT1, CLRATNO);
2704 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2706 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2707 printf(" byte 0x%x\n", ahc->send_msg_perror);
2709 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2713 msgdone = ahc->msgout_index == ahc->msgout_len;
2716 * The target has requested a retry.
2717 * Re-assert ATN, reset our message index to
2720 ahc->msgout_index = 0;
2721 ahc_assert_atn(ahc);
2724 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2726 /* Last byte is signified by dropping ATN */
2727 ahc_outb(ahc, CLRSINT1, CLRATNO);
2731 * Clear our interrupt status and present
2732 * the next byte on the bus.
2734 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2736 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2737 printf(" byte 0x%x\n",
2738 ahc->msgout_buf[ahc->msgout_index]);
2740 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2743 case MSG_TYPE_INITIATOR_MSGIN:
2749 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2750 ahc_print_devinfo(ahc, &devinfo);
2751 printf("INITIATOR_MSG_IN");
2754 phasemis = bus_phase != P_MESGIN;
2757 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2758 printf(" PHASEMIS %s\n",
2759 ahc_lookup_phase_entry(bus_phase)
2763 ahc->msgin_index = 0;
2764 if (bus_phase == P_MESGOUT
2765 && (ahc->send_msg_perror == TRUE
2766 || (ahc->msgout_len != 0
2767 && ahc->msgout_index == 0))) {
2768 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2775 /* Pull the byte in without acking it */
2776 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2778 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2779 printf(" byte 0x%x\n",
2780 ahc->msgin_buf[ahc->msgin_index]);
2783 message_done = ahc_parse_msg(ahc, &devinfo);
2787 * Clear our incoming message buffer in case there
2788 * is another message following this one.
2790 ahc->msgin_index = 0;
2793 * If this message illicited a response,
2794 * assert ATN so the target takes us to the
2795 * message out phase.
2797 if (ahc->msgout_len != 0) {
2799 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2800 ahc_print_devinfo(ahc, &devinfo);
2801 printf("Asserting ATN for response\n");
2804 ahc_assert_atn(ahc);
2809 if (message_done == MSGLOOP_TERMINATED) {
2813 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2814 ahc_inb(ahc, SCSIDATL);
2818 case MSG_TYPE_TARGET_MSGIN:
2822 if (ahc->msgout_len == 0)
2823 panic("Target MSGIN with no active message");
2826 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2827 ahc_print_devinfo(ahc, &devinfo);
2828 printf("TARGET_MSG_IN");
2833 * If we interrupted a mesgout session, the initiator
2834 * will not know this until our first REQ. So, we
2835 * only honor mesgout requests after we've sent our
2838 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2839 && ahc->msgout_index > 0) {
2841 * Change gears and see if this messages is
2842 * of interest to us or should be passed back
2846 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2847 printf(" Honoring ATN Request.\n");
2849 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2852 * Disable SCSI Programmed I/O during the
2853 * phase change so as to avoid phantom REQs.
2855 ahc_outb(ahc, SXFRCTL0,
2856 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2859 * Since SPIORDY asserts when ACK is asserted
2860 * for P_MSGOUT, and SPIORDY's assertion triggered
2861 * our entry into this routine, wait for ACK to
2862 * *de-assert* before changing phases.
2864 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2867 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2870 * All phase line changes require a bus
2871 * settle delay before REQ is asserted.
2872 * [SCSI SPI4 10.7.1]
2874 ahc_flush_device_writes(ahc);
2875 aic_delay(AHC_BUSSETTLE_DELAY);
2877 ahc->msgin_index = 0;
2878 /* Enable SCSI Programmed I/O to REQ for first byte */
2879 ahc_outb(ahc, SXFRCTL0,
2880 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2884 msgdone = ahc->msgout_index == ahc->msgout_len;
2886 ahc_outb(ahc, SXFRCTL0,
2887 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2893 * Present the next byte on the bus.
2896 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2897 printf(" byte 0x%x\n",
2898 ahc->msgout_buf[ahc->msgout_index]);
2900 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2901 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2904 case MSG_TYPE_TARGET_MSGOUT:
2910 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2911 ahc_print_devinfo(ahc, &devinfo);
2912 printf("TARGET_MSG_OUT");
2916 * The initiator signals that this is
2917 * the last byte by dropping ATN.
2919 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2922 * Read the latched byte, but turn off SPIOEN first
2923 * so that we don't inadvertently cause a REQ for the
2926 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2927 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2930 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2931 printf(" byte 0x%x\n",
2932 ahc->msgin_buf[ahc->msgin_index]);
2935 msgdone = ahc_parse_msg(ahc, &devinfo);
2936 if (msgdone == MSGLOOP_TERMINATED) {
2938 * The message is *really* done in that it caused
2939 * us to go to bus free. The sequencer has already
2940 * been reset at this point, so pull the ejection
2949 * XXX Read spec about initiator dropping ATN too soon
2950 * and use msgdone to detect it.
2952 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2953 ahc->msgin_index = 0;
2956 * If this message illicited a response, transition
2957 * to the Message in phase and send it.
2959 if (ahc->msgout_len != 0) {
2961 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2962 ahc_print_devinfo(ahc, &devinfo);
2963 printf(" preparing response.\n");
2966 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2969 * All phase line changes require a bus
2970 * settle delay before REQ is asserted.
2971 * [SCSI SPI4 10.7.1] When transitioning
2972 * from an OUT to an IN phase, we must
2973 * also wait a data release delay to allow
2974 * the initiator time to release the data
2975 * lines. [SCSI SPI4 10.12]
2977 ahc_flush_device_writes(ahc);
2978 aic_delay(AHC_BUSSETTLE_DELAY
2979 + AHC_DATARELEASE_DELAY);
2982 * Enable SCSI Programmed I/O. This will
2983 * immediately cause SPIORDY to assert,
2984 * and the sequencer will call our message
2987 ahc_outb(ahc, SXFRCTL0,
2988 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2989 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2990 ahc->msgin_index = 0;
2998 /* Ask for the next byte. */
2999 ahc_outb(ahc, SXFRCTL0,
3000 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3006 panic("Unknown REQINIT message type");
3010 ahc_clear_msg_state(ahc);
3011 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3013 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3017 * See if we sent a particular extended message to the target.
3018 * If "full" is true, return true only if the target saw the full
3019 * message. If "full" is false, return true if the target saw at
3020 * least the first byte of the message.
3023 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3031 while (index < ahc->msgout_len) {
3032 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3035 end_index = index + 1 + ahc->msgout_buf[index + 1];
3036 if (ahc->msgout_buf[index+2] == msgval
3037 && type == AHCMSG_EXT) {
3039 if (ahc->msgout_index > end_index)
3041 } else if (ahc->msgout_index > index)
3045 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3046 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3047 /* Skip tag type and tag id or residue param*/
3050 /* Single byte message */
3051 if (type == AHCMSG_1B
3052 && ahc->msgout_buf[index] == msgval
3053 && ahc->msgout_index > index)
3065 * Wait for a complete incoming message, parse it, and respond accordingly.
3068 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3070 struct ahc_initiator_tinfo *tinfo;
3071 struct ahc_tmode_tstate *tstate;
3075 u_int targ_scsirate;
3077 done = MSGLOOP_IN_PROG;
3080 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3081 devinfo->target, &tstate);
3082 targ_scsirate = tinfo->scsirate;
3085 * Parse as much of the message as is available,
3086 * rejecting it if we don't support it. When
3087 * the entire message is available and has been
3088 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3089 * that we have parsed an entire message.
3091 * In the case of extended messages, we accept the length
3092 * byte outright and perform more checking once we know the
3093 * extended message type.
3095 switch (ahc->msgin_buf[0]) {
3096 case MSG_DISCONNECT:
3097 case MSG_SAVEDATAPOINTER:
3098 case MSG_CMDCOMPLETE:
3099 case MSG_RESTOREPOINTERS:
3100 case MSG_IGN_WIDE_RESIDUE:
3102 * End our message loop as these are messages
3103 * the sequencer handles on its own.
3105 done = MSGLOOP_TERMINATED;
3107 case MSG_MESSAGE_REJECT:
3108 response = ahc_handle_msg_reject(ahc, devinfo);
3111 done = MSGLOOP_MSGCOMPLETE;
3115 /* Wait for enough of the message to begin validation */
3116 if (ahc->msgin_index < 2)
3118 switch (ahc->msgin_buf[2]) {
3121 struct ahc_syncrate *syncrate;
3127 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3133 * Wait until we have both args before validating
3134 * and acting on this message.
3136 * Add one to MSG_EXT_SDTR_LEN to account for
3137 * the extended message preamble.
3139 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3142 period = ahc->msgin_buf[3];
3144 saved_offset = offset = ahc->msgin_buf[4];
3145 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3148 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3149 targ_scsirate & WIDEXFER,
3152 printf("(%s:%c:%d:%d): Received "
3153 "SDTR period %x, offset %x\n\t"
3154 "Filtered to period %x, offset %x\n",
3155 ahc_name(ahc), devinfo->channel,
3156 devinfo->target, devinfo->lun,
3157 ahc->msgin_buf[3], saved_offset,
3160 ahc_set_syncrate(ahc, devinfo,
3162 offset, ppr_options,
3163 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3167 * See if we initiated Sync Negotiation
3168 * and didn't have to fall down to async
3171 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3173 if (saved_offset != offset) {
3174 /* Went too low - force async */
3179 * Send our own SDTR in reply
3182 && devinfo->role == ROLE_INITIATOR) {
3183 printf("(%s:%c:%d:%d): Target "
3185 ahc_name(ahc), devinfo->channel,
3186 devinfo->target, devinfo->lun);
3188 ahc->msgout_index = 0;
3189 ahc->msgout_len = 0;
3190 ahc_construct_sdtr(ahc, devinfo,
3192 ahc->msgout_index = 0;
3195 done = MSGLOOP_MSGCOMPLETE;
3202 u_int sending_reply;
3204 sending_reply = FALSE;
3205 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3211 * Wait until we have our arg before validating
3212 * and acting on this message.
3214 * Add one to MSG_EXT_WDTR_LEN to account for
3215 * the extended message preamble.
3217 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3220 bus_width = ahc->msgin_buf[3];
3221 saved_width = bus_width;
3222 ahc_validate_width(ahc, tinfo, &bus_width,
3225 printf("(%s:%c:%d:%d): Received WDTR "
3226 "%x filtered to %x\n",
3227 ahc_name(ahc), devinfo->channel,
3228 devinfo->target, devinfo->lun,
3229 saved_width, bus_width);
3232 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3234 * Don't send a WDTR back to the
3235 * target, since we asked first.
3236 * If the width went higher than our
3237 * request, reject it.
3239 if (saved_width > bus_width) {
3241 printf("(%s:%c:%d:%d): requested %dBit "
3242 "transfers. Rejecting...\n",
3243 ahc_name(ahc), devinfo->channel,
3244 devinfo->target, devinfo->lun,
3245 8 * (0x01 << bus_width));
3250 * Send our own WDTR in reply
3253 && devinfo->role == ROLE_INITIATOR) {
3254 printf("(%s:%c:%d:%d): Target "
3256 ahc_name(ahc), devinfo->channel,
3257 devinfo->target, devinfo->lun);
3259 ahc->msgout_index = 0;
3260 ahc->msgout_len = 0;
3261 ahc_construct_wdtr(ahc, devinfo, bus_width);
3262 ahc->msgout_index = 0;
3264 sending_reply = TRUE;
3267 * After a wide message, we are async, but
3268 * some devices don't seem to honor this portion
3269 * of the spec. Force a renegotiation of the
3270 * sync component of our transfer agreement even
3271 * if our goal is async. By updating our width
3272 * after forcing the negotiation, we avoid
3273 * renegotiating for width.
3275 ahc_update_neg_request(ahc, devinfo, tstate,
3276 tinfo, AHC_NEG_ALWAYS);
3277 ahc_set_width(ahc, devinfo, bus_width,
3278 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3280 if (sending_reply == FALSE && reject == FALSE) {
3282 * We will always have an SDTR to send.
3284 ahc->msgout_index = 0;
3285 ahc->msgout_len = 0;
3286 ahc_build_transfer_msg(ahc, devinfo);
3287 ahc->msgout_index = 0;
3290 done = MSGLOOP_MSGCOMPLETE;
3295 struct ahc_syncrate *syncrate;
3302 u_int saved_ppr_options;
3304 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3310 * Wait until we have all args before validating
3311 * and acting on this message.
3313 * Add one to MSG_EXT_PPR_LEN to account for
3314 * the extended message preamble.
3316 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3319 period = ahc->msgin_buf[3];
3320 offset = ahc->msgin_buf[5];
3321 bus_width = ahc->msgin_buf[6];
3322 saved_width = bus_width;
3323 ppr_options = ahc->msgin_buf[7];
3325 * According to the spec, a DT only
3326 * period factor with no DT option
3327 * set implies async.
3329 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3332 saved_ppr_options = ppr_options;
3333 saved_offset = offset;
3336 * Mask out any options we don't support
3337 * on any controller. Transfer options are
3338 * only available if we are negotiating wide.
3340 ppr_options &= MSG_EXT_PPR_DT_REQ;
3344 ahc_validate_width(ahc, tinfo, &bus_width,
3346 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3349 ahc_validate_offset(ahc, tinfo, syncrate,
3353 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3355 * If we are unable to do any of the
3356 * requested options (we went too low),
3357 * then we'll have to reject the message.
3359 if (saved_width > bus_width
3360 || saved_offset != offset
3361 || saved_ppr_options != ppr_options) {
3370 if (devinfo->role != ROLE_TARGET)
3371 printf("(%s:%c:%d:%d): Target "
3373 ahc_name(ahc), devinfo->channel,
3374 devinfo->target, devinfo->lun);
3376 printf("(%s:%c:%d:%d): Initiator "
3378 ahc_name(ahc), devinfo->channel,
3379 devinfo->target, devinfo->lun);
3380 ahc->msgout_index = 0;
3381 ahc->msgout_len = 0;
3382 ahc_construct_ppr(ahc, devinfo, period, offset,
3383 bus_width, ppr_options);
3384 ahc->msgout_index = 0;
3388 printf("(%s:%c:%d:%d): Received PPR width %x, "
3389 "period %x, offset %x,options %x\n"
3390 "\tFiltered to width %x, period %x, "
3391 "offset %x, options %x\n",
3392 ahc_name(ahc), devinfo->channel,
3393 devinfo->target, devinfo->lun,
3394 saved_width, ahc->msgin_buf[3],
3395 saved_offset, saved_ppr_options,
3396 bus_width, period, offset, ppr_options);
3398 ahc_set_width(ahc, devinfo, bus_width,
3399 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3401 ahc_set_syncrate(ahc, devinfo,
3403 offset, ppr_options,
3404 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3406 done = MSGLOOP_MSGCOMPLETE;
3410 /* Unknown extended message. Reject it. */
3416 #ifdef AHC_TARGET_MODE
3417 case MSG_BUS_DEV_RESET:
3418 ahc_handle_devreset(ahc, devinfo,
3420 "Bus Device Reset Received",
3421 /*verbose_level*/0);
3423 done = MSGLOOP_TERMINATED;
3427 case MSG_CLEAR_QUEUE:
3431 /* Target mode messages */
3432 if (devinfo->role != ROLE_TARGET) {
3436 tag = SCB_LIST_NULL;
3437 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3438 tag = ahc_inb(ahc, INITIATOR_TAG);
3439 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3440 devinfo->lun, tag, ROLE_TARGET,
3443 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3444 if (tstate != NULL) {
3445 struct ahc_tmode_lstate* lstate;
3447 lstate = tstate->enabled_luns[devinfo->lun];
3448 if (lstate != NULL) {
3449 ahc_queue_lstate_event(ahc, lstate,
3450 devinfo->our_scsiid,
3453 ahc_send_lstate_events(ahc, lstate);
3457 done = MSGLOOP_TERMINATED;
3461 case MSG_TERM_IO_PROC:
3469 * Setup to reject the message.
3471 ahc->msgout_index = 0;
3472 ahc->msgout_len = 1;
3473 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3474 done = MSGLOOP_MSGCOMPLETE;
3478 if (done != MSGLOOP_IN_PROG && !response)
3479 /* Clear the outgoing message buffer */
3480 ahc->msgout_len = 0;
3486 * Process a message reject message.
3489 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3492 * What we care about here is if we had an
3493 * outstanding SDTR or WDTR message for this
3494 * target. If we did, this is a signal that
3495 * the target is refusing negotiation.
3498 struct ahc_initiator_tinfo *tinfo;
3499 struct ahc_tmode_tstate *tstate;
3504 scb_index = ahc_inb(ahc, SCB_TAG);
3505 scb = ahc_lookup_scb(ahc, scb_index);
3506 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3507 devinfo->our_scsiid,
3508 devinfo->target, &tstate);
3509 /* Might be necessary */
3510 last_msg = ahc_inb(ahc, LAST_MSG);
3512 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3514 * Target does not support the PPR message.
3515 * Attempt to negotiate SPI-2 style.
3518 printf("(%s:%c:%d:%d): PPR Rejected. "
3519 "Trying WDTR/SDTR\n",
3520 ahc_name(ahc), devinfo->channel,
3521 devinfo->target, devinfo->lun);
3523 tinfo->goal.ppr_options = 0;
3524 tinfo->curr.transport_version = 2;
3525 tinfo->goal.transport_version = 2;
3526 ahc->msgout_index = 0;
3527 ahc->msgout_len = 0;
3528 ahc_build_transfer_msg(ahc, devinfo);
3529 ahc->msgout_index = 0;
3531 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3532 /* note 8bit xfers */
3533 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3534 "8bit transfers\n", ahc_name(ahc),
3535 devinfo->channel, devinfo->target, devinfo->lun);
3536 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3537 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3540 * No need to clear the sync rate. If the target
3541 * did not accept the command, our syncrate is
3542 * unaffected. If the target started the negotiation,
3543 * but rejected our response, we already cleared the
3544 * sync rate before sending our WDTR.
3546 if (tinfo->goal.offset != tinfo->curr.offset) {
3547 /* Start the sync negotiation */
3548 ahc->msgout_index = 0;
3549 ahc->msgout_len = 0;
3550 ahc_build_transfer_msg(ahc, devinfo);
3551 ahc->msgout_index = 0;
3554 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3555 /* note asynch xfers and clear flag */
3556 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3557 /*offset*/0, /*ppr_options*/0,
3558 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3560 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3561 "Using asynchronous transfers\n",
3562 ahc_name(ahc), devinfo->channel,
3563 devinfo->target, devinfo->lun);
3564 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3568 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3570 if (tag_type == MSG_SIMPLE_TASK) {
3571 printf("(%s:%c:%d:%d): refuses tagged commands. "
3572 "Performing non-tagged I/O\n", ahc_name(ahc),
3573 devinfo->channel, devinfo->target, devinfo->lun);
3574 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3577 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3578 "Performing simple queue tagged I/O only\n",
3579 ahc_name(ahc), devinfo->channel, devinfo->target,
3580 devinfo->lun, tag_type == MSG_ORDERED_TASK
3581 ? "ordered" : "head of queue");
3582 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3587 * Resend the identify for this CCB as the target
3588 * may believe that the selection is invalid otherwise.
3590 ahc_outb(ahc, SCB_CONTROL,
3591 ahc_inb(ahc, SCB_CONTROL) & mask);
3592 scb->hscb->control &= mask;
3593 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3594 /*type*/MSG_SIMPLE_TASK);
3595 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3596 ahc_assert_atn(ahc);
3599 * This transaction is now at the head of
3600 * the untagged queue for this target.
3602 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3603 struct scb_tailq *untagged_q;
3606 &(ahc->untagged_queues[devinfo->target_offset]);
3607 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3608 scb->flags |= SCB_UNTAGGEDQ;
3610 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3614 * Requeue all tagged commands for this target
3615 * currently in our possession so they can be
3616 * converted to untagged commands.
3618 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3619 SCB_GET_CHANNEL(ahc, scb),
3620 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3621 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3625 * Otherwise, we ignore it.
3627 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3628 ahc_name(ahc), devinfo->channel, devinfo->target,
3635 * Process an ingnore wide residue message.
3638 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3643 scb_index = ahc_inb(ahc, SCB_TAG);
3644 scb = ahc_lookup_scb(ahc, scb_index);
3646 * XXX Actually check data direction in the sequencer?
3647 * Perhaps add datadir to some spare bits in the hscb?
3649 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3650 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3652 * Ignore the message if we haven't
3653 * seen an appropriate data phase yet.
3657 * If the residual occurred on the last
3658 * transfer and the transfer request was
3659 * expected to end on an odd count, do
3660 * nothing. Otherwise, subtract a byte
3661 * and update the residual count accordingly.
3665 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3666 if ((sgptr & SG_LIST_NULL) != 0
3667 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3669 * If the residual occurred on the last
3670 * transfer and the transfer request was
3671 * expected to end on an odd count, do
3675 struct ahc_dma_seg *sg;
3680 /* Pull in all of the sgptr */
3681 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3682 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3684 if ((sgptr & SG_LIST_NULL) != 0) {
3686 * The residual data count is not updated
3687 * for the command run to completion case.
3688 * Explicitly zero the count.
3690 data_cnt &= ~AHC_SG_LEN_MASK;
3693 data_addr = ahc_inl(ahc, SHADDR);
3697 sgptr &= SG_PTR_MASK;
3699 sg = ahc_sg_bus_to_virt(scb, sgptr);
3702 * The residual sg ptr points to the next S/G
3703 * to load so we must go back one.
3706 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3707 if (sg != scb->sg_list
3708 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3710 sglen = aic_le32toh(sg->len);
3712 * Preserve High Address and SG_LIST bits
3713 * while setting the count to 1.
3715 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3716 data_addr = aic_le32toh(sg->addr)
3717 + (sglen & AHC_SG_LEN_MASK) - 1;
3720 * Increment sg so it points to the
3724 sgptr = ahc_sg_virt_to_bus(scb, sg);
3726 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3727 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3729 * Toggle the "oddness" of the transfer length
3730 * to handle this mid-transfer ignore wide
3731 * residue. This ensures that the oddness is
3732 * correct for subsequent data transfers.
3734 ahc_outb(ahc, SCB_LUN,
3735 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3741 * Reinitialize the data pointers for the active transfer
3742 * based on its current residual.
3745 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3748 struct ahc_dma_seg *sg;
3754 scb_index = ahc_inb(ahc, SCB_TAG);
3755 scb = ahc_lookup_scb(ahc, scb_index);
3756 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3757 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3758 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3759 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3761 sgptr &= SG_PTR_MASK;
3762 sg = ahc_sg_bus_to_virt(scb, sgptr);
3764 /* The residual sg_ptr always points to the next sg */
3767 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3768 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3769 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3771 dataptr = aic_le32toh(sg->addr)
3772 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3774 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3777 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3778 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3779 ahc_outb(ahc, HADDR,
3780 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3781 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3783 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3784 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3785 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3786 ahc_outb(ahc, HADDR, dataptr);
3787 ahc_outb(ahc, HCNT + 2, resid >> 16);
3788 ahc_outb(ahc, HCNT + 1, resid >> 8);
3789 ahc_outb(ahc, HCNT, resid);
3790 if ((ahc->features & AHC_ULTRA2) == 0) {
3791 ahc_outb(ahc, STCNT + 2, resid >> 16);
3792 ahc_outb(ahc, STCNT + 1, resid >> 8);
3793 ahc_outb(ahc, STCNT, resid);
3798 * Handle the effects of issuing a bus device reset message.
3801 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3802 cam_status status, char *message, int verbose_level)
3804 #ifdef AHC_TARGET_MODE
3805 struct ahc_tmode_tstate* tstate;
3810 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3811 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3814 #ifdef AHC_TARGET_MODE
3816 * Send an immediate notify ccb to all target mord peripheral
3817 * drivers affected by this action.
3819 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3820 if (tstate != NULL) {
3821 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3822 struct ahc_tmode_lstate* lstate;
3824 lstate = tstate->enabled_luns[lun];
3828 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3829 MSG_BUS_DEV_RESET, /*arg*/0);
3830 ahc_send_lstate_events(ahc, lstate);
3836 * Go back to async/narrow transfers and renegotiate.
3838 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3839 AHC_TRANS_CUR, /*paused*/TRUE);
3840 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3841 /*period*/0, /*offset*/0, /*ppr_options*/0,
3842 AHC_TRANS_CUR, /*paused*/TRUE);
3844 if (status != CAM_SEL_TIMEOUT)
3845 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3846 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3849 && (verbose_level <= bootverbose))
3850 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3851 message, devinfo->channel, devinfo->target, found);
3854 #ifdef AHC_TARGET_MODE
3856 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3861 * To facilitate adding multiple messages together,
3862 * each routine should increment the index and len
3863 * variables instead of setting them explicitly.
3865 ahc->msgout_index = 0;
3866 ahc->msgout_len = 0;
3868 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3869 ahc_build_transfer_msg(ahc, devinfo);
3871 panic("ahc_intr: AWAITING target message with no message");
3873 ahc->msgout_index = 0;
3874 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3877 /**************************** Initialization **********************************/
3879 * Allocate a controller structure for a new device
3880 * and perform initial initializion.
3883 ahc_alloc(void *platform_arg, char *name)
3885 struct ahc_softc *ahc;
3889 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3891 printf("aic7xxx: cannot malloc softc!\n");
3892 free(name, M_DEVBUF);
3896 ahc = device_get_softc((device_t)platform_arg);
3898 memset(ahc, 0, sizeof(*ahc));
3899 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3900 M_DEVBUF, M_NOWAIT);
3901 if (ahc->seep_config == NULL) {
3903 free(ahc, M_DEVBUF);
3905 free(name, M_DEVBUF);
3908 LIST_INIT(&ahc->pending_scbs);
3909 LIST_INIT(&ahc->timedout_scbs);
3910 /* We don't know our unit number until the OSM sets it */
3913 ahc->description = NULL;
3915 ahc->channel_b = 'B';
3916 ahc->chip = AHC_NONE;
3917 ahc->features = AHC_FENONE;
3918 ahc->bugs = AHC_BUGNONE;
3919 ahc->flags = AHC_FNONE;
3921 * Default to all error reporting enabled with the
3922 * sequencer operating at its fastest speed.
3923 * The bus attach code may modify this.
3925 ahc->seqctl = FASTMODE;
3927 for (i = 0; i < AHC_NUM_TARGETS; i++)
3928 TAILQ_INIT(&ahc->untagged_queues[i]);
3929 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3938 ahc_softc_init(struct ahc_softc *ahc)
3941 /* The IRQMS bit is only valid on VL and EISA chips */
3942 if ((ahc->chip & AHC_PCI) == 0)
3943 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3946 ahc->pause = ahc->unpause | PAUSE;
3947 /* XXX The shared scb data stuff should be deprecated */
3948 if (ahc->scb_data == NULL) {
3949 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3950 M_DEVBUF, M_NOWAIT);
3951 if (ahc->scb_data == NULL)
3953 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3960 ahc_softc_insert(struct ahc_softc *ahc)
3962 struct ahc_softc *list_ahc;
3964 #if AIC_PCI_CONFIG > 0
3966 * Second Function PCI devices need to inherit some
3967 * settings from function 0.
3969 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3970 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3971 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3972 aic_dev_softc_t list_pci;
3973 aic_dev_softc_t pci;
3975 list_pci = list_ahc->dev_softc;
3976 pci = ahc->dev_softc;
3977 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3978 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3979 struct ahc_softc *master;
3980 struct ahc_softc *slave;
3982 if (aic_get_pci_function(list_pci) == 0) {
3989 slave->flags &= ~AHC_BIOS_ENABLED;
3991 master->flags & AHC_BIOS_ENABLED;
3992 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3994 master->flags & AHC_PRIMARY_CHANNEL;
4002 * Insertion sort into our list of softcs.
4004 list_ahc = TAILQ_FIRST(&ahc_tailq);
4005 while (list_ahc != NULL
4006 && ahc_softc_comp(ahc, list_ahc) <= 0)
4007 list_ahc = TAILQ_NEXT(list_ahc, links);
4008 if (list_ahc != NULL)
4009 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4011 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4016 ahc_set_unit(struct ahc_softc *ahc, int unit)
4022 ahc_set_name(struct ahc_softc *ahc, char *name)
4024 if (ahc->name != NULL)
4025 free(ahc->name, M_DEVBUF);
4030 ahc_free(struct ahc_softc *ahc)
4034 ahc_terminate_recovery_thread(ahc);
4035 switch (ahc->init_level) {
4041 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4042 ahc->shared_data_dmamap);
4045 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4046 ahc->shared_data_dmamap);
4049 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4052 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4060 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4062 ahc_platform_free(ahc);
4063 ahc_fini_scbdata(ahc);
4064 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4065 struct ahc_tmode_tstate *tstate;
4067 tstate = ahc->enabled_targets[i];
4068 if (tstate != NULL) {
4069 #ifdef AHC_TARGET_MODE
4072 for (j = 0; j < AHC_NUM_LUNS; j++) {
4073 struct ahc_tmode_lstate *lstate;
4075 lstate = tstate->enabled_luns[j];
4076 if (lstate != NULL) {
4077 xpt_free_path(lstate->path);
4078 free(lstate, M_DEVBUF);
4082 free(tstate, M_DEVBUF);
4085 #ifdef AHC_TARGET_MODE
4086 if (ahc->black_hole != NULL) {
4087 xpt_free_path(ahc->black_hole->path);
4088 free(ahc->black_hole, M_DEVBUF);
4091 if (ahc->name != NULL)
4092 free(ahc->name, M_DEVBUF);
4093 if (ahc->seep_config != NULL)
4094 free(ahc->seep_config, M_DEVBUF);
4096 free(ahc, M_DEVBUF);
4102 ahc_shutdown(void *arg)
4104 struct ahc_softc *ahc;
4107 ahc = (struct ahc_softc *)arg;
4109 /* This will reset most registers to 0, but not all */
4110 ahc_reset(ahc, /*reinit*/FALSE);
4111 ahc_outb(ahc, SCSISEQ, 0);
4112 ahc_outb(ahc, SXFRCTL0, 0);
4113 ahc_outb(ahc, DSPCISTATUS, 0);
4115 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4116 ahc_outb(ahc, i, 0);
4120 * Reset the controller and record some information about it
4121 * that is only available just after a reset. If "reinit" is
4122 * non-zero, this reset occurred after initial configuration
4123 * and the caller requests that the chip be fully reinitialized
4124 * to a runable state. Chip interrupts are *not* enabled after
4125 * a reinitialization. The caller must enable interrupts via
4126 * ahc_intr_enable().
4129 ahc_reset(struct ahc_softc *ahc, int reinit)
4132 u_int sxfrctl1_a, sxfrctl1_b;
4137 * Preserve the value of the SXFRCTL1 register for all channels.
4138 * It contains settings that affect termination and we don't want
4139 * to disturb the integrity of the bus.
4143 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4147 * Save channel B's settings in case this chip
4148 * is setup for TWIN channel operation.
4150 sblkctl = ahc_inb(ahc, SBLKCTL);
4151 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4152 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4153 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4155 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4157 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4160 * Ensure that the reset has finished. We delay 1000us
4161 * prior to reading the register to make sure the chip
4162 * has sufficiently completed its reset to handle register
4168 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4171 printf("%s: WARNING - Failed chip reset! "
4172 "Trying to initialize anyway.\n", ahc_name(ahc));
4174 ahc_outb(ahc, HCNTRL, ahc->pause);
4176 /* Determine channel configuration */
4177 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4178 /* No Twin Channel PCI cards */
4179 if ((ahc->chip & AHC_PCI) != 0)
4180 sblkctl &= ~SELBUSB;
4183 /* Single Narrow Channel */
4187 ahc->features |= AHC_WIDE;
4191 ahc->features |= AHC_TWIN;
4194 printf(" Unsupported adapter type. Ignoring\n");
4201 * We must always initialize STPWEN to 1 before we
4202 * restore the saved values. STPWEN is initialized
4203 * to a tri-state condition which can only be cleared
4206 if ((ahc->features & AHC_TWIN) != 0) {
4209 sblkctl = ahc_inb(ahc, SBLKCTL);
4210 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4211 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4212 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4214 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4219 * If a recovery action has forced a chip reset,
4220 * re-initialize the chip to our liking.
4222 error = ahc->bus_chip_init(ahc);
4232 * Determine the number of SCBs available on the controller
4235 ahc_probe_scbs(struct ahc_softc *ahc) {
4238 for (i = 0; i < AHC_SCB_MAX; i++) {
4239 ahc_outb(ahc, SCBPTR, i);
4240 ahc_outb(ahc, SCB_BASE, i);
4241 if (ahc_inb(ahc, SCB_BASE) != i)
4243 ahc_outb(ahc, SCBPTR, 0);
4244 if (ahc_inb(ahc, SCB_BASE) != 0)
4251 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4255 baddr = (bus_addr_t *)arg;
4256 *baddr = segs->ds_addr;
4260 ahc_build_free_scb_list(struct ahc_softc *ahc)
4266 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4269 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4272 ahc_outb(ahc, SCBPTR, i);
4275 * Touch all SCB bytes to avoid parity errors
4276 * should one of our debugging routines read
4277 * an otherwise uninitiatlized byte.
4279 for (j = 0; j < scbsize; j++)
4280 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4282 /* Clear the control byte. */
4283 ahc_outb(ahc, SCB_CONTROL, 0);
4285 /* Set the next pointer */
4286 if ((ahc->flags & AHC_PAGESCBS) != 0)
4287 ahc_outb(ahc, SCB_NEXT, i+1);
4289 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4291 /* Make the tag number, SCSIID, and lun invalid */
4292 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4293 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4294 ahc_outb(ahc, SCB_LUN, 0xFF);
4297 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4298 /* SCB 0 heads the free list. */
4299 ahc_outb(ahc, FREE_SCBH, 0);
4302 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4305 /* Make sure that the last SCB terminates the free list */
4306 ahc_outb(ahc, SCBPTR, i-1);
4307 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4311 ahc_init_scbdata(struct ahc_softc *ahc)
4313 struct scb_data *scb_data;
4315 scb_data = ahc->scb_data;
4316 SLIST_INIT(&scb_data->free_scbs);
4317 SLIST_INIT(&scb_data->sg_maps);
4319 /* Allocate SCB resources */
4320 scb_data->scbarray =
4321 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4322 M_DEVBUF, M_NOWAIT);
4323 if (scb_data->scbarray == NULL)
4325 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4327 /* Determine the number of hardware SCBs and initialize them */
4329 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4330 if (ahc->scb_data->maxhscbs == 0) {
4331 printf("%s: No SCB space found\n", ahc_name(ahc));
4336 * Create our DMA tags. These tags define the kinds of device
4337 * accessible memory allocations and memory mappings we will
4338 * need to perform during normal operation.
4340 * Unless we need to further restrict the allocation, we rely
4341 * on the restrictions of the parent dmat, hence the common
4342 * use of MAXADDR and MAXSIZE.
4345 /* DMA tag for our hardware scb structures */
4346 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4347 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4348 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4349 /*highaddr*/BUS_SPACE_MAXADDR,
4350 /*filter*/NULL, /*filterarg*/NULL,
4351 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4353 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4354 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4358 scb_data->init_level++;
4360 /* Allocation for our hscbs */
4361 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4362 (void **)&scb_data->hscbs,
4363 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4364 &scb_data->hscb_dmamap) != 0) {
4368 scb_data->init_level++;
4370 /* And permanently map them */
4371 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4373 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4374 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4376 scb_data->init_level++;
4378 /* DMA tag for our sense buffers */
4379 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4380 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4381 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4382 /*highaddr*/BUS_SPACE_MAXADDR,
4383 /*filter*/NULL, /*filterarg*/NULL,
4384 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4386 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4387 /*flags*/0, &scb_data->sense_dmat) != 0) {
4391 scb_data->init_level++;
4394 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4395 (void **)&scb_data->sense,
4396 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4400 scb_data->init_level++;
4402 /* And permanently map them */
4403 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4405 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4406 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4408 scb_data->init_level++;
4410 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4411 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4412 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4413 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4414 /*highaddr*/BUS_SPACE_MAXADDR,
4415 /*filter*/NULL, /*filterarg*/NULL,
4416 PAGE_SIZE, /*nsegments*/1,
4417 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4418 /*flags*/0, &scb_data->sg_dmat) != 0) {
4422 scb_data->init_level++;
4424 /* Perform initial CCB allocation */
4425 memset(scb_data->hscbs, 0,
4426 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4427 while (ahc_alloc_scbs(ahc) != 0)
4430 if (scb_data->numscbs == 0) {
4431 printf("%s: ahc_init_scbdata - "
4432 "Unable to allocate initial scbs\n",
4438 * Reserve the next queued SCB.
4440 ahc->next_queued_scb = ahc_get_scb(ahc);
4443 * Note that we were successful
4453 ahc_fini_scbdata(struct ahc_softc *ahc)
4455 struct scb_data *scb_data;
4457 scb_data = ahc->scb_data;
4458 if (scb_data == NULL)
4461 switch (scb_data->init_level) {
4465 struct sg_map_node *sg_map;
4467 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4468 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4469 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4471 aic_dmamem_free(ahc, scb_data->sg_dmat,
4474 free(sg_map, M_DEVBUF);
4476 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4479 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4480 scb_data->sense_dmamap);
4482 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4483 scb_data->sense_dmamap);
4485 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4487 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4488 scb_data->hscb_dmamap);
4490 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4491 scb_data->hscb_dmamap);
4493 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4498 if (scb_data->scbarray != NULL)
4499 free(scb_data->scbarray, M_DEVBUF);
4503 ahc_alloc_scbs(struct ahc_softc *ahc)
4505 struct scb_data *scb_data;
4506 struct scb *next_scb;
4507 struct sg_map_node *sg_map;
4508 bus_addr_t physaddr;
4509 struct ahc_dma_seg *segs;
4513 scb_data = ahc->scb_data;
4514 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4515 /* Can't allocate any more */
4518 next_scb = &scb_data->scbarray[scb_data->numscbs];
4520 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4525 /* Allocate S/G space for the next batch of SCBS */
4526 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4527 (void **)&sg_map->sg_vaddr,
4528 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4529 &sg_map->sg_dmamap) != 0) {
4530 free(sg_map, M_DEVBUF);
4534 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4536 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4537 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4538 &sg_map->sg_physaddr, /*flags*/0);
4540 segs = sg_map->sg_vaddr;
4541 physaddr = sg_map->sg_physaddr;
4543 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4544 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4545 for (i = 0; i < newcount; i++) {
4546 struct scb_platform_data *pdata;
4550 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4551 M_DEVBUF, M_NOWAIT);
4554 next_scb->platform_data = pdata;
4555 next_scb->sg_map = sg_map;
4556 next_scb->sg_list = segs;
4558 * The sequencer always starts with the second entry.
4559 * The first entry is embedded in the scb.
4561 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4562 next_scb->ahc_softc = ahc;
4563 next_scb->flags = SCB_FLAG_NONE;
4565 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4570 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4571 next_scb->hscb->tag = ahc->scb_data->numscbs;
4572 aic_timer_init(&next_scb->io_timer);
4573 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4574 next_scb, links.sle);
4576 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4578 ahc->scb_data->numscbs++;
4584 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4588 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4590 if ((ahc->features & AHC_TWIN) != 0)
4591 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4592 "B SCSI Id=%d, primary %c, ",
4593 ahc->our_id, ahc->our_id_b,
4594 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4600 if ((ahc->features & AHC_ULTRA) != 0) {
4602 } else if ((ahc->features & AHC_DT) != 0) {
4603 speed = "Ultra160 ";
4604 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4607 if ((ahc->features & AHC_WIDE) != 0) {
4612 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4613 speed, type, ahc->channel, ahc->our_id);
4617 if ((ahc->flags & AHC_PAGESCBS) != 0)
4618 sprintf(buf, "%d/%d SCBs",
4619 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4621 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4625 ahc_chip_init(struct ahc_softc *ahc)
4631 u_int scsiseq_template;
4634 ahc_outb(ahc, SEQ_FLAGS, 0);
4635 ahc_outb(ahc, SEQ_FLAGS2, 0);
4637 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4638 if (ahc->features & AHC_TWIN) {
4640 * Setup Channel B first.
4642 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4643 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4644 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4645 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4646 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4647 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4648 if ((ahc->features & AHC_ULTRA2) != 0)
4649 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4650 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4651 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4653 /* Select Channel A */
4654 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4656 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4657 if ((ahc->features & AHC_ULTRA2) != 0)
4658 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4660 ahc_outb(ahc, SCSIID, ahc->our_id);
4661 scsi_conf = ahc_inb(ahc, SCSICONF);
4662 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4664 |ENSTIMER|ACTNEGEN);
4665 if ((ahc->features & AHC_ULTRA2) != 0)
4666 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4667 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4668 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4670 /* There are no untagged SCBs active yet. */
4671 for (i = 0; i < 16; i++) {
4672 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4673 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4677 * The SCB based BTT allows an entry per
4678 * target and lun pair.
4680 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4681 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4685 /* All of our queues are empty */
4686 for (i = 0; i < 256; i++)
4687 ahc->qoutfifo[i] = SCB_LIST_NULL;
4688 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4690 for (i = 0; i < 256; i++)
4691 ahc->qinfifo[i] = SCB_LIST_NULL;
4693 if ((ahc->features & AHC_MULTI_TID) != 0) {
4694 ahc_outb(ahc, TARGID, 0);
4695 ahc_outb(ahc, TARGID + 1, 0);
4699 * Tell the sequencer where it can find our arrays in memory.
4701 physaddr = ahc->scb_data->hscb_busaddr;
4702 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4703 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4704 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4705 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4707 physaddr = ahc->shared_data_busaddr;
4708 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4709 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4710 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4711 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4714 * Initialize the group code to command length table.
4715 * This overrides the values in TARG_SCSIRATE, so only
4716 * setup the table after we have processed that information.
4718 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4719 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4720 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4721 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4722 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4723 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4724 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4725 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4727 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4728 ahc_outb(ahc, HS_MAILBOX, 0);
4730 /* Tell the sequencer of our initial queue positions */
4731 if ((ahc->features & AHC_TARGETMODE) != 0) {
4732 ahc->tqinfifonext = 1;
4733 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4734 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4736 ahc->qinfifonext = 0;
4737 ahc->qoutfifonext = 0;
4738 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4739 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4740 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4741 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4742 ahc_outb(ahc, SDSCB_QOFF, 0);
4744 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4745 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4746 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4749 /* We don't have any waiting selections */
4750 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4752 /* Our disconnection list is empty too */
4753 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4755 /* Message out buffer starts empty */
4756 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4759 * Setup the allowed SCSI Sequences based on operational mode.
4760 * If we are a target, we'll enalbe select in operations once
4761 * we've had a lun enabled.
4763 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4764 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4765 scsiseq_template |= ENRSELI;
4766 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4768 /* Initialize our list of free SCBs. */
4769 ahc_build_free_scb_list(ahc);
4772 * Tell the sequencer which SCB will be the next one it receives.
4774 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4777 * Load the Sequencer program and Enable the adapter
4781 printf("%s: Downloading Sequencer Program...",
4784 error = ahc_loadseq(ahc);
4788 if ((ahc->features & AHC_ULTRA2) != 0) {
4792 * Wait for up to 500ms for our transceivers
4793 * to settle. If the adapter does not have
4794 * a cable attached, the transceivers may
4795 * never settle, so don't complain if we
4799 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4808 * Start the board, ready for normal operation
4811 ahc_init(struct ahc_softc *ahc)
4820 size_t driver_data_size;
4823 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4824 ahc->flags |= AHC_SEQUENCER_DEBUG;
4827 #ifdef AHC_PRINT_SRAM
4828 printf("Scratch Ram:");
4829 for (i = 0x20; i < 0x5f; i++) {
4830 if (((i % 8) == 0) && (i != 0)) {
4833 printf (" 0x%x", ahc_inb(ahc, i));
4835 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4836 for (i = 0x70; i < 0x7f; i++) {
4837 if (((i % 8) == 0) && (i != 0)) {
4840 printf (" 0x%x", ahc_inb(ahc, i));
4845 * Reading uninitialized scratch ram may
4846 * generate parity errors.
4848 ahc_outb(ahc, CLRINT, CLRPARERR);
4849 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4854 * Assume we have a board at this stage and it has been reset.
4856 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4857 ahc->our_id = ahc->our_id_b = 7;
4860 * Default to allowing initiator operations.
4862 ahc->flags |= AHC_INITIATORROLE;
4865 * Only allow target mode features if this unit has them enabled.
4867 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4868 ahc->features &= ~AHC_TARGETMODE;
4871 /* DMA tag for mapping buffers into device visible space. */
4872 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4873 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4874 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4875 ? (bus_addr_t)0x7FFFFFFFFFULL
4876 : BUS_SPACE_MAXADDR_32BIT,
4877 /*highaddr*/BUS_SPACE_MAXADDR,
4878 /*filter*/NULL, /*filterarg*/NULL,
4879 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4880 /*nsegments*/AHC_NSEG,
4881 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4882 /*flags*/BUS_DMA_ALLOCNOW,
4883 &ahc->buffer_dmat) != 0) {
4891 * DMA tag for our command fifos and other data in system memory
4892 * the card's sequencer must be able to access. For initiator
4893 * roles, we need to allocate space for the qinfifo and qoutfifo.
4894 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4895 * When providing for the target mode role, we must additionally
4896 * provide space for the incoming target command fifo and an extra
4897 * byte to deal with a dma bug in some chip versions.
4899 driver_data_size = 2 * 256 * sizeof(uint8_t);
4900 if ((ahc->features & AHC_TARGETMODE) != 0)
4901 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4902 + /*DMA WideOdd Bug Buffer*/1;
4903 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4904 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4905 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4906 /*highaddr*/BUS_SPACE_MAXADDR,
4907 /*filter*/NULL, /*filterarg*/NULL,
4910 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4911 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4917 /* Allocation of driver data */
4918 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4919 (void **)&ahc->qoutfifo,
4920 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4921 &ahc->shared_data_dmamap) != 0) {
4927 /* And permanently map it in */
4928 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4929 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4930 &ahc->shared_data_busaddr, /*flags*/0);
4932 if ((ahc->features & AHC_TARGETMODE) != 0) {
4933 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4934 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4935 ahc->dma_bug_buf = ahc->shared_data_busaddr
4936 + driver_data_size - 1;
4937 /* All target command blocks start out invalid. */
4938 for (i = 0; i < AHC_TMODE_CMDS; i++)
4939 ahc->targetcmds[i].cmd_valid = 0;
4940 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4941 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4943 ahc->qinfifo = &ahc->qoutfifo[256];
4947 /* Allocate SCB data now that buffer_dmat is initialized */
4948 if (ahc->scb_data->maxhscbs == 0)
4949 if (ahc_init_scbdata(ahc) != 0)
4953 * Allocate a tstate to house information for our
4954 * initiator presence on the bus as well as the user
4955 * data for any target mode initiator.
4957 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4958 printf("%s: unable to allocate ahc_tmode_tstate. "
4959 "Failing attach\n", ahc_name(ahc));
4963 if ((ahc->features & AHC_TWIN) != 0) {
4964 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4965 printf("%s: unable to allocate ahc_tmode_tstate. "
4966 "Failing attach\n", ahc_name(ahc));
4972 * Fire up a recovery thread for this controller.
4974 error = ahc_spawn_recovery_thread(ahc);
4978 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4979 ahc->flags |= AHC_PAGESCBS;
4981 ahc->flags &= ~AHC_PAGESCBS;
4985 if (ahc_debug & AHC_SHOW_MISC) {
4986 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4987 "ahc_dma %u bytes\n",
4989 (u_int)sizeof(struct hardware_scb),
4990 (u_int)sizeof(struct scb),
4991 (u_int)sizeof(struct ahc_dma_seg));
4993 #endif /* AHC_DEBUG */
4996 * Look at the information that board initialization or
4997 * the board bios has left us.
4999 if (ahc->features & AHC_TWIN) {
5000 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5001 if ((scsi_conf & RESET_SCSI) != 0
5002 && (ahc->flags & AHC_INITIATORROLE) != 0)
5003 ahc->flags |= AHC_RESET_BUS_B;
5006 scsi_conf = ahc_inb(ahc, SCSICONF);
5007 if ((scsi_conf & RESET_SCSI) != 0
5008 && (ahc->flags & AHC_INITIATORROLE) != 0)
5009 ahc->flags |= AHC_RESET_BUS_A;
5012 tagenable = ALL_TARGETS_MASK;
5014 /* Grab the disconnection disable table and invert it for our needs */
5015 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5016 printf("%s: Host Adapter Bios disabled. Using default SCSI "
5017 "device parameters\n", ahc_name(ahc));
5018 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5019 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5020 discenable = ALL_TARGETS_MASK;
5021 if ((ahc->features & AHC_ULTRA) != 0)
5022 ultraenb = ALL_TARGETS_MASK;
5024 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5025 | ahc_inb(ahc, DISC_DSB));
5026 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5027 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5028 | ahc_inb(ahc, ULTRA_ENB);
5031 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5034 for (i = 0; i <= max_targ; i++) {
5035 struct ahc_initiator_tinfo *tinfo;
5036 struct ahc_tmode_tstate *tstate;
5042 our_id = ahc->our_id;
5044 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5046 our_id = ahc->our_id_b;
5049 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5050 target_id, &tstate);
5051 /* Default to async narrow across the board */
5052 memset(tinfo, 0, sizeof(*tinfo));
5053 if (ahc->flags & AHC_USEDEFAULTS) {
5054 if ((ahc->features & AHC_WIDE) != 0)
5055 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5058 * These will be truncated when we determine the
5059 * connection type we have with the target.
5061 tinfo->user.period = ahc_syncrates->period;
5062 tinfo->user.offset = MAX_OFFSET;
5067 /* Take the settings leftover in scratch RAM. */
5068 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5070 if ((ahc->features & AHC_ULTRA2) != 0) {
5074 if ((scsirate & SOFS) == 0x0F) {
5076 * Haven't negotiated yet,
5077 * so the format is different.
5079 scsirate = (scsirate & SXFR) >> 4
5082 | (scsirate & WIDEXFER);
5083 offset = MAX_OFFSET_ULTRA2;
5085 offset = ahc_inb(ahc, TARG_OFFSET + i);
5086 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5087 /* Set to the lowest sync rate, 5MHz */
5089 maxsync = AHC_SYNCRATE_ULTRA2;
5090 if ((ahc->features & AHC_DT) != 0)
5091 maxsync = AHC_SYNCRATE_DT;
5092 tinfo->user.period =
5093 ahc_find_period(ahc, scsirate, maxsync);
5095 tinfo->user.period = 0;
5097 tinfo->user.offset = MAX_OFFSET;
5098 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5099 && (ahc->features & AHC_DT) != 0)
5100 tinfo->user.ppr_options =
5102 } else if ((scsirate & SOFS) != 0) {
5103 if ((scsirate & SXFR) == 0x40
5104 && (ultraenb & mask) != 0) {
5105 /* Treat 10MHz as a non-ultra speed */
5109 tinfo->user.period =
5110 ahc_find_period(ahc, scsirate,
5112 ? AHC_SYNCRATE_ULTRA
5113 : AHC_SYNCRATE_FAST);
5114 if (tinfo->user.period != 0)
5115 tinfo->user.offset = MAX_OFFSET;
5117 if (tinfo->user.period == 0)
5118 tinfo->user.offset = 0;
5119 if ((scsirate & WIDEXFER) != 0
5120 && (ahc->features & AHC_WIDE) != 0)
5121 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5122 tinfo->user.protocol_version = 4;
5123 if ((ahc->features & AHC_DT) != 0)
5124 tinfo->user.transport_version = 3;
5126 tinfo->user.transport_version = 2;
5127 tinfo->goal.protocol_version = 2;
5128 tinfo->goal.transport_version = 2;
5129 tinfo->curr.protocol_version = 2;
5130 tinfo->curr.transport_version = 2;
5132 tstate->ultraenb = 0;
5134 ahc->user_discenable = discenable;
5135 ahc->user_tagenable = tagenable;
5137 return (ahc->bus_chip_init(ahc));
5141 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5145 hcntrl = ahc_inb(ahc, HCNTRL);
5147 ahc->pause &= ~INTEN;
5148 ahc->unpause &= ~INTEN;
5151 ahc->pause |= INTEN;
5152 ahc->unpause |= INTEN;
5154 ahc_outb(ahc, HCNTRL, hcntrl);
5158 * Ensure that the card is paused in a location
5159 * outside of all critical sections and that all
5160 * pending work is completed prior to returning.
5161 * This routine should only be called from outside
5162 * an interrupt context.
5165 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5172 ahc->flags |= AHC_ALL_INTERRUPTS;
5178 * Give the sequencer some time to service
5179 * any active selections.
5186 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5187 intstat = ahc_inb(ahc, INTSTAT);
5188 if ((intstat & INT_PEND) == 0) {
5189 ahc_clear_critical_section(ahc);
5190 intstat = ahc_inb(ahc, INTSTAT);
5193 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5194 && ((intstat & INT_PEND) != 0
5195 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5196 if (maxloops == 0) {
5197 printf("Infinite interrupt loop, INTSTAT = %x",
5198 ahc_inb(ahc, INTSTAT));
5200 ahc_platform_flushwork(ahc);
5201 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5205 ahc_suspend(struct ahc_softc *ahc)
5208 ahc_pause_and_flushwork(ahc);
5210 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5215 #ifdef AHC_TARGET_MODE
5217 * XXX What about ATIOs that have not yet been serviced?
5218 * Perhaps we should just refuse to be suspended if we
5219 * are acting in a target role.
5221 if (ahc->pending_device != NULL) {
5231 ahc_resume(struct ahc_softc *ahc)
5234 ahc_reset(ahc, /*reinit*/TRUE);
5235 ahc_intr_enable(ahc, TRUE);
5240 /************************** Busy Target Table *********************************/
5242 * Return the untagged transaction id for a given target/channel lun.
5243 * Optionally, clear the entry.
5246 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5249 u_int target_offset;
5251 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5254 saved_scbptr = ahc_inb(ahc, SCBPTR);
5255 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5256 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5257 ahc_outb(ahc, SCBPTR, saved_scbptr);
5259 target_offset = TCL_TARGET_OFFSET(tcl);
5260 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5267 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5269 u_int target_offset;
5271 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5274 saved_scbptr = ahc_inb(ahc, SCBPTR);
5275 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5276 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5277 ahc_outb(ahc, SCBPTR, saved_scbptr);
5279 target_offset = TCL_TARGET_OFFSET(tcl);
5280 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5285 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5287 u_int target_offset;
5289 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5292 saved_scbptr = ahc_inb(ahc, SCBPTR);
5293 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5294 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5295 ahc_outb(ahc, SCBPTR, saved_scbptr);
5297 target_offset = TCL_TARGET_OFFSET(tcl);
5298 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5302 /************************** SCB and SCB queue management **********************/
5304 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5305 char channel, int lun, u_int tag, role_t role)
5307 int targ = SCB_GET_TARGET(ahc, scb);
5308 char chan = SCB_GET_CHANNEL(ahc, scb);
5309 int slun = SCB_GET_LUN(scb);
5312 match = ((chan == channel) || (channel == ALL_CHANNELS));
5314 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5316 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5318 #ifdef AHC_TARGET_MODE
5321 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5322 if (role == ROLE_INITIATOR) {
5323 match = (group != XPT_FC_GROUP_TMODE)
5324 && ((tag == scb->hscb->tag)
5325 || (tag == SCB_LIST_NULL));
5326 } else if (role == ROLE_TARGET) {
5327 match = (group == XPT_FC_GROUP_TMODE)
5328 && ((tag == scb->io_ctx->csio.tag_id)
5329 || (tag == SCB_LIST_NULL));
5331 #else /* !AHC_TARGET_MODE */
5332 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5333 #endif /* AHC_TARGET_MODE */
5340 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5346 target = SCB_GET_TARGET(ahc, scb);
5347 lun = SCB_GET_LUN(scb);
5348 channel = SCB_GET_CHANNEL(ahc, scb);
5350 ahc_search_qinfifo(ahc, target, channel, lun,
5351 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5352 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5354 ahc_platform_freeze_devq(ahc, scb);
5358 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5360 struct scb *prev_scb;
5363 if (ahc_qinfifo_count(ahc) != 0) {
5367 prev_pos = ahc->qinfifonext - 1;
5368 prev_tag = ahc->qinfifo[prev_pos];
5369 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5371 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5372 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5373 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5375 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5380 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5383 if (prev_scb == NULL) {
5384 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5386 prev_scb->hscb->next = scb->hscb->tag;
5387 ahc_sync_scb(ahc, prev_scb,
5388 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5390 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5391 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5392 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5396 ahc_qinfifo_count(struct ahc_softc *ahc)
5401 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5402 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5403 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5405 qinpos = ahc_inb(ahc, QINPOS);
5406 diff = ahc->qinfifonext - qinpos;
5411 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5412 int lun, u_int tag, role_t role, uint32_t status,
5413 ahc_search_action action)
5416 struct scb *prev_scb;
5426 qintail = ahc->qinfifonext;
5427 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5429 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5430 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5432 qinstart = ahc_inb(ahc, QINPOS);
5437 if (action == SEARCH_COMPLETE) {
5439 * Don't attempt to run any queued untagged transactions
5440 * until we are done with the abort process.
5442 ahc_freeze_untagged_queues(ahc);
5446 * Start with an empty queue. Entries that are not chosen
5447 * for removal will be re-added to the queue as we go.
5449 ahc->qinfifonext = qinpos;
5450 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5452 while (qinpos != qintail) {
5453 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5455 printf("qinpos = %d, SCB index = %d\n",
5456 qinpos, ahc->qinfifo[qinpos]);
5460 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5462 * We found an scb that needs to be acted on.
5466 case SEARCH_COMPLETE:
5471 ostat = aic_get_transaction_status(scb);
5472 if (ostat == CAM_REQ_INPROG)
5473 aic_set_transaction_status(scb, status);
5474 cstat = aic_get_transaction_status(scb);
5475 if (cstat != CAM_REQ_CMP)
5476 aic_freeze_scb(scb);
5477 if ((scb->flags & SCB_ACTIVE) == 0)
5478 printf("Inactive SCB in qinfifo\n");
5486 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5491 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5497 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5498 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5500 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5503 if (action != SEARCH_COUNT
5505 && (qinstart != ahc->qinfifonext)) {
5507 * The sequencer may be in the process of dmaing
5508 * down the SCB at the beginning of the queue.
5509 * This could be problematic if either the first,
5510 * or the second SCB is removed from the queue
5511 * (the first SCB includes a pointer to the "next"
5512 * SCB to dma). If we have removed any entries, swap
5513 * the first element in the queue with the next HSCB
5514 * so the sequencer will notice that NEXT_QUEUED_SCB
5515 * has changed during its dma attempt and will retry
5518 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5521 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5522 found, qinstart, ahc->qinfifonext);
5523 panic("First/Second Qinfifo fixup\n");
5526 * ahc_swap_with_next_hscb forces our next pointer to
5527 * point to the reserved SCB for future commands. Save
5528 * and restore our original next pointer to maintain
5531 next = scb->hscb->next;
5532 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5533 ahc_swap_with_next_hscb(ahc, scb);
5534 scb->hscb->next = next;
5535 ahc->qinfifo[qinstart] = scb->hscb->tag;
5537 /* Tell the card about the new head of the qinfifo. */
5538 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5540 /* Fixup the tail "next" pointer. */
5541 qintail = ahc->qinfifonext - 1;
5542 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5543 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5547 * Search waiting for selection list.
5549 curscbptr = ahc_inb(ahc, SCBPTR);
5550 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5551 prev = SCB_LIST_NULL;
5553 while (next != SCB_LIST_NULL) {
5556 ahc_outb(ahc, SCBPTR, next);
5557 scb_index = ahc_inb(ahc, SCB_TAG);
5558 if (scb_index >= ahc->scb_data->numscbs) {
5559 printf("Waiting List inconsistency. "
5560 "SCB index == %d, yet numscbs == %d.",
5561 scb_index, ahc->scb_data->numscbs);
5562 ahc_dump_card_state(ahc);
5563 panic("for safety");
5565 scb = ahc_lookup_scb(ahc, scb_index);
5567 printf("scb_index = %d, next = %d\n",
5569 panic("Waiting List traversal\n");
5571 if (ahc_match_scb(ahc, scb, target, channel,
5572 lun, SCB_LIST_NULL, role)) {
5574 * We found an scb that needs to be acted on.
5578 case SEARCH_COMPLETE:
5583 ostat = aic_get_transaction_status(scb);
5584 if (ostat == CAM_REQ_INPROG)
5585 aic_set_transaction_status(scb,
5587 cstat = aic_get_transaction_status(scb);
5588 if (cstat != CAM_REQ_CMP)
5589 aic_freeze_scb(scb);
5590 if ((scb->flags & SCB_ACTIVE) == 0)
5591 printf("Inactive SCB in Wait List\n");
5596 next = ahc_rem_wscb(ahc, next, prev);
5600 next = ahc_inb(ahc, SCB_NEXT);
5606 next = ahc_inb(ahc, SCB_NEXT);
5609 ahc_outb(ahc, SCBPTR, curscbptr);
5611 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5612 channel, lun, status, action);
5614 if (action == SEARCH_COMPLETE)
5615 ahc_release_untagged_queues(ahc);
5620 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5621 int target, char channel, int lun, uint32_t status,
5622 ahc_search_action action)
5629 if (action == SEARCH_COMPLETE) {
5631 * Don't attempt to run any queued untagged transactions
5632 * until we are done with the abort process.
5634 ahc_freeze_untagged_queues(ahc);
5639 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5641 if (target != CAM_TARGET_WILDCARD) {
5651 for (; i < maxtarget; i++) {
5652 struct scb_tailq *untagged_q;
5653 struct scb *next_scb;
5655 untagged_q = &(ahc->untagged_queues[i]);
5656 next_scb = TAILQ_FIRST(untagged_q);
5657 while (next_scb != NULL) {
5659 next_scb = TAILQ_NEXT(scb, links.tqe);
5662 * The head of the list may be the currently
5663 * active untagged command for a device.
5664 * We're only searching for commands that
5665 * have not been started. A transaction
5666 * marked active but still in the qinfifo
5667 * is removed by the qinfifo scanning code
5670 if ((scb->flags & SCB_ACTIVE) != 0)
5673 if (ahc_match_scb(ahc, scb, target, channel, lun,
5674 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5675 || (ctx != NULL && ctx != scb->io_ctx))
5679 * We found an scb that needs to be acted on.
5683 case SEARCH_COMPLETE:
5688 ostat = aic_get_transaction_status(scb);
5689 if (ostat == CAM_REQ_INPROG)
5690 aic_set_transaction_status(scb, status);
5691 cstat = aic_get_transaction_status(scb);
5692 if (cstat != CAM_REQ_CMP)
5693 aic_freeze_scb(scb);
5698 scb->flags &= ~SCB_UNTAGGEDQ;
5699 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5707 if (action == SEARCH_COMPLETE)
5708 ahc_release_untagged_queues(ahc);
5713 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5714 int lun, u_int tag, int stop_on_first, int remove,
5724 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5725 prev = SCB_LIST_NULL;
5728 /* restore this when we're done */
5729 active_scb = ahc_inb(ahc, SCBPTR);
5731 /* Silence compiler */
5732 active_scb = SCB_LIST_NULL;
5734 while (next != SCB_LIST_NULL) {
5737 ahc_outb(ahc, SCBPTR, next);
5738 scb_index = ahc_inb(ahc, SCB_TAG);
5739 if (scb_index >= ahc->scb_data->numscbs) {
5740 printf("Disconnected List inconsistency. "
5741 "SCB index == %d, yet numscbs == %d.",
5742 scb_index, ahc->scb_data->numscbs);
5743 ahc_dump_card_state(ahc);
5744 panic("for safety");
5748 panic("Disconnected List Loop. "
5749 "cur SCBPTR == %x, prev SCBPTR == %x.",
5752 scbp = ahc_lookup_scb(ahc, scb_index);
5753 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5754 tag, ROLE_INITIATOR)) {
5758 ahc_rem_scb_from_disc_list(ahc, prev, next);
5761 next = ahc_inb(ahc, SCB_NEXT);
5767 next = ahc_inb(ahc, SCB_NEXT);
5771 ahc_outb(ahc, SCBPTR, active_scb);
5776 * Remove an SCB from the on chip list of disconnected transactions.
5777 * This is empty/unused if we are not performing SCB paging.
5780 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5784 ahc_outb(ahc, SCBPTR, scbptr);
5785 next = ahc_inb(ahc, SCB_NEXT);
5787 ahc_outb(ahc, SCB_CONTROL, 0);
5789 ahc_add_curscb_to_free_list(ahc);
5791 if (prev != SCB_LIST_NULL) {
5792 ahc_outb(ahc, SCBPTR, prev);
5793 ahc_outb(ahc, SCB_NEXT, next);
5795 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5801 * Add the SCB as selected by SCBPTR onto the on chip list of
5802 * free hardware SCBs. This list is empty/unused if we are not
5803 * performing SCB paging.
5806 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5809 * Invalidate the tag so that our abort
5810 * routines don't think it's active.
5812 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5814 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5815 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5816 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5821 * Manipulate the waiting for selection list and return the
5822 * scb that follows the one that we remove.
5825 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5830 * Select the SCB we want to abort and
5831 * pull the next pointer out of it.
5833 curscb = ahc_inb(ahc, SCBPTR);
5834 ahc_outb(ahc, SCBPTR, scbpos);
5835 next = ahc_inb(ahc, SCB_NEXT);
5837 /* Clear the necessary fields */
5838 ahc_outb(ahc, SCB_CONTROL, 0);
5840 ahc_add_curscb_to_free_list(ahc);
5842 /* update the waiting list */
5843 if (prev == SCB_LIST_NULL) {
5844 /* First in the list */
5845 ahc_outb(ahc, WAITING_SCBH, next);
5848 * Ensure we aren't attempting to perform
5849 * selection for this entry.
5851 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5854 * Select the scb that pointed to us
5855 * and update its next pointer.
5857 ahc_outb(ahc, SCBPTR, prev);
5858 ahc_outb(ahc, SCB_NEXT, next);
5862 * Point us back at the original scb position.
5864 ahc_outb(ahc, SCBPTR, curscb);
5868 /******************************** Error Handling ******************************/
5870 * Abort all SCBs that match the given description (target/channel/lun/tag),
5871 * setting their status to the passed in status if the status has not already
5872 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5873 * is paused before it is called.
5876 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5877 int lun, u_int tag, role_t role, uint32_t status)
5880 struct scb *scbp_next;
5890 * Don't attempt to run any queued untagged transactions
5891 * until we are done with the abort process.
5893 ahc_freeze_untagged_queues(ahc);
5895 /* restore this when we're done */
5896 active_scb = ahc_inb(ahc, SCBPTR);
5898 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5899 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5902 * Clean out the busy target table for any untagged commands.
5906 if (target != CAM_TARGET_WILDCARD) {
5913 if (lun == CAM_LUN_WILDCARD) {
5915 * Unless we are using an SCB based
5916 * busy targets table, there is only
5917 * one table entry for all luns of
5922 if ((ahc->flags & AHC_SCB_BTT) != 0)
5923 maxlun = AHC_NUM_LUNS;
5929 if (role != ROLE_TARGET) {
5930 for (;i < maxtarget; i++) {
5931 for (j = minlun;j < maxlun; j++) {
5935 tcl = BUILD_TCL(i << 4, j);
5936 scbid = ahc_index_busy_tcl(ahc, tcl);
5937 scbp = ahc_lookup_scb(ahc, scbid);
5939 || ahc_match_scb(ahc, scbp, target, channel,
5940 lun, tag, role) == 0)
5942 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5947 * Go through the disconnected list and remove any entries we
5948 * have queued for completion, 0'ing their control byte too.
5949 * We save the active SCB and restore it ourselves, so there
5950 * is no reason for this search to restore it too.
5952 ahc_search_disc_list(ahc, target, channel, lun, tag,
5953 /*stop_on_first*/FALSE, /*remove*/TRUE,
5954 /*save_state*/FALSE);
5958 * Go through the hardware SCB array looking for commands that
5959 * were active but not on any list. In some cases, these remnants
5960 * might not still have mappings in the scbindex array (e.g. unexpected
5961 * bus free with the same scb queued for an abort). Don't hold this
5964 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5967 ahc_outb(ahc, SCBPTR, i);
5968 scbid = ahc_inb(ahc, SCB_TAG);
5969 scbp = ahc_lookup_scb(ahc, scbid);
5970 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5972 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5973 ahc_add_curscb_to_free_list(ahc);
5977 * Go through the pending CCB list and look for
5978 * commands for this target that are still active.
5979 * These are other tagged commands that were
5980 * disconnected when the reset occurred.
5982 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5983 while (scbp_next != NULL) {
5985 scbp_next = LIST_NEXT(scbp, pending_links);
5986 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5989 ostat = aic_get_transaction_status(scbp);
5990 if (ostat == CAM_REQ_INPROG)
5991 aic_set_transaction_status(scbp, status);
5992 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
5993 aic_freeze_scb(scbp);
5994 if ((scbp->flags & SCB_ACTIVE) == 0)
5995 printf("Inactive SCB on pending list\n");
5996 ahc_done(ahc, scbp);
6000 ahc_outb(ahc, SCBPTR, active_scb);
6001 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6002 ahc_release_untagged_queues(ahc);
6007 ahc_reset_current_bus(struct ahc_softc *ahc)
6011 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6012 scsiseq = ahc_inb(ahc, SCSISEQ);
6013 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6014 ahc_flush_device_writes(ahc);
6015 aic_delay(AHC_BUSRESET_DELAY);
6016 /* Turn off the bus reset */
6017 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6019 ahc_clear_intstat(ahc);
6021 /* Re-enable reset interrupts */
6022 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6026 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6028 struct ahc_devinfo devinfo;
6029 u_int initiator, target, max_scsiid;
6037 ahc->pending_device = NULL;
6039 ahc_compile_devinfo(&devinfo,
6040 CAM_TARGET_WILDCARD,
6041 CAM_TARGET_WILDCARD,
6043 channel, ROLE_UNKNOWN);
6046 /* Make sure the sequencer is in a safe location. */
6047 ahc_clear_critical_section(ahc);
6050 * Run our command complete fifos to ensure that we perform
6051 * completion processing on any commands that 'completed'
6052 * before the reset occurred.
6054 ahc_run_qoutfifo(ahc);
6055 #ifdef AHC_TARGET_MODE
6057 * XXX - In Twin mode, the tqinfifo may have commands
6058 * for an unaffected channel in it. However, if
6059 * we have run out of ATIO resources to drain that
6060 * queue, we may not get them all out here. Further,
6061 * the blocked transactions for the reset channel
6062 * should just be killed off, irrespecitve of whether
6063 * we are blocked on ATIO resources. Write a routine
6064 * to compact the tqinfifo appropriately.
6066 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6067 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6072 * Reset the bus if we are initiating this reset
6074 sblkctl = ahc_inb(ahc, SBLKCTL);
6076 if ((ahc->features & AHC_TWIN) != 0
6077 && ((sblkctl & SELBUSB) != 0))
6079 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6080 if (cur_channel != channel) {
6081 /* Case 1: Command for another bus is active
6082 * Stealthily reset the other bus without
6083 * upsetting the current bus.
6085 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6086 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6087 #ifdef AHC_TARGET_MODE
6089 * Bus resets clear ENSELI, so we cannot
6090 * defer re-enabling bus reset interrupts
6091 * if we are in target mode.
6093 if ((ahc->flags & AHC_TARGETROLE) != 0)
6094 simode1 |= ENSCSIRST;
6096 ahc_outb(ahc, SIMODE1, simode1);
6098 ahc_reset_current_bus(ahc);
6099 ahc_clear_intstat(ahc);
6100 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6101 ahc_outb(ahc, SBLKCTL, sblkctl);
6102 restart_needed = FALSE;
6104 /* Case 2: A command from this bus is active or we're idle */
6105 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6106 #ifdef AHC_TARGET_MODE
6108 * Bus resets clear ENSELI, so we cannot
6109 * defer re-enabling bus reset interrupts
6110 * if we are in target mode.
6112 if ((ahc->flags & AHC_TARGETROLE) != 0)
6113 simode1 |= ENSCSIRST;
6115 ahc_outb(ahc, SIMODE1, simode1);
6117 ahc_reset_current_bus(ahc);
6118 ahc_clear_intstat(ahc);
6119 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6120 restart_needed = TRUE;
6124 * Clean up all the state information for the
6125 * pending transactions on this bus.
6127 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6128 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6129 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6131 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6133 #ifdef AHC_TARGET_MODE
6135 * Send an immediate notify ccb to all target more peripheral
6136 * drivers affected by this action.
6138 for (target = 0; target <= max_scsiid; target++) {
6139 struct ahc_tmode_tstate* tstate;
6142 tstate = ahc->enabled_targets[target];
6145 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6146 struct ahc_tmode_lstate* lstate;
6148 lstate = tstate->enabled_luns[lun];
6152 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6153 EVENT_TYPE_BUS_RESET, /*arg*/0);
6154 ahc_send_lstate_events(ahc, lstate);
6158 /* Notify the XPT that a bus reset occurred */
6159 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6160 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6163 * Revert to async/narrow transfers until we renegotiate.
6165 for (target = 0; target <= max_scsiid; target++) {
6166 if (ahc->enabled_targets[target] == NULL)
6168 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6169 struct ahc_devinfo devinfo;
6171 ahc_compile_devinfo(&devinfo, target, initiator,
6173 channel, ROLE_UNKNOWN);
6174 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6175 AHC_TRANS_CUR, /*paused*/TRUE);
6176 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6177 /*period*/0, /*offset*/0,
6178 /*ppr_options*/0, AHC_TRANS_CUR,
6190 /***************************** Residual Processing ****************************/
6192 * Calculate the residual for a just completed SCB.
6195 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6197 struct hardware_scb *hscb;
6198 struct status_pkt *spkt;
6200 uint32_t resid_sgptr;
6206 * SG_RESID_VALID clear in sgptr.
6207 * 2) Transferless command
6208 * 3) Never performed any transfers.
6209 * sgptr has SG_FULL_RESID set.
6210 * 4) No residual but target did not
6211 * save data pointers after the
6212 * last transfer, so sgptr was
6214 * 5) We have a partial residual.
6215 * Use residual_sgptr to determine
6220 sgptr = aic_le32toh(hscb->sgptr);
6221 if ((sgptr & SG_RESID_VALID) == 0)
6224 sgptr &= ~SG_RESID_VALID;
6226 if ((sgptr & SG_LIST_NULL) != 0)
6230 spkt = &hscb->shared_data.status;
6231 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6232 if ((sgptr & SG_FULL_RESID) != 0) {
6234 resid = aic_get_transfer_length(scb);
6235 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6238 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6239 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6243 struct ahc_dma_seg *sg;
6246 * Remainder of the SG where the transfer
6249 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6250 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6252 /* The residual sg_ptr always points to the next sg */
6256 * Add up the contents of all residual
6257 * SG segments that are after the SG where
6258 * the transfer stopped.
6260 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6262 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6265 if ((scb->flags & SCB_SENSE) == 0)
6266 aic_set_residual(scb, resid);
6268 aic_set_sense_residual(scb, resid);
6271 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6272 ahc_print_path(ahc, scb);
6273 printf("Handled %sResidual of %d bytes\n",
6274 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6279 /******************************* Target Mode **********************************/
6280 #ifdef AHC_TARGET_MODE
6282 * Add a target mode event to this lun's queue
6285 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6286 u_int initiator_id, u_int event_type, u_int event_arg)
6288 struct ahc_tmode_event *event;
6291 xpt_freeze_devq(lstate->path, /*count*/1);
6292 if (lstate->event_w_idx >= lstate->event_r_idx)
6293 pending = lstate->event_w_idx - lstate->event_r_idx;
6295 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6296 - (lstate->event_r_idx - lstate->event_w_idx);
6298 if (event_type == EVENT_TYPE_BUS_RESET
6299 || event_type == MSG_BUS_DEV_RESET) {
6301 * Any earlier events are irrelevant, so reset our buffer.
6302 * This has the effect of allowing us to deal with reset
6303 * floods (an external device holding down the reset line)
6304 * without losing the event that is really interesting.
6306 lstate->event_r_idx = 0;
6307 lstate->event_w_idx = 0;
6308 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6311 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6312 xpt_print_path(lstate->path);
6313 printf("immediate event %x:%x lost\n",
6314 lstate->event_buffer[lstate->event_r_idx].event_type,
6315 lstate->event_buffer[lstate->event_r_idx].event_arg);
6316 lstate->event_r_idx++;
6317 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6318 lstate->event_r_idx = 0;
6319 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6322 event = &lstate->event_buffer[lstate->event_w_idx];
6323 event->initiator_id = initiator_id;
6324 event->event_type = event_type;
6325 event->event_arg = event_arg;
6326 lstate->event_w_idx++;
6327 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6328 lstate->event_w_idx = 0;
6332 * Send any target mode events queued up waiting
6333 * for immediate notify resources.
6336 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6338 struct ccb_hdr *ccbh;
6339 struct ccb_immediate_notify *inot;
6341 while (lstate->event_r_idx != lstate->event_w_idx
6342 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6343 struct ahc_tmode_event *event;
6345 event = &lstate->event_buffer[lstate->event_r_idx];
6346 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6347 inot = (struct ccb_immediate_notify *)ccbh;
6348 switch (event->event_type) {
6349 case EVENT_TYPE_BUS_RESET:
6350 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6353 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6354 inot->arg = event->event_type;
6355 inot->seq_id = event->event_arg;
6358 inot->initiator_id = event->initiator_id;
6359 xpt_done((union ccb *)inot);
6360 lstate->event_r_idx++;
6361 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6362 lstate->event_r_idx = 0;
6367 /******************** Sequencer Program Patching/Download *********************/
6371 ahc_dumpseq(struct ahc_softc* ahc)
6375 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6376 ahc_outb(ahc, SEQADDR0, 0);
6377 ahc_outb(ahc, SEQADDR1, 0);
6378 for (i = 0; i < ahc->instruction_ram_size; i++) {
6379 uint8_t ins_bytes[4];
6381 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6382 printf("0x%08x\n", ins_bytes[0] << 24
6383 | ins_bytes[1] << 16
6391 ahc_loadseq(struct ahc_softc *ahc)
6393 struct cs cs_table[num_critical_sections];
6394 u_int begin_set[num_critical_sections];
6395 u_int end_set[num_critical_sections];
6396 struct patch *cur_patch;
6401 u_int sg_prefetch_cnt;
6403 uint8_t download_consts[7];
6406 * Start out with 0 critical sections
6407 * that apply to this firmware load.
6411 memset(begin_set, 0, sizeof(begin_set));
6412 memset(end_set, 0, sizeof(end_set));
6414 /* Setup downloadable constant table */
6415 download_consts[QOUTFIFO_OFFSET] = 0;
6416 if (ahc->targetcmds != NULL)
6417 download_consts[QOUTFIFO_OFFSET] += 32;
6418 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6419 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6420 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6421 sg_prefetch_cnt = ahc->pci_cachesize;
6422 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6423 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6424 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6425 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6426 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6428 cur_patch = patches;
6431 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6432 ahc_outb(ahc, SEQADDR0, 0);
6433 ahc_outb(ahc, SEQADDR1, 0);
6435 for (i = 0; i < sizeof(seqprog)/4; i++) {
6436 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6438 * Don't download this instruction as it
6439 * is in a patch that was removed.
6444 if (downloaded == ahc->instruction_ram_size) {
6446 * We're about to exceed the instruction
6447 * storage capacity for this chip. Fail
6450 printf("\n%s: Program too large for instruction memory "
6451 "size of %d!\n", ahc_name(ahc),
6452 ahc->instruction_ram_size);
6457 * Move through the CS table until we find a CS
6458 * that might apply to this instruction.
6460 for (; cur_cs < num_critical_sections; cur_cs++) {
6461 if (critical_sections[cur_cs].end <= i) {
6462 if (begin_set[cs_count] == TRUE
6463 && end_set[cs_count] == FALSE) {
6464 cs_table[cs_count].end = downloaded;
6465 end_set[cs_count] = TRUE;
6470 if (critical_sections[cur_cs].begin <= i
6471 && begin_set[cs_count] == FALSE) {
6472 cs_table[cs_count].begin = downloaded;
6473 begin_set[cs_count] = TRUE;
6477 ahc_download_instr(ahc, i, download_consts);
6481 ahc->num_critical_sections = cs_count;
6482 if (cs_count != 0) {
6483 cs_count *= sizeof(struct cs);
6484 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6485 if (ahc->critical_sections == NULL)
6486 panic("ahc_loadseq: Could not malloc");
6487 memcpy(ahc->critical_sections, cs_table, cs_count);
6489 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6492 printf(" %d instructions downloaded\n", downloaded);
6493 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6494 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6500 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6501 u_int start_instr, u_int *skip_addr)
6503 struct patch *cur_patch;
6504 struct patch *last_patch;
6507 num_patches = sizeof(patches)/sizeof(struct patch);
6508 last_patch = &patches[num_patches];
6509 cur_patch = *start_patch;
6511 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6512 if (cur_patch->patch_func(ahc) == 0) {
6513 /* Start rejecting code */
6514 *skip_addr = start_instr + cur_patch->skip_instr;
6515 cur_patch += cur_patch->skip_patch;
6517 /* Accepted this patch. Advance to the next
6518 * one and wait for our instruction pointer to
6525 *start_patch = cur_patch;
6526 if (start_instr < *skip_addr)
6527 /* Still skipping */
6534 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6536 union ins_formats instr;
6537 struct ins_format1 *fmt1_ins;
6538 struct ins_format3 *fmt3_ins;
6542 * The firmware is always compiled into a little endian format.
6544 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6546 fmt1_ins = &instr.format1;
6549 /* Pull the opcode */
6550 opcode = instr.format1.opcode;
6561 struct patch *cur_patch;
6567 fmt3_ins = &instr.format3;
6569 address = fmt3_ins->address;
6570 cur_patch = patches;
6573 for (i = 0; i < address;) {
6574 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6576 if (skip_addr > i) {
6579 end_addr = MIN(address, skip_addr);
6580 address_offset += end_addr - i;
6586 address -= address_offset;
6587 fmt3_ins->address = address;
6596 if (fmt1_ins->parity != 0) {
6597 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6599 fmt1_ins->parity = 0;
6600 if ((ahc->features & AHC_CMD_CHAN) == 0
6601 && opcode == AIC_OP_BMOV) {
6603 * Block move was added at the same time
6604 * as the command channel. Verify that
6605 * this is only a move of a single element
6606 * and convert the BMOV to a MOV
6607 * (AND with an immediate of FF).
6609 if (fmt1_ins->immediate != 1)
6610 panic("%s: BMOV not supported\n",
6612 fmt1_ins->opcode = AIC_OP_AND;
6613 fmt1_ins->immediate = 0xff;
6617 if ((ahc->features & AHC_ULTRA2) != 0) {
6620 /* Calculate odd parity for the instruction */
6621 for (i = 0, count = 0; i < 31; i++) {
6625 if ((instr.integer & mask) != 0)
6628 if ((count & 0x01) == 0)
6629 instr.format1.parity = 1;
6631 /* Compress the instruction for older sequencers */
6632 if (fmt3_ins != NULL) {
6635 | (fmt3_ins->source << 8)
6636 | (fmt3_ins->address << 16)
6637 | (fmt3_ins->opcode << 25);
6641 | (fmt1_ins->source << 8)
6642 | (fmt1_ins->destination << 16)
6643 | (fmt1_ins->ret << 24)
6644 | (fmt1_ins->opcode << 25);
6647 /* The sequencer is a little endian cpu */
6648 instr.integer = aic_htole32(instr.integer);
6649 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6652 panic("Unknown opcode encountered in seq program");
6658 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6659 const char *name, u_int address, u_int value,
6660 u_int *cur_column, u_int wrap_point)
6666 if (cur_column == NULL) {
6668 cur_column = &dummy_column;
6671 if (*cur_column >= wrap_point) {
6675 printed = printf("%s[0x%x]", name, value);
6676 if (table == NULL) {
6677 printed += printf(" ");
6678 *cur_column += printed;
6682 while (printed_mask != 0xFF) {
6685 for (entry = 0; entry < num_entries; entry++) {
6686 if (((value & table[entry].mask)
6687 != table[entry].value)
6688 || ((printed_mask & table[entry].mask)
6689 == table[entry].mask))
6692 printed += printf("%s%s",
6693 printed_mask == 0 ? ":(" : "|",
6695 printed_mask |= table[entry].mask;
6699 if (entry >= num_entries)
6702 if (printed_mask != 0)
6703 printed += printf(") ");
6705 printed += printf(" ");
6706 if (cur_column != NULL)
6707 *cur_column += printed;
6712 ahc_dump_card_state(struct ahc_softc *ahc)
6715 struct scb_tailq *untagged_q;
6726 uint8_t saved_scbptr;
6728 if (ahc_is_paused(ahc)) {
6735 saved_scbptr = ahc_inb(ahc, SCBPTR);
6736 last_phase = ahc_inb(ahc, LASTPHASE);
6737 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6738 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6739 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6740 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6742 printf("Card was paused\n");
6743 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6744 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6745 ahc_inb(ahc, ARG_2));
6746 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6747 ahc_inb(ahc, SCBPTR));
6749 if ((ahc->features & AHC_DT) != 0)
6750 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6751 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6752 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6753 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6754 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6755 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6756 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6757 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6758 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6759 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6760 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6761 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6762 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6763 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6764 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6765 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6766 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6767 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6768 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6772 for (i = 0; i < STACK_SIZE; i++)
6773 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6774 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6775 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6776 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6778 printf("QINFIFO entries: ");
6779 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6780 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6781 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6783 qinpos = ahc_inb(ahc, QINPOS);
6784 qintail = ahc->qinfifonext;
6785 while (qinpos != qintail) {
6786 printf("%d ", ahc->qinfifo[qinpos]);
6791 printf("Waiting Queue entries: ");
6792 scb_index = ahc_inb(ahc, WAITING_SCBH);
6794 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6795 ahc_outb(ahc, SCBPTR, scb_index);
6796 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6797 scb_index = ahc_inb(ahc, SCB_NEXT);
6801 printf("Disconnected Queue entries: ");
6802 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6804 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6805 ahc_outb(ahc, SCBPTR, scb_index);
6806 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6807 scb_index = ahc_inb(ahc, SCB_NEXT);
6811 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6812 printf("QOUTFIFO entries: ");
6813 qoutpos = ahc->qoutfifonext;
6815 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6816 printf("%d ", ahc->qoutfifo[qoutpos]);
6821 printf("Sequencer Free SCB List: ");
6822 scb_index = ahc_inb(ahc, FREE_SCBH);
6824 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6825 ahc_outb(ahc, SCBPTR, scb_index);
6826 printf("%d ", scb_index);
6827 scb_index = ahc_inb(ahc, SCB_NEXT);
6831 printf("Sequencer SCB Info: ");
6832 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6833 ahc_outb(ahc, SCBPTR, i);
6834 cur_col = printf("\n%3d ", i);
6836 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6837 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6838 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6839 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6843 printf("Pending list: ");
6845 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6848 cur_col = printf("\n%3d ", scb->hscb->tag);
6849 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6850 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6851 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6852 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6853 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6855 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6857 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6863 printf("Kernel Free SCB list: ");
6865 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6868 printf("%d ", scb->hscb->tag);
6872 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6873 for (target = 0; target <= maxtarget; target++) {
6874 untagged_q = &ahc->untagged_queues[target];
6875 if (TAILQ_FIRST(untagged_q) == NULL)
6877 printf("Untagged Q(%d): ", target);
6879 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6882 printf("%d ", scb->hscb->tag);
6887 ahc_platform_dump_card_state(ahc);
6888 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6889 ahc_outb(ahc, SCBPTR, saved_scbptr);
6894 /*************************** Timeout Handling *********************************/
6896 ahc_timeout(struct scb *scb)
6898 struct ahc_softc *ahc;
6900 ahc = scb->ahc_softc;
6901 if ((scb->flags & SCB_ACTIVE) != 0) {
6902 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6903 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6905 scb->flags |= SCB_TIMEDOUT;
6907 ahc_wakeup_recovery_thread(ahc);
6912 * Re-schedule a timeout for the passed in SCB if we determine that some
6913 * other SCB is in the process of recovery or an SCB with a longer
6914 * timeout is still pending. Limit our search to just "other_scb"
6915 * if it is non-NULL.
6918 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6919 struct scb *other_scb)
6924 ahc_print_path(ahc, scb);
6925 printf("Other SCB Timeout%s",
6926 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6927 ? " again\n" : "\n");
6929 newtimeout = aic_get_timeout(scb);
6930 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6932 if (other_scb != NULL) {
6933 if ((other_scb->flags
6934 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6935 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6937 newtimeout = MAX(aic_get_timeout(other_scb),
6941 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6942 if ((other_scb->flags
6943 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6944 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6947 MAX(aic_get_timeout(other_scb),
6954 aic_scb_timer_reset(scb, newtimeout);
6956 ahc_print_path(ahc, scb);
6957 printf("No other SCB worth waiting for...\n");
6960 return (found != 0);
6964 * ahc_recover_commands determines if any of the commands that have currently
6965 * timedout are the root cause for this timeout. Innocent commands are given
6966 * a new timeout while we wait for the command executing on the bus to timeout.
6967 * This routine is invoked from a thread context so we are allowed to sleep.
6968 * Our lock is not held on entry.
6971 ahc_recover_commands(struct ahc_softc *ahc)
6979 * Pause the controller and manually flush any
6980 * commands that have just completed but that our
6981 * interrupt handler has yet to see.
6983 ahc_pause_and_flushwork(ahc);
6985 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
6987 * The timedout commands have already
6988 * completed. This typically means
6989 * that either the timeout value was on
6990 * the hairy edge of what the device
6991 * requires or - more likely - interrupts
6992 * are not happening.
6994 printf("%s: Timedout SCBs already complete. "
6995 "Interrupts may not be functioning.\n", ahc_name(ahc));
7001 printf("%s: Recovery Initiated\n", ahc_name(ahc));
7002 ahc_dump_card_state(ahc);
7004 last_phase = ahc_inb(ahc, LASTPHASE);
7005 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7006 u_int active_scb_index;
7013 target = SCB_GET_TARGET(ahc, scb);
7014 channel = SCB_GET_CHANNEL(ahc, scb);
7015 lun = SCB_GET_LUN(scb);
7017 ahc_print_path(ahc, scb);
7018 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7019 if (scb->sg_count > 0) {
7020 for (i = 0; i < scb->sg_count; i++) {
7021 printf("sg[%d] - Addr 0x%x : Length %d\n",
7023 scb->sg_list[i].addr,
7024 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7027 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7029 * Been down this road before.
7030 * Do a full bus reset.
7032 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7034 found = ahc_reset_channel(ahc, channel,
7035 /*Initiate Reset*/TRUE);
7036 printf("%s: Issued Channel %c Bus Reset. "
7037 "%d SCBs aborted\n", ahc_name(ahc), channel,
7043 * Remove the command from the timedout list in
7044 * preparation for requeing it.
7046 LIST_REMOVE(scb, timedout_links);
7047 scb->flags &= ~SCB_TIMEDOUT;
7050 * If we are a target, transition to bus free and report
7053 * The target/initiator that is holding up the bus may not
7054 * be the same as the one that triggered this timeout
7055 * (different commands have different timeout lengths).
7056 * If the bus is idle and we are actiing as the initiator
7057 * for this request, queue a BDR message to the timed out
7058 * target. Otherwise, if the timed out transaction is
7060 * Initiator transaction:
7061 * Stuff the message buffer with a BDR message and assert
7062 * ATN in the hopes that the target will let go of the bus
7063 * and go to the mesgout phase. If this fails, we'll
7064 * get another timeout 2 seconds later which will attempt
7067 * Target transaction:
7068 * Transition to BUS FREE and report the error.
7069 * It's good to be the target!
7071 saved_scbptr = ahc_inb(ahc, SCBPTR);
7072 active_scb_index = ahc_inb(ahc, SCB_TAG);
7074 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7075 && (active_scb_index < ahc->scb_data->numscbs)) {
7076 struct scb *active_scb;
7079 * If the active SCB is not us, assume that
7080 * the active SCB has a longer timeout than
7081 * the timedout SCB, and wait for the active
7084 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7085 if (active_scb != scb) {
7086 if (ahc_other_scb_timeout(ahc, scb,
7093 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7095 * Send back any queued up transactions
7096 * and properly record the error condition.
7098 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7099 SCB_GET_CHANNEL(ahc, scb),
7105 /* Will clear us from the bus */
7110 ahc_set_recoveryscb(ahc, active_scb);
7111 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7112 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7113 ahc_print_path(ahc, active_scb);
7114 printf("BDR message in message buffer\n");
7115 active_scb->flags |= SCB_DEVICE_RESET;
7116 aic_scb_timer_reset(scb, 2 * 1000);
7117 } else if (last_phase != P_BUSFREE
7118 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7120 * SCB is not identified, there
7121 * is no pending REQ, and the sequencer
7122 * has not seen a busfree. Looks like
7123 * a stuck connection waiting to
7124 * go busfree. Reset the bus.
7126 printf("%s: Connection stuck awaiting busfree or "
7127 "Identify Msg.\n", ahc_name(ahc));
7132 if (last_phase != P_BUSFREE
7133 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7134 /* Hung target selection. Goto busfree */
7135 printf("%s: Hung target selection\n",
7141 /* XXX Shouldn't panic. Just punt instead? */
7142 if ((scb->flags & SCB_TARGET_SCB) != 0)
7143 panic("Timed-out target SCB but bus idle");
7145 if (ahc_search_qinfifo(ahc, target, channel, lun,
7146 scb->hscb->tag, ROLE_INITIATOR,
7147 /*status*/0, SEARCH_COUNT) > 0) {
7148 disconnected = FALSE;
7150 disconnected = TRUE;
7154 ahc_set_recoveryscb(ahc, scb);
7156 * Actually re-queue this SCB in an attempt
7157 * to select the device before it reconnects.
7158 * In either case (selection or reselection),
7159 * we will now issue a target reset to the
7162 * Set the MK_MESSAGE control bit indicating
7163 * that we desire to send a message. We
7164 * also set the disconnected flag since
7165 * in the paging case there is no guarantee
7166 * that our SCB control byte matches the
7167 * version on the card. We don't want the
7168 * sequencer to abort the command thinking
7169 * an unsolicited reselection occurred.
7171 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7172 scb->flags |= SCB_DEVICE_RESET;
7175 * Remove any cached copy of this SCB in the
7176 * disconnected list in preparation for the
7177 * queuing of our abort SCB. We use the
7178 * same element in the SCB, SCB_NEXT, for
7179 * both the qinfifo and the disconnected list.
7181 ahc_search_disc_list(ahc, target, channel,
7182 lun, scb->hscb->tag,
7183 /*stop_on_first*/TRUE,
7185 /*save_state*/FALSE);
7188 * In the non-paging case, the sequencer will
7189 * never re-reference the in-core SCB.
7190 * To make sure we are notified during
7191 * reslection, set the MK_MESSAGE flag in
7192 * the card's copy of the SCB.
7194 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7195 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7196 ahc_outb(ahc, SCB_CONTROL,
7197 ahc_inb(ahc, SCB_CONTROL)
7202 * Clear out any entries in the QINFIFO first
7203 * so we are the next SCB for this target
7206 ahc_search_qinfifo(ahc,
7207 SCB_GET_TARGET(ahc, scb),
7208 channel, SCB_GET_LUN(scb),
7213 ahc_print_path(ahc, scb);
7214 printf("Queuing a BDR SCB\n");
7215 ahc_qinfifo_requeue_tail(ahc, scb);
7216 ahc_outb(ahc, SCBPTR, saved_scbptr);
7217 aic_scb_timer_reset(scb, 2 * 1000);
7219 /* Go "immediately" to the bus reset */
7220 /* This shouldn't happen */
7221 ahc_set_recoveryscb(ahc, scb);
7222 ahc_print_path(ahc, scb);
7223 printf("SCB %d: Immediate reset. "
7224 "Flags = 0x%x\n", scb->hscb->tag,
7233 * Any remaining SCBs were not the "culprit", so remove
7234 * them from the timeout list. The timer for these commands
7235 * will be reset once the recovery SCB completes.
7237 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7238 LIST_REMOVE(scb, timedout_links);
7239 scb->flags &= ~SCB_TIMEDOUT;
7248 /************************* Target Mode ****************************************/
7249 #ifdef AHC_TARGET_MODE
7251 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7252 struct ahc_tmode_tstate **tstate,
7253 struct ahc_tmode_lstate **lstate,
7254 int notfound_failure)
7257 if ((ahc->features & AHC_TARGETMODE) == 0)
7258 return (CAM_REQ_INVALID);
7261 * Handle the 'black hole' device that sucks up
7262 * requests to unattached luns on enabled targets.
7264 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7265 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7267 *lstate = ahc->black_hole;
7271 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7272 if (ccb->ccb_h.target_id > max_id)
7273 return (CAM_TID_INVALID);
7275 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7276 return (CAM_LUN_INVALID);
7278 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7280 if (*tstate != NULL)
7282 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7285 if (notfound_failure != 0 && *lstate == NULL)
7286 return (CAM_PATH_INVALID);
7288 return (CAM_REQ_CMP);
7292 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7294 struct ahc_tmode_tstate *tstate;
7295 struct ahc_tmode_lstate *lstate;
7296 struct ccb_en_lun *cel;
7305 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7306 /*notfound_failure*/FALSE);
7308 if (status != CAM_REQ_CMP) {
7309 ccb->ccb_h.status = status;
7313 if (cam_sim_bus(sim) == 0)
7314 our_id = ahc->our_id;
7316 our_id = ahc->our_id_b;
7318 if (ccb->ccb_h.target_id != our_id
7319 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7321 * our_id represents our initiator ID, or
7322 * the ID of the first target to have an
7323 * enabled lun in target mode. There are
7324 * two cases that may preclude enabling a
7325 * target id other than our_id.
7327 * o our_id is for an active initiator role.
7328 * Since the hardware does not support
7329 * reselections to the initiator role at
7330 * anything other than our_id, and our_id
7331 * is used by the hardware to indicate the
7332 * ID to use for both select-out and
7333 * reselect-out operations, the only target
7334 * ID we can support in this mode is our_id.
7336 * o The MULTARGID feature is not available and
7337 * a previous target mode ID has been enabled.
7339 if ((ahc->features & AHC_MULTIROLE) != 0) {
7340 if ((ahc->features & AHC_MULTI_TID) != 0
7341 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7343 * Only allow additional targets if
7344 * the initiator role is disabled.
7345 * The hardware cannot handle a re-select-in
7346 * on the initiator id during a re-select-out
7347 * on a different target id.
7349 status = CAM_TID_INVALID;
7350 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7351 || ahc->enabled_luns > 0) {
7353 * Only allow our target id to change
7354 * if the initiator role is not configured
7355 * and there are no enabled luns which
7356 * are attached to the currently registered
7359 status = CAM_TID_INVALID;
7361 } else if ((ahc->features & AHC_MULTI_TID) == 0
7362 && ahc->enabled_luns > 0) {
7363 status = CAM_TID_INVALID;
7367 if (status != CAM_REQ_CMP) {
7368 ccb->ccb_h.status = status;
7373 * We now have an id that is valid.
7374 * If we aren't in target mode, switch modes.
7376 if ((ahc->flags & AHC_TARGETROLE) == 0
7377 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7378 ahc_flag saved_flags;
7380 printf("Configuring Target Mode\n");
7381 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7382 ccb->ccb_h.status = CAM_BUSY;
7385 saved_flags = ahc->flags;
7386 ahc->flags |= AHC_TARGETROLE;
7387 if ((ahc->features & AHC_MULTIROLE) == 0)
7388 ahc->flags &= ~AHC_INITIATORROLE;
7390 error = ahc_loadseq(ahc);
7393 * Restore original configuration and notify
7394 * the caller that we cannot support target mode.
7395 * Since the adapter started out in this
7396 * configuration, the firmware load will succeed,
7397 * so there is no point in checking ahc_loadseq's
7400 ahc->flags = saved_flags;
7401 (void)ahc_loadseq(ahc);
7403 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7409 target = ccb->ccb_h.target_id;
7410 lun = ccb->ccb_h.target_lun;
7411 channel = SIM_CHANNEL(ahc, sim);
7412 target_mask = 0x01 << target;
7416 if (cel->enable != 0) {
7419 /* Are we already enabled?? */
7420 if (lstate != NULL) {
7421 xpt_print_path(ccb->ccb_h.path);
7422 printf("Lun already enabled\n");
7423 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7427 if (cel->grp6_len != 0
7428 || cel->grp7_len != 0) {
7430 * Don't (yet?) support vendor
7431 * specific commands.
7433 ccb->ccb_h.status = CAM_REQ_INVALID;
7434 printf("Non-zero Group Codes\n");
7440 * Setup our data structures.
7442 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7443 tstate = ahc_alloc_tstate(ahc, target, channel);
7444 if (tstate == NULL) {
7445 xpt_print_path(ccb->ccb_h.path);
7446 printf("Couldn't allocate tstate\n");
7447 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7451 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7452 if (lstate == NULL) {
7453 xpt_print_path(ccb->ccb_h.path);
7454 printf("Couldn't allocate lstate\n");
7455 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7458 memset(lstate, 0, sizeof(*lstate));
7459 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7460 xpt_path_path_id(ccb->ccb_h.path),
7461 xpt_path_target_id(ccb->ccb_h.path),
7462 xpt_path_lun_id(ccb->ccb_h.path));
7463 if (status != CAM_REQ_CMP) {
7464 free(lstate, M_DEVBUF);
7465 xpt_print_path(ccb->ccb_h.path);
7466 printf("Couldn't allocate path\n");
7467 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7470 SLIST_INIT(&lstate->accept_tios);
7471 SLIST_INIT(&lstate->immed_notifies);
7473 if (target != CAM_TARGET_WILDCARD) {
7474 tstate->enabled_luns[lun] = lstate;
7475 ahc->enabled_luns++;
7477 if ((ahc->features & AHC_MULTI_TID) != 0) {
7480 targid_mask = ahc_inb(ahc, TARGID)
7481 | (ahc_inb(ahc, TARGID + 1) << 8);
7483 targid_mask |= target_mask;
7484 ahc_outb(ahc, TARGID, targid_mask);
7485 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7487 ahc_update_scsiid(ahc, targid_mask);
7492 channel = SIM_CHANNEL(ahc, sim);
7493 our_id = SIM_SCSI_ID(ahc, sim);
7496 * This can only happen if selections
7499 if (target != our_id) {
7504 sblkctl = ahc_inb(ahc, SBLKCTL);
7505 cur_channel = (sblkctl & SELBUSB)
7507 if ((ahc->features & AHC_TWIN) == 0)
7509 swap = cur_channel != channel;
7511 ahc->our_id = target;
7513 ahc->our_id_b = target;
7516 ahc_outb(ahc, SBLKCTL,
7519 ahc_outb(ahc, SCSIID, target);
7522 ahc_outb(ahc, SBLKCTL, sblkctl);
7526 ahc->black_hole = lstate;
7527 /* Allow select-in operations */
7528 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7529 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7531 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7532 scsiseq = ahc_inb(ahc, SCSISEQ);
7534 ahc_outb(ahc, SCSISEQ, scsiseq);
7537 ccb->ccb_h.status = CAM_REQ_CMP;
7538 xpt_print_path(ccb->ccb_h.path);
7539 printf("Lun now enabled for target mode\n");
7544 if (lstate == NULL) {
7545 ccb->ccb_h.status = CAM_LUN_INVALID;
7549 ccb->ccb_h.status = CAM_REQ_CMP;
7550 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7551 struct ccb_hdr *ccbh;
7553 ccbh = &scb->io_ctx->ccb_h;
7554 if (ccbh->func_code == XPT_CONT_TARGET_IO
7555 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7556 printf("CTIO pending\n");
7557 ccb->ccb_h.status = CAM_REQ_INVALID;
7562 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7563 printf("ATIOs pending\n");
7564 ccb->ccb_h.status = CAM_REQ_INVALID;
7567 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7568 printf("INOTs pending\n");
7569 ccb->ccb_h.status = CAM_REQ_INVALID;
7572 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7576 xpt_print_path(ccb->ccb_h.path);
7577 printf("Target mode disabled\n");
7578 xpt_free_path(lstate->path);
7579 free(lstate, M_DEVBUF);
7582 /* Can we clean up the target too? */
7583 if (target != CAM_TARGET_WILDCARD) {
7584 tstate->enabled_luns[lun] = NULL;
7585 ahc->enabled_luns--;
7586 for (empty = 1, i = 0; i < 8; i++)
7587 if (tstate->enabled_luns[i] != NULL) {
7593 ahc_free_tstate(ahc, target, channel,
7595 if (ahc->features & AHC_MULTI_TID) {
7598 targid_mask = ahc_inb(ahc, TARGID)
7599 | (ahc_inb(ahc, TARGID + 1)
7602 targid_mask &= ~target_mask;
7603 ahc_outb(ahc, TARGID, targid_mask);
7604 ahc_outb(ahc, TARGID+1,
7605 (targid_mask >> 8));
7606 ahc_update_scsiid(ahc, targid_mask);
7610 ahc->black_hole = NULL;
7613 * We can't allow selections without
7614 * our black hole device.
7618 if (ahc->enabled_luns == 0) {
7619 /* Disallow select-in */
7622 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7624 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7625 scsiseq = ahc_inb(ahc, SCSISEQ);
7627 ahc_outb(ahc, SCSISEQ, scsiseq);
7629 if ((ahc->features & AHC_MULTIROLE) == 0) {
7630 printf("Configuring Initiator Mode\n");
7631 ahc->flags &= ~AHC_TARGETROLE;
7632 ahc->flags |= AHC_INITIATORROLE;
7634 * Returning to a configuration that
7635 * fit previously will always succeed.
7637 (void)ahc_loadseq(ahc);
7640 * Unpaused. The extra unpause
7641 * that follows is harmless.
7650 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7655 if ((ahc->features & AHC_MULTI_TID) == 0)
7656 panic("ahc_update_scsiid called on non-multitid unit\n");
7659 * Since we will rely on the TARGID mask
7660 * for selection enables, ensure that OID
7661 * in SCSIID is not set to some other ID
7662 * that we don't want to allow selections on.
7664 if ((ahc->features & AHC_ULTRA2) != 0)
7665 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7667 scsiid = ahc_inb(ahc, SCSIID);
7668 scsiid_mask = 0x1 << (scsiid & OID);
7669 if ((targid_mask & scsiid_mask) == 0) {
7672 /* ffs counts from 1 */
7673 our_id = ffs(targid_mask);
7675 our_id = ahc->our_id;
7681 if ((ahc->features & AHC_ULTRA2) != 0)
7682 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7684 ahc_outb(ahc, SCSIID, scsiid);
7688 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7690 struct target_cmd *cmd;
7693 * If the card supports auto-access pause,
7694 * we can access the card directly regardless
7695 * of whether it is paused or not.
7697 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7700 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7701 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7703 * Only advance through the queue if we
7704 * have the resources to process the command.
7706 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7710 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7711 ahc->shared_data_dmamap,
7712 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7713 sizeof(struct target_cmd),
7714 BUS_DMASYNC_PREREAD);
7715 ahc->tqinfifonext++;
7718 * Lazily update our position in the target mode incoming
7719 * command queue as seen by the sequencer.
7721 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7722 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7725 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7726 hs_mailbox &= ~HOST_TQINPOS;
7727 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7728 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7732 ahc_outb(ahc, KERNEL_TQINPOS,
7733 ahc->tqinfifonext & HOST_TQINPOS);
7742 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7744 struct ahc_tmode_tstate *tstate;
7745 struct ahc_tmode_lstate *lstate;
7746 struct ccb_accept_tio *atio;
7752 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7753 target = SCSIID_OUR_ID(cmd->scsiid);
7754 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7757 tstate = ahc->enabled_targets[target];
7760 lstate = tstate->enabled_luns[lun];
7763 * Commands for disabled luns go to the black hole driver.
7766 lstate = ahc->black_hole;
7768 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7770 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7772 * Wait for more ATIOs from the peripheral driver for this lun.
7775 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7778 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7780 if (ahc_debug & AHC_SHOW_TQIN) {
7781 printf("Incoming command from %d for %d:%d%s\n",
7782 initiator, target, lun,
7783 lstate == ahc->black_hole ? "(Black Holed)" : "");
7786 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7788 if (lstate == ahc->black_hole) {
7789 /* Fill in the wildcards */
7790 atio->ccb_h.target_id = target;
7791 atio->ccb_h.target_lun = lun;
7795 * Package it up and send it off to
7796 * whomever has this lun enabled.
7798 atio->sense_len = 0;
7799 atio->init_id = initiator;
7800 if (byte[0] != 0xFF) {
7801 /* Tag was included */
7802 atio->tag_action = *byte++;
7803 atio->tag_id = *byte++;
7804 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
7806 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
7810 /* Okay. Now determine the cdb size based on the command code */
7811 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7827 /* Only copy the opcode. */
7829 printf("Reserved or VU command code type encountered\n");
7833 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7835 atio->ccb_h.status |= CAM_CDB_RECVD;
7837 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7839 * We weren't allowed to disconnect.
7840 * We're hanging on the bus until a
7841 * continue target I/O comes in response
7842 * to this accept tio.
7845 if (ahc_debug & AHC_SHOW_TQIN) {
7846 printf("Received Immediate Command %d:%d:%d - %p\n",
7847 initiator, target, lun, ahc->pending_device);
7850 ahc->pending_device = lstate;
7851 aic_freeze_ccb((union ccb *)atio);
7852 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7854 xpt_done((union ccb*)atio);