2 * Core routines and tables shareable across OS platforms.
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <dev/aic7xxx/aic7xxx_osm.h>
53 #include <dev/aic7xxx/aic7xxx_inline.h>
54 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
57 /****************************** Softc Data ************************************/
58 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
60 /***************************** Lookup Tables **********************************/
61 char *ahc_chip_names[] =
80 * Hardware error codes.
82 struct ahc_hard_error_entry {
87 static struct ahc_hard_error_entry ahc_hard_errors[] = {
88 { ILLHADDR, "Illegal Host Access" },
89 { ILLSADDR, "Illegal Sequencer Address referrenced" },
90 { ILLOPCODE, "Illegal Opcode in sequencer program" },
91 { SQPARERR, "Sequencer Parity Error" },
92 { DPARERR, "Data-path Parity Error" },
93 { MPARERR, "Scratch or SCB Memory Parity Error" },
94 { PCIERRSTAT, "PCI Error detected" },
95 { CIOPARERR, "CIOBUS Parity Error" },
97 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
99 static struct ahc_phase_table_entry ahc_phase_table[] =
101 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
102 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
103 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
104 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
105 { P_COMMAND, MSG_NOOP, "in Command phase" },
106 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
107 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
108 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
109 { P_BUSFREE, MSG_NOOP, "while idle" },
110 { 0, MSG_NOOP, "in unknown phase" }
114 * In most cases we only wish to itterate over real phases, so
115 * exclude the last element from the count.
117 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
120 * Valid SCSIRATE values. (p. 3-17)
121 * Provides a mapping of transfer periods in ns to the proper value to
122 * stick in the scsixfer reg.
124 static struct ahc_syncrate ahc_syncrates[] =
126 /* ultra2 fast/ultra period rate */
127 { 0x42, 0x000, 9, "80.0" },
128 { 0x03, 0x000, 10, "40.0" },
129 { 0x04, 0x000, 11, "33.0" },
130 { 0x05, 0x100, 12, "20.0" },
131 { 0x06, 0x110, 15, "16.0" },
132 { 0x07, 0x120, 18, "13.4" },
133 { 0x08, 0x000, 25, "10.0" },
134 { 0x19, 0x010, 31, "8.0" },
135 { 0x1a, 0x020, 37, "6.67" },
136 { 0x1b, 0x030, 43, "5.7" },
137 { 0x1c, 0x040, 50, "5.0" },
138 { 0x00, 0x050, 56, "4.4" },
139 { 0x00, 0x060, 62, "4.0" },
140 { 0x00, 0x070, 68, "3.6" },
141 { 0x00, 0x000, 0, NULL }
144 /* Our Sequencer Program */
145 #include "aic7xxx_seq.h"
147 /**************************** Function Declarations ***************************/
148 static void ahc_force_renegotiation(struct ahc_softc *ahc,
149 struct ahc_devinfo *devinfo);
150 static struct ahc_tmode_tstate*
151 ahc_alloc_tstate(struct ahc_softc *ahc,
152 u_int scsi_id, char channel);
153 #ifdef AHC_TARGET_MODE
154 static void ahc_free_tstate(struct ahc_softc *ahc,
155 u_int scsi_id, char channel, int force);
157 static struct ahc_syncrate*
158 ahc_devlimited_syncrate(struct ahc_softc *ahc,
159 struct ahc_initiator_tinfo *,
163 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
164 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo);
166 static void ahc_scb_devinfo(struct ahc_softc *ahc,
167 struct ahc_devinfo *devinfo,
169 static void ahc_assert_atn(struct ahc_softc *ahc);
170 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
171 struct ahc_devinfo *devinfo,
173 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
174 struct ahc_devinfo *devinfo);
175 static void ahc_construct_sdtr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset);
178 static void ahc_construct_wdtr(struct ahc_softc *ahc,
179 struct ahc_devinfo *devinfo,
181 static void ahc_construct_ppr(struct ahc_softc *ahc,
182 struct ahc_devinfo *devinfo,
183 u_int period, u_int offset,
184 u_int bus_width, u_int ppr_options);
185 static void ahc_clear_msg_state(struct ahc_softc *ahc);
186 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
187 static void ahc_handle_message_phase(struct ahc_softc *ahc);
193 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
194 u_int msgval, int full);
195 static int ahc_parse_msg(struct ahc_softc *ahc,
196 struct ahc_devinfo *devinfo);
197 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
198 struct ahc_devinfo *devinfo);
199 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
200 struct ahc_devinfo *devinfo);
201 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
202 static void ahc_handle_devreset(struct ahc_softc *ahc,
203 struct ahc_devinfo *devinfo,
204 cam_status status, char *message,
206 #ifdef AHC_TARGET_MODE
207 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
208 struct ahc_devinfo *devinfo,
212 static bus_dmamap_callback_t ahc_dmamap_cb;
213 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
214 static int ahc_init_scbdata(struct ahc_softc *ahc);
215 static void ahc_fini_scbdata(struct ahc_softc *ahc);
216 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
217 struct scb *prev_scb,
219 static int ahc_qinfifo_count(struct ahc_softc *ahc);
220 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
221 u_int prev, u_int scbptr);
222 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
223 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
224 u_int scbpos, u_int prev);
225 static void ahc_reset_current_bus(struct ahc_softc *ahc);
227 static void ahc_dumpseq(struct ahc_softc *ahc);
229 static int ahc_loadseq(struct ahc_softc *ahc);
230 static int ahc_check_patch(struct ahc_softc *ahc,
231 struct patch **start_patch,
232 u_int start_instr, u_int *skip_addr);
233 static void ahc_download_instr(struct ahc_softc *ahc,
234 u_int instrptr, uint8_t *dconsts);
235 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
237 struct scb *other_scb);
238 #ifdef AHC_TARGET_MODE
239 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
240 struct ahc_tmode_lstate *lstate,
244 static void ahc_update_scsiid(struct ahc_softc *ahc,
246 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
247 struct target_cmd *cmd);
249 /************************* Sequencer Execution Control ************************/
251 * Restart the sequencer program from address zero
254 ahc_restart(struct ahc_softc *ahc)
259 /* No more pending messages. */
260 ahc_clear_msg_state(ahc);
262 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
263 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
264 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
265 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
266 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
267 ahc_outb(ahc, SAVED_LUN, 0xFF);
270 * Ensure that the sequencer's idea of TQINPOS
271 * matches our own. The sequencer increments TQINPOS
272 * only after it sees a DMA complete and a reset could
273 * occur before the increment leaving the kernel to believe
274 * the command arrived but the sequencer to not.
276 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
278 /* Always allow reselection */
279 ahc_outb(ahc, SCSISEQ,
280 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
281 if ((ahc->features & AHC_CMD_CHAN) != 0) {
282 /* Ensure that no DMA operations are in progress */
283 ahc_outb(ahc, CCSCBCNT, 0);
284 ahc_outb(ahc, CCSGCTL, 0);
285 ahc_outb(ahc, CCSCBCTL, 0);
288 * If we were in the process of DMA'ing SCB data into
289 * an SCB, replace that SCB on the free list. This prevents
292 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
293 ahc_add_curscb_to_free_list(ahc);
294 ahc_outb(ahc, SEQ_FLAGS2,
295 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
299 * Clear any pending sequencer interrupt. It is no
300 * longer relevant since we're resetting the Program
303 ahc_outb(ahc, CLRINT, CLRSEQINT);
305 ahc_outb(ahc, MWI_RESIDUAL, 0);
306 ahc_outb(ahc, SEQCTL, ahc->seqctl);
307 ahc_outb(ahc, SEQADDR0, 0);
308 ahc_outb(ahc, SEQADDR1, 0);
313 /************************* Input/Output Queues ********************************/
315 ahc_run_qoutfifo(struct ahc_softc *ahc)
320 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
321 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
323 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
324 if ((ahc->qoutfifonext & 0x03) == 0x03) {
328 * Clear 32bits of QOUTFIFO at a time
329 * so that we don't clobber an incoming
330 * byte DMA to the array on architectures
331 * that only support 32bit load and store
334 modnext = ahc->qoutfifonext & ~0x3;
335 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
336 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
337 ahc->shared_data_dmamap,
338 /*offset*/modnext, /*len*/4,
339 BUS_DMASYNC_PREREAD);
343 scb = ahc_lookup_scb(ahc, scb_index);
345 printf("%s: WARNING no command for scb %d "
346 "(cmdcmplt)\nQOUTPOS = %d\n",
347 ahc_name(ahc), scb_index,
348 (ahc->qoutfifonext - 1) & 0xFF);
353 * Save off the residual
356 ahc_update_residual(ahc, scb);
362 ahc_run_untagged_queues(struct ahc_softc *ahc)
366 for (i = 0; i < 16; i++)
367 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
371 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
375 if (ahc->untagged_queue_lock != 0)
378 if ((scb = TAILQ_FIRST(queue)) != NULL
379 && (scb->flags & SCB_ACTIVE) == 0) {
380 scb->flags |= SCB_ACTIVE;
382 * Timers are disabled while recovery is in progress.
384 aic_scb_timer_start(scb);
385 ahc_queue_scb(ahc, scb);
389 /************************* Interrupt Handling *********************************/
391 ahc_handle_brkadrint(struct ahc_softc *ahc)
394 * We upset the sequencer :-(
395 * Lookup the error message
400 error = ahc_inb(ahc, ERROR);
401 for (i = 0; error != 1 && i < num_errors; i++)
403 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
404 ahc_name(ahc), ahc_hard_errors[i].errmesg,
405 ahc_inb(ahc, SEQADDR0) |
406 (ahc_inb(ahc, SEQADDR1) << 8));
408 ahc_dump_card_state(ahc);
410 /* Tell everyone that this HBA is no longer available */
411 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
412 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
415 /* Disable all interrupt sources by resetting the controller */
420 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
423 struct ahc_devinfo devinfo;
425 ahc_fetch_devinfo(ahc, &devinfo);
428 * Clear the upper byte that holds SEQINT status
429 * codes and clear the SEQINT bit. We will unpause
430 * the sequencer, if appropriate, after servicing
433 ahc_outb(ahc, CLRINT, CLRSEQINT);
434 switch (intstat & SEQINT_MASK) {
438 struct hardware_scb *hscb;
441 * Set the default return value to 0 (don't
442 * send sense). The sense code will change
445 ahc_outb(ahc, RETURN_1, 0);
448 * The sequencer will notify us when a command
449 * has an error that would be of interest to
450 * the kernel. This allows us to leave the sequencer
451 * running in the common case of command completes
452 * without error. The sequencer will already have
453 * dma'd the SCB back up to us, so we can reference
454 * the in kernel copy directly.
456 scb_index = ahc_inb(ahc, SCB_TAG);
457 scb = ahc_lookup_scb(ahc, scb_index);
459 ahc_print_devinfo(ahc, &devinfo);
460 printf("ahc_intr - referenced scb "
461 "not valid during seqint 0x%x scb(%d)\n",
463 ahc_dump_card_state(ahc);
470 /* Don't want to clobber the original sense code */
471 if ((scb->flags & SCB_SENSE) != 0) {
473 * Clear the SCB_SENSE Flag and have
474 * the sequencer do a normal command
477 scb->flags &= ~SCB_SENSE;
478 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
481 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
482 /* Freeze the queue until the client sees the error. */
483 ahc_freeze_devq(ahc, scb);
485 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
486 switch (hscb->shared_data.status.scsi_status) {
488 printf("%s: Interrupted for staus of 0???\n",
491 case SCSI_STATUS_CMD_TERMINATED:
492 case SCSI_STATUS_CHECK_COND:
494 struct ahc_dma_seg *sg;
495 struct scsi_sense *sc;
496 struct ahc_initiator_tinfo *targ_info;
497 struct ahc_tmode_tstate *tstate;
498 struct ahc_transinfo *tinfo;
500 if (ahc_debug & AHC_SHOW_SENSE) {
501 ahc_print_path(ahc, scb);
502 printf("SCB %d: requests Check Status\n",
507 if (aic_perform_autosense(scb) == 0)
510 targ_info = ahc_fetch_transinfo(ahc,
515 tinfo = &targ_info->curr;
517 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
519 * Save off the residual if there is one.
521 ahc_update_residual(ahc, scb);
523 if (ahc_debug & AHC_SHOW_SENSE) {
524 ahc_print_path(ahc, scb);
525 printf("Sending Sense\n");
528 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
529 sg->len = aic_get_sense_bufsize(ahc, scb);
530 sg->len |= AHC_DMA_LAST_SEG;
532 /* Fixup byte order */
533 sg->addr = aic_htole32(sg->addr);
534 sg->len = aic_htole32(sg->len);
536 sc->opcode = REQUEST_SENSE;
538 if (tinfo->protocol_version <= SCSI_REV_2
539 && SCB_GET_LUN(scb) < 8)
540 sc->byte2 = SCB_GET_LUN(scb) << 5;
543 sc->length = sg->len;
547 * We can't allow the target to disconnect.
548 * This will be an untagged transaction and
549 * having the target disconnect will make this
550 * transaction indestinguishable from outstanding
551 * tagged transactions.
556 * This request sense could be because the
557 * the device lost power or in some other
558 * way has lost our transfer negotiations.
559 * Renegotiate if appropriate. Unit attention
560 * errors will be reported before any data
563 if (aic_get_residual(scb)
564 == aic_get_transfer_length(scb)) {
565 ahc_update_neg_request(ahc, &devinfo,
567 AHC_NEG_IF_NON_ASYNC);
569 if (tstate->auto_negotiate & devinfo.target_mask) {
570 hscb->control |= MK_MESSAGE;
571 scb->flags &= ~SCB_NEGOTIATE;
572 scb->flags |= SCB_AUTO_NEGOTIATE;
574 hscb->cdb_len = sizeof(*sc);
575 hscb->dataptr = sg->addr;
576 hscb->datacnt = sg->len;
577 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
578 hscb->sgptr = aic_htole32(hscb->sgptr);
580 scb->flags |= SCB_SENSE;
581 ahc_qinfifo_requeue_tail(ahc, scb);
582 ahc_outb(ahc, RETURN_1, SEND_SENSE);
584 * Ensure we have enough time to actually
585 * retrieve the sense, but only schedule
586 * the timer if we are not in recovery or
587 * this is a recovery SCB that is allowed
588 * to have an active timer.
590 if (ahc->scb_data->recovery_scbs == 0
591 || (scb->flags & SCB_RECOVERY_SCB) != 0)
592 aic_scb_timer_reset(scb, 5 * 1000);
602 /* Ensure we don't leave the selection hardware on */
603 ahc_outb(ahc, SCSISEQ,
604 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
606 printf("%s:%c:%d: no active SCB for reconnecting "
607 "target - issuing BUS DEVICE RESET\n",
608 ahc_name(ahc), devinfo.channel, devinfo.target);
609 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
610 "ARG_1 == 0x%x ACCUM = 0x%x\n",
611 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
612 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
613 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
615 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
616 ahc_index_busy_tcl(ahc,
617 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
618 ahc_inb(ahc, SAVED_LUN))),
619 ahc_inb(ahc, SINDEX));
620 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
621 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
622 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
623 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
624 ahc_inb(ahc, SCB_CONTROL));
625 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
626 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
627 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
628 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
629 ahc_dump_card_state(ahc);
630 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
632 ahc->msgout_index = 0;
633 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
634 ahc_outb(ahc, MSG_OUT, HOST_MSG);
640 u_int rejbyte = ahc_inb(ahc, ACCUM);
641 printf("%s:%c:%d: Warning - unknown message received from "
642 "target (0x%x). Rejecting\n",
643 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
646 case PROTO_VIOLATION:
648 ahc_handle_proto_violation(ahc);
652 ahc_handle_ign_wide_residue(ahc, &devinfo);
655 ahc_reinitialize_dataptrs(ahc);
661 lastphase = ahc_inb(ahc, LASTPHASE);
662 printf("%s:%c:%d: unknown scsi bus phase %x, "
663 "lastphase = 0x%x. Attempting to continue\n",
664 ahc_name(ahc), devinfo.channel, devinfo.target,
665 lastphase, ahc_inb(ahc, SCSISIGI));
672 lastphase = ahc_inb(ahc, LASTPHASE);
673 printf("%s:%c:%d: Missed busfree. "
674 "Lastphase = 0x%x, Curphase = 0x%x\n",
675 ahc_name(ahc), devinfo.channel, devinfo.target,
676 lastphase, ahc_inb(ahc, SCSISIGI));
683 * The sequencer has encountered a message phase
684 * that requires host assistance for completion.
685 * While handling the message phase(s), we will be
686 * notified by the sequencer after each byte is
687 * transferred so we can track bus phase changes.
689 * If this is the first time we've seen a HOST_MSG_LOOP
690 * interrupt, initialize the state of the host message
693 if (ahc->msg_type == MSG_TYPE_NONE) {
698 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
699 if (bus_phase != P_MESGIN
700 && bus_phase != P_MESGOUT) {
701 printf("ahc_intr: HOST_MSG_LOOP bad "
705 * Probably transitioned to bus free before
706 * we got here. Just punt the message.
708 ahc_clear_intstat(ahc);
713 scb_index = ahc_inb(ahc, SCB_TAG);
714 scb = ahc_lookup_scb(ahc, scb_index);
715 if (devinfo.role == ROLE_INITIATOR) {
717 panic("HOST_MSG_LOOP with "
718 "invalid SCB %x\n", scb_index);
720 if (bus_phase == P_MESGOUT)
721 ahc_setup_initiator_msgout(ahc,
726 MSG_TYPE_INITIATOR_MSGIN;
727 ahc->msgin_index = 0;
730 #ifdef AHC_TARGET_MODE
732 if (bus_phase == P_MESGOUT) {
734 MSG_TYPE_TARGET_MSGOUT;
735 ahc->msgin_index = 0;
738 ahc_setup_target_msgin(ahc,
745 ahc_handle_message_phase(ahc);
751 * If we've cleared the parity error interrupt
752 * but the sequencer still believes that SCSIPERR
753 * is true, it must be that the parity error is
754 * for the currently presented byte on the bus,
755 * and we are not in a phase (data-in) where we will
756 * eventually ack this byte. Ack the byte and
757 * throw it away in the hope that the target will
758 * take us to message out to deliver the appropriate
761 if ((intstat & SCSIINT) == 0
762 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
764 if ((ahc->features & AHC_DT) == 0) {
768 * The hardware will only let you ack bytes
769 * if the expected phase in SCSISIGO matches
770 * the current phase. Make sure this is
771 * currently the case.
773 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
774 ahc_outb(ahc, LASTPHASE, curphase);
775 ahc_outb(ahc, SCSISIGO, curphase);
777 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
781 * In a data phase. Faster to bitbucket
782 * the data than to individually ack each
783 * byte. This is also the only strategy
784 * that will work with AUTOACK enabled.
786 ahc_outb(ahc, SXFRCTL1,
787 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
789 while (--wait != 0) {
790 if ((ahc_inb(ahc, SCSISIGI)
795 ahc_outb(ahc, SXFRCTL1,
796 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
801 ahc_print_devinfo(ahc, &devinfo);
802 printf("Unable to clear parity error. "
804 scb_index = ahc_inb(ahc, SCB_TAG);
805 scb = ahc_lookup_scb(ahc, scb_index);
807 aic_set_transaction_status(scb,
809 ahc_reset_channel(ahc, devinfo.channel,
813 ahc_inb(ahc, SCSIDATL);
821 * When the sequencer detects an overrun, it
822 * places the controller in "BITBUCKET" mode
823 * and allows the target to complete its transfer.
824 * Unfortunately, none of the counters get updated
825 * when the controller is in this mode, so we have
826 * no way of knowing how large the overrun was.
828 u_int scbindex = ahc_inb(ahc, SCB_TAG);
829 u_int lastphase = ahc_inb(ahc, LASTPHASE);
832 scb = ahc_lookup_scb(ahc, scbindex);
833 for (i = 0; i < num_phases; i++) {
834 if (lastphase == ahc_phase_table[i].phase)
837 ahc_print_path(ahc, scb);
838 printf("data overrun detected %s."
840 ahc_phase_table[i].phasemsg,
842 ahc_print_path(ahc, scb);
843 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
844 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
845 aic_get_transfer_length(scb), scb->sg_count);
846 if (scb->sg_count > 0) {
847 for (i = 0; i < scb->sg_count; i++) {
849 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
851 (aic_le32toh(scb->sg_list[i].len) >> 24
852 & SG_HIGH_ADDR_BITS),
853 aic_le32toh(scb->sg_list[i].addr),
854 aic_le32toh(scb->sg_list[i].len)
859 * Set this and it will take effect when the
860 * target does a command complete.
862 ahc_freeze_devq(ahc, scb);
863 if ((scb->flags & SCB_SENSE) == 0) {
864 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
866 scb->flags &= ~SCB_SENSE;
867 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
871 if ((ahc->features & AHC_ULTRA2) != 0) {
873 * Clear the channel in case we return
874 * to data phase later.
876 ahc_outb(ahc, SXFRCTL0,
877 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
878 ahc_outb(ahc, SXFRCTL0,
879 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
881 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
884 /* Ensure HHADDR is 0 for future DMA operations. */
885 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
886 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
887 ahc_outb(ahc, HADDR, 0);
888 ahc_outb(ahc, DSCOMMAND1, dscommand1);
896 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
897 ahc_name(ahc), devinfo.channel, devinfo.target,
899 scbindex = ahc_inb(ahc, SCB_TAG);
900 scb = ahc_lookup_scb(ahc, scbindex);
902 && (scb->flags & SCB_RECOVERY_SCB) != 0)
904 * Ensure that we didn't put a second instance of this
905 * SCB into the QINFIFO.
907 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
908 SCB_GET_CHANNEL(ahc, scb),
909 SCB_GET_LUN(scb), scb->hscb->tag,
910 ROLE_INITIATOR, /*status*/0,
916 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
917 ahc_dump_card_state(ahc);
925 scbptr = ahc_inb(ahc, SCBPTR);
926 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
927 scbptr, ahc_inb(ahc, ARG_1),
928 ahc->scb_data->hscbs[scbptr].tag);
929 ahc_dump_card_state(ahc);
935 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
936 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
937 "ARG_1 == 0x%x ACCUM = 0x%x\n",
938 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
939 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
940 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
941 "SINDEX == 0x%x\n, A == 0x%x\n",
942 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
943 ahc_index_busy_tcl(ahc,
944 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
945 ahc_inb(ahc, SAVED_LUN))),
946 ahc_inb(ahc, SINDEX),
947 ahc_inb(ahc, ACCUM));
948 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
949 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
950 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
951 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
952 ahc_inb(ahc, SCB_CONTROL));
953 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
954 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
955 ahc_dump_card_state(ahc);
960 printf("ahc_intr: seqint, "
961 "intstat == 0x%x, scsisigi = 0x%x\n",
962 intstat, ahc_inb(ahc, SCSISIGI));
967 * The sequencer is paused immediately on
968 * a SEQINT, so we should restart it when
975 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
984 if ((ahc->features & AHC_TWIN) != 0
985 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
989 intr_channel = cur_channel;
991 if ((ahc->features & AHC_ULTRA2) != 0)
992 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
995 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
996 if (status == 0 && status0 == 0) {
997 if ((ahc->features & AHC_TWIN) != 0) {
998 /* Try the other channel */
999 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1000 status = ahc_inb(ahc, SSTAT1)
1001 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1002 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1005 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1006 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1012 /* Make sure the sequencer is in a safe location. */
1013 ahc_clear_critical_section(ahc);
1015 scb_index = ahc_inb(ahc, SCB_TAG);
1016 scb = ahc_lookup_scb(ahc, scb_index);
1018 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1021 if ((ahc->features & AHC_ULTRA2) != 0
1022 && (status0 & IOERR) != 0) {
1025 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1026 printf("%s: Transceiver State Has Changed to %s mode\n",
1027 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1028 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1030 * When transitioning to SE mode, the reset line
1031 * glitches, triggering an arbitration bug in some
1032 * Ultra2 controllers. This bug is cleared when we
1033 * assert the reset line. Since a reset glitch has
1034 * already occurred with this transition and a
1035 * transceiver state change is handled just like
1036 * a bus reset anyway, asserting the reset line
1037 * ourselves is safe.
1039 ahc_reset_channel(ahc, intr_channel,
1040 /*Initiate Reset*/now_lvd == 0);
1041 } else if ((status & SCSIRSTI) != 0) {
1042 printf("%s: Someone reset channel %c\n",
1043 ahc_name(ahc), intr_channel);
1044 if (intr_channel != cur_channel)
1045 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1046 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1047 } else if ((status & SCSIPERR) != 0) {
1049 * Determine the bus phase and queue an appropriate message.
1050 * SCSIPERR is latched true as soon as a parity error
1051 * occurs. If the sequencer acked the transfer that
1052 * caused the parity error and the currently presented
1053 * transfer on the bus has correct parity, SCSIPERR will
1054 * be cleared by CLRSCSIPERR. Use this to determine if
1055 * we should look at the last phase the sequencer recorded,
1056 * or the current phase presented on the bus.
1058 struct ahc_devinfo devinfo;
1068 lastphase = ahc_inb(ahc, LASTPHASE);
1069 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1070 sstat2 = ahc_inb(ahc, SSTAT2);
1071 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1073 * For all phases save DATA, the sequencer won't
1074 * automatically ack a byte that has a parity error
1075 * in it. So the only way that the current phase
1076 * could be 'data-in' is if the parity error is for
1077 * an already acked byte in the data phase. During
1078 * synchronous data-in transfers, we may actually
1079 * ack bytes before latching the current phase in
1080 * LASTPHASE, leading to the discrepancy between
1081 * curphase and lastphase.
1083 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1084 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1085 errorphase = curphase;
1087 errorphase = lastphase;
1089 for (i = 0; i < num_phases; i++) {
1090 if (errorphase == ahc_phase_table[i].phase)
1093 mesg_out = ahc_phase_table[i].mesg_out;
1096 if (SCB_IS_SILENT(scb))
1099 ahc_print_path(ahc, scb);
1100 scb->flags |= SCB_TRANSMISSION_ERROR;
1102 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1103 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1104 scsirate = ahc_inb(ahc, SCSIRATE);
1105 if (silent == FALSE) {
1106 printf("parity error detected %s. "
1107 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1108 ahc_phase_table[i].phasemsg,
1109 ahc_inw(ahc, SEQADDR0),
1111 if ((ahc->features & AHC_DT) != 0) {
1112 if ((sstat2 & CRCVALERR) != 0)
1113 printf("\tCRC Value Mismatch\n");
1114 if ((sstat2 & CRCENDERR) != 0)
1115 printf("\tNo terminal CRC packet "
1117 if ((sstat2 & CRCREQERR) != 0)
1118 printf("\tIllegal CRC packet "
1120 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1121 printf("\tUnexpected %sDT Data Phase\n",
1122 (scsirate & SINGLE_EDGE)
1127 if ((ahc->features & AHC_DT) != 0
1128 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1130 * This error applies regardless of
1131 * data direction, so ignore the value
1132 * in the phase table.
1134 mesg_out = MSG_INITIATOR_DET_ERR;
1138 * We've set the hardware to assert ATN if we
1139 * get a parity error on "in" phases, so all we
1140 * need to do is stuff the message buffer with
1141 * the appropriate message. "In" phases have set
1142 * mesg_out to something other than MSG_NOP.
1144 if (mesg_out != MSG_NOOP) {
1145 if (ahc->msg_type != MSG_TYPE_NONE)
1146 ahc->send_msg_perror = TRUE;
1148 ahc_outb(ahc, MSG_OUT, mesg_out);
1151 * Force a renegotiation with this target just in
1152 * case we are out of sync for some external reason
1153 * unknown (or unreported) by the target.
1155 ahc_fetch_devinfo(ahc, &devinfo);
1156 ahc_force_renegotiation(ahc, &devinfo);
1158 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1160 } else if ((status & SELTO) != 0) {
1163 /* Stop the selection */
1164 ahc_outb(ahc, SCSISEQ, 0);
1166 /* No more pending messages */
1167 ahc_clear_msg_state(ahc);
1169 /* Clear interrupt state */
1170 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1171 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1174 * Although the driver does not care about the
1175 * 'Selection in Progress' status bit, the busy
1176 * LED does. SELINGO is only cleared by a successful
1177 * selection, so we must manually clear it to insure
1178 * the LED turns off just incase no future successful
1179 * selections occur (e.g. no devices on the bus).
1181 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1183 scbptr = ahc_inb(ahc, WAITING_SCBH);
1184 ahc_outb(ahc, SCBPTR, scbptr);
1185 scb_index = ahc_inb(ahc, SCB_TAG);
1187 scb = ahc_lookup_scb(ahc, scb_index);
1189 printf("%s: ahc_intr - referenced scb not "
1190 "valid during SELTO scb(%d, %d)\n",
1191 ahc_name(ahc), scbptr, scb_index);
1192 ahc_dump_card_state(ahc);
1194 struct ahc_devinfo devinfo;
1196 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1197 ahc_print_path(ahc, scb);
1198 printf("Saw Selection Timeout for SCB 0x%x\n",
1202 ahc_scb_devinfo(ahc, &devinfo, scb);
1203 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1204 ahc_freeze_devq(ahc, scb);
1207 * Cancel any pending transactions on the device
1208 * now that it seems to be missing. This will
1209 * also revert us to async/narrow transfers until
1210 * we can renegotiate with the device.
1212 ahc_handle_devreset(ahc, &devinfo,
1214 "Selection Timeout",
1215 /*verbose_level*/1);
1217 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1219 } else if ((status & BUSFREE) != 0
1220 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1221 struct ahc_devinfo devinfo;
1226 u_int initiator_role_id;
1231 * Clear our selection hardware as soon as possible.
1232 * We may have an entry in the waiting Q for this target,
1233 * that is affected by this busfree and we don't want to
1234 * go about selecting the target while we handle the event.
1236 ahc_outb(ahc, SCSISEQ,
1237 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1240 * Disable busfree interrupts and clear the busfree
1241 * interrupt status. We do this here so that several
1242 * bus transactions occur prior to clearing the SCSIINT
1243 * latch. It can take a bit for the clearing to take effect.
1245 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1246 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1249 * Look at what phase we were last in.
1250 * If its message out, chances are pretty good
1251 * that the busfree was in response to one of
1252 * our abort requests.
1254 lastphase = ahc_inb(ahc, LASTPHASE);
1255 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1256 saved_lun = ahc_inb(ahc, SAVED_LUN);
1257 target = SCSIID_TARGET(ahc, saved_scsiid);
1258 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1259 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1260 ahc_compile_devinfo(&devinfo, initiator_role_id,
1261 target, saved_lun, channel, ROLE_INITIATOR);
1264 if (lastphase == P_MESGOUT) {
1267 tag = SCB_LIST_NULL;
1268 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1269 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1270 if (ahc->msgout_buf[ahc->msgout_index - 1]
1272 tag = scb->hscb->tag;
1273 ahc_print_path(ahc, scb);
1274 printf("SCB %d - Abort%s Completed.\n",
1275 scb->hscb->tag, tag == SCB_LIST_NULL ?
1277 ahc_abort_scbs(ahc, target, channel,
1282 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1283 MSG_BUS_DEV_RESET, TRUE)) {
1286 * Don't mark the user's request for this BDR
1287 * as completing with CAM_BDR_SENT. CAM3
1288 * specifies CAM_REQ_CMP.
1291 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1292 && ahc_match_scb(ahc, scb, target, channel,
1296 aic_set_transaction_status(scb, CAM_REQ_CMP);
1299 ahc_compile_devinfo(&devinfo,
1305 ahc_handle_devreset(ahc, &devinfo,
1308 /*verbose_level*/0);
1310 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1311 MSG_EXT_PPR, FALSE)) {
1312 struct ahc_initiator_tinfo *tinfo;
1313 struct ahc_tmode_tstate *tstate;
1316 * PPR Rejected. Try non-ppr negotiation
1317 * and retry command.
1319 tinfo = ahc_fetch_transinfo(ahc,
1324 tinfo->curr.transport_version = 2;
1325 tinfo->goal.transport_version = 2;
1326 tinfo->goal.ppr_options = 0;
1327 ahc_qinfifo_requeue_tail(ahc, scb);
1329 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1330 MSG_EXT_WDTR, FALSE)) {
1332 * Negotiation Rejected. Go-narrow and
1335 ahc_set_width(ahc, &devinfo,
1336 MSG_EXT_WDTR_BUS_8_BIT,
1337 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1339 ahc_qinfifo_requeue_tail(ahc, scb);
1341 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1342 MSG_EXT_SDTR, FALSE)) {
1344 * Negotiation Rejected. Go-async and
1347 ahc_set_syncrate(ahc, &devinfo,
1349 /*period*/0, /*offset*/0,
1351 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1353 ahc_qinfifo_requeue_tail(ahc, scb);
1357 if (printerror != 0) {
1363 if ((scb->hscb->control & TAG_ENB) != 0)
1364 tag = scb->hscb->tag;
1366 tag = SCB_LIST_NULL;
1367 ahc_print_path(ahc, scb);
1368 ahc_abort_scbs(ahc, target, channel,
1369 SCB_GET_LUN(scb), tag,
1374 * We had not fully identified this connection,
1375 * so we cannot abort anything.
1377 printf("%s: ", ahc_name(ahc));
1379 for (i = 0; i < num_phases; i++) {
1380 if (lastphase == ahc_phase_table[i].phase)
1383 if (lastphase != P_BUSFREE) {
1385 * Renegotiate with this device at the
1386 * next opportunity just in case this busfree
1387 * is due to a negotiation mismatch with the
1390 ahc_force_renegotiation(ahc, &devinfo);
1392 printf("Unexpected busfree %s\n"
1393 "SEQADDR == 0x%x\n",
1394 ahc_phase_table[i].phasemsg,
1395 ahc_inb(ahc, SEQADDR0)
1396 | (ahc_inb(ahc, SEQADDR1) << 8));
1398 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1401 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1402 ahc_name(ahc), status);
1403 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1408 * Force renegotiation to occur the next time we initiate
1409 * a command to the current device.
1412 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1414 struct ahc_initiator_tinfo *targ_info;
1415 struct ahc_tmode_tstate *tstate;
1417 targ_info = ahc_fetch_transinfo(ahc,
1419 devinfo->our_scsiid,
1422 ahc_update_neg_request(ahc, devinfo, tstate,
1423 targ_info, AHC_NEG_IF_NON_ASYNC);
1426 #define AHC_MAX_STEPS 2000
1428 ahc_clear_critical_section(struct ahc_softc *ahc)
1435 if (ahc->num_critical_sections == 0)
1447 seqaddr = ahc_inb(ahc, SEQADDR0)
1448 | (ahc_inb(ahc, SEQADDR1) << 8);
1451 * Seqaddr represents the next instruction to execute,
1452 * so we are really executing the instruction just
1455 cs = ahc->critical_sections;
1456 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1458 if (cs->begin < seqaddr && cs->end >= seqaddr)
1462 if (i == ahc->num_critical_sections)
1465 if (steps > AHC_MAX_STEPS) {
1466 printf("%s: Infinite loop in critical section\n",
1468 ahc_dump_card_state(ahc);
1469 panic("critical section loop");
1473 if (stepping == FALSE) {
1476 * Disable all interrupt sources so that the
1477 * sequencer will not be stuck by a pausing
1478 * interrupt condition while we attempt to
1479 * leave a critical section.
1481 simode0 = ahc_inb(ahc, SIMODE0);
1482 ahc_outb(ahc, SIMODE0, 0);
1483 simode1 = ahc_inb(ahc, SIMODE1);
1484 if ((ahc->features & AHC_DT) != 0)
1486 * On DT class controllers, we
1487 * use the enhanced busfree logic.
1488 * Unfortunately we cannot re-enable
1489 * busfree detection within the
1490 * current connection, so we must
1491 * leave it on while single stepping.
1493 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1495 ahc_outb(ahc, SIMODE1, 0);
1496 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1497 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1500 if ((ahc->features & AHC_DT) != 0) {
1501 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1502 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1504 ahc_outb(ahc, HCNTRL, ahc->unpause);
1505 while (!ahc_is_paused(ahc))
1509 ahc_outb(ahc, SIMODE0, simode0);
1510 ahc_outb(ahc, SIMODE1, simode1);
1511 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1516 * Clear any pending interrupt status.
1519 ahc_clear_intstat(struct ahc_softc *ahc)
1521 /* Clear any interrupt conditions this may have caused */
1522 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1523 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1525 ahc_flush_device_writes(ahc);
1526 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1527 ahc_flush_device_writes(ahc);
1528 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1529 ahc_flush_device_writes(ahc);
1532 /**************************** Debugging Routines ******************************/
1534 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1538 ahc_print_scb(struct scb *scb)
1542 struct hardware_scb *hscb = scb->hscb;
1544 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1550 printf("Shared Data: ");
1551 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1552 printf("%#02x", hscb->shared_data.cdb[i]);
1553 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1554 aic_le32toh(hscb->dataptr),
1555 aic_le32toh(hscb->datacnt),
1556 aic_le32toh(hscb->sgptr),
1558 if (scb->sg_count > 0) {
1559 for (i = 0; i < scb->sg_count; i++) {
1560 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1562 (aic_le32toh(scb->sg_list[i].len) >> 24
1563 & SG_HIGH_ADDR_BITS),
1564 aic_le32toh(scb->sg_list[i].addr),
1565 aic_le32toh(scb->sg_list[i].len));
1570 /************************* Transfer Negotiation *******************************/
1572 * Allocate per target mode instance (ID we respond to as a target)
1573 * transfer negotiation data structures.
1575 static struct ahc_tmode_tstate *
1576 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1578 struct ahc_tmode_tstate *master_tstate;
1579 struct ahc_tmode_tstate *tstate;
1582 master_tstate = ahc->enabled_targets[ahc->our_id];
1583 if (channel == 'B') {
1585 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1587 if (ahc->enabled_targets[scsi_id] != NULL
1588 && ahc->enabled_targets[scsi_id] != master_tstate)
1589 panic("%s: ahc_alloc_tstate - Target already allocated",
1591 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1592 M_DEVBUF, M_NOWAIT);
1597 * If we have allocated a master tstate, copy user settings from
1598 * the master tstate (taken from SRAM or the EEPROM) for this
1599 * channel, but reset our current and goal settings to async/narrow
1600 * until an initiator talks to us.
1602 if (master_tstate != NULL) {
1603 memcpy(tstate, master_tstate, sizeof(*tstate));
1604 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1605 tstate->ultraenb = 0;
1606 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1607 memset(&tstate->transinfo[i].curr, 0,
1608 sizeof(tstate->transinfo[i].curr));
1609 memset(&tstate->transinfo[i].goal, 0,
1610 sizeof(tstate->transinfo[i].goal));
1613 memset(tstate, 0, sizeof(*tstate));
1614 ahc->enabled_targets[scsi_id] = tstate;
1618 #ifdef AHC_TARGET_MODE
1620 * Free per target mode instance (ID we respond to as a target)
1621 * transfer negotiation data structures.
1624 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1626 struct ahc_tmode_tstate *tstate;
1629 * Don't clean up our "master" tstate.
1630 * It has our default user settings.
1632 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1633 || (channel == 'A' && scsi_id == ahc->our_id))
1639 tstate = ahc->enabled_targets[scsi_id];
1641 free(tstate, M_DEVBUF);
1642 ahc->enabled_targets[scsi_id] = NULL;
1647 * Called when we have an active connection to a target on the bus,
1648 * this function finds the nearest syncrate to the input period limited
1649 * by the capabilities of the bus connectivity of and sync settings for
1652 struct ahc_syncrate *
1653 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1654 struct ahc_initiator_tinfo *tinfo,
1655 u_int *period, u_int *ppr_options, role_t role)
1657 struct ahc_transinfo *transinfo;
1660 if ((ahc->features & AHC_ULTRA2) != 0) {
1661 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1662 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1663 maxsync = AHC_SYNCRATE_DT;
1665 maxsync = AHC_SYNCRATE_ULTRA;
1666 /* Can't do DT on an SE bus */
1667 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1669 } else if ((ahc->features & AHC_ULTRA) != 0) {
1670 maxsync = AHC_SYNCRATE_ULTRA;
1672 maxsync = AHC_SYNCRATE_FAST;
1675 * Never allow a value higher than our current goal
1676 * period otherwise we may allow a target initiated
1677 * negotiation to go above the limit as set by the
1678 * user. In the case of an initiator initiated
1679 * sync negotiation, we limit based on the user
1680 * setting. This allows the system to still accept
1681 * incoming negotiations even if target initiated
1682 * negotiation is not performed.
1684 if (role == ROLE_TARGET)
1685 transinfo = &tinfo->user;
1687 transinfo = &tinfo->goal;
1688 *ppr_options &= transinfo->ppr_options;
1689 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1690 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1691 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1693 if (transinfo->period == 0) {
1698 *period = MAX(*period, transinfo->period);
1699 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1703 * Look up the valid period to SCSIRATE conversion in our table.
1704 * Return the period and offset that should be sent to the target
1705 * if this was the beginning of an SDTR.
1707 struct ahc_syncrate *
1708 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1709 u_int *ppr_options, u_int maxsync)
1711 struct ahc_syncrate *syncrate;
1713 if ((ahc->features & AHC_DT) == 0)
1714 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1716 /* Skip all DT only entries if DT is not available */
1717 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1718 && maxsync < AHC_SYNCRATE_ULTRA2)
1719 maxsync = AHC_SYNCRATE_ULTRA2;
1721 for (syncrate = &ahc_syncrates[maxsync];
1722 syncrate->rate != NULL;
1726 * The Ultra2 table doesn't go as low
1727 * as for the Fast/Ultra cards.
1729 if ((ahc->features & AHC_ULTRA2) != 0
1730 && (syncrate->sxfr_u2 == 0))
1733 if (*period <= syncrate->period) {
1735 * When responding to a target that requests
1736 * sync, the requested rate may fall between
1737 * two rates that we can output, but still be
1738 * a rate that we can receive. Because of this,
1739 * we want to respond to the target with
1740 * the same rate that it sent to us even
1741 * if the period we use to send data to it
1742 * is lower. Only lower the response period
1745 if (syncrate == &ahc_syncrates[maxsync])
1746 *period = syncrate->period;
1749 * At some speeds, we only support
1752 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1753 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1759 || (syncrate->rate == NULL)
1760 || ((ahc->features & AHC_ULTRA2) != 0
1761 && (syncrate->sxfr_u2 == 0))) {
1762 /* Use asynchronous transfers. */
1765 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1771 * Convert from an entry in our syncrate table to the SCSI equivalent
1772 * sync "period" factor.
1775 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1777 struct ahc_syncrate *syncrate;
1779 if ((ahc->features & AHC_ULTRA2) != 0)
1780 scsirate &= SXFR_ULTRA2;
1784 syncrate = &ahc_syncrates[maxsync];
1785 while (syncrate->rate != NULL) {
1787 if ((ahc->features & AHC_ULTRA2) != 0) {
1788 if (syncrate->sxfr_u2 == 0)
1790 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1791 return (syncrate->period);
1792 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1793 return (syncrate->period);
1797 return (0); /* async */
1801 * Truncate the given synchronous offset to a value the
1802 * current adapter type and syncrate are capable of.
1805 ahc_validate_offset(struct ahc_softc *ahc,
1806 struct ahc_initiator_tinfo *tinfo,
1807 struct ahc_syncrate *syncrate,
1808 u_int *offset, int wide, role_t role)
1812 /* Limit offset to what we can do */
1813 if (syncrate == NULL) {
1815 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1816 maxoffset = MAX_OFFSET_ULTRA2;
1819 maxoffset = MAX_OFFSET_16BIT;
1821 maxoffset = MAX_OFFSET_8BIT;
1823 *offset = MIN(*offset, maxoffset);
1824 if (tinfo != NULL) {
1825 if (role == ROLE_TARGET)
1826 *offset = MIN(*offset, tinfo->user.offset);
1828 *offset = MIN(*offset, tinfo->goal.offset);
1833 * Truncate the given transfer width parameter to a value the
1834 * current adapter type is capable of.
1837 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1838 u_int *bus_width, role_t role)
1840 switch (*bus_width) {
1842 if (ahc->features & AHC_WIDE) {
1844 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1848 case MSG_EXT_WDTR_BUS_8_BIT:
1849 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1852 if (tinfo != NULL) {
1853 if (role == ROLE_TARGET)
1854 *bus_width = MIN(tinfo->user.width, *bus_width);
1856 *bus_width = MIN(tinfo->goal.width, *bus_width);
1861 * Update the bitmask of targets for which the controller should
1862 * negotiate with at the next convenient opportunity. This currently
1863 * means the next time we send the initial identify messages for
1864 * a new transaction.
1867 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1868 struct ahc_tmode_tstate *tstate,
1869 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1871 u_int auto_negotiate_orig;
1873 auto_negotiate_orig = tstate->auto_negotiate;
1874 if (neg_type == AHC_NEG_ALWAYS) {
1876 * Force our "current" settings to be
1877 * unknown so that unless a bus reset
1878 * occurs the need to renegotiate is
1879 * recorded persistently.
1881 if ((ahc->features & AHC_WIDE) != 0)
1882 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1883 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1884 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1886 if (tinfo->curr.period != tinfo->goal.period
1887 || tinfo->curr.width != tinfo->goal.width
1888 || tinfo->curr.offset != tinfo->goal.offset
1889 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1890 || (neg_type == AHC_NEG_IF_NON_ASYNC
1891 && (tinfo->goal.offset != 0
1892 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1893 || tinfo->goal.ppr_options != 0)))
1894 tstate->auto_negotiate |= devinfo->target_mask;
1896 tstate->auto_negotiate &= ~devinfo->target_mask;
1898 return (auto_negotiate_orig != tstate->auto_negotiate);
1902 * Update the user/goal/curr tables of synchronous negotiation
1903 * parameters as well as, in the case of a current or active update,
1904 * any data structures on the host controller. In the case of an
1905 * active update, the specified target is currently talking to us on
1906 * the bus, so the transfer parameter update must take effect
1910 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1911 struct ahc_syncrate *syncrate, u_int period,
1912 u_int offset, u_int ppr_options, u_int type, int paused)
1914 struct ahc_initiator_tinfo *tinfo;
1915 struct ahc_tmode_tstate *tstate;
1922 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1925 if (syncrate == NULL) {
1930 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1931 devinfo->target, &tstate);
1933 if ((type & AHC_TRANS_USER) != 0) {
1934 tinfo->user.period = period;
1935 tinfo->user.offset = offset;
1936 tinfo->user.ppr_options = ppr_options;
1939 if ((type & AHC_TRANS_GOAL) != 0) {
1940 tinfo->goal.period = period;
1941 tinfo->goal.offset = offset;
1942 tinfo->goal.ppr_options = ppr_options;
1945 old_period = tinfo->curr.period;
1946 old_offset = tinfo->curr.offset;
1947 old_ppr = tinfo->curr.ppr_options;
1949 if ((type & AHC_TRANS_CUR) != 0
1950 && (old_period != period
1951 || old_offset != offset
1952 || old_ppr != ppr_options)) {
1956 scsirate = tinfo->scsirate;
1957 if ((ahc->features & AHC_ULTRA2) != 0) {
1959 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1960 if (syncrate != NULL) {
1961 scsirate |= syncrate->sxfr_u2;
1962 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1963 scsirate |= ENABLE_CRC;
1965 scsirate |= SINGLE_EDGE;
1969 scsirate &= ~(SXFR|SOFS);
1971 * Ensure Ultra mode is set properly for
1974 tstate->ultraenb &= ~devinfo->target_mask;
1975 if (syncrate != NULL) {
1976 if (syncrate->sxfr & ULTRA_SXFR) {
1978 devinfo->target_mask;
1980 scsirate |= syncrate->sxfr & SXFR;
1981 scsirate |= offset & SOFS;
1986 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1987 sxfrctl0 &= ~FAST20;
1988 if (tstate->ultraenb & devinfo->target_mask)
1990 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1994 ahc_outb(ahc, SCSIRATE, scsirate);
1995 if ((ahc->features & AHC_ULTRA2) != 0)
1996 ahc_outb(ahc, SCSIOFFSET, offset);
1999 tinfo->scsirate = scsirate;
2000 tinfo->curr.period = period;
2001 tinfo->curr.offset = offset;
2002 tinfo->curr.ppr_options = ppr_options;
2004 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2005 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2008 printf("%s: target %d synchronous at %sMHz%s, "
2009 "offset = 0x%x\n", ahc_name(ahc),
2010 devinfo->target, syncrate->rate,
2011 (ppr_options & MSG_EXT_PPR_DT_REQ)
2012 ? " DT" : "", offset);
2014 printf("%s: target %d using "
2015 "asynchronous transfers\n",
2016 ahc_name(ahc), devinfo->target);
2021 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2022 tinfo, AHC_NEG_TO_GOAL);
2025 ahc_update_pending_scbs(ahc);
2029 * Update the user/goal/curr tables of wide negotiation
2030 * parameters as well as, in the case of a current or active update,
2031 * any data structures on the host controller. In the case of an
2032 * active update, the specified target is currently talking to us on
2033 * the bus, so the transfer parameter update must take effect
2037 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2038 u_int width, u_int type, int paused)
2040 struct ahc_initiator_tinfo *tinfo;
2041 struct ahc_tmode_tstate *tstate;
2046 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2048 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2049 devinfo->target, &tstate);
2051 if ((type & AHC_TRANS_USER) != 0)
2052 tinfo->user.width = width;
2054 if ((type & AHC_TRANS_GOAL) != 0)
2055 tinfo->goal.width = width;
2057 oldwidth = tinfo->curr.width;
2058 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2062 scsirate = tinfo->scsirate;
2063 scsirate &= ~WIDEXFER;
2064 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2065 scsirate |= WIDEXFER;
2067 tinfo->scsirate = scsirate;
2070 ahc_outb(ahc, SCSIRATE, scsirate);
2072 tinfo->curr.width = width;
2074 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2075 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2077 printf("%s: target %d using %dbit transfers\n",
2078 ahc_name(ahc), devinfo->target,
2079 8 * (0x01 << width));
2083 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2084 tinfo, AHC_NEG_TO_GOAL);
2086 ahc_update_pending_scbs(ahc);
2090 * Update the current state of tagged queuing for a given target.
2093 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2096 ahc_platform_set_tags(ahc, devinfo, alg);
2097 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2098 devinfo->lun, AC_TRANSFER_NEG, &alg);
2102 * When the transfer settings for a connection change, update any
2103 * in-transit SCBs to contain the new data so the hardware will
2104 * be set correctly during future (re)selections.
2107 ahc_update_pending_scbs(struct ahc_softc *ahc)
2109 struct scb *pending_scb;
2110 int pending_scb_count;
2116 * Traverse the pending SCB list and ensure that all of the
2117 * SCBs there have the proper settings.
2119 pending_scb_count = 0;
2120 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2121 struct ahc_devinfo devinfo;
2122 struct hardware_scb *pending_hscb;
2123 struct ahc_initiator_tinfo *tinfo;
2124 struct ahc_tmode_tstate *tstate;
2126 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2127 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2129 devinfo.target, &tstate);
2130 pending_hscb = pending_scb->hscb;
2131 pending_hscb->control &= ~ULTRAENB;
2132 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2133 pending_hscb->control |= ULTRAENB;
2134 pending_hscb->scsirate = tinfo->scsirate;
2135 pending_hscb->scsioffset = tinfo->curr.offset;
2136 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2137 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2138 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2139 pending_hscb->control &= ~MK_MESSAGE;
2141 ahc_sync_scb(ahc, pending_scb,
2142 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2143 pending_scb_count++;
2146 if (pending_scb_count == 0)
2149 if (ahc_is_paused(ahc)) {
2156 saved_scbptr = ahc_inb(ahc, SCBPTR);
2157 /* Ensure that the hscbs down on the card match the new information */
2158 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2159 struct hardware_scb *pending_hscb;
2163 ahc_outb(ahc, SCBPTR, i);
2164 scb_tag = ahc_inb(ahc, SCB_TAG);
2165 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2166 if (pending_scb == NULL)
2169 pending_hscb = pending_scb->hscb;
2170 control = ahc_inb(ahc, SCB_CONTROL);
2171 control &= ~(ULTRAENB|MK_MESSAGE);
2172 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2173 ahc_outb(ahc, SCB_CONTROL, control);
2174 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2175 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2177 ahc_outb(ahc, SCBPTR, saved_scbptr);
2183 /**************************** Pathing Information *****************************/
2185 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2191 if (ahc_inb(ahc, SSTAT0) & TARGET)
2194 role = ROLE_INITIATOR;
2196 if (role == ROLE_TARGET
2197 && (ahc->features & AHC_MULTI_TID) != 0
2198 && (ahc_inb(ahc, SEQ_FLAGS)
2199 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2200 /* We were selected, so pull our id from TARGIDIN */
2201 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2202 } else if ((ahc->features & AHC_ULTRA2) != 0)
2203 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2205 our_id = ahc_inb(ahc, SCSIID) & OID;
2207 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2208 ahc_compile_devinfo(devinfo,
2210 SCSIID_TARGET(ahc, saved_scsiid),
2211 ahc_inb(ahc, SAVED_LUN),
2212 SCSIID_CHANNEL(ahc, saved_scsiid),
2216 struct ahc_phase_table_entry*
2217 ahc_lookup_phase_entry(int phase)
2219 struct ahc_phase_table_entry *entry;
2220 struct ahc_phase_table_entry *last_entry;
2223 * num_phases doesn't include the default entry which
2224 * will be returned if the phase doesn't match.
2226 last_entry = &ahc_phase_table[num_phases];
2227 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2228 if (phase == entry->phase)
2235 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2236 u_int lun, char channel, role_t role)
2238 devinfo->our_scsiid = our_id;
2239 devinfo->target = target;
2241 devinfo->target_offset = target;
2242 devinfo->channel = channel;
2243 devinfo->role = role;
2245 devinfo->target_offset += 8;
2246 devinfo->target_mask = (0x01 << devinfo->target_offset);
2250 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2252 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2253 devinfo->target, devinfo->lun);
2257 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2263 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2264 role = ROLE_INITIATOR;
2265 if ((scb->flags & SCB_TARGET_SCB) != 0)
2267 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2268 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2272 /************************ Message Phase Processing ****************************/
2274 ahc_assert_atn(struct ahc_softc *ahc)
2279 if ((ahc->features & AHC_DT) == 0)
2280 scsisigo |= ahc_inb(ahc, SCSISIGI);
2281 ahc_outb(ahc, SCSISIGO, scsisigo);
2285 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2286 * or enters the initial message out phase, we are interrupted. Fill our
2287 * outgoing message buffer with the appropriate message and beging handing
2288 * the message phase(s) manually.
2291 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2295 * To facilitate adding multiple messages together,
2296 * each routine should increment the index and len
2297 * variables instead of setting them explicitly.
2299 ahc->msgout_index = 0;
2300 ahc->msgout_len = 0;
2302 if ((scb->flags & SCB_DEVICE_RESET) == 0
2303 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2306 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2307 if ((scb->hscb->control & DISCENB) != 0)
2308 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2309 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2312 if ((scb->hscb->control & TAG_ENB) != 0) {
2313 ahc->msgout_buf[ahc->msgout_index++] =
2314 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2315 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2316 ahc->msgout_len += 2;
2320 if (scb->flags & SCB_DEVICE_RESET) {
2321 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2323 ahc_print_path(ahc, scb);
2324 printf("Bus Device Reset Message Sent\n");
2326 * Clear our selection hardware in advance of
2327 * the busfree. We may have an entry in the waiting
2328 * Q for this target, and we don't want to go about
2329 * selecting while we handle the busfree and blow it
2332 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2333 } else if ((scb->flags & SCB_ABORT) != 0) {
2334 if ((scb->hscb->control & TAG_ENB) != 0)
2335 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2337 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2339 ahc_print_path(ahc, scb);
2340 printf("Abort%s Message Sent\n",
2341 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2343 * Clear our selection hardware in advance of
2344 * the busfree. We may have an entry in the waiting
2345 * Q for this target, and we don't want to go about
2346 * selecting while we handle the busfree and blow it
2349 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2350 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2351 ahc_build_transfer_msg(ahc, devinfo);
2353 printf("ahc_intr: AWAITING_MSG for an SCB that "
2354 "does not have a waiting message\n");
2355 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2356 devinfo->target_mask);
2357 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2358 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2359 ahc_inb(ahc, MSG_OUT), scb->flags);
2363 * Clear the MK_MESSAGE flag from the SCB so we aren't
2364 * asked to send this message again.
2366 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2367 scb->hscb->control &= ~MK_MESSAGE;
2368 ahc->msgout_index = 0;
2369 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2373 * Build an appropriate transfer negotiation message for the
2374 * currently active target.
2377 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2380 * We need to initiate transfer negotiations.
2381 * If our current and goal settings are identical,
2382 * we want to renegotiate due to a check condition.
2384 struct ahc_initiator_tinfo *tinfo;
2385 struct ahc_tmode_tstate *tstate;
2386 struct ahc_syncrate *rate;
2394 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2395 devinfo->target, &tstate);
2397 * Filter our period based on the current connection.
2398 * If we can't perform DT transfers on this segment (not in LVD
2399 * mode for instance), then our decision to issue a PPR message
2402 period = tinfo->goal.period;
2403 offset = tinfo->goal.offset;
2404 ppr_options = tinfo->goal.ppr_options;
2405 /* Target initiated PPR is not allowed in the SCSI spec */
2406 if (devinfo->role == ROLE_TARGET)
2408 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2409 &ppr_options, devinfo->role);
2410 dowide = tinfo->curr.width != tinfo->goal.width;
2411 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2413 * Only use PPR if we have options that need it, even if the device
2414 * claims to support it. There might be an expander in the way
2417 doppr = ppr_options != 0;
2419 if (!dowide && !dosync && !doppr) {
2420 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2421 dosync = tinfo->goal.offset != 0;
2424 if (!dowide && !dosync && !doppr) {
2426 * Force async with a WDTR message if we have a wide bus,
2427 * or just issue an SDTR with a 0 offset.
2429 if ((ahc->features & AHC_WIDE) != 0)
2435 ahc_print_devinfo(ahc, devinfo);
2436 printf("Ensuring async\n");
2440 /* Target initiated PPR is not allowed in the SCSI spec */
2441 if (devinfo->role == ROLE_TARGET)
2445 * Both the PPR message and SDTR message require the
2446 * goal syncrate to be limited to what the target device
2447 * is capable of handling (based on whether an LVD->SE
2448 * expander is on the bus), so combine these two cases.
2449 * Regardless, guarantee that if we are using WDTR and SDTR
2450 * messages that WDTR comes first.
2452 if (doppr || (dosync && !dowide)) {
2454 offset = tinfo->goal.offset;
2455 ahc_validate_offset(ahc, tinfo, rate, &offset,
2456 doppr ? tinfo->goal.width
2457 : tinfo->curr.width,
2460 ahc_construct_ppr(ahc, devinfo, period, offset,
2461 tinfo->goal.width, ppr_options);
2463 ahc_construct_sdtr(ahc, devinfo, period, offset);
2466 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2471 * Build a synchronous negotiation message in our message
2472 * buffer based on the input parameters.
2475 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2476 u_int period, u_int offset)
2479 period = AHC_ASYNC_XFER_PERIOD;
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2483 ahc->msgout_buf[ahc->msgout_index++] = period;
2484 ahc->msgout_buf[ahc->msgout_index++] = offset;
2485 ahc->msgout_len += 5;
2487 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2488 ahc_name(ahc), devinfo->channel, devinfo->target,
2489 devinfo->lun, period, offset);
2494 * Build a wide negotiation message in our message
2495 * buffer based on the input parameters.
2498 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2501 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2502 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2504 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2505 ahc->msgout_len += 4;
2507 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2508 ahc_name(ahc), devinfo->channel, devinfo->target,
2509 devinfo->lun, bus_width);
2514 * Build a parallel protocol request message in our message
2515 * buffer based on the input parameters.
2518 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2519 u_int period, u_int offset, u_int bus_width,
2523 period = AHC_ASYNC_XFER_PERIOD;
2524 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2525 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2526 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2527 ahc->msgout_buf[ahc->msgout_index++] = period;
2528 ahc->msgout_buf[ahc->msgout_index++] = 0;
2529 ahc->msgout_buf[ahc->msgout_index++] = offset;
2530 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2531 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2532 ahc->msgout_len += 8;
2534 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2535 "offset %x, ppr_options %x\n", ahc_name(ahc),
2536 devinfo->channel, devinfo->target, devinfo->lun,
2537 bus_width, period, offset, ppr_options);
2542 * Clear any active message state.
2545 ahc_clear_msg_state(struct ahc_softc *ahc)
2547 ahc->msgout_len = 0;
2548 ahc->msgin_index = 0;
2549 ahc->msg_type = MSG_TYPE_NONE;
2550 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2552 * The target didn't care to respond to our
2553 * message request, so clear ATN.
2555 ahc_outb(ahc, CLRSINT1, CLRATNO);
2557 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2558 ahc_outb(ahc, SEQ_FLAGS2,
2559 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2563 ahc_handle_proto_violation(struct ahc_softc *ahc)
2565 struct ahc_devinfo devinfo;
2573 ahc_fetch_devinfo(ahc, &devinfo);
2574 scbid = ahc_inb(ahc, SCB_TAG);
2575 scb = ahc_lookup_scb(ahc, scbid);
2576 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2577 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2578 lastphase = ahc_inb(ahc, LASTPHASE);
2579 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2582 * The reconnecting target either did not send an
2583 * identify message, or did, but we didn't find an SCB
2586 ahc_print_devinfo(ahc, &devinfo);
2587 printf("Target did not send an IDENTIFY message. "
2588 "LASTPHASE = 0x%x.\n", lastphase);
2590 } else if (scb == NULL) {
2592 * We don't seem to have an SCB active for this
2593 * transaction. Print an error and reset the bus.
2595 ahc_print_devinfo(ahc, &devinfo);
2596 printf("No SCB found during protocol violation\n");
2597 goto proto_violation_reset;
2599 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2600 if ((seq_flags & NO_CDB_SENT) != 0) {
2601 ahc_print_path(ahc, scb);
2602 printf("No or incomplete CDB sent to device.\n");
2603 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2605 * The target never bothered to provide status to
2606 * us prior to completing the command. Since we don't
2607 * know the disposition of this command, we must attempt
2608 * to abort it. Assert ATN and prepare to send an abort
2611 ahc_print_path(ahc, scb);
2612 printf("Completed command without status.\n");
2614 ahc_print_path(ahc, scb);
2615 printf("Unknown protocol violation.\n");
2616 ahc_dump_card_state(ahc);
2619 if ((lastphase & ~P_DATAIN_DT) == 0
2620 || lastphase == P_COMMAND) {
2621 proto_violation_reset:
2623 * Target either went directly to data/command
2624 * phase or didn't respond to our ATN.
2625 * The only safe thing to do is to blow
2626 * it away with a bus reset.
2628 found = ahc_reset_channel(ahc, 'A', TRUE);
2629 printf("%s: Issued Channel %c Bus Reset. "
2630 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2633 * Leave the selection hardware off in case
2634 * this abort attempt will affect yet to
2637 ahc_outb(ahc, SCSISEQ,
2638 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2639 ahc_assert_atn(ahc);
2640 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2642 ahc_print_devinfo(ahc, &devinfo);
2643 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2644 ahc->msgout_len = 1;
2645 ahc->msgout_index = 0;
2646 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2648 ahc_print_path(ahc, scb);
2649 scb->flags |= SCB_ABORT;
2651 printf("Protocol violation %s. Attempting to abort.\n",
2652 ahc_lookup_phase_entry(curphase)->phasemsg);
2657 * Manual message loop handler.
2660 ahc_handle_message_phase(struct ahc_softc *ahc)
2662 struct ahc_devinfo devinfo;
2666 ahc_fetch_devinfo(ahc, &devinfo);
2667 end_session = FALSE;
2668 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2671 switch (ahc->msg_type) {
2672 case MSG_TYPE_INITIATOR_MSGOUT:
2678 if (ahc->msgout_len == 0)
2679 panic("HOST_MSG_LOOP interrupt with no active message");
2682 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2683 ahc_print_devinfo(ahc, &devinfo);
2684 printf("INITIATOR_MSG_OUT");
2687 phasemis = bus_phase != P_MESGOUT;
2690 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2691 printf(" PHASEMIS %s\n",
2692 ahc_lookup_phase_entry(bus_phase)
2696 if (bus_phase == P_MESGIN) {
2698 * Change gears and see if
2699 * this messages is of interest to
2700 * us or should be passed back to
2703 ahc_outb(ahc, CLRSINT1, CLRATNO);
2704 ahc->send_msg_perror = FALSE;
2705 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2706 ahc->msgin_index = 0;
2713 if (ahc->send_msg_perror) {
2714 ahc_outb(ahc, CLRSINT1, CLRATNO);
2715 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2717 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2718 printf(" byte 0x%x\n", ahc->send_msg_perror);
2720 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2724 msgdone = ahc->msgout_index == ahc->msgout_len;
2727 * The target has requested a retry.
2728 * Re-assert ATN, reset our message index to
2731 ahc->msgout_index = 0;
2732 ahc_assert_atn(ahc);
2735 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2737 /* Last byte is signified by dropping ATN */
2738 ahc_outb(ahc, CLRSINT1, CLRATNO);
2742 * Clear our interrupt status and present
2743 * the next byte on the bus.
2745 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2748 printf(" byte 0x%x\n",
2749 ahc->msgout_buf[ahc->msgout_index]);
2751 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2754 case MSG_TYPE_INITIATOR_MSGIN:
2760 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2761 ahc_print_devinfo(ahc, &devinfo);
2762 printf("INITIATOR_MSG_IN");
2765 phasemis = bus_phase != P_MESGIN;
2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2769 printf(" PHASEMIS %s\n",
2770 ahc_lookup_phase_entry(bus_phase)
2774 ahc->msgin_index = 0;
2775 if (bus_phase == P_MESGOUT
2776 && (ahc->send_msg_perror == TRUE
2777 || (ahc->msgout_len != 0
2778 && ahc->msgout_index == 0))) {
2779 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2786 /* Pull the byte in without acking it */
2787 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2790 printf(" byte 0x%x\n",
2791 ahc->msgin_buf[ahc->msgin_index]);
2794 message_done = ahc_parse_msg(ahc, &devinfo);
2798 * Clear our incoming message buffer in case there
2799 * is another message following this one.
2801 ahc->msgin_index = 0;
2804 * If this message illicited a response,
2805 * assert ATN so the target takes us to the
2806 * message out phase.
2808 if (ahc->msgout_len != 0) {
2810 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2811 ahc_print_devinfo(ahc, &devinfo);
2812 printf("Asserting ATN for response\n");
2815 ahc_assert_atn(ahc);
2820 if (message_done == MSGLOOP_TERMINATED) {
2824 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2825 ahc_inb(ahc, SCSIDATL);
2829 case MSG_TYPE_TARGET_MSGIN:
2833 if (ahc->msgout_len == 0)
2834 panic("Target MSGIN with no active message");
2837 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2838 ahc_print_devinfo(ahc, &devinfo);
2839 printf("TARGET_MSG_IN");
2844 * If we interrupted a mesgout session, the initiator
2845 * will not know this until our first REQ. So, we
2846 * only honor mesgout requests after we've sent our
2849 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2850 && ahc->msgout_index > 0) {
2853 * Change gears and see if this messages is
2854 * of interest to us or should be passed back
2858 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2859 printf(" Honoring ATN Request.\n");
2861 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2864 * Disable SCSI Programmed I/O during the
2865 * phase change so as to avoid phantom REQs.
2867 ahc_outb(ahc, SXFRCTL0,
2868 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2871 * Since SPIORDY asserts when ACK is asserted
2872 * for P_MSGOUT, and SPIORDY's assertion triggered
2873 * our entry into this routine, wait for ACK to
2874 * *de-assert* before changing phases.
2876 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2879 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2882 * All phase line changes require a bus
2883 * settle delay before REQ is asserted.
2884 * [SCSI SPI4 10.7.1]
2886 ahc_flush_device_writes(ahc);
2887 aic_delay(AHC_BUSSETTLE_DELAY);
2889 ahc->msgin_index = 0;
2890 /* Enable SCSI Programmed I/O to REQ for first byte */
2891 ahc_outb(ahc, SXFRCTL0,
2892 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2896 msgdone = ahc->msgout_index == ahc->msgout_len;
2898 ahc_outb(ahc, SXFRCTL0,
2899 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2905 * Present the next byte on the bus.
2908 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2909 printf(" byte 0x%x\n",
2910 ahc->msgout_buf[ahc->msgout_index]);
2912 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2913 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2916 case MSG_TYPE_TARGET_MSGOUT:
2922 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2923 ahc_print_devinfo(ahc, &devinfo);
2924 printf("TARGET_MSG_OUT");
2928 * The initiator signals that this is
2929 * the last byte by dropping ATN.
2931 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2934 * Read the latched byte, but turn off SPIOEN first
2935 * so that we don't inadvertently cause a REQ for the
2938 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2939 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2942 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2943 printf(" byte 0x%x\n",
2944 ahc->msgin_buf[ahc->msgin_index]);
2947 msgdone = ahc_parse_msg(ahc, &devinfo);
2948 if (msgdone == MSGLOOP_TERMINATED) {
2950 * The message is *really* done in that it caused
2951 * us to go to bus free. The sequencer has already
2952 * been reset at this point, so pull the ejection
2961 * XXX Read spec about initiator dropping ATN too soon
2962 * and use msgdone to detect it.
2964 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2965 ahc->msgin_index = 0;
2968 * If this message illicited a response, transition
2969 * to the Message in phase and send it.
2971 if (ahc->msgout_len != 0) {
2973 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2974 ahc_print_devinfo(ahc, &devinfo);
2975 printf(" preparing response.\n");
2978 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2981 * All phase line changes require a bus
2982 * settle delay before REQ is asserted.
2983 * [SCSI SPI4 10.7.1] When transitioning
2984 * from an OUT to an IN phase, we must
2985 * also wait a data release delay to allow
2986 * the initiator time to release the data
2987 * lines. [SCSI SPI4 10.12]
2989 ahc_flush_device_writes(ahc);
2990 aic_delay(AHC_BUSSETTLE_DELAY
2991 + AHC_DATARELEASE_DELAY);
2994 * Enable SCSI Programmed I/O. This will
2995 * immediately cause SPIORDY to assert,
2996 * and the sequencer will call our message
2999 ahc_outb(ahc, SXFRCTL0,
3000 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3001 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3002 ahc->msgin_index = 0;
3010 /* Ask for the next byte. */
3011 ahc_outb(ahc, SXFRCTL0,
3012 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3018 panic("Unknown REQINIT message type");
3022 ahc_clear_msg_state(ahc);
3023 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3025 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3029 * See if we sent a particular extended message to the target.
3030 * If "full" is true, return true only if the target saw the full
3031 * message. If "full" is false, return true if the target saw at
3032 * least the first byte of the message.
3035 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3043 while (index < ahc->msgout_len) {
3044 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3047 end_index = index + 1 + ahc->msgout_buf[index + 1];
3048 if (ahc->msgout_buf[index+2] == msgval
3049 && type == AHCMSG_EXT) {
3052 if (ahc->msgout_index > end_index)
3054 } else if (ahc->msgout_index > index)
3058 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3059 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3061 /* Skip tag type and tag id or residue param*/
3064 /* Single byte message */
3065 if (type == AHCMSG_1B
3066 && ahc->msgout_buf[index] == msgval
3067 && ahc->msgout_index > index)
3079 * Wait for a complete incoming message, parse it, and respond accordingly.
3082 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3084 struct ahc_initiator_tinfo *tinfo;
3085 struct ahc_tmode_tstate *tstate;
3089 u_int targ_scsirate;
3091 done = MSGLOOP_IN_PROG;
3094 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3095 devinfo->target, &tstate);
3096 targ_scsirate = tinfo->scsirate;
3099 * Parse as much of the message as is available,
3100 * rejecting it if we don't support it. When
3101 * the entire message is available and has been
3102 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3103 * that we have parsed an entire message.
3105 * In the case of extended messages, we accept the length
3106 * byte outright and perform more checking once we know the
3107 * extended message type.
3109 switch (ahc->msgin_buf[0]) {
3110 case MSG_DISCONNECT:
3111 case MSG_SAVEDATAPOINTER:
3112 case MSG_CMDCOMPLETE:
3113 case MSG_RESTOREPOINTERS:
3114 case MSG_IGN_WIDE_RESIDUE:
3116 * End our message loop as these are messages
3117 * the sequencer handles on its own.
3119 done = MSGLOOP_TERMINATED;
3121 case MSG_MESSAGE_REJECT:
3122 response = ahc_handle_msg_reject(ahc, devinfo);
3125 done = MSGLOOP_MSGCOMPLETE;
3129 /* Wait for enough of the message to begin validation */
3130 if (ahc->msgin_index < 2)
3132 switch (ahc->msgin_buf[2]) {
3135 struct ahc_syncrate *syncrate;
3141 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3147 * Wait until we have both args before validating
3148 * and acting on this message.
3150 * Add one to MSG_EXT_SDTR_LEN to account for
3151 * the extended message preamble.
3153 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3156 period = ahc->msgin_buf[3];
3158 saved_offset = offset = ahc->msgin_buf[4];
3159 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3162 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3163 targ_scsirate & WIDEXFER,
3166 printf("(%s:%c:%d:%d): Received "
3167 "SDTR period %x, offset %x\n\t"
3168 "Filtered to period %x, offset %x\n",
3169 ahc_name(ahc), devinfo->channel,
3170 devinfo->target, devinfo->lun,
3171 ahc->msgin_buf[3], saved_offset,
3174 ahc_set_syncrate(ahc, devinfo,
3176 offset, ppr_options,
3177 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3181 * See if we initiated Sync Negotiation
3182 * and didn't have to fall down to async
3185 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3187 if (saved_offset != offset) {
3188 /* Went too low - force async */
3193 * Send our own SDTR in reply
3196 && devinfo->role == ROLE_INITIATOR) {
3197 printf("(%s:%c:%d:%d): Target "
3199 ahc_name(ahc), devinfo->channel,
3200 devinfo->target, devinfo->lun);
3202 ahc->msgout_index = 0;
3203 ahc->msgout_len = 0;
3204 ahc_construct_sdtr(ahc, devinfo,
3206 ahc->msgout_index = 0;
3209 done = MSGLOOP_MSGCOMPLETE;
3216 u_int sending_reply;
3218 sending_reply = FALSE;
3219 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3225 * Wait until we have our arg before validating
3226 * and acting on this message.
3228 * Add one to MSG_EXT_WDTR_LEN to account for
3229 * the extended message preamble.
3231 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3234 bus_width = ahc->msgin_buf[3];
3235 saved_width = bus_width;
3236 ahc_validate_width(ahc, tinfo, &bus_width,
3239 printf("(%s:%c:%d:%d): Received WDTR "
3240 "%x filtered to %x\n",
3241 ahc_name(ahc), devinfo->channel,
3242 devinfo->target, devinfo->lun,
3243 saved_width, bus_width);
3246 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3248 * Don't send a WDTR back to the
3249 * target, since we asked first.
3250 * If the width went higher than our
3251 * request, reject it.
3253 if (saved_width > bus_width) {
3255 printf("(%s:%c:%d:%d): requested %dBit "
3256 "transfers. Rejecting...\n",
3257 ahc_name(ahc), devinfo->channel,
3258 devinfo->target, devinfo->lun,
3259 8 * (0x01 << bus_width));
3264 * Send our own WDTR in reply
3267 && devinfo->role == ROLE_INITIATOR) {
3268 printf("(%s:%c:%d:%d): Target "
3270 ahc_name(ahc), devinfo->channel,
3271 devinfo->target, devinfo->lun);
3273 ahc->msgout_index = 0;
3274 ahc->msgout_len = 0;
3275 ahc_construct_wdtr(ahc, devinfo, bus_width);
3276 ahc->msgout_index = 0;
3278 sending_reply = TRUE;
3281 * After a wide message, we are async, but
3282 * some devices don't seem to honor this portion
3283 * of the spec. Force a renegotiation of the
3284 * sync component of our transfer agreement even
3285 * if our goal is async. By updating our width
3286 * after forcing the negotiation, we avoid
3287 * renegotiating for width.
3289 ahc_update_neg_request(ahc, devinfo, tstate,
3290 tinfo, AHC_NEG_ALWAYS);
3291 ahc_set_width(ahc, devinfo, bus_width,
3292 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3294 if (sending_reply == FALSE && reject == FALSE) {
3297 * We will always have an SDTR to send.
3299 ahc->msgout_index = 0;
3300 ahc->msgout_len = 0;
3301 ahc_build_transfer_msg(ahc, devinfo);
3302 ahc->msgout_index = 0;
3305 done = MSGLOOP_MSGCOMPLETE;
3310 struct ahc_syncrate *syncrate;
3317 u_int saved_ppr_options;
3319 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3325 * Wait until we have all args before validating
3326 * and acting on this message.
3328 * Add one to MSG_EXT_PPR_LEN to account for
3329 * the extended message preamble.
3331 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3334 period = ahc->msgin_buf[3];
3335 offset = ahc->msgin_buf[5];
3336 bus_width = ahc->msgin_buf[6];
3337 saved_width = bus_width;
3338 ppr_options = ahc->msgin_buf[7];
3340 * According to the spec, a DT only
3341 * period factor with no DT option
3342 * set implies async.
3344 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3347 saved_ppr_options = ppr_options;
3348 saved_offset = offset;
3351 * Mask out any options we don't support
3352 * on any controller. Transfer options are
3353 * only available if we are negotiating wide.
3355 ppr_options &= MSG_EXT_PPR_DT_REQ;
3359 ahc_validate_width(ahc, tinfo, &bus_width,
3361 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3364 ahc_validate_offset(ahc, tinfo, syncrate,
3368 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3370 * If we are unable to do any of the
3371 * requested options (we went too low),
3372 * then we'll have to reject the message.
3374 if (saved_width > bus_width
3375 || saved_offset != offset
3376 || saved_ppr_options != ppr_options) {
3385 if (devinfo->role != ROLE_TARGET)
3386 printf("(%s:%c:%d:%d): Target "
3388 ahc_name(ahc), devinfo->channel,
3389 devinfo->target, devinfo->lun);
3391 printf("(%s:%c:%d:%d): Initiator "
3393 ahc_name(ahc), devinfo->channel,
3394 devinfo->target, devinfo->lun);
3395 ahc->msgout_index = 0;
3396 ahc->msgout_len = 0;
3397 ahc_construct_ppr(ahc, devinfo, period, offset,
3398 bus_width, ppr_options);
3399 ahc->msgout_index = 0;
3403 printf("(%s:%c:%d:%d): Received PPR width %x, "
3404 "period %x, offset %x,options %x\n"
3405 "\tFiltered to width %x, period %x, "
3406 "offset %x, options %x\n",
3407 ahc_name(ahc), devinfo->channel,
3408 devinfo->target, devinfo->lun,
3409 saved_width, ahc->msgin_buf[3],
3410 saved_offset, saved_ppr_options,
3411 bus_width, period, offset, ppr_options);
3413 ahc_set_width(ahc, devinfo, bus_width,
3414 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3416 ahc_set_syncrate(ahc, devinfo,
3418 offset, ppr_options,
3419 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3421 done = MSGLOOP_MSGCOMPLETE;
3425 /* Unknown extended message. Reject it. */
3431 #ifdef AHC_TARGET_MODE
3432 case MSG_BUS_DEV_RESET:
3433 ahc_handle_devreset(ahc, devinfo,
3435 "Bus Device Reset Received",
3436 /*verbose_level*/0);
3438 done = MSGLOOP_TERMINATED;
3442 case MSG_CLEAR_QUEUE:
3446 /* Target mode messages */
3447 if (devinfo->role != ROLE_TARGET) {
3451 tag = SCB_LIST_NULL;
3452 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3453 tag = ahc_inb(ahc, INITIATOR_TAG);
3454 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3455 devinfo->lun, tag, ROLE_TARGET,
3458 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3459 if (tstate != NULL) {
3460 struct ahc_tmode_lstate* lstate;
3462 lstate = tstate->enabled_luns[devinfo->lun];
3463 if (lstate != NULL) {
3464 ahc_queue_lstate_event(ahc, lstate,
3465 devinfo->our_scsiid,
3468 ahc_send_lstate_events(ahc, lstate);
3472 done = MSGLOOP_TERMINATED;
3476 case MSG_TERM_IO_PROC:
3484 * Setup to reject the message.
3486 ahc->msgout_index = 0;
3487 ahc->msgout_len = 1;
3488 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3489 done = MSGLOOP_MSGCOMPLETE;
3493 if (done != MSGLOOP_IN_PROG && !response)
3494 /* Clear the outgoing message buffer */
3495 ahc->msgout_len = 0;
3501 * Process a message reject message.
3504 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3507 * What we care about here is if we had an
3508 * outstanding SDTR or WDTR message for this
3509 * target. If we did, this is a signal that
3510 * the target is refusing negotiation.
3513 struct ahc_initiator_tinfo *tinfo;
3514 struct ahc_tmode_tstate *tstate;
3519 scb_index = ahc_inb(ahc, SCB_TAG);
3520 scb = ahc_lookup_scb(ahc, scb_index);
3521 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3522 devinfo->our_scsiid,
3523 devinfo->target, &tstate);
3524 /* Might be necessary */
3525 last_msg = ahc_inb(ahc, LAST_MSG);
3527 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3529 * Target does not support the PPR message.
3530 * Attempt to negotiate SPI-2 style.
3533 printf("(%s:%c:%d:%d): PPR Rejected. "
3534 "Trying WDTR/SDTR\n",
3535 ahc_name(ahc), devinfo->channel,
3536 devinfo->target, devinfo->lun);
3538 tinfo->goal.ppr_options = 0;
3539 tinfo->curr.transport_version = 2;
3540 tinfo->goal.transport_version = 2;
3541 ahc->msgout_index = 0;
3542 ahc->msgout_len = 0;
3543 ahc_build_transfer_msg(ahc, devinfo);
3544 ahc->msgout_index = 0;
3546 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3548 /* note 8bit xfers */
3549 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3550 "8bit transfers\n", ahc_name(ahc),
3551 devinfo->channel, devinfo->target, devinfo->lun);
3552 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3553 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3556 * No need to clear the sync rate. If the target
3557 * did not accept the command, our syncrate is
3558 * unaffected. If the target started the negotiation,
3559 * but rejected our response, we already cleared the
3560 * sync rate before sending our WDTR.
3562 if (tinfo->goal.offset != tinfo->curr.offset) {
3564 /* Start the sync negotiation */
3565 ahc->msgout_index = 0;
3566 ahc->msgout_len = 0;
3567 ahc_build_transfer_msg(ahc, devinfo);
3568 ahc->msgout_index = 0;
3571 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3572 /* note asynch xfers and clear flag */
3573 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3574 /*offset*/0, /*ppr_options*/0,
3575 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3577 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3578 "Using asynchronous transfers\n",
3579 ahc_name(ahc), devinfo->channel,
3580 devinfo->target, devinfo->lun);
3581 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3585 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3587 if (tag_type == MSG_SIMPLE_TASK) {
3588 printf("(%s:%c:%d:%d): refuses tagged commands. "
3589 "Performing non-tagged I/O\n", ahc_name(ahc),
3590 devinfo->channel, devinfo->target, devinfo->lun);
3591 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3594 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3595 "Performing simple queue tagged I/O only\n",
3596 ahc_name(ahc), devinfo->channel, devinfo->target,
3597 devinfo->lun, tag_type == MSG_ORDERED_TASK
3598 ? "ordered" : "head of queue");
3599 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3604 * Resend the identify for this CCB as the target
3605 * may believe that the selection is invalid otherwise.
3607 ahc_outb(ahc, SCB_CONTROL,
3608 ahc_inb(ahc, SCB_CONTROL) & mask);
3609 scb->hscb->control &= mask;
3610 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3611 /*type*/MSG_SIMPLE_TASK);
3612 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3613 ahc_assert_atn(ahc);
3616 * This transaction is now at the head of
3617 * the untagged queue for this target.
3619 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3620 struct scb_tailq *untagged_q;
3623 &(ahc->untagged_queues[devinfo->target_offset]);
3624 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3625 scb->flags |= SCB_UNTAGGEDQ;
3627 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3631 * Requeue all tagged commands for this target
3632 * currently in our possession so they can be
3633 * converted to untagged commands.
3635 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3636 SCB_GET_CHANNEL(ahc, scb),
3637 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3638 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3642 * Otherwise, we ignore it.
3644 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3645 ahc_name(ahc), devinfo->channel, devinfo->target,
3652 * Process an ingnore wide residue message.
3655 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3660 scb_index = ahc_inb(ahc, SCB_TAG);
3661 scb = ahc_lookup_scb(ahc, scb_index);
3663 * XXX Actually check data direction in the sequencer?
3664 * Perhaps add datadir to some spare bits in the hscb?
3666 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3667 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3669 * Ignore the message if we haven't
3670 * seen an appropriate data phase yet.
3674 * If the residual occurred on the last
3675 * transfer and the transfer request was
3676 * expected to end on an odd count, do
3677 * nothing. Otherwise, subtract a byte
3678 * and update the residual count accordingly.
3682 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3683 if ((sgptr & SG_LIST_NULL) != 0
3684 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3686 * If the residual occurred on the last
3687 * transfer and the transfer request was
3688 * expected to end on an odd count, do
3692 struct ahc_dma_seg *sg;
3697 /* Pull in all of the sgptr */
3698 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3699 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3701 if ((sgptr & SG_LIST_NULL) != 0) {
3703 * The residual data count is not updated
3704 * for the command run to completion case.
3705 * Explicitly zero the count.
3707 data_cnt &= ~AHC_SG_LEN_MASK;
3710 data_addr = ahc_inl(ahc, SHADDR);
3714 sgptr &= SG_PTR_MASK;
3716 sg = ahc_sg_bus_to_virt(scb, sgptr);
3719 * The residual sg ptr points to the next S/G
3720 * to load so we must go back one.
3723 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3724 if (sg != scb->sg_list
3725 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3728 sglen = aic_le32toh(sg->len);
3730 * Preserve High Address and SG_LIST bits
3731 * while setting the count to 1.
3733 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3734 data_addr = aic_le32toh(sg->addr)
3735 + (sglen & AHC_SG_LEN_MASK) - 1;
3738 * Increment sg so it points to the
3742 sgptr = ahc_sg_virt_to_bus(scb, sg);
3744 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3745 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3747 * Toggle the "oddness" of the transfer length
3748 * to handle this mid-transfer ignore wide
3749 * residue. This ensures that the oddness is
3750 * correct for subsequent data transfers.
3752 ahc_outb(ahc, SCB_LUN,
3753 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3760 * Reinitialize the data pointers for the active transfer
3761 * based on its current residual.
3764 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3767 struct ahc_dma_seg *sg;
3773 scb_index = ahc_inb(ahc, SCB_TAG);
3774 scb = ahc_lookup_scb(ahc, scb_index);
3775 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3776 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3777 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3778 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3780 sgptr &= SG_PTR_MASK;
3781 sg = ahc_sg_bus_to_virt(scb, sgptr);
3783 /* The residual sg_ptr always points to the next sg */
3786 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3787 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3788 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3790 dataptr = aic_le32toh(sg->addr)
3791 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3793 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3796 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3797 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3798 ahc_outb(ahc, HADDR,
3799 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3800 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3802 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3803 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3804 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3805 ahc_outb(ahc, HADDR, dataptr);
3806 ahc_outb(ahc, HCNT + 2, resid >> 16);
3807 ahc_outb(ahc, HCNT + 1, resid >> 8);
3808 ahc_outb(ahc, HCNT, resid);
3809 if ((ahc->features & AHC_ULTRA2) == 0) {
3810 ahc_outb(ahc, STCNT + 2, resid >> 16);
3811 ahc_outb(ahc, STCNT + 1, resid >> 8);
3812 ahc_outb(ahc, STCNT, resid);
3817 * Handle the effects of issuing a bus device reset message.
3820 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3821 cam_status status, char *message, int verbose_level)
3823 #ifdef AHC_TARGET_MODE
3824 struct ahc_tmode_tstate* tstate;
3829 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3830 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3833 #ifdef AHC_TARGET_MODE
3835 * Send an immediate notify ccb to all target mord peripheral
3836 * drivers affected by this action.
3838 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3839 if (tstate != NULL) {
3840 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3841 struct ahc_tmode_lstate* lstate;
3843 lstate = tstate->enabled_luns[lun];
3847 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3848 MSG_BUS_DEV_RESET, /*arg*/0);
3849 ahc_send_lstate_events(ahc, lstate);
3855 * Go back to async/narrow transfers and renegotiate.
3857 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3858 AHC_TRANS_CUR, /*paused*/TRUE);
3859 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3860 /*period*/0, /*offset*/0, /*ppr_options*/0,
3861 AHC_TRANS_CUR, /*paused*/TRUE);
3863 if (status != CAM_SEL_TIMEOUT)
3864 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3865 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3868 && (verbose_level <= bootverbose))
3869 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3870 message, devinfo->channel, devinfo->target, found);
3873 #ifdef AHC_TARGET_MODE
3875 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3880 * To facilitate adding multiple messages together,
3881 * each routine should increment the index and len
3882 * variables instead of setting them explicitly.
3884 ahc->msgout_index = 0;
3885 ahc->msgout_len = 0;
3887 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3888 ahc_build_transfer_msg(ahc, devinfo);
3890 panic("ahc_intr: AWAITING target message with no message");
3892 ahc->msgout_index = 0;
3893 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3896 /**************************** Initialization **********************************/
3898 * Allocate a controller structure for a new device
3899 * and perform initial initializion.
3902 ahc_alloc(void *platform_arg, char *name)
3904 struct ahc_softc *ahc;
3908 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3910 printf("aic7xxx: cannot malloc softc!\n");
3911 free(name, M_DEVBUF);
3915 ahc = device_get_softc((device_t)platform_arg);
3917 memset(ahc, 0, sizeof(*ahc));
3918 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3919 M_DEVBUF, M_NOWAIT);
3920 if (ahc->seep_config == NULL) {
3922 free(ahc, M_DEVBUF);
3924 free(name, M_DEVBUF);
3927 LIST_INIT(&ahc->pending_scbs);
3928 LIST_INIT(&ahc->timedout_scbs);
3929 /* We don't know our unit number until the OSM sets it */
3932 ahc->description = NULL;
3934 ahc->channel_b = 'B';
3935 ahc->chip = AHC_NONE;
3936 ahc->features = AHC_FENONE;
3937 ahc->bugs = AHC_BUGNONE;
3938 ahc->flags = AHC_FNONE;
3940 * Default to all error reporting enabled with the
3941 * sequencer operating at its fastest speed.
3942 * The bus attach code may modify this.
3944 ahc->seqctl = FASTMODE;
3946 for (i = 0; i < AHC_NUM_TARGETS; i++)
3947 TAILQ_INIT(&ahc->untagged_queues[i]);
3948 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3957 ahc_softc_init(struct ahc_softc *ahc)
3960 /* The IRQMS bit is only valid on VL and EISA chips */
3961 if ((ahc->chip & AHC_PCI) == 0)
3962 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3965 ahc->pause = ahc->unpause | PAUSE;
3966 /* XXX The shared scb data stuff should be deprecated */
3967 if (ahc->scb_data == NULL) {
3968 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3969 M_DEVBUF, M_NOWAIT);
3970 if (ahc->scb_data == NULL)
3972 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3979 ahc_softc_insert(struct ahc_softc *ahc)
3981 struct ahc_softc *list_ahc;
3983 #if AIC_PCI_CONFIG > 0
3985 * Second Function PCI devices need to inherit some
3986 * settings from function 0.
3988 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3989 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3990 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3991 aic_dev_softc_t list_pci;
3992 aic_dev_softc_t pci;
3994 list_pci = list_ahc->dev_softc;
3995 pci = ahc->dev_softc;
3996 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3997 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3998 struct ahc_softc *master;
3999 struct ahc_softc *slave;
4001 if (aic_get_pci_function(list_pci) == 0) {
4008 slave->flags &= ~AHC_BIOS_ENABLED;
4010 master->flags & AHC_BIOS_ENABLED;
4011 slave->flags &= ~AHC_PRIMARY_CHANNEL;
4013 master->flags & AHC_PRIMARY_CHANNEL;
4021 * Insertion sort into our list of softcs.
4023 list_ahc = TAILQ_FIRST(&ahc_tailq);
4024 while (list_ahc != NULL
4025 && ahc_softc_comp(ahc, list_ahc) <= 0)
4026 list_ahc = TAILQ_NEXT(list_ahc, links);
4027 if (list_ahc != NULL)
4028 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4030 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4035 ahc_set_unit(struct ahc_softc *ahc, int unit)
4041 ahc_set_name(struct ahc_softc *ahc, char *name)
4043 if (ahc->name != NULL)
4044 free(ahc->name, M_DEVBUF);
4049 ahc_free(struct ahc_softc *ahc)
4053 ahc_terminate_recovery_thread(ahc);
4054 switch (ahc->init_level) {
4060 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4061 ahc->shared_data_dmamap);
4064 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4065 ahc->shared_data_dmamap);
4068 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4071 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4079 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4081 ahc_platform_free(ahc);
4082 ahc_fini_scbdata(ahc);
4083 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4084 struct ahc_tmode_tstate *tstate;
4086 tstate = ahc->enabled_targets[i];
4087 if (tstate != NULL) {
4088 #ifdef AHC_TARGET_MODE
4091 for (j = 0; j < AHC_NUM_LUNS; j++) {
4092 struct ahc_tmode_lstate *lstate;
4094 lstate = tstate->enabled_luns[j];
4095 if (lstate != NULL) {
4096 xpt_free_path(lstate->path);
4097 free(lstate, M_DEVBUF);
4101 free(tstate, M_DEVBUF);
4104 #ifdef AHC_TARGET_MODE
4105 if (ahc->black_hole != NULL) {
4106 xpt_free_path(ahc->black_hole->path);
4107 free(ahc->black_hole, M_DEVBUF);
4110 if (ahc->name != NULL)
4111 free(ahc->name, M_DEVBUF);
4112 if (ahc->seep_config != NULL)
4113 free(ahc->seep_config, M_DEVBUF);
4115 free(ahc, M_DEVBUF);
4121 ahc_shutdown(void *arg)
4123 struct ahc_softc *ahc;
4126 ahc = (struct ahc_softc *)arg;
4128 /* This will reset most registers to 0, but not all */
4129 ahc_reset(ahc, /*reinit*/FALSE);
4130 ahc_outb(ahc, SCSISEQ, 0);
4131 ahc_outb(ahc, SXFRCTL0, 0);
4132 ahc_outb(ahc, DSPCISTATUS, 0);
4134 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4135 ahc_outb(ahc, i, 0);
4139 * Reset the controller and record some information about it
4140 * that is only available just after a reset. If "reinit" is
4141 * non-zero, this reset occurred after initial configuration
4142 * and the caller requests that the chip be fully reinitialized
4143 * to a runable state. Chip interrupts are *not* enabled after
4144 * a reinitialization. The caller must enable interrupts via
4145 * ahc_intr_enable().
4148 ahc_reset(struct ahc_softc *ahc, int reinit)
4151 u_int sxfrctl1_a, sxfrctl1_b;
4156 * Preserve the value of the SXFRCTL1 register for all channels.
4157 * It contains settings that affect termination and we don't want
4158 * to disturb the integrity of the bus.
4162 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4166 * Save channel B's settings in case this chip
4167 * is setup for TWIN channel operation.
4169 sblkctl = ahc_inb(ahc, SBLKCTL);
4170 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4171 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4172 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4174 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4176 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4179 * Ensure that the reset has finished. We delay 1000us
4180 * prior to reading the register to make sure the chip
4181 * has sufficiently completed its reset to handle register
4187 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4190 printf("%s: WARNING - Failed chip reset! "
4191 "Trying to initialize anyway.\n", ahc_name(ahc));
4193 ahc_outb(ahc, HCNTRL, ahc->pause);
4195 /* Determine channel configuration */
4196 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4197 /* No Twin Channel PCI cards */
4198 if ((ahc->chip & AHC_PCI) != 0)
4199 sblkctl &= ~SELBUSB;
4202 /* Single Narrow Channel */
4206 ahc->features |= AHC_WIDE;
4210 ahc->features |= AHC_TWIN;
4213 printf(" Unsupported adapter type. Ignoring\n");
4220 * We must always initialize STPWEN to 1 before we
4221 * restore the saved values. STPWEN is initialized
4222 * to a tri-state condition which can only be cleared
4225 if ((ahc->features & AHC_TWIN) != 0) {
4228 sblkctl = ahc_inb(ahc, SBLKCTL);
4229 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4230 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4231 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4233 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4238 * If a recovery action has forced a chip reset,
4239 * re-initialize the chip to our liking.
4241 error = ahc->bus_chip_init(ahc);
4251 * Determine the number of SCBs available on the controller
4254 ahc_probe_scbs(struct ahc_softc *ahc) {
4257 for (i = 0; i < AHC_SCB_MAX; i++) {
4259 ahc_outb(ahc, SCBPTR, i);
4260 ahc_outb(ahc, SCB_BASE, i);
4261 if (ahc_inb(ahc, SCB_BASE) != i)
4263 ahc_outb(ahc, SCBPTR, 0);
4264 if (ahc_inb(ahc, SCB_BASE) != 0)
4271 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4275 baddr = (bus_addr_t *)arg;
4276 *baddr = segs->ds_addr;
4280 ahc_build_free_scb_list(struct ahc_softc *ahc)
4286 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4289 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4292 ahc_outb(ahc, SCBPTR, i);
4295 * Touch all SCB bytes to avoid parity errors
4296 * should one of our debugging routines read
4297 * an otherwise uninitiatlized byte.
4299 for (j = 0; j < scbsize; j++)
4300 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4302 /* Clear the control byte. */
4303 ahc_outb(ahc, SCB_CONTROL, 0);
4305 /* Set the next pointer */
4306 if ((ahc->flags & AHC_PAGESCBS) != 0)
4307 ahc_outb(ahc, SCB_NEXT, i+1);
4309 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4311 /* Make the tag number, SCSIID, and lun invalid */
4312 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4313 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4314 ahc_outb(ahc, SCB_LUN, 0xFF);
4317 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4318 /* SCB 0 heads the free list. */
4319 ahc_outb(ahc, FREE_SCBH, 0);
4322 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4325 /* Make sure that the last SCB terminates the free list */
4326 ahc_outb(ahc, SCBPTR, i-1);
4327 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4331 ahc_init_scbdata(struct ahc_softc *ahc)
4333 struct scb_data *scb_data;
4335 scb_data = ahc->scb_data;
4336 SLIST_INIT(&scb_data->free_scbs);
4337 SLIST_INIT(&scb_data->sg_maps);
4339 /* Allocate SCB resources */
4340 scb_data->scbarray =
4341 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4342 M_DEVBUF, M_NOWAIT);
4343 if (scb_data->scbarray == NULL)
4345 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4347 /* Determine the number of hardware SCBs and initialize them */
4349 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4350 if (ahc->scb_data->maxhscbs == 0) {
4351 printf("%s: No SCB space found\n", ahc_name(ahc));
4356 * Create our DMA tags. These tags define the kinds of device
4357 * accessible memory allocations and memory mappings we will
4358 * need to perform during normal operation.
4360 * Unless we need to further restrict the allocation, we rely
4361 * on the restrictions of the parent dmat, hence the common
4362 * use of MAXADDR and MAXSIZE.
4365 /* DMA tag for our hardware scb structures */
4366 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4367 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4368 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4369 /*highaddr*/BUS_SPACE_MAXADDR,
4370 /*filter*/NULL, /*filterarg*/NULL,
4371 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4373 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4374 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4378 scb_data->init_level++;
4380 /* Allocation for our hscbs */
4381 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4382 (void **)&scb_data->hscbs,
4383 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4384 &scb_data->hscb_dmamap) != 0) {
4388 scb_data->init_level++;
4390 /* And permanently map them */
4391 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4393 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4394 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4396 scb_data->init_level++;
4398 /* DMA tag for our sense buffers */
4399 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4400 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4401 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4402 /*highaddr*/BUS_SPACE_MAXADDR,
4403 /*filter*/NULL, /*filterarg*/NULL,
4404 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4406 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4407 /*flags*/0, &scb_data->sense_dmat) != 0) {
4411 scb_data->init_level++;
4414 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4415 (void **)&scb_data->sense,
4416 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4420 scb_data->init_level++;
4422 /* And permanently map them */
4423 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4425 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4426 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4428 scb_data->init_level++;
4430 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4431 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4432 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4433 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4434 /*highaddr*/BUS_SPACE_MAXADDR,
4435 /*filter*/NULL, /*filterarg*/NULL,
4436 PAGE_SIZE, /*nsegments*/1,
4437 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4438 /*flags*/0, &scb_data->sg_dmat) != 0) {
4442 scb_data->init_level++;
4444 /* Perform initial CCB allocation */
4445 memset(scb_data->hscbs, 0,
4446 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4447 while (ahc_alloc_scbs(ahc) != 0)
4450 if (scb_data->numscbs == 0) {
4451 printf("%s: ahc_init_scbdata - "
4452 "Unable to allocate initial scbs\n",
4458 * Reserve the next queued SCB.
4460 ahc->next_queued_scb = ahc_get_scb(ahc);
4463 * Note that we were successful
4473 ahc_fini_scbdata(struct ahc_softc *ahc)
4475 struct scb_data *scb_data;
4477 scb_data = ahc->scb_data;
4478 if (scb_data == NULL)
4481 switch (scb_data->init_level) {
4485 struct sg_map_node *sg_map;
4487 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4488 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4489 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4491 aic_dmamem_free(ahc, scb_data->sg_dmat,
4494 free(sg_map, M_DEVBUF);
4496 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4499 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4500 scb_data->sense_dmamap);
4502 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4503 scb_data->sense_dmamap);
4505 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4507 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4508 scb_data->hscb_dmamap);
4510 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4511 scb_data->hscb_dmamap);
4513 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4518 if (scb_data->scbarray != NULL)
4519 free(scb_data->scbarray, M_DEVBUF);
4523 ahc_alloc_scbs(struct ahc_softc *ahc)
4525 struct scb_data *scb_data;
4526 struct scb *next_scb;
4527 struct sg_map_node *sg_map;
4528 bus_addr_t physaddr;
4529 struct ahc_dma_seg *segs;
4533 scb_data = ahc->scb_data;
4534 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4535 /* Can't allocate any more */
4538 next_scb = &scb_data->scbarray[scb_data->numscbs];
4540 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4545 /* Allocate S/G space for the next batch of SCBS */
4546 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4547 (void **)&sg_map->sg_vaddr,
4548 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4549 &sg_map->sg_dmamap) != 0) {
4550 free(sg_map, M_DEVBUF);
4554 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4556 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4557 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4558 &sg_map->sg_physaddr, /*flags*/0);
4560 segs = sg_map->sg_vaddr;
4561 physaddr = sg_map->sg_physaddr;
4563 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4564 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4565 for (i = 0; i < newcount; i++) {
4566 struct scb_platform_data *pdata;
4570 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4571 M_DEVBUF, M_NOWAIT);
4574 next_scb->platform_data = pdata;
4575 next_scb->sg_map = sg_map;
4576 next_scb->sg_list = segs;
4578 * The sequencer always starts with the second entry.
4579 * The first entry is embedded in the scb.
4581 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4582 next_scb->ahc_softc = ahc;
4583 next_scb->flags = SCB_FLAG_NONE;
4585 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4590 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4591 next_scb->hscb->tag = ahc->scb_data->numscbs;
4592 aic_timer_init(&next_scb->io_timer);
4593 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4594 next_scb, links.sle);
4596 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4598 ahc->scb_data->numscbs++;
4604 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4608 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4610 if ((ahc->features & AHC_TWIN) != 0)
4611 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4612 "B SCSI Id=%d, primary %c, ",
4613 ahc->our_id, ahc->our_id_b,
4614 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4620 if ((ahc->features & AHC_ULTRA) != 0) {
4622 } else if ((ahc->features & AHC_DT) != 0) {
4623 speed = "Ultra160 ";
4624 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4627 if ((ahc->features & AHC_WIDE) != 0) {
4632 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4633 speed, type, ahc->channel, ahc->our_id);
4637 if ((ahc->flags & AHC_PAGESCBS) != 0)
4638 sprintf(buf, "%d/%d SCBs",
4639 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4641 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4645 ahc_chip_init(struct ahc_softc *ahc)
4651 u_int scsiseq_template;
4654 ahc_outb(ahc, SEQ_FLAGS, 0);
4655 ahc_outb(ahc, SEQ_FLAGS2, 0);
4657 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4658 if (ahc->features & AHC_TWIN) {
4661 * Setup Channel B first.
4663 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4664 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4665 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4666 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4667 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4668 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4669 if ((ahc->features & AHC_ULTRA2) != 0)
4670 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4671 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4672 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4674 /* Select Channel A */
4675 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4677 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4678 if ((ahc->features & AHC_ULTRA2) != 0)
4679 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4681 ahc_outb(ahc, SCSIID, ahc->our_id);
4682 scsi_conf = ahc_inb(ahc, SCSICONF);
4683 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4685 |ENSTIMER|ACTNEGEN);
4686 if ((ahc->features & AHC_ULTRA2) != 0)
4687 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4688 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4689 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4691 /* There are no untagged SCBs active yet. */
4692 for (i = 0; i < 16; i++) {
4693 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4694 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4698 * The SCB based BTT allows an entry per
4699 * target and lun pair.
4701 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4702 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4706 /* All of our queues are empty */
4707 for (i = 0; i < 256; i++)
4708 ahc->qoutfifo[i] = SCB_LIST_NULL;
4709 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4711 for (i = 0; i < 256; i++)
4712 ahc->qinfifo[i] = SCB_LIST_NULL;
4714 if ((ahc->features & AHC_MULTI_TID) != 0) {
4715 ahc_outb(ahc, TARGID, 0);
4716 ahc_outb(ahc, TARGID + 1, 0);
4720 * Tell the sequencer where it can find our arrays in memory.
4722 physaddr = ahc->scb_data->hscb_busaddr;
4723 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4724 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4725 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4726 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4728 physaddr = ahc->shared_data_busaddr;
4729 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4730 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4731 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4732 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4735 * Initialize the group code to command length table.
4736 * This overrides the values in TARG_SCSIRATE, so only
4737 * setup the table after we have processed that information.
4739 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4740 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4741 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4742 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4743 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4744 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4745 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4746 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4748 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4749 ahc_outb(ahc, HS_MAILBOX, 0);
4751 /* Tell the sequencer of our initial queue positions */
4752 if ((ahc->features & AHC_TARGETMODE) != 0) {
4753 ahc->tqinfifonext = 1;
4754 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4755 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4757 ahc->qinfifonext = 0;
4758 ahc->qoutfifonext = 0;
4759 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4760 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4761 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4762 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4763 ahc_outb(ahc, SDSCB_QOFF, 0);
4765 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4766 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4767 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4770 /* We don't have any waiting selections */
4771 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4773 /* Our disconnection list is empty too */
4774 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4776 /* Message out buffer starts empty */
4777 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4780 * Setup the allowed SCSI Sequences based on operational mode.
4781 * If we are a target, we'll enalbe select in operations once
4782 * we've had a lun enabled.
4784 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4785 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4786 scsiseq_template |= ENRSELI;
4787 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4789 /* Initialize our list of free SCBs. */
4790 ahc_build_free_scb_list(ahc);
4793 * Tell the sequencer which SCB will be the next one it receives.
4795 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4798 * Load the Sequencer program and Enable the adapter
4802 printf("%s: Downloading Sequencer Program...",
4805 error = ahc_loadseq(ahc);
4809 if ((ahc->features & AHC_ULTRA2) != 0) {
4813 * Wait for up to 500ms for our transceivers
4814 * to settle. If the adapter does not have
4815 * a cable attached, the transceivers may
4816 * never settle, so don't complain if we
4820 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4829 * Start the board, ready for normal operation
4832 ahc_init(struct ahc_softc *ahc)
4841 size_t driver_data_size;
4844 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4845 ahc->flags |= AHC_SEQUENCER_DEBUG;
4848 #ifdef AHC_PRINT_SRAM
4849 printf("Scratch Ram:");
4850 for (i = 0x20; i < 0x5f; i++) {
4851 if (((i % 8) == 0) && (i != 0)) {
4854 printf (" 0x%x", ahc_inb(ahc, i));
4856 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4857 for (i = 0x70; i < 0x7f; i++) {
4858 if (((i % 8) == 0) && (i != 0)) {
4861 printf (" 0x%x", ahc_inb(ahc, i));
4866 * Reading uninitialized scratch ram may
4867 * generate parity errors.
4869 ahc_outb(ahc, CLRINT, CLRPARERR);
4870 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4875 * Assume we have a board at this stage and it has been reset.
4877 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4878 ahc->our_id = ahc->our_id_b = 7;
4881 * Default to allowing initiator operations.
4883 ahc->flags |= AHC_INITIATORROLE;
4886 * Only allow target mode features if this unit has them enabled.
4888 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4889 ahc->features &= ~AHC_TARGETMODE;
4892 /* DMA tag for mapping buffers into device visible space. */
4893 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4894 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4895 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4896 ? (bus_addr_t)0x7FFFFFFFFFULL
4897 : BUS_SPACE_MAXADDR_32BIT,
4898 /*highaddr*/BUS_SPACE_MAXADDR,
4899 /*filter*/NULL, /*filterarg*/NULL,
4900 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4901 /*nsegments*/AHC_NSEG,
4902 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4903 /*flags*/BUS_DMA_ALLOCNOW,
4904 &ahc->buffer_dmat) != 0) {
4912 * DMA tag for our command fifos and other data in system memory
4913 * the card's sequencer must be able to access. For initiator
4914 * roles, we need to allocate space for the qinfifo and qoutfifo.
4915 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4916 * When providing for the target mode role, we must additionally
4917 * provide space for the incoming target command fifo and an extra
4918 * byte to deal with a dma bug in some chip versions.
4920 driver_data_size = 2 * 256 * sizeof(uint8_t);
4921 if ((ahc->features & AHC_TARGETMODE) != 0)
4922 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4923 + /*DMA WideOdd Bug Buffer*/1;
4924 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4925 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4926 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4927 /*highaddr*/BUS_SPACE_MAXADDR,
4928 /*filter*/NULL, /*filterarg*/NULL,
4931 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4932 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4938 /* Allocation of driver data */
4939 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4940 (void **)&ahc->qoutfifo,
4941 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4942 &ahc->shared_data_dmamap) != 0) {
4948 /* And permanently map it in */
4949 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4950 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4951 &ahc->shared_data_busaddr, /*flags*/0);
4953 if ((ahc->features & AHC_TARGETMODE) != 0) {
4954 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4955 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4956 ahc->dma_bug_buf = ahc->shared_data_busaddr
4957 + driver_data_size - 1;
4958 /* All target command blocks start out invalid. */
4959 for (i = 0; i < AHC_TMODE_CMDS; i++)
4960 ahc->targetcmds[i].cmd_valid = 0;
4961 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4962 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4964 ahc->qinfifo = &ahc->qoutfifo[256];
4968 /* Allocate SCB data now that buffer_dmat is initialized */
4969 if (ahc->scb_data->maxhscbs == 0)
4970 if (ahc_init_scbdata(ahc) != 0)
4974 * Allocate a tstate to house information for our
4975 * initiator presence on the bus as well as the user
4976 * data for any target mode initiator.
4978 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4979 printf("%s: unable to allocate ahc_tmode_tstate. "
4980 "Failing attach\n", ahc_name(ahc));
4984 if ((ahc->features & AHC_TWIN) != 0) {
4985 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4986 printf("%s: unable to allocate ahc_tmode_tstate. "
4987 "Failing attach\n", ahc_name(ahc));
4993 * Fire up a recovery thread for this controller.
4995 error = ahc_spawn_recovery_thread(ahc);
4999 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5000 ahc->flags |= AHC_PAGESCBS;
5002 ahc->flags &= ~AHC_PAGESCBS;
5006 if (ahc_debug & AHC_SHOW_MISC) {
5007 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
5008 "ahc_dma %u bytes\n",
5010 (u_int)sizeof(struct hardware_scb),
5011 (u_int)sizeof(struct scb),
5012 (u_int)sizeof(struct ahc_dma_seg));
5014 #endif /* AHC_DEBUG */
5017 * Look at the information that board initialization or
5018 * the board bios has left us.
5020 if (ahc->features & AHC_TWIN) {
5021 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5022 if ((scsi_conf & RESET_SCSI) != 0
5023 && (ahc->flags & AHC_INITIATORROLE) != 0)
5024 ahc->flags |= AHC_RESET_BUS_B;
5027 scsi_conf = ahc_inb(ahc, SCSICONF);
5028 if ((scsi_conf & RESET_SCSI) != 0
5029 && (ahc->flags & AHC_INITIATORROLE) != 0)
5030 ahc->flags |= AHC_RESET_BUS_A;
5033 tagenable = ALL_TARGETS_MASK;
5035 /* Grab the disconnection disable table and invert it for our needs */
5036 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5037 printf("%s: Host Adapter Bios disabled. Using default SCSI "
5038 "device parameters\n", ahc_name(ahc));
5039 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5040 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5041 discenable = ALL_TARGETS_MASK;
5042 if ((ahc->features & AHC_ULTRA) != 0)
5043 ultraenb = ALL_TARGETS_MASK;
5045 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5046 | ahc_inb(ahc, DISC_DSB));
5047 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5048 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5049 | ahc_inb(ahc, ULTRA_ENB);
5052 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5055 for (i = 0; i <= max_targ; i++) {
5056 struct ahc_initiator_tinfo *tinfo;
5057 struct ahc_tmode_tstate *tstate;
5063 our_id = ahc->our_id;
5065 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5067 our_id = ahc->our_id_b;
5070 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5071 target_id, &tstate);
5072 /* Default to async narrow across the board */
5073 memset(tinfo, 0, sizeof(*tinfo));
5074 if (ahc->flags & AHC_USEDEFAULTS) {
5075 if ((ahc->features & AHC_WIDE) != 0)
5076 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5079 * These will be truncated when we determine the
5080 * connection type we have with the target.
5082 tinfo->user.period = ahc_syncrates->period;
5083 tinfo->user.offset = MAX_OFFSET;
5088 /* Take the settings leftover in scratch RAM. */
5089 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5091 if ((ahc->features & AHC_ULTRA2) != 0) {
5095 if ((scsirate & SOFS) == 0x0F) {
5097 * Haven't negotiated yet,
5098 * so the format is different.
5100 scsirate = (scsirate & SXFR) >> 4
5103 | (scsirate & WIDEXFER);
5104 offset = MAX_OFFSET_ULTRA2;
5106 offset = ahc_inb(ahc, TARG_OFFSET + i);
5107 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5108 /* Set to the lowest sync rate, 5MHz */
5110 maxsync = AHC_SYNCRATE_ULTRA2;
5111 if ((ahc->features & AHC_DT) != 0)
5112 maxsync = AHC_SYNCRATE_DT;
5113 tinfo->user.period =
5114 ahc_find_period(ahc, scsirate, maxsync);
5116 tinfo->user.period = 0;
5118 tinfo->user.offset = MAX_OFFSET;
5119 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5120 && (ahc->features & AHC_DT) != 0)
5121 tinfo->user.ppr_options =
5123 } else if ((scsirate & SOFS) != 0) {
5124 if ((scsirate & SXFR) == 0x40
5125 && (ultraenb & mask) != 0) {
5126 /* Treat 10MHz as a non-ultra speed */
5130 tinfo->user.period =
5131 ahc_find_period(ahc, scsirate,
5133 ? AHC_SYNCRATE_ULTRA
5134 : AHC_SYNCRATE_FAST);
5135 if (tinfo->user.period != 0)
5136 tinfo->user.offset = MAX_OFFSET;
5138 if (tinfo->user.period == 0)
5139 tinfo->user.offset = 0;
5140 if ((scsirate & WIDEXFER) != 0
5141 && (ahc->features & AHC_WIDE) != 0)
5142 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5143 tinfo->user.protocol_version = 4;
5144 if ((ahc->features & AHC_DT) != 0)
5145 tinfo->user.transport_version = 3;
5147 tinfo->user.transport_version = 2;
5148 tinfo->goal.protocol_version = 2;
5149 tinfo->goal.transport_version = 2;
5150 tinfo->curr.protocol_version = 2;
5151 tinfo->curr.transport_version = 2;
5153 tstate->ultraenb = 0;
5155 ahc->user_discenable = discenable;
5156 ahc->user_tagenable = tagenable;
5158 return (ahc->bus_chip_init(ahc));
5162 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5166 hcntrl = ahc_inb(ahc, HCNTRL);
5168 ahc->pause &= ~INTEN;
5169 ahc->unpause &= ~INTEN;
5172 ahc->pause |= INTEN;
5173 ahc->unpause |= INTEN;
5175 ahc_outb(ahc, HCNTRL, hcntrl);
5179 * Ensure that the card is paused in a location
5180 * outside of all critical sections and that all
5181 * pending work is completed prior to returning.
5182 * This routine should only be called from outside
5183 * an interrupt context.
5186 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5193 ahc->flags |= AHC_ALL_INTERRUPTS;
5199 * Give the sequencer some time to service
5200 * any active selections.
5207 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5208 intstat = ahc_inb(ahc, INTSTAT);
5209 if ((intstat & INT_PEND) == 0) {
5210 ahc_clear_critical_section(ahc);
5211 intstat = ahc_inb(ahc, INTSTAT);
5214 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5215 && ((intstat & INT_PEND) != 0
5216 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5217 if (maxloops == 0) {
5218 printf("Infinite interrupt loop, INTSTAT = %x",
5219 ahc_inb(ahc, INTSTAT));
5221 ahc_platform_flushwork(ahc);
5222 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5226 ahc_suspend(struct ahc_softc *ahc)
5229 ahc_pause_and_flushwork(ahc);
5231 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5236 #ifdef AHC_TARGET_MODE
5238 * XXX What about ATIOs that have not yet been serviced?
5239 * Perhaps we should just refuse to be suspended if we
5240 * are acting in a target role.
5242 if (ahc->pending_device != NULL) {
5252 ahc_resume(struct ahc_softc *ahc)
5255 ahc_reset(ahc, /*reinit*/TRUE);
5256 ahc_intr_enable(ahc, TRUE);
5261 /************************** Busy Target Table *********************************/
5263 * Return the untagged transaction id for a given target/channel lun.
5264 * Optionally, clear the entry.
5267 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5270 u_int target_offset;
5272 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5275 saved_scbptr = ahc_inb(ahc, SCBPTR);
5276 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5277 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5278 ahc_outb(ahc, SCBPTR, saved_scbptr);
5280 target_offset = TCL_TARGET_OFFSET(tcl);
5281 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5288 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5290 u_int target_offset;
5292 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5295 saved_scbptr = ahc_inb(ahc, SCBPTR);
5296 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5297 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5298 ahc_outb(ahc, SCBPTR, saved_scbptr);
5300 target_offset = TCL_TARGET_OFFSET(tcl);
5301 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5306 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5308 u_int target_offset;
5310 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5313 saved_scbptr = ahc_inb(ahc, SCBPTR);
5314 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5315 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5316 ahc_outb(ahc, SCBPTR, saved_scbptr);
5318 target_offset = TCL_TARGET_OFFSET(tcl);
5319 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5323 /************************** SCB and SCB queue management **********************/
5325 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5326 char channel, int lun, u_int tag, role_t role)
5328 int targ = SCB_GET_TARGET(ahc, scb);
5329 char chan = SCB_GET_CHANNEL(ahc, scb);
5330 int slun = SCB_GET_LUN(scb);
5333 match = ((chan == channel) || (channel == ALL_CHANNELS));
5335 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5337 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5339 #ifdef AHC_TARGET_MODE
5342 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5343 if (role == ROLE_INITIATOR) {
5344 match = (group != XPT_FC_GROUP_TMODE)
5345 && ((tag == scb->hscb->tag)
5346 || (tag == SCB_LIST_NULL));
5347 } else if (role == ROLE_TARGET) {
5348 match = (group == XPT_FC_GROUP_TMODE)
5349 && ((tag == scb->io_ctx->csio.tag_id)
5350 || (tag == SCB_LIST_NULL));
5352 #else /* !AHC_TARGET_MODE */
5353 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5354 #endif /* AHC_TARGET_MODE */
5361 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5367 target = SCB_GET_TARGET(ahc, scb);
5368 lun = SCB_GET_LUN(scb);
5369 channel = SCB_GET_CHANNEL(ahc, scb);
5371 ahc_search_qinfifo(ahc, target, channel, lun,
5372 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5373 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5375 ahc_platform_freeze_devq(ahc, scb);
5379 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5381 struct scb *prev_scb;
5384 if (ahc_qinfifo_count(ahc) != 0) {
5388 prev_pos = ahc->qinfifonext - 1;
5389 prev_tag = ahc->qinfifo[prev_pos];
5390 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5392 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5393 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5394 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5396 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5401 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5404 if (prev_scb == NULL) {
5405 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5407 prev_scb->hscb->next = scb->hscb->tag;
5408 ahc_sync_scb(ahc, prev_scb,
5409 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5411 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5412 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5413 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5417 ahc_qinfifo_count(struct ahc_softc *ahc)
5422 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5423 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5424 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5426 qinpos = ahc_inb(ahc, QINPOS);
5427 diff = ahc->qinfifonext - qinpos;
5432 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5433 int lun, u_int tag, role_t role, uint32_t status,
5434 ahc_search_action action)
5437 struct scb *prev_scb;
5447 qintail = ahc->qinfifonext;
5448 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5450 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5451 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5453 qinstart = ahc_inb(ahc, QINPOS);
5458 if (action == SEARCH_COMPLETE) {
5460 * Don't attempt to run any queued untagged transactions
5461 * until we are done with the abort process.
5463 ahc_freeze_untagged_queues(ahc);
5467 * Start with an empty queue. Entries that are not chosen
5468 * for removal will be re-added to the queue as we go.
5470 ahc->qinfifonext = qinpos;
5471 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5473 while (qinpos != qintail) {
5474 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5476 printf("qinpos = %d, SCB index = %d\n",
5477 qinpos, ahc->qinfifo[qinpos]);
5481 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5483 * We found an scb that needs to be acted on.
5487 case SEARCH_COMPLETE:
5492 ostat = aic_get_transaction_status(scb);
5493 if (ostat == CAM_REQ_INPROG)
5494 aic_set_transaction_status(scb, status);
5495 cstat = aic_get_transaction_status(scb);
5496 if (cstat != CAM_REQ_CMP)
5497 aic_freeze_scb(scb);
5498 if ((scb->flags & SCB_ACTIVE) == 0)
5499 printf("Inactive SCB in qinfifo\n");
5507 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5512 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5518 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5519 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5521 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5524 if (action != SEARCH_COUNT
5526 && (qinstart != ahc->qinfifonext)) {
5528 * The sequencer may be in the process of dmaing
5529 * down the SCB at the beginning of the queue.
5530 * This could be problematic if either the first,
5531 * or the second SCB is removed from the queue
5532 * (the first SCB includes a pointer to the "next"
5533 * SCB to dma). If we have removed any entries, swap
5534 * the first element in the queue with the next HSCB
5535 * so the sequencer will notice that NEXT_QUEUED_SCB
5536 * has changed during its dma attempt and will retry
5539 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5542 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5543 found, qinstart, ahc->qinfifonext);
5544 panic("First/Second Qinfifo fixup\n");
5547 * ahc_swap_with_next_hscb forces our next pointer to
5548 * point to the reserved SCB for future commands. Save
5549 * and restore our original next pointer to maintain
5552 next = scb->hscb->next;
5553 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5554 ahc_swap_with_next_hscb(ahc, scb);
5555 scb->hscb->next = next;
5556 ahc->qinfifo[qinstart] = scb->hscb->tag;
5558 /* Tell the card about the new head of the qinfifo. */
5559 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5561 /* Fixup the tail "next" pointer. */
5562 qintail = ahc->qinfifonext - 1;
5563 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5564 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5568 * Search waiting for selection list.
5570 curscbptr = ahc_inb(ahc, SCBPTR);
5571 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5572 prev = SCB_LIST_NULL;
5574 while (next != SCB_LIST_NULL) {
5577 ahc_outb(ahc, SCBPTR, next);
5578 scb_index = ahc_inb(ahc, SCB_TAG);
5579 if (scb_index >= ahc->scb_data->numscbs) {
5580 printf("Waiting List inconsistency. "
5581 "SCB index == %d, yet numscbs == %d.",
5582 scb_index, ahc->scb_data->numscbs);
5583 ahc_dump_card_state(ahc);
5584 panic("for safety");
5586 scb = ahc_lookup_scb(ahc, scb_index);
5588 printf("scb_index = %d, next = %d\n",
5590 panic("Waiting List traversal\n");
5592 if (ahc_match_scb(ahc, scb, target, channel,
5593 lun, SCB_LIST_NULL, role)) {
5595 * We found an scb that needs to be acted on.
5599 case SEARCH_COMPLETE:
5604 ostat = aic_get_transaction_status(scb);
5605 if (ostat == CAM_REQ_INPROG)
5606 aic_set_transaction_status(scb,
5608 cstat = aic_get_transaction_status(scb);
5609 if (cstat != CAM_REQ_CMP)
5610 aic_freeze_scb(scb);
5611 if ((scb->flags & SCB_ACTIVE) == 0)
5612 printf("Inactive SCB in Wait List\n");
5617 next = ahc_rem_wscb(ahc, next, prev);
5621 next = ahc_inb(ahc, SCB_NEXT);
5627 next = ahc_inb(ahc, SCB_NEXT);
5630 ahc_outb(ahc, SCBPTR, curscbptr);
5632 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5633 channel, lun, status, action);
5635 if (action == SEARCH_COMPLETE)
5636 ahc_release_untagged_queues(ahc);
5641 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5642 int target, char channel, int lun, uint32_t status,
5643 ahc_search_action action)
5650 if (action == SEARCH_COMPLETE) {
5652 * Don't attempt to run any queued untagged transactions
5653 * until we are done with the abort process.
5655 ahc_freeze_untagged_queues(ahc);
5660 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5663 if (target != CAM_TARGET_WILDCARD) {
5674 for (; i < maxtarget; i++) {
5675 struct scb_tailq *untagged_q;
5676 struct scb *next_scb;
5678 untagged_q = &(ahc->untagged_queues[i]);
5679 next_scb = TAILQ_FIRST(untagged_q);
5680 while (next_scb != NULL) {
5683 next_scb = TAILQ_NEXT(scb, links.tqe);
5686 * The head of the list may be the currently
5687 * active untagged command for a device.
5688 * We're only searching for commands that
5689 * have not been started. A transaction
5690 * marked active but still in the qinfifo
5691 * is removed by the qinfifo scanning code
5694 if ((scb->flags & SCB_ACTIVE) != 0)
5697 if (ahc_match_scb(ahc, scb, target, channel, lun,
5698 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5699 || (ctx != NULL && ctx != scb->io_ctx))
5703 * We found an scb that needs to be acted on.
5707 case SEARCH_COMPLETE:
5712 ostat = aic_get_transaction_status(scb);
5713 if (ostat == CAM_REQ_INPROG)
5714 aic_set_transaction_status(scb, status);
5715 cstat = aic_get_transaction_status(scb);
5716 if (cstat != CAM_REQ_CMP)
5717 aic_freeze_scb(scb);
5722 scb->flags &= ~SCB_UNTAGGEDQ;
5723 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5731 if (action == SEARCH_COMPLETE)
5732 ahc_release_untagged_queues(ahc);
5737 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5738 int lun, u_int tag, int stop_on_first, int remove,
5748 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5749 prev = SCB_LIST_NULL;
5752 /* restore this when we're done */
5753 active_scb = ahc_inb(ahc, SCBPTR);
5755 /* Silence compiler */
5756 active_scb = SCB_LIST_NULL;
5758 while (next != SCB_LIST_NULL) {
5761 ahc_outb(ahc, SCBPTR, next);
5762 scb_index = ahc_inb(ahc, SCB_TAG);
5763 if (scb_index >= ahc->scb_data->numscbs) {
5764 printf("Disconnected List inconsistency. "
5765 "SCB index == %d, yet numscbs == %d.",
5766 scb_index, ahc->scb_data->numscbs);
5767 ahc_dump_card_state(ahc);
5768 panic("for safety");
5772 panic("Disconnected List Loop. "
5773 "cur SCBPTR == %x, prev SCBPTR == %x.",
5776 scbp = ahc_lookup_scb(ahc, scb_index);
5777 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5778 tag, ROLE_INITIATOR)) {
5782 ahc_rem_scb_from_disc_list(ahc, prev, next);
5785 next = ahc_inb(ahc, SCB_NEXT);
5791 next = ahc_inb(ahc, SCB_NEXT);
5795 ahc_outb(ahc, SCBPTR, active_scb);
5800 * Remove an SCB from the on chip list of disconnected transactions.
5801 * This is empty/unused if we are not performing SCB paging.
5804 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5808 ahc_outb(ahc, SCBPTR, scbptr);
5809 next = ahc_inb(ahc, SCB_NEXT);
5811 ahc_outb(ahc, SCB_CONTROL, 0);
5813 ahc_add_curscb_to_free_list(ahc);
5815 if (prev != SCB_LIST_NULL) {
5816 ahc_outb(ahc, SCBPTR, prev);
5817 ahc_outb(ahc, SCB_NEXT, next);
5819 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5825 * Add the SCB as selected by SCBPTR onto the on chip list of
5826 * free hardware SCBs. This list is empty/unused if we are not
5827 * performing SCB paging.
5830 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5833 * Invalidate the tag so that our abort
5834 * routines don't think it's active.
5836 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5838 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5839 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5840 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5845 * Manipulate the waiting for selection list and return the
5846 * scb that follows the one that we remove.
5849 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5854 * Select the SCB we want to abort and
5855 * pull the next pointer out of it.
5857 curscb = ahc_inb(ahc, SCBPTR);
5858 ahc_outb(ahc, SCBPTR, scbpos);
5859 next = ahc_inb(ahc, SCB_NEXT);
5861 /* Clear the necessary fields */
5862 ahc_outb(ahc, SCB_CONTROL, 0);
5864 ahc_add_curscb_to_free_list(ahc);
5866 /* update the waiting list */
5867 if (prev == SCB_LIST_NULL) {
5868 /* First in the list */
5869 ahc_outb(ahc, WAITING_SCBH, next);
5872 * Ensure we aren't attempting to perform
5873 * selection for this entry.
5875 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5878 * Select the scb that pointed to us
5879 * and update its next pointer.
5881 ahc_outb(ahc, SCBPTR, prev);
5882 ahc_outb(ahc, SCB_NEXT, next);
5886 * Point us back at the original scb position.
5888 ahc_outb(ahc, SCBPTR, curscb);
5892 /******************************** Error Handling ******************************/
5894 * Abort all SCBs that match the given description (target/channel/lun/tag),
5895 * setting their status to the passed in status if the status has not already
5896 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5897 * is paused before it is called.
5900 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5901 int lun, u_int tag, role_t role, uint32_t status)
5904 struct scb *scbp_next;
5914 * Don't attempt to run any queued untagged transactions
5915 * until we are done with the abort process.
5917 ahc_freeze_untagged_queues(ahc);
5919 /* restore this when we're done */
5920 active_scb = ahc_inb(ahc, SCBPTR);
5922 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5923 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5926 * Clean out the busy target table for any untagged commands.
5930 if (target != CAM_TARGET_WILDCARD) {
5937 if (lun == CAM_LUN_WILDCARD) {
5940 * Unless we are using an SCB based
5941 * busy targets table, there is only
5942 * one table entry for all luns of
5947 if ((ahc->flags & AHC_SCB_BTT) != 0)
5948 maxlun = AHC_NUM_LUNS;
5954 if (role != ROLE_TARGET) {
5955 for (;i < maxtarget; i++) {
5956 for (j = minlun;j < maxlun; j++) {
5960 tcl = BUILD_TCL(i << 4, j);
5961 scbid = ahc_index_busy_tcl(ahc, tcl);
5962 scbp = ahc_lookup_scb(ahc, scbid);
5964 || ahc_match_scb(ahc, scbp, target, channel,
5965 lun, tag, role) == 0)
5967 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5972 * Go through the disconnected list and remove any entries we
5973 * have queued for completion, 0'ing their control byte too.
5974 * We save the active SCB and restore it ourselves, so there
5975 * is no reason for this search to restore it too.
5977 ahc_search_disc_list(ahc, target, channel, lun, tag,
5978 /*stop_on_first*/FALSE, /*remove*/TRUE,
5979 /*save_state*/FALSE);
5983 * Go through the hardware SCB array looking for commands that
5984 * were active but not on any list. In some cases, these remnants
5985 * might not still have mappings in the scbindex array (e.g. unexpected
5986 * bus free with the same scb queued for an abort). Don't hold this
5989 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5992 ahc_outb(ahc, SCBPTR, i);
5993 scbid = ahc_inb(ahc, SCB_TAG);
5994 scbp = ahc_lookup_scb(ahc, scbid);
5995 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5997 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5998 ahc_add_curscb_to_free_list(ahc);
6002 * Go through the pending CCB list and look for
6003 * commands for this target that are still active.
6004 * These are other tagged commands that were
6005 * disconnected when the reset occurred.
6007 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6008 while (scbp_next != NULL) {
6010 scbp_next = LIST_NEXT(scbp, pending_links);
6011 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6014 ostat = aic_get_transaction_status(scbp);
6015 if (ostat == CAM_REQ_INPROG)
6016 aic_set_transaction_status(scbp, status);
6017 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
6018 aic_freeze_scb(scbp);
6019 if ((scbp->flags & SCB_ACTIVE) == 0)
6020 printf("Inactive SCB on pending list\n");
6021 ahc_done(ahc, scbp);
6025 ahc_outb(ahc, SCBPTR, active_scb);
6026 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6027 ahc_release_untagged_queues(ahc);
6032 ahc_reset_current_bus(struct ahc_softc *ahc)
6036 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6037 scsiseq = ahc_inb(ahc, SCSISEQ);
6038 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6039 ahc_flush_device_writes(ahc);
6040 aic_delay(AHC_BUSRESET_DELAY);
6041 /* Turn off the bus reset */
6042 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6044 ahc_clear_intstat(ahc);
6046 /* Re-enable reset interrupts */
6047 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6051 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6053 struct ahc_devinfo devinfo;
6054 u_int initiator, target, max_scsiid;
6062 ahc->pending_device = NULL;
6064 ahc_compile_devinfo(&devinfo,
6065 CAM_TARGET_WILDCARD,
6066 CAM_TARGET_WILDCARD,
6068 channel, ROLE_UNKNOWN);
6071 /* Make sure the sequencer is in a safe location. */
6072 ahc_clear_critical_section(ahc);
6075 * Run our command complete fifos to ensure that we perform
6076 * completion processing on any commands that 'completed'
6077 * before the reset occurred.
6079 ahc_run_qoutfifo(ahc);
6080 #ifdef AHC_TARGET_MODE
6082 * XXX - In Twin mode, the tqinfifo may have commands
6083 * for an unaffected channel in it. However, if
6084 * we have run out of ATIO resources to drain that
6085 * queue, we may not get them all out here. Further,
6086 * the blocked transactions for the reset channel
6087 * should just be killed off, irrespecitve of whether
6088 * we are blocked on ATIO resources. Write a routine
6089 * to compact the tqinfifo appropriately.
6091 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6092 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6097 * Reset the bus if we are initiating this reset
6099 sblkctl = ahc_inb(ahc, SBLKCTL);
6101 if ((ahc->features & AHC_TWIN) != 0
6102 && ((sblkctl & SELBUSB) != 0))
6104 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6105 if (cur_channel != channel) {
6106 /* Case 1: Command for another bus is active
6107 * Stealthily reset the other bus without
6108 * upsetting the current bus.
6110 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6111 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6112 #ifdef AHC_TARGET_MODE
6114 * Bus resets clear ENSELI, so we cannot
6115 * defer re-enabling bus reset interrupts
6116 * if we are in target mode.
6118 if ((ahc->flags & AHC_TARGETROLE) != 0)
6119 simode1 |= ENSCSIRST;
6121 ahc_outb(ahc, SIMODE1, simode1);
6123 ahc_reset_current_bus(ahc);
6124 ahc_clear_intstat(ahc);
6125 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6126 ahc_outb(ahc, SBLKCTL, sblkctl);
6127 restart_needed = FALSE;
6129 /* Case 2: A command from this bus is active or we're idle */
6130 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6131 #ifdef AHC_TARGET_MODE
6133 * Bus resets clear ENSELI, so we cannot
6134 * defer re-enabling bus reset interrupts
6135 * if we are in target mode.
6137 if ((ahc->flags & AHC_TARGETROLE) != 0)
6138 simode1 |= ENSCSIRST;
6140 ahc_outb(ahc, SIMODE1, simode1);
6142 ahc_reset_current_bus(ahc);
6143 ahc_clear_intstat(ahc);
6144 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6145 restart_needed = TRUE;
6149 * Clean up all the state information for the
6150 * pending transactions on this bus.
6152 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6153 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6154 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6156 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6158 #ifdef AHC_TARGET_MODE
6160 * Send an immediate notify ccb to all target more peripheral
6161 * drivers affected by this action.
6163 for (target = 0; target <= max_scsiid; target++) {
6164 struct ahc_tmode_tstate* tstate;
6167 tstate = ahc->enabled_targets[target];
6170 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6171 struct ahc_tmode_lstate* lstate;
6173 lstate = tstate->enabled_luns[lun];
6177 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6178 EVENT_TYPE_BUS_RESET, /*arg*/0);
6179 ahc_send_lstate_events(ahc, lstate);
6183 /* Notify the XPT that a bus reset occurred */
6184 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6185 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6188 * Revert to async/narrow transfers until we renegotiate.
6190 for (target = 0; target <= max_scsiid; target++) {
6192 if (ahc->enabled_targets[target] == NULL)
6194 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6195 struct ahc_devinfo devinfo;
6197 ahc_compile_devinfo(&devinfo, target, initiator,
6199 channel, ROLE_UNKNOWN);
6200 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6201 AHC_TRANS_CUR, /*paused*/TRUE);
6202 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6203 /*period*/0, /*offset*/0,
6204 /*ppr_options*/0, AHC_TRANS_CUR,
6217 /***************************** Residual Processing ****************************/
6219 * Calculate the residual for a just completed SCB.
6222 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6224 struct hardware_scb *hscb;
6225 struct status_pkt *spkt;
6227 uint32_t resid_sgptr;
6233 * SG_RESID_VALID clear in sgptr.
6234 * 2) Transferless command
6235 * 3) Never performed any transfers.
6236 * sgptr has SG_FULL_RESID set.
6237 * 4) No residual but target did not
6238 * save data pointers after the
6239 * last transfer, so sgptr was
6241 * 5) We have a partial residual.
6242 * Use residual_sgptr to determine
6247 sgptr = aic_le32toh(hscb->sgptr);
6248 if ((sgptr & SG_RESID_VALID) == 0)
6251 sgptr &= ~SG_RESID_VALID;
6253 if ((sgptr & SG_LIST_NULL) != 0)
6257 spkt = &hscb->shared_data.status;
6258 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6259 if ((sgptr & SG_FULL_RESID) != 0) {
6261 resid = aic_get_transfer_length(scb);
6262 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6265 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6266 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6270 struct ahc_dma_seg *sg;
6273 * Remainder of the SG where the transfer
6276 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6277 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6279 /* The residual sg_ptr always points to the next sg */
6283 * Add up the contents of all residual
6284 * SG segments that are after the SG where
6285 * the transfer stopped.
6287 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6289 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6292 if ((scb->flags & SCB_SENSE) == 0)
6293 aic_set_residual(scb, resid);
6295 aic_set_sense_residual(scb, resid);
6298 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6299 ahc_print_path(ahc, scb);
6300 printf("Handled %sResidual of %d bytes\n",
6301 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6306 /******************************* Target Mode **********************************/
6307 #ifdef AHC_TARGET_MODE
6309 * Add a target mode event to this lun's queue
6312 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6313 u_int initiator_id, u_int event_type, u_int event_arg)
6315 struct ahc_tmode_event *event;
6318 xpt_freeze_devq(lstate->path, /*count*/1);
6319 if (lstate->event_w_idx >= lstate->event_r_idx)
6320 pending = lstate->event_w_idx - lstate->event_r_idx;
6322 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6323 - (lstate->event_r_idx - lstate->event_w_idx);
6325 if (event_type == EVENT_TYPE_BUS_RESET
6326 || event_type == MSG_BUS_DEV_RESET) {
6328 * Any earlier events are irrelevant, so reset our buffer.
6329 * This has the effect of allowing us to deal with reset
6330 * floods (an external device holding down the reset line)
6331 * without losing the event that is really interesting.
6333 lstate->event_r_idx = 0;
6334 lstate->event_w_idx = 0;
6335 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6338 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6339 xpt_print_path(lstate->path);
6340 printf("immediate event %x:%x lost\n",
6341 lstate->event_buffer[lstate->event_r_idx].event_type,
6342 lstate->event_buffer[lstate->event_r_idx].event_arg);
6343 lstate->event_r_idx++;
6344 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6345 lstate->event_r_idx = 0;
6346 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6349 event = &lstate->event_buffer[lstate->event_w_idx];
6350 event->initiator_id = initiator_id;
6351 event->event_type = event_type;
6352 event->event_arg = event_arg;
6353 lstate->event_w_idx++;
6354 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6355 lstate->event_w_idx = 0;
6359 * Send any target mode events queued up waiting
6360 * for immediate notify resources.
6363 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6365 struct ccb_hdr *ccbh;
6366 struct ccb_immediate_notify *inot;
6368 while (lstate->event_r_idx != lstate->event_w_idx
6369 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6370 struct ahc_tmode_event *event;
6372 event = &lstate->event_buffer[lstate->event_r_idx];
6373 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6374 inot = (struct ccb_immediate_notify *)ccbh;
6375 switch (event->event_type) {
6376 case EVENT_TYPE_BUS_RESET:
6377 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6380 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6381 inot->arg = event->event_type;
6382 inot->seq_id = event->event_arg;
6385 inot->initiator_id = event->initiator_id;
6386 xpt_done((union ccb *)inot);
6387 lstate->event_r_idx++;
6388 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6389 lstate->event_r_idx = 0;
6394 /******************** Sequencer Program Patching/Download *********************/
6398 ahc_dumpseq(struct ahc_softc* ahc)
6402 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6403 ahc_outb(ahc, SEQADDR0, 0);
6404 ahc_outb(ahc, SEQADDR1, 0);
6405 for (i = 0; i < ahc->instruction_ram_size; i++) {
6406 uint8_t ins_bytes[4];
6408 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6409 printf("0x%08x\n", ins_bytes[0] << 24
6410 | ins_bytes[1] << 16
6418 ahc_loadseq(struct ahc_softc *ahc)
6420 struct cs cs_table[num_critical_sections];
6421 u_int begin_set[num_critical_sections];
6422 u_int end_set[num_critical_sections];
6423 struct patch *cur_patch;
6428 u_int sg_prefetch_cnt;
6430 uint8_t download_consts[7];
6433 * Start out with 0 critical sections
6434 * that apply to this firmware load.
6438 memset(begin_set, 0, sizeof(begin_set));
6439 memset(end_set, 0, sizeof(end_set));
6441 /* Setup downloadable constant table */
6442 download_consts[QOUTFIFO_OFFSET] = 0;
6443 if (ahc->targetcmds != NULL)
6444 download_consts[QOUTFIFO_OFFSET] += 32;
6445 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6446 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6447 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6448 sg_prefetch_cnt = ahc->pci_cachesize;
6449 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6450 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6451 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6452 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6453 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6455 cur_patch = patches;
6458 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6459 ahc_outb(ahc, SEQADDR0, 0);
6460 ahc_outb(ahc, SEQADDR1, 0);
6462 for (i = 0; i < sizeof(seqprog)/4; i++) {
6463 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6465 * Don't download this instruction as it
6466 * is in a patch that was removed.
6471 if (downloaded == ahc->instruction_ram_size) {
6473 * We're about to exceed the instruction
6474 * storage capacity for this chip. Fail
6477 printf("\n%s: Program too large for instruction memory "
6478 "size of %d!\n", ahc_name(ahc),
6479 ahc->instruction_ram_size);
6484 * Move through the CS table until we find a CS
6485 * that might apply to this instruction.
6487 for (; cur_cs < num_critical_sections; cur_cs++) {
6488 if (critical_sections[cur_cs].end <= i) {
6489 if (begin_set[cs_count] == TRUE
6490 && end_set[cs_count] == FALSE) {
6491 cs_table[cs_count].end = downloaded;
6492 end_set[cs_count] = TRUE;
6497 if (critical_sections[cur_cs].begin <= i
6498 && begin_set[cs_count] == FALSE) {
6499 cs_table[cs_count].begin = downloaded;
6500 begin_set[cs_count] = TRUE;
6504 ahc_download_instr(ahc, i, download_consts);
6508 ahc->num_critical_sections = cs_count;
6509 if (cs_count != 0) {
6511 cs_count *= sizeof(struct cs);
6512 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6513 if (ahc->critical_sections == NULL)
6514 panic("ahc_loadseq: Could not malloc");
6515 memcpy(ahc->critical_sections, cs_table, cs_count);
6517 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6520 printf(" %d instructions downloaded\n", downloaded);
6521 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6522 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6528 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6529 u_int start_instr, u_int *skip_addr)
6531 struct patch *cur_patch;
6532 struct patch *last_patch;
6535 num_patches = sizeof(patches)/sizeof(struct patch);
6536 last_patch = &patches[num_patches];
6537 cur_patch = *start_patch;
6539 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6541 if (cur_patch->patch_func(ahc) == 0) {
6543 /* Start rejecting code */
6544 *skip_addr = start_instr + cur_patch->skip_instr;
6545 cur_patch += cur_patch->skip_patch;
6547 /* Accepted this patch. Advance to the next
6548 * one and wait for our instruction pointer to
6555 *start_patch = cur_patch;
6556 if (start_instr < *skip_addr)
6557 /* Still skipping */
6564 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6566 union ins_formats instr;
6567 struct ins_format1 *fmt1_ins;
6568 struct ins_format3 *fmt3_ins;
6572 * The firmware is always compiled into a little endian format.
6574 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6576 fmt1_ins = &instr.format1;
6579 /* Pull the opcode */
6580 opcode = instr.format1.opcode;
6591 struct patch *cur_patch;
6597 fmt3_ins = &instr.format3;
6599 address = fmt3_ins->address;
6600 cur_patch = patches;
6603 for (i = 0; i < address;) {
6605 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6607 if (skip_addr > i) {
6610 end_addr = MIN(address, skip_addr);
6611 address_offset += end_addr - i;
6617 address -= address_offset;
6618 fmt3_ins->address = address;
6627 if (fmt1_ins->parity != 0) {
6628 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6630 fmt1_ins->parity = 0;
6631 if ((ahc->features & AHC_CMD_CHAN) == 0
6632 && opcode == AIC_OP_BMOV) {
6634 * Block move was added at the same time
6635 * as the command channel. Verify that
6636 * this is only a move of a single element
6637 * and convert the BMOV to a MOV
6638 * (AND with an immediate of FF).
6640 if (fmt1_ins->immediate != 1)
6641 panic("%s: BMOV not supported\n",
6643 fmt1_ins->opcode = AIC_OP_AND;
6644 fmt1_ins->immediate = 0xff;
6648 if ((ahc->features & AHC_ULTRA2) != 0) {
6651 /* Calculate odd parity for the instruction */
6652 for (i = 0, count = 0; i < 31; i++) {
6656 if ((instr.integer & mask) != 0)
6659 if ((count & 0x01) == 0)
6660 instr.format1.parity = 1;
6662 /* Compress the instruction for older sequencers */
6663 if (fmt3_ins != NULL) {
6666 | (fmt3_ins->source << 8)
6667 | (fmt3_ins->address << 16)
6668 | (fmt3_ins->opcode << 25);
6672 | (fmt1_ins->source << 8)
6673 | (fmt1_ins->destination << 16)
6674 | (fmt1_ins->ret << 24)
6675 | (fmt1_ins->opcode << 25);
6678 /* The sequencer is a little endian cpu */
6679 instr.integer = aic_htole32(instr.integer);
6680 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6683 panic("Unknown opcode encountered in seq program");
6689 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6690 const char *name, u_int address, u_int value,
6691 u_int *cur_column, u_int wrap_point)
6697 if (cur_column == NULL) {
6699 cur_column = &dummy_column;
6702 if (*cur_column >= wrap_point) {
6706 printed = printf("%s[0x%x]", name, value);
6707 if (table == NULL) {
6708 printed += printf(" ");
6709 *cur_column += printed;
6713 while (printed_mask != 0xFF) {
6716 for (entry = 0; entry < num_entries; entry++) {
6717 if (((value & table[entry].mask)
6718 != table[entry].value)
6719 || ((printed_mask & table[entry].mask)
6720 == table[entry].mask))
6723 printed += printf("%s%s",
6724 printed_mask == 0 ? ":(" : "|",
6726 printed_mask |= table[entry].mask;
6730 if (entry >= num_entries)
6733 if (printed_mask != 0)
6734 printed += printf(") ");
6736 printed += printf(" ");
6737 if (cur_column != NULL)
6738 *cur_column += printed;
6743 ahc_dump_card_state(struct ahc_softc *ahc)
6746 struct scb_tailq *untagged_q;
6757 uint8_t saved_scbptr;
6759 if (ahc_is_paused(ahc)) {
6766 saved_scbptr = ahc_inb(ahc, SCBPTR);
6767 last_phase = ahc_inb(ahc, LASTPHASE);
6768 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6769 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6770 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6771 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6773 printf("Card was paused\n");
6774 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6775 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6776 ahc_inb(ahc, ARG_2));
6777 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6778 ahc_inb(ahc, SCBPTR));
6780 if ((ahc->features & AHC_DT) != 0)
6781 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6782 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6783 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6784 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6785 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6786 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6787 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6788 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6789 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6790 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6791 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6792 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6793 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6794 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6795 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6796 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6797 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6798 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6799 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6803 for (i = 0; i < STACK_SIZE; i++)
6804 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6805 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6806 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6807 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6809 printf("QINFIFO entries: ");
6810 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6811 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6812 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6814 qinpos = ahc_inb(ahc, QINPOS);
6815 qintail = ahc->qinfifonext;
6816 while (qinpos != qintail) {
6817 printf("%d ", ahc->qinfifo[qinpos]);
6822 printf("Waiting Queue entries: ");
6823 scb_index = ahc_inb(ahc, WAITING_SCBH);
6825 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6826 ahc_outb(ahc, SCBPTR, scb_index);
6827 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6828 scb_index = ahc_inb(ahc, SCB_NEXT);
6832 printf("Disconnected Queue entries: ");
6833 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6835 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6836 ahc_outb(ahc, SCBPTR, scb_index);
6837 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6838 scb_index = ahc_inb(ahc, SCB_NEXT);
6842 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6843 printf("QOUTFIFO entries: ");
6844 qoutpos = ahc->qoutfifonext;
6846 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6847 printf("%d ", ahc->qoutfifo[qoutpos]);
6852 printf("Sequencer Free SCB List: ");
6853 scb_index = ahc_inb(ahc, FREE_SCBH);
6855 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6856 ahc_outb(ahc, SCBPTR, scb_index);
6857 printf("%d ", scb_index);
6858 scb_index = ahc_inb(ahc, SCB_NEXT);
6862 printf("Sequencer SCB Info: ");
6863 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6864 ahc_outb(ahc, SCBPTR, i);
6865 cur_col = printf("\n%3d ", i);
6867 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6868 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6869 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6870 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6874 printf("Pending list: ");
6876 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6879 cur_col = printf("\n%3d ", scb->hscb->tag);
6880 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6881 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6882 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6883 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6884 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6886 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6888 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6894 printf("Kernel Free SCB list: ");
6896 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6899 printf("%d ", scb->hscb->tag);
6903 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6904 for (target = 0; target <= maxtarget; target++) {
6905 untagged_q = &ahc->untagged_queues[target];
6906 if (TAILQ_FIRST(untagged_q) == NULL)
6908 printf("Untagged Q(%d): ", target);
6910 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6913 printf("%d ", scb->hscb->tag);
6918 ahc_platform_dump_card_state(ahc);
6919 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6920 ahc_outb(ahc, SCBPTR, saved_scbptr);
6925 /*************************** Timeout Handling *********************************/
6927 ahc_timeout(struct scb *scb)
6929 struct ahc_softc *ahc;
6931 ahc = scb->ahc_softc;
6932 if ((scb->flags & SCB_ACTIVE) != 0) {
6933 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6934 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6936 scb->flags |= SCB_TIMEDOUT;
6938 ahc_wakeup_recovery_thread(ahc);
6943 * Re-schedule a timeout for the passed in SCB if we determine that some
6944 * other SCB is in the process of recovery or an SCB with a longer
6945 * timeout is still pending. Limit our search to just "other_scb"
6946 * if it is non-NULL.
6949 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6950 struct scb *other_scb)
6955 ahc_print_path(ahc, scb);
6956 printf("Other SCB Timeout%s",
6957 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6958 ? " again\n" : "\n");
6960 newtimeout = aic_get_timeout(scb);
6961 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6963 if (other_scb != NULL) {
6964 if ((other_scb->flags
6965 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6966 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6968 newtimeout = MAX(aic_get_timeout(other_scb),
6972 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6973 if ((other_scb->flags
6974 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6975 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6978 MAX(aic_get_timeout(other_scb),
6985 aic_scb_timer_reset(scb, newtimeout);
6987 ahc_print_path(ahc, scb);
6988 printf("No other SCB worth waiting for...\n");
6991 return (found != 0);
6995 * ahc_recover_commands determines if any of the commands that have currently
6996 * timedout are the root cause for this timeout. Innocent commands are given
6997 * a new timeout while we wait for the command executing on the bus to timeout.
6998 * This routine is invoked from a thread context so we are allowed to sleep.
6999 * Our lock is not held on entry.
7002 ahc_recover_commands(struct ahc_softc *ahc)
7010 * Pause the controller and manually flush any
7011 * commands that have just completed but that our
7012 * interrupt handler has yet to see.
7014 ahc_pause_and_flushwork(ahc);
7016 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
7018 * The timedout commands have already
7019 * completed. This typically means
7020 * that either the timeout value was on
7021 * the hairy edge of what the device
7022 * requires or - more likely - interrupts
7023 * are not happening.
7025 printf("%s: Timedout SCBs already complete. "
7026 "Interrupts may not be functioning.\n", ahc_name(ahc));
7032 printf("%s: Recovery Initiated\n", ahc_name(ahc));
7033 ahc_dump_card_state(ahc);
7035 last_phase = ahc_inb(ahc, LASTPHASE);
7036 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7037 u_int active_scb_index;
7044 target = SCB_GET_TARGET(ahc, scb);
7045 channel = SCB_GET_CHANNEL(ahc, scb);
7046 lun = SCB_GET_LUN(scb);
7048 ahc_print_path(ahc, scb);
7049 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7050 if (scb->sg_count > 0) {
7051 for (i = 0; i < scb->sg_count; i++) {
7052 printf("sg[%d] - Addr 0x%x : Length %d\n",
7054 scb->sg_list[i].addr,
7055 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7058 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7060 * Been down this road before.
7061 * Do a full bus reset.
7063 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7065 found = ahc_reset_channel(ahc, channel,
7066 /*Initiate Reset*/TRUE);
7067 printf("%s: Issued Channel %c Bus Reset. "
7068 "%d SCBs aborted\n", ahc_name(ahc), channel,
7074 * Remove the command from the timedout list in
7075 * preparation for requeing it.
7077 LIST_REMOVE(scb, timedout_links);
7078 scb->flags &= ~SCB_TIMEDOUT;
7081 * If we are a target, transition to bus free and report
7084 * The target/initiator that is holding up the bus may not
7085 * be the same as the one that triggered this timeout
7086 * (different commands have different timeout lengths).
7087 * If the bus is idle and we are actiing as the initiator
7088 * for this request, queue a BDR message to the timed out
7089 * target. Otherwise, if the timed out transaction is
7091 * Initiator transaction:
7092 * Stuff the message buffer with a BDR message and assert
7093 * ATN in the hopes that the target will let go of the bus
7094 * and go to the mesgout phase. If this fails, we'll
7095 * get another timeout 2 seconds later which will attempt
7098 * Target transaction:
7099 * Transition to BUS FREE and report the error.
7100 * It's good to be the target!
7102 saved_scbptr = ahc_inb(ahc, SCBPTR);
7103 active_scb_index = ahc_inb(ahc, SCB_TAG);
7105 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7106 && (active_scb_index < ahc->scb_data->numscbs)) {
7107 struct scb *active_scb;
7110 * If the active SCB is not us, assume that
7111 * the active SCB has a longer timeout than
7112 * the timedout SCB, and wait for the active
7115 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7116 if (active_scb != scb) {
7117 if (ahc_other_scb_timeout(ahc, scb,
7124 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7127 * Send back any queued up transactions
7128 * and properly record the error condition.
7130 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7131 SCB_GET_CHANNEL(ahc, scb),
7137 /* Will clear us from the bus */
7142 ahc_set_recoveryscb(ahc, active_scb);
7143 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7144 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7145 ahc_print_path(ahc, active_scb);
7146 printf("BDR message in message buffer\n");
7147 active_scb->flags |= SCB_DEVICE_RESET;
7148 aic_scb_timer_reset(scb, 2 * 1000);
7149 } else if (last_phase != P_BUSFREE
7150 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7152 * SCB is not identified, there
7153 * is no pending REQ, and the sequencer
7154 * has not seen a busfree. Looks like
7155 * a stuck connection waiting to
7156 * go busfree. Reset the bus.
7158 printf("%s: Connection stuck awaiting busfree or "
7159 "Identify Msg.\n", ahc_name(ahc));
7164 if (last_phase != P_BUSFREE
7165 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7166 /* Hung target selection. Goto busfree */
7167 printf("%s: Hung target selection\n",
7173 /* XXX Shouldn't panic. Just punt instead? */
7174 if ((scb->flags & SCB_TARGET_SCB) != 0)
7175 panic("Timed-out target SCB but bus idle");
7177 if (ahc_search_qinfifo(ahc, target, channel, lun,
7178 scb->hscb->tag, ROLE_INITIATOR,
7179 /*status*/0, SEARCH_COUNT) > 0) {
7180 disconnected = FALSE;
7182 disconnected = TRUE;
7187 ahc_set_recoveryscb(ahc, scb);
7189 * Actually re-queue this SCB in an attempt
7190 * to select the device before it reconnects.
7191 * In either case (selection or reselection),
7192 * we will now issue a target reset to the
7195 * Set the MK_MESSAGE control bit indicating
7196 * that we desire to send a message. We
7197 * also set the disconnected flag since
7198 * in the paging case there is no guarantee
7199 * that our SCB control byte matches the
7200 * version on the card. We don't want the
7201 * sequencer to abort the command thinking
7202 * an unsolicited reselection occurred.
7204 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7205 scb->flags |= SCB_DEVICE_RESET;
7208 * Remove any cached copy of this SCB in the
7209 * disconnected list in preparation for the
7210 * queuing of our abort SCB. We use the
7211 * same element in the SCB, SCB_NEXT, for
7212 * both the qinfifo and the disconnected list.
7214 ahc_search_disc_list(ahc, target, channel,
7215 lun, scb->hscb->tag,
7216 /*stop_on_first*/TRUE,
7218 /*save_state*/FALSE);
7221 * In the non-paging case, the sequencer will
7222 * never re-reference the in-core SCB.
7223 * To make sure we are notified during
7224 * reslection, set the MK_MESSAGE flag in
7225 * the card's copy of the SCB.
7227 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7228 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7229 ahc_outb(ahc, SCB_CONTROL,
7230 ahc_inb(ahc, SCB_CONTROL)
7235 * Clear out any entries in the QINFIFO first
7236 * so we are the next SCB for this target
7239 ahc_search_qinfifo(ahc,
7240 SCB_GET_TARGET(ahc, scb),
7241 channel, SCB_GET_LUN(scb),
7246 ahc_print_path(ahc, scb);
7247 printf("Queuing a BDR SCB\n");
7248 ahc_qinfifo_requeue_tail(ahc, scb);
7249 ahc_outb(ahc, SCBPTR, saved_scbptr);
7250 aic_scb_timer_reset(scb, 2 * 1000);
7252 /* Go "immediately" to the bus reset */
7253 /* This shouldn't happen */
7254 ahc_set_recoveryscb(ahc, scb);
7255 ahc_print_path(ahc, scb);
7256 printf("SCB %d: Immediate reset. "
7257 "Flags = 0x%x\n", scb->hscb->tag,
7266 * Any remaining SCBs were not the "culprit", so remove
7267 * them from the timeout list. The timer for these commands
7268 * will be reset once the recovery SCB completes.
7270 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7272 LIST_REMOVE(scb, timedout_links);
7273 scb->flags &= ~SCB_TIMEDOUT;
7282 /************************* Target Mode ****************************************/
7283 #ifdef AHC_TARGET_MODE
7285 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7286 struct ahc_tmode_tstate **tstate,
7287 struct ahc_tmode_lstate **lstate,
7288 int notfound_failure)
7291 if ((ahc->features & AHC_TARGETMODE) == 0)
7292 return (CAM_REQ_INVALID);
7295 * Handle the 'black hole' device that sucks up
7296 * requests to unattached luns on enabled targets.
7298 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7299 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7301 *lstate = ahc->black_hole;
7305 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7306 if (ccb->ccb_h.target_id > max_id)
7307 return (CAM_TID_INVALID);
7309 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7310 return (CAM_LUN_INVALID);
7312 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7314 if (*tstate != NULL)
7316 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7319 if (notfound_failure != 0 && *lstate == NULL)
7320 return (CAM_PATH_INVALID);
7322 return (CAM_REQ_CMP);
7326 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7328 struct ahc_tmode_tstate *tstate;
7329 struct ahc_tmode_lstate *lstate;
7330 struct ccb_en_lun *cel;
7339 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7340 /*notfound_failure*/FALSE);
7342 if (status != CAM_REQ_CMP) {
7343 ccb->ccb_h.status = status;
7347 if (cam_sim_bus(sim) == 0)
7348 our_id = ahc->our_id;
7350 our_id = ahc->our_id_b;
7352 if (ccb->ccb_h.target_id != our_id
7353 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7355 * our_id represents our initiator ID, or
7356 * the ID of the first target to have an
7357 * enabled lun in target mode. There are
7358 * two cases that may preclude enabling a
7359 * target id other than our_id.
7361 * o our_id is for an active initiator role.
7362 * Since the hardware does not support
7363 * reselections to the initiator role at
7364 * anything other than our_id, and our_id
7365 * is used by the hardware to indicate the
7366 * ID to use for both select-out and
7367 * reselect-out operations, the only target
7368 * ID we can support in this mode is our_id.
7370 * o The MULTARGID feature is not available and
7371 * a previous target mode ID has been enabled.
7373 if ((ahc->features & AHC_MULTIROLE) != 0) {
7375 if ((ahc->features & AHC_MULTI_TID) != 0
7376 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7378 * Only allow additional targets if
7379 * the initiator role is disabled.
7380 * The hardware cannot handle a re-select-in
7381 * on the initiator id during a re-select-out
7382 * on a different target id.
7384 status = CAM_TID_INVALID;
7385 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7386 || ahc->enabled_luns > 0) {
7388 * Only allow our target id to change
7389 * if the initiator role is not configured
7390 * and there are no enabled luns which
7391 * are attached to the currently registered
7394 status = CAM_TID_INVALID;
7396 } else if ((ahc->features & AHC_MULTI_TID) == 0
7397 && ahc->enabled_luns > 0) {
7399 status = CAM_TID_INVALID;
7403 if (status != CAM_REQ_CMP) {
7404 ccb->ccb_h.status = status;
7409 * We now have an id that is valid.
7410 * If we aren't in target mode, switch modes.
7412 if ((ahc->flags & AHC_TARGETROLE) == 0
7413 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7414 ahc_flag saved_flags;
7416 printf("Configuring Target Mode\n");
7417 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7418 ccb->ccb_h.status = CAM_BUSY;
7421 saved_flags = ahc->flags;
7422 ahc->flags |= AHC_TARGETROLE;
7423 if ((ahc->features & AHC_MULTIROLE) == 0)
7424 ahc->flags &= ~AHC_INITIATORROLE;
7426 error = ahc_loadseq(ahc);
7429 * Restore original configuration and notify
7430 * the caller that we cannot support target mode.
7431 * Since the adapter started out in this
7432 * configuration, the firmware load will succeed,
7433 * so there is no point in checking ahc_loadseq's
7436 ahc->flags = saved_flags;
7437 (void)ahc_loadseq(ahc);
7439 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7445 target = ccb->ccb_h.target_id;
7446 lun = ccb->ccb_h.target_lun;
7447 channel = SIM_CHANNEL(ahc, sim);
7448 target_mask = 0x01 << target;
7452 if (cel->enable != 0) {
7455 /* Are we already enabled?? */
7456 if (lstate != NULL) {
7457 xpt_print_path(ccb->ccb_h.path);
7458 printf("Lun already enabled\n");
7459 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7463 if (cel->grp6_len != 0
7464 || cel->grp7_len != 0) {
7466 * Don't (yet?) support vendor
7467 * specific commands.
7469 ccb->ccb_h.status = CAM_REQ_INVALID;
7470 printf("Non-zero Group Codes\n");
7476 * Setup our data structures.
7478 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7479 tstate = ahc_alloc_tstate(ahc, target, channel);
7480 if (tstate == NULL) {
7481 xpt_print_path(ccb->ccb_h.path);
7482 printf("Couldn't allocate tstate\n");
7483 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7487 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7488 if (lstate == NULL) {
7489 xpt_print_path(ccb->ccb_h.path);
7490 printf("Couldn't allocate lstate\n");
7491 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7494 memset(lstate, 0, sizeof(*lstate));
7495 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7496 xpt_path_path_id(ccb->ccb_h.path),
7497 xpt_path_target_id(ccb->ccb_h.path),
7498 xpt_path_lun_id(ccb->ccb_h.path));
7499 if (status != CAM_REQ_CMP) {
7500 free(lstate, M_DEVBUF);
7501 xpt_print_path(ccb->ccb_h.path);
7502 printf("Couldn't allocate path\n");
7503 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7506 SLIST_INIT(&lstate->accept_tios);
7507 SLIST_INIT(&lstate->immed_notifies);
7509 if (target != CAM_TARGET_WILDCARD) {
7510 tstate->enabled_luns[lun] = lstate;
7511 ahc->enabled_luns++;
7513 if ((ahc->features & AHC_MULTI_TID) != 0) {
7516 targid_mask = ahc_inb(ahc, TARGID)
7517 | (ahc_inb(ahc, TARGID + 1) << 8);
7519 targid_mask |= target_mask;
7520 ahc_outb(ahc, TARGID, targid_mask);
7521 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7523 ahc_update_scsiid(ahc, targid_mask);
7528 channel = SIM_CHANNEL(ahc, sim);
7529 our_id = SIM_SCSI_ID(ahc, sim);
7532 * This can only happen if selections
7535 if (target != our_id) {
7540 sblkctl = ahc_inb(ahc, SBLKCTL);
7541 cur_channel = (sblkctl & SELBUSB)
7543 if ((ahc->features & AHC_TWIN) == 0)
7545 swap = cur_channel != channel;
7547 ahc->our_id = target;
7549 ahc->our_id_b = target;
7552 ahc_outb(ahc, SBLKCTL,
7555 ahc_outb(ahc, SCSIID, target);
7558 ahc_outb(ahc, SBLKCTL, sblkctl);
7562 ahc->black_hole = lstate;
7563 /* Allow select-in operations */
7564 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7565 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7567 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7568 scsiseq = ahc_inb(ahc, SCSISEQ);
7570 ahc_outb(ahc, SCSISEQ, scsiseq);
7573 ccb->ccb_h.status = CAM_REQ_CMP;
7574 xpt_print_path(ccb->ccb_h.path);
7575 printf("Lun now enabled for target mode\n");
7580 if (lstate == NULL) {
7581 ccb->ccb_h.status = CAM_LUN_INVALID;
7585 ccb->ccb_h.status = CAM_REQ_CMP;
7586 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7587 struct ccb_hdr *ccbh;
7589 ccbh = &scb->io_ctx->ccb_h;
7590 if (ccbh->func_code == XPT_CONT_TARGET_IO
7591 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7592 printf("CTIO pending\n");
7593 ccb->ccb_h.status = CAM_REQ_INVALID;
7598 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7599 printf("ATIOs pending\n");
7600 ccb->ccb_h.status = CAM_REQ_INVALID;
7603 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7604 printf("INOTs pending\n");
7605 ccb->ccb_h.status = CAM_REQ_INVALID;
7608 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7612 xpt_print_path(ccb->ccb_h.path);
7613 printf("Target mode disabled\n");
7614 xpt_free_path(lstate->path);
7615 free(lstate, M_DEVBUF);
7618 /* Can we clean up the target too? */
7619 if (target != CAM_TARGET_WILDCARD) {
7620 tstate->enabled_luns[lun] = NULL;
7621 ahc->enabled_luns--;
7622 for (empty = 1, i = 0; i < 8; i++)
7623 if (tstate->enabled_luns[i] != NULL) {
7629 ahc_free_tstate(ahc, target, channel,
7631 if (ahc->features & AHC_MULTI_TID) {
7634 targid_mask = ahc_inb(ahc, TARGID)
7635 | (ahc_inb(ahc, TARGID + 1)
7638 targid_mask &= ~target_mask;
7639 ahc_outb(ahc, TARGID, targid_mask);
7640 ahc_outb(ahc, TARGID+1,
7641 (targid_mask >> 8));
7642 ahc_update_scsiid(ahc, targid_mask);
7647 ahc->black_hole = NULL;
7650 * We can't allow selections without
7651 * our black hole device.
7655 if (ahc->enabled_luns == 0) {
7656 /* Disallow select-in */
7659 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7661 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7662 scsiseq = ahc_inb(ahc, SCSISEQ);
7664 ahc_outb(ahc, SCSISEQ, scsiseq);
7666 if ((ahc->features & AHC_MULTIROLE) == 0) {
7667 printf("Configuring Initiator Mode\n");
7668 ahc->flags &= ~AHC_TARGETROLE;
7669 ahc->flags |= AHC_INITIATORROLE;
7671 * Returning to a configuration that
7672 * fit previously will always succeed.
7674 (void)ahc_loadseq(ahc);
7677 * Unpaused. The extra unpause
7678 * that follows is harmless.
7687 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7692 if ((ahc->features & AHC_MULTI_TID) == 0)
7693 panic("ahc_update_scsiid called on non-multitid unit\n");
7696 * Since we will rely on the TARGID mask
7697 * for selection enables, ensure that OID
7698 * in SCSIID is not set to some other ID
7699 * that we don't want to allow selections on.
7701 if ((ahc->features & AHC_ULTRA2) != 0)
7702 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7704 scsiid = ahc_inb(ahc, SCSIID);
7705 scsiid_mask = 0x1 << (scsiid & OID);
7706 if ((targid_mask & scsiid_mask) == 0) {
7709 /* ffs counts from 1 */
7710 our_id = ffs(targid_mask);
7712 our_id = ahc->our_id;
7718 if ((ahc->features & AHC_ULTRA2) != 0)
7719 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7721 ahc_outb(ahc, SCSIID, scsiid);
7725 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7727 struct target_cmd *cmd;
7730 * If the card supports auto-access pause,
7731 * we can access the card directly regardless
7732 * of whether it is paused or not.
7734 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7737 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7738 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7741 * Only advance through the queue if we
7742 * have the resources to process the command.
7744 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7748 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7749 ahc->shared_data_dmamap,
7750 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7751 sizeof(struct target_cmd),
7752 BUS_DMASYNC_PREREAD);
7753 ahc->tqinfifonext++;
7756 * Lazily update our position in the target mode incoming
7757 * command queue as seen by the sequencer.
7759 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7760 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7763 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7764 hs_mailbox &= ~HOST_TQINPOS;
7765 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7766 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7770 ahc_outb(ahc, KERNEL_TQINPOS,
7771 ahc->tqinfifonext & HOST_TQINPOS);
7780 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7782 struct ahc_tmode_tstate *tstate;
7783 struct ahc_tmode_lstate *lstate;
7784 struct ccb_accept_tio *atio;
7790 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7791 target = SCSIID_OUR_ID(cmd->scsiid);
7792 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7795 tstate = ahc->enabled_targets[target];
7798 lstate = tstate->enabled_luns[lun];
7801 * Commands for disabled luns go to the black hole driver.
7804 lstate = ahc->black_hole;
7806 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7808 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7810 * Wait for more ATIOs from the peripheral driver for this lun.
7813 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7816 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7818 if (ahc_debug & AHC_SHOW_TQIN) {
7819 printf("Incoming command from %d for %d:%d%s\n",
7820 initiator, target, lun,
7821 lstate == ahc->black_hole ? "(Black Holed)" : "");
7824 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7826 if (lstate == ahc->black_hole) {
7827 /* Fill in the wildcards */
7828 atio->ccb_h.target_id = target;
7829 atio->ccb_h.target_lun = lun;
7833 * Package it up and send it off to
7834 * whomever has this lun enabled.
7836 atio->sense_len = 0;
7837 atio->init_id = initiator;
7838 if (byte[0] != 0xFF) {
7839 /* Tag was included */
7840 atio->tag_action = *byte++;
7841 atio->tag_id = *byte++;
7842 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
7844 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
7848 /* Okay. Now determine the cdb size based on the command code */
7849 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7865 /* Only copy the opcode. */
7867 printf("Reserved or VU command code type encountered\n");
7871 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7873 atio->ccb_h.status |= CAM_CDB_RECVD;
7875 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7877 * We weren't allowed to disconnect.
7878 * We're hanging on the bus until a
7879 * continue target I/O comes in response
7880 * to this accept tio.
7883 if (ahc_debug & AHC_SHOW_TQIN) {
7884 printf("Received Immediate Command %d:%d:%d - %p\n",
7885 initiator, target, lun, ahc->pending_device);
7888 ahc->pending_device = lstate;
7889 aic_freeze_ccb((union ccb *)atio);
7890 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7892 xpt_done((union ccb*)atio);