sys/dev/aic7xxx/aic7xxx.c

   1 /*-
   2  * Core routines and tables shareable across OS platforms.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  *
   6  * Copyright (c) 1994-2002 Justin T. Gibbs.
   7  * Copyright (c) 2000-2002 Adaptec Inc.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    substantially similar to the "NO WARRANTY" disclaimer below
  18  *    ("Disclaimer") and any redistribution must be conditioned upon
  19  *    including a substantially similar Disclaimer requirement for further
  20  *    binary redistribution.
  21  * 3. Neither the names of the above-listed copyright holders nor the names
  22  *    of any contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * Alternatively, this software may be distributed under the terms of the
  26  * GNU General Public License ("GPL") version 2 as published by the Free
  27  * Software Foundation.
  28  *
  29  * NO WARRANTY
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  38  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  39  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGES.
  41  *
  42  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
  43  */
  44
  45 #ifdef __linux__
  46 #include "aic7xxx_osm.h"
  47 #include "aic7xxx_inline.h"
  48 #include "aicasm/aicasm_insformat.h"
  49 #else
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52 #include <dev/aic7xxx/aic7xxx_osm.h>
  53 #include <dev/aic7xxx/aic7xxx_inline.h>
  54 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
  55 #endif
  56
  57 /****************************** Softc Data ************************************/
  58 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
  59
  60 /***************************** Lookup Tables **********************************/
  61 char *ahc_chip_names[] =
  62 {
  63         "NONE",
  64         "aic7770",
  65         "aic7850",
  66         "aic7855",
  67         "aic7859",
  68         "aic7860",
  69         "aic7870",
  70         "aic7880",
  71         "aic7895",
  72         "aic7895C",
  73         "aic7890/91",
  74         "aic7896/97",
  75         "aic7892",
  76         "aic7899"
  77 };
  78
  79 /*
  80  * Hardware error codes.
  81  */
  82 struct ahc_hard_error_entry {
  83         uint8_t errno;
  84         char *errmesg;
  85 };
  86
  87 static struct ahc_hard_error_entry ahc_hard_errors[] = {
  88         { ILLHADDR,     "Illegal Host Access" },
  89         { ILLSADDR,     "Illegal Sequencer Address referrenced" },
  90         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
  91         { SQPARERR,     "Sequencer Parity Error" },
  92         { DPARERR,      "Data-path Parity Error" },
  93         { MPARERR,      "Scratch or SCB Memory Parity Error" },
  94         { PCIERRSTAT,   "PCI Error detected" },
  95         { CIOPARERR,    "CIOBUS Parity Error" },
  96 };
  97 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
  98
  99 static struct ahc_phase_table_entry ahc_phase_table[] =
 100 {
 101         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
 102         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
 103         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
 104         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
 105         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
 106         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
 107         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
 108         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
 109         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
 110         { 0,            MSG_NOOP,               "in unknown phase"      }
 111 };
 112
 113 /*
 114  * In most cases we only wish to itterate over real phases, so
 115  * exclude the last element from the count.
 116  */
 117 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
 118
 119 /*
 120  * Valid SCSIRATE values.  (p. 3-17)
 121  * Provides a mapping of transfer periods in ns to the proper value to
 122  * stick in the scsixfer reg.
 123  */
 124 static struct ahc_syncrate ahc_syncrates[] =
 125 {
 126       /* ultra2    fast/ultra  period     rate */
 127         { 0x42,      0x000,      9,      "80.0" },
 128         { 0x03,      0x000,     10,      "40.0" },
 129         { 0x04,      0x000,     11,      "33.0" },
 130         { 0x05,      0x100,     12,      "20.0" },
 131         { 0x06,      0x110,     15,      "16.0" },
 132         { 0x07,      0x120,     18,      "13.4" },
 133         { 0x08,      0x000,     25,      "10.0" },
 134         { 0x19,      0x010,     31,      "8.0"  },
 135         { 0x1a,      0x020,     37,      "6.67" },
 136         { 0x1b,      0x030,     43,      "5.7"  },
 137         { 0x1c,      0x040,     50,      "5.0"  },
 138         { 0x00,      0x050,     56,      "4.4"  },
 139         { 0x00,      0x060,     62,      "4.0"  },
 140         { 0x00,      0x070,     68,      "3.6"  },
 141         { 0x00,      0x000,      0,      NULL   }
 142 };
 143
 144 /* Our Sequencer Program */
 145 #include "aic7xxx_seq.h"
 146
 147 /**************************** Function Declarations ***************************/
 148 static void             ahc_force_renegotiation(struct ahc_softc *ahc,
 149                                                 struct ahc_devinfo *devinfo);
 150 static struct ahc_tmode_tstate*
 151                         ahc_alloc_tstate(struct ahc_softc *ahc,
 152                                          u_int scsi_id, char channel);
 153 #ifdef AHC_TARGET_MODE
 154 static void             ahc_free_tstate(struct ahc_softc *ahc,
 155                                         u_int scsi_id, char channel, int force);
 156 #endif
 157 static struct ahc_syncrate*
 158                         ahc_devlimited_syncrate(struct ahc_softc *ahc,
 159                                                 struct ahc_initiator_tinfo *,
 160                                                 u_int *period,
 161                                                 u_int *ppr_options,
 162                                                 role_t role);
 163 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
 164 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
 165                                           struct ahc_devinfo *devinfo);
 166 static void             ahc_scb_devinfo(struct ahc_softc *ahc,
 167                                         struct ahc_devinfo *devinfo,
 168                                         struct scb *scb);
 169 static void             ahc_assert_atn(struct ahc_softc *ahc);
 170 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
 171                                                    struct ahc_devinfo *devinfo,
 172                                                    struct scb *scb);
 173 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
 174                                                struct ahc_devinfo *devinfo);
 175 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
 176                                            struct ahc_devinfo *devinfo,
 177                                            u_int period, u_int offset);
 178 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
 179                                            struct ahc_devinfo *devinfo,
 180                                            u_int bus_width);
 181 static void             ahc_construct_ppr(struct ahc_softc *ahc,
 182                                           struct ahc_devinfo *devinfo,
 183                                           u_int period, u_int offset,
 184                                           u_int bus_width, u_int ppr_options);
 185 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
 186 static void             ahc_handle_proto_violation(struct ahc_softc *ahc);
 187 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
 188 typedef enum {
 189         AHCMSG_1B,
 190         AHCMSG_2B,
 191         AHCMSG_EXT
 192 } ahc_msgtype;
 193 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
 194                                      u_int msgval, int full);
 195 static int              ahc_parse_msg(struct ahc_softc *ahc,
 196                                       struct ahc_devinfo *devinfo);
 197 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
 198                                               struct ahc_devinfo *devinfo);
 199 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
 200                                                 struct ahc_devinfo *devinfo);
 201 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
 202 static void             ahc_handle_devreset(struct ahc_softc *ahc,
 203                                             struct ahc_devinfo *devinfo,
 204                                             cam_status status, char *message,
 205                                             int verbose_level);
 206 #ifdef AHC_TARGET_MODE
 207 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
 208                                                struct ahc_devinfo *devinfo,
 209                                                struct scb *scb);
 210 #endif
 211
 212 static bus_dmamap_callback_t    ahc_dmamap_cb;
 213 static void                     ahc_build_free_scb_list(struct ahc_softc *ahc);
 214 static int                      ahc_init_scbdata(struct ahc_softc *ahc);
 215 static void                     ahc_fini_scbdata(struct ahc_softc *ahc);
 216 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
 217                                             struct scb *prev_scb,
 218                                             struct scb *scb);
 219 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
 220 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
 221                                                    u_int prev, u_int scbptr);
 222 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
 223 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
 224                                      u_int scbpos, u_int prev);
 225 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
 226 #ifdef AHC_DUMP_SEQ
 227 static void             ahc_dumpseq(struct ahc_softc *ahc);
 228 #endif
 229 static int              ahc_loadseq(struct ahc_softc *ahc);
 230 static int              ahc_check_patch(struct ahc_softc *ahc,
 231                                         struct patch **start_patch,
 232                                         u_int start_instr, u_int *skip_addr);
 233 static void             ahc_download_instr(struct ahc_softc *ahc,
 234                                            u_int instrptr, uint8_t *dconsts);
 235 static int              ahc_other_scb_timeout(struct ahc_softc *ahc,
 236                                               struct scb *scb,
 237                                               struct scb *other_scb);
 238 #ifdef AHC_TARGET_MODE
 239 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
 240                                                struct ahc_tmode_lstate *lstate,
 241                                                u_int initiator_id,
 242                                                u_int event_type,
 243                                                u_int event_arg);
 244 static void             ahc_update_scsiid(struct ahc_softc *ahc,
 245                                           u_int targid_mask);
 246 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
 247                                               struct target_cmd *cmd);
 248 #endif
 249 /************************* Sequencer Execution Control ************************/
 250 /*
 251  * Restart the sequencer program from address zero
 252  */
 253 void
 254 ahc_restart(struct ahc_softc *ahc)
 255 {
 256
 257         ahc_pause(ahc);
 258
 259         /* No more pending messages. */
 260         ahc_clear_msg_state(ahc);
 261
 262         ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
 263         ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
 264         ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
 265         ahc_outb(ahc, LASTPHASE, P_BUSFREE);
 266         ahc_outb(ahc, SAVED_SCSIID, 0xFF);
 267         ahc_outb(ahc, SAVED_LUN, 0xFF);
 268
 269         /*
 270          * Ensure that the sequencer's idea of TQINPOS
 271          * matches our own.  The sequencer increments TQINPOS
 272          * only after it sees a DMA complete and a reset could
 273          * occur before the increment leaving the kernel to believe
 274          * the command arrived but the sequencer to not.
 275          */
 276         ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
 277
 278         /* Always allow reselection */
 279         ahc_outb(ahc, SCSISEQ,
 280                  ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
 281         if ((ahc->features & AHC_CMD_CHAN) != 0) {
 282                 /* Ensure that no DMA operations are in progress */
 283                 ahc_outb(ahc, CCSCBCNT, 0);
 284                 ahc_outb(ahc, CCSGCTL, 0);
 285                 ahc_outb(ahc, CCSCBCTL, 0);
 286         }
 287         /*
 288          * If we were in the process of DMA'ing SCB data into
 289          * an SCB, replace that SCB on the free list.  This prevents
 290          * an SCB leak.
 291          */
 292         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
 293                 ahc_add_curscb_to_free_list(ahc);
 294                 ahc_outb(ahc, SEQ_FLAGS2,
 295                          ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
 296         }
 297
 298         /*
 299          * Clear any pending sequencer interrupt.  It is no
 300          * longer relevant since we're resetting the Program
 301          * Counter.
 302          */
 303         ahc_outb(ahc, CLRINT, CLRSEQINT);
 304
 305         ahc_outb(ahc, MWI_RESIDUAL, 0);
 306         ahc_outb(ahc, SEQCTL, ahc->seqctl);
 307         ahc_outb(ahc, SEQADDR0, 0);
 308         ahc_outb(ahc, SEQADDR1, 0);
 309
 310         ahc_unpause(ahc);
 311 }
 312
 313 /************************* Input/Output Queues ********************************/
 314 void
 315 ahc_run_qoutfifo(struct ahc_softc *ahc)
 316 {
 317         struct scb *scb;
 318         u_int  scb_index;
 319
 320         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
 321         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
 322                 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
 323                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
 324                         u_int modnext;
 325
 326                         /*
 327                          * Clear 32bits of QOUTFIFO at a time
 328                          * so that we don't clobber an incoming
 329                          * byte DMA to the array on architectures
 330                          * that only support 32bit load and store
 331                          * operations.
 332                          */
 333                         modnext = ahc->qoutfifonext & ~0x3;
 334                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
 335                         aic_dmamap_sync(ahc, ahc->shared_data_dmat,
 336                                         ahc->shared_data_dmamap,
 337                                         /*offset*/modnext, /*len*/4,
 338                                         BUS_DMASYNC_PREREAD);
 339                 }
 340                 ahc->qoutfifonext++;
 341
 342                 scb = ahc_lookup_scb(ahc, scb_index);
 343                 if (scb == NULL) {
 344                         printf("%s: WARNING no command for scb %d "
 345                                "(cmdcmplt)\nQOUTPOS = %d\n",
 346                                ahc_name(ahc), scb_index,
 347                                (ahc->qoutfifonext - 1) & 0xFF);
 348                         continue;
 349                 }
 350
 351                 /*
 352                  * Save off the residual
 353                  * if there is one.
 354                  */
 355                 ahc_update_residual(ahc, scb);
 356                 ahc_done(ahc, scb);
 357         }
 358 }
 359
 360 void
 361 ahc_run_untagged_queues(struct ahc_softc *ahc)
 362 {
 363         int i;
 364
 365         for (i = 0; i < 16; i++)
 366                 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
 367 }
 368
 369 void
 370 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
 371 {
 372         struct scb *scb;
 373
 374         if (ahc->untagged_queue_lock != 0)
 375                 return;
 376
 377         if ((scb = TAILQ_FIRST(queue)) != NULL
 378          && (scb->flags & SCB_ACTIVE) == 0) {
 379                 scb->flags |= SCB_ACTIVE;
 380                 /*
 381                  * Timers are disabled while recovery is in progress.
 382                  */
 383                 aic_scb_timer_start(scb);
 384                 ahc_queue_scb(ahc, scb);
 385         }
 386 }
 387
 388 /************************* Interrupt Handling *********************************/
 389 void
 390 ahc_handle_brkadrint(struct ahc_softc *ahc)
 391 {
 392         /*
 393          * We upset the sequencer :-(
 394          * Lookup the error message
 395          */
 396         int i;
 397         int error;
 398
 399         error = ahc_inb(ahc, ERROR);
 400         for (i = 0; error != 1 && i < num_errors; i++)
 401                 error >>= 1;
 402         printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
 403                ahc_name(ahc), ahc_hard_errors[i].errmesg,
 404                ahc_inb(ahc, SEQADDR0) |
 405                (ahc_inb(ahc, SEQADDR1) << 8));
 406
 407         ahc_dump_card_state(ahc);
 408
 409         /* Tell everyone that this HBA is no longer available */
 410         ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
 411                        CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
 412                        CAM_NO_HBA);
 413
 414         /* Disable all interrupt sources by resetting the controller */
 415         ahc_shutdown(ahc);
 416 }
 417
 418 void
 419 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
 420 {
 421         struct scb *scb;
 422         struct ahc_devinfo devinfo;
 423
 424         ahc_fetch_devinfo(ahc, &devinfo);
 425
 426         /*
 427          * Clear the upper byte that holds SEQINT status
 428          * codes and clear the SEQINT bit. We will unpause
 429          * the sequencer, if appropriate, after servicing
 430          * the request.
 431          */
 432         ahc_outb(ahc, CLRINT, CLRSEQINT);
 433         switch (intstat & SEQINT_MASK) {
 434         case BAD_STATUS:
 435         {
 436                 u_int  scb_index;
 437                 struct hardware_scb *hscb;
 438
 439                 /*
 440                  * Set the default return value to 0 (don't
 441                  * send sense).  The sense code will change
 442                  * this if needed.
 443                  */
 444                 ahc_outb(ahc, RETURN_1, 0);
 445
 446                 /*
 447                  * The sequencer will notify us when a command
 448                  * has an error that would be of interest to
 449                  * the kernel.  This allows us to leave the sequencer
 450                  * running in the common case of command completes
 451                  * without error.  The sequencer will already have
 452                  * dma'd the SCB back up to us, so we can reference
 453                  * the in kernel copy directly.
 454                  */
 455                 scb_index = ahc_inb(ahc, SCB_TAG);
 456                 scb = ahc_lookup_scb(ahc, scb_index);
 457                 if (scb == NULL) {
 458                         ahc_print_devinfo(ahc, &devinfo);
 459                         printf("ahc_intr - referenced scb "
 460                                "not valid during seqint 0x%x scb(%d)\n",
 461                                intstat, scb_index);
 462                         ahc_dump_card_state(ahc);
 463                         panic("for safety");
 464                         goto unpause;
 465                 }
 466
 467                 hscb = scb->hscb;
 468
 469                 /* Don't want to clobber the original sense code */
 470                 if ((scb->flags & SCB_SENSE) != 0) {
 471                         /*
 472                          * Clear the SCB_SENSE Flag and have
 473                          * the sequencer do a normal command
 474                          * complete.
 475                          */
 476                         scb->flags &= ~SCB_SENSE;
 477                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
 478                         break;
 479                 }
 480                 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
 481                 /* Freeze the queue until the client sees the error. */
 482                 ahc_freeze_devq(ahc, scb);
 483                 aic_freeze_scb(scb);
 484                 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
 485                 switch (hscb->shared_data.status.scsi_status) {
 486                 case SCSI_STATUS_OK:
 487                         printf("%s: Interrupted for staus of 0???\n",
 488                                ahc_name(ahc));
 489                         break;
 490                 case SCSI_STATUS_CMD_TERMINATED:
 491                 case SCSI_STATUS_CHECK_COND:
 492                 {
 493                         struct ahc_dma_seg *sg;
 494                         struct scsi_sense *sc;
 495                         struct ahc_initiator_tinfo *targ_info;
 496                         struct ahc_tmode_tstate *tstate;
 497                         struct ahc_transinfo *tinfo;
 498 #ifdef AHC_DEBUG
 499                         if (ahc_debug & AHC_SHOW_SENSE) {
 500                                 ahc_print_path(ahc, scb);
 501                                 printf("SCB %d: requests Check Status\n",
 502                                        scb->hscb->tag);
 503                         }
 504 #endif
 505
 506                         if (aic_perform_autosense(scb) == 0)
 507                                 break;
 508
 509                         targ_info = ahc_fetch_transinfo(ahc,
 510                                                         devinfo.channel,
 511                                                         devinfo.our_scsiid,
 512                                                         devinfo.target,
 513                                                         &tstate);
 514                         tinfo = &targ_info->curr;
 515                         sg = scb->sg_list;
 516                         sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
 517                         /*
 518                          * Save off the residual if there is one.
 519                          */
 520                         ahc_update_residual(ahc, scb);
 521 #ifdef AHC_DEBUG
 522                         if (ahc_debug & AHC_SHOW_SENSE) {
 523                                 ahc_print_path(ahc, scb);
 524                                 printf("Sending Sense\n");
 525                         }
 526 #endif
 527                         sg->addr = ahc_get_sense_bufaddr(ahc, scb);
 528                         sg->len = aic_get_sense_bufsize(ahc, scb);
 529                         sg->len |= AHC_DMA_LAST_SEG;
 530
 531                         /* Fixup byte order */
 532                         sg->addr = aic_htole32(sg->addr);
 533                         sg->len = aic_htole32(sg->len);
 534
 535                         sc->opcode = REQUEST_SENSE;
 536                         sc->byte2 = 0;
 537                         if (tinfo->protocol_version <= SCSI_REV_2
 538                          && SCB_GET_LUN(scb) < 8)
 539                                 sc->byte2 = SCB_GET_LUN(scb) << 5;
 540                         sc->unused[0] = 0;
 541                         sc->unused[1] = 0;
 542                         sc->length = sg->len;
 543                         sc->control = 0;
 544
 545                         /*
 546                          * We can't allow the target to disconnect.
 547                          * This will be an untagged transaction and
 548                          * having the target disconnect will make this
 549                          * transaction indestinguishable from outstanding
 550                          * tagged transactions.
 551                          */
 552                         hscb->control = 0;
 553
 554                         /*
 555                          * This request sense could be because the
 556                          * the device lost power or in some other
 557                          * way has lost our transfer negotiations.
 558                          * Renegotiate if appropriate.  Unit attention
 559                          * errors will be reported before any data
 560                          * phases occur.
 561                          */
 562                         if (aic_get_residual(scb)
 563                          == aic_get_transfer_length(scb)) {
 564                                 ahc_update_neg_request(ahc, &devinfo,
 565                                                        tstate, targ_info,
 566                                                        AHC_NEG_IF_NON_ASYNC);
 567                         }
 568                         if (tstate->auto_negotiate & devinfo.target_mask) {
 569                                 hscb->control |= MK_MESSAGE;
 570                                 scb->flags &= ~SCB_NEGOTIATE;
 571                                 scb->flags |= SCB_AUTO_NEGOTIATE;
 572                         }
 573                         hscb->cdb_len = sizeof(*sc);
 574                         hscb->dataptr = sg->addr;
 575                         hscb->datacnt = sg->len;
 576                         hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
 577                         hscb->sgptr = aic_htole32(hscb->sgptr);
 578                         scb->sg_count = 1;
 579                         scb->flags |= SCB_SENSE;
 580                         ahc_qinfifo_requeue_tail(ahc, scb);
 581                         ahc_outb(ahc, RETURN_1, SEND_SENSE);
 582                         /*
 583                          * Ensure we have enough time to actually
 584                          * retrieve the sense, but only schedule
 585                          * the timer if we are not in recovery or
 586                          * this is a recovery SCB that is allowed
 587                          * to have an active timer.
 588                          */
 589                         if (ahc->scb_data->recovery_scbs == 0
 590                          || (scb->flags & SCB_RECOVERY_SCB) != 0)
 591                                 aic_scb_timer_reset(scb, 5 * 1000);
 592                         break;
 593                 }
 594                 default:
 595                         break;
 596                 }
 597                 break;
 598         }
 599         case NO_MATCH:
 600         {
 601                 /* Ensure we don't leave the selection hardware on */
 602                 ahc_outb(ahc, SCSISEQ,
 603                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
 604
 605                 printf("%s:%c:%d: no active SCB for reconnecting "
 606                        "target - issuing BUS DEVICE RESET\n",
 607                        ahc_name(ahc), devinfo.channel, devinfo.target);
 608                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
 609                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
 610                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
 611                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
 612                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
 613                        "SINDEX == 0x%x\n",
 614                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
 615                        ahc_index_busy_tcl(ahc,
 616                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
 617                                       ahc_inb(ahc, SAVED_LUN))),
 618                        ahc_inb(ahc, SINDEX));
 619                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
 620                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
 621                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
 622                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
 623                        ahc_inb(ahc, SCB_CONTROL));
 624                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
 625                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
 626                 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
 627                 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
 628                 ahc_dump_card_state(ahc);
 629                 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
 630                 ahc->msgout_len = 1;
 631                 ahc->msgout_index = 0;
 632                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
 633                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
 634                 ahc_assert_atn(ahc);
 635                 break;
 636         }
 637         case SEND_REJECT:
 638         {
 639                 u_int rejbyte = ahc_inb(ahc, ACCUM);
 640                 printf("%s:%c:%d: Warning - unknown message received from "
 641                        "target (0x%x).  Rejecting\n",
 642                        ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
 643                 break;
 644         }
 645         case PROTO_VIOLATION:
 646         {
 647                 ahc_handle_proto_violation(ahc);
 648                 break;
 649         }
 650         case IGN_WIDE_RES:
 651                 ahc_handle_ign_wide_residue(ahc, &devinfo);
 652                 break;
 653         case PDATA_REINIT:
 654                 ahc_reinitialize_dataptrs(ahc);
 655                 break;
 656         case BAD_PHASE:
 657         {
 658                 u_int lastphase;
 659
 660                 lastphase = ahc_inb(ahc, LASTPHASE);
 661                 printf("%s:%c:%d: unknown scsi bus phase %x, "
 662                        "lastphase = 0x%x.  Attempting to continue\n",
 663                        ahc_name(ahc), devinfo.channel, devinfo.target,
 664                        lastphase, ahc_inb(ahc, SCSISIGI));
 665                 break;
 666         }
 667         case MISSED_BUSFREE:
 668         {
 669                 u_int lastphase;
 670
 671                 lastphase = ahc_inb(ahc, LASTPHASE);
 672                 printf("%s:%c:%d: Missed busfree. "
 673                        "Lastphase = 0x%x, Curphase = 0x%x\n",
 674                        ahc_name(ahc), devinfo.channel, devinfo.target,
 675                        lastphase, ahc_inb(ahc, SCSISIGI));
 676                 ahc_restart(ahc);
 677                 return;
 678         }
 679         case HOST_MSG_LOOP:
 680         {
 681                 /*
 682                  * The sequencer has encountered a message phase
 683                  * that requires host assistance for completion.
 684                  * While handling the message phase(s), we will be
 685                  * notified by the sequencer after each byte is
 686                  * transferred so we can track bus phase changes.
 687                  *
 688                  * If this is the first time we've seen a HOST_MSG_LOOP
 689                  * interrupt, initialize the state of the host message
 690                  * loop.
 691                  */
 692                 if (ahc->msg_type == MSG_TYPE_NONE) {
 693                         struct scb *scb;
 694                         u_int scb_index;
 695                         u_int bus_phase;
 696
 697                         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
 698                         if (bus_phase != P_MESGIN
 699                          && bus_phase != P_MESGOUT) {
 700                                 printf("ahc_intr: HOST_MSG_LOOP bad "
 701                                        "phase 0x%x\n",
 702                                       bus_phase);
 703                                 /*
 704                                  * Probably transitioned to bus free before
 705                                  * we got here.  Just punt the message.
 706                                  */
 707                                 ahc_clear_intstat(ahc);
 708                                 ahc_restart(ahc);
 709                                 return;
 710                         }
 711
 712                         scb_index = ahc_inb(ahc, SCB_TAG);
 713                         scb = ahc_lookup_scb(ahc, scb_index);
 714                         if (devinfo.role == ROLE_INITIATOR) {
 715                                 if (scb == NULL)
 716                                         panic("HOST_MSG_LOOP with "
 717                                               "invalid SCB %x\n", scb_index);
 718
 719                                 if (bus_phase == P_MESGOUT)
 720                                         ahc_setup_initiator_msgout(ahc,
 721                                                                    &devinfo,
 722                                                                    scb);
 723                                 else {
 724                                         ahc->msg_type =
 725                                             MSG_TYPE_INITIATOR_MSGIN;
 726                                         ahc->msgin_index = 0;
 727                                 }
 728                         }
 729 #ifdef AHC_TARGET_MODE
 730                         else {
 731                                 if (bus_phase == P_MESGOUT) {
 732                                         ahc->msg_type =
 733                                             MSG_TYPE_TARGET_MSGOUT;
 734                                         ahc->msgin_index = 0;
 735                                 }
 736                                 else
 737                                         ahc_setup_target_msgin(ahc,
 738                                                                &devinfo,
 739                                                                scb);
 740                         }
 741 #endif
 742                 }
 743
 744                 ahc_handle_message_phase(ahc);
 745                 break;
 746         }
 747         case PERR_DETECTED:
 748         {
 749                 /*
 750                  * If we've cleared the parity error interrupt
 751                  * but the sequencer still believes that SCSIPERR
 752                  * is true, it must be that the parity error is
 753                  * for the currently presented byte on the bus,
 754                  * and we are not in a phase (data-in) where we will
 755                  * eventually ack this byte.  Ack the byte and
 756                  * throw it away in the hope that the target will
 757                  * take us to message out to deliver the appropriate
 758                  * error message.
 759                  */
 760                 if ((intstat & SCSIINT) == 0
 761                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
 762                         if ((ahc->features & AHC_DT) == 0) {
 763                                 u_int curphase;
 764
 765                                 /*
 766                                  * The hardware will only let you ack bytes
 767                                  * if the expected phase in SCSISIGO matches
 768                                  * the current phase.  Make sure this is
 769                                  * currently the case.
 770                                  */
 771                                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
 772                                 ahc_outb(ahc, LASTPHASE, curphase);
 773                                 ahc_outb(ahc, SCSISIGO, curphase);
 774                         }
 775                         if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
 776                                 int wait;
 777
 778                                 /*
 779                                  * In a data phase.  Faster to bitbucket
 780                                  * the data than to individually ack each
 781                                  * byte.  This is also the only strategy
 782                                  * that will work with AUTOACK enabled.
 783                                  */
 784                                 ahc_outb(ahc, SXFRCTL1,
 785                                          ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
 786                                 wait = 5000;
 787                                 while (--wait != 0) {
 788                                         if ((ahc_inb(ahc, SCSISIGI)
 789                                           & (CDI|MSGI)) != 0)
 790                                                 break;
 791                                         aic_delay(100);
 792                                 }
 793                                 ahc_outb(ahc, SXFRCTL1,
 794                                          ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
 795                                 if (wait == 0) {
 796                                         struct  scb *scb;
 797                                         u_int   scb_index;
 798
 799                                         ahc_print_devinfo(ahc, &devinfo);
 800                                         printf("Unable to clear parity error.  "
 801                                                "Resetting bus.\n");
 802                                         scb_index = ahc_inb(ahc, SCB_TAG);
 803                                         scb = ahc_lookup_scb(ahc, scb_index);
 804                                         if (scb != NULL)
 805                                                 aic_set_transaction_status(scb,
 806                                                     CAM_UNCOR_PARITY);
 807                                         ahc_reset_channel(ahc, devinfo.channel,
 808                                                           /*init reset*/TRUE);
 809                                 }
 810                         } else {
 811                                 ahc_inb(ahc, SCSIDATL);
 812                         }
 813                 }
 814                 break;
 815         }
 816         case DATA_OVERRUN:
 817         {
 818                 /*
 819                  * When the sequencer detects an overrun, it
 820                  * places the controller in "BITBUCKET" mode
 821                  * and allows the target to complete its transfer.
 822                  * Unfortunately, none of the counters get updated
 823                  * when the controller is in this mode, so we have
 824                  * no way of knowing how large the overrun was.
 825                  */
 826                 u_int scbindex = ahc_inb(ahc, SCB_TAG);
 827                 u_int lastphase = ahc_inb(ahc, LASTPHASE);
 828                 u_int i;
 829
 830                 scb = ahc_lookup_scb(ahc, scbindex);
 831                 for (i = 0; i < num_phases; i++) {
 832                         if (lastphase == ahc_phase_table[i].phase)
 833                                 break;
 834                 }
 835                 ahc_print_path(ahc, scb);
 836                 printf("data overrun detected %s."
 837                        "  Tag == 0x%x.\n",
 838                        ahc_phase_table[i].phasemsg,
 839                        scb->hscb->tag);
 840                 ahc_print_path(ahc, scb);
 841                 printf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
 842                        ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
 843                        aic_get_transfer_length(scb), scb->sg_count);
 844                 if (scb->sg_count > 0) {
 845                         for (i = 0; i < scb->sg_count; i++) {
 846                                 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
 847                                        i,
 848                                        (aic_le32toh(scb->sg_list[i].len) >> 24
 849                                         & SG_HIGH_ADDR_BITS),
 850                                        aic_le32toh(scb->sg_list[i].addr),
 851                                        aic_le32toh(scb->sg_list[i].len)
 852                                        & AHC_SG_LEN_MASK);
 853                         }
 854                 }
 855                 /*
 856                  * Set this and it will take effect when the
 857                  * target does a command complete.
 858                  */
 859                 ahc_freeze_devq(ahc, scb);
 860                 if ((scb->flags & SCB_SENSE) == 0) {
 861                         aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
 862                 } else {
 863                         scb->flags &= ~SCB_SENSE;
 864                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
 865                 }
 866                 aic_freeze_scb(scb);
 867
 868                 if ((ahc->features & AHC_ULTRA2) != 0) {
 869                         /*
 870                          * Clear the channel in case we return
 871                          * to data phase later.
 872                          */
 873                         ahc_outb(ahc, SXFRCTL0,
 874                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
 875                         ahc_outb(ahc, SXFRCTL0,
 876                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
 877                 }
 878                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
 879                         u_int dscommand1;
 880
 881                         /* Ensure HHADDR is 0 for future DMA operations. */
 882                         dscommand1 = ahc_inb(ahc, DSCOMMAND1);
 883                         ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
 884                         ahc_outb(ahc, HADDR, 0);
 885                         ahc_outb(ahc, DSCOMMAND1, dscommand1);
 886                 }
 887                 break;
 888         }
 889         case MKMSG_FAILED:
 890         {
 891                 u_int scbindex;
 892
 893                 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
 894                        ahc_name(ahc), devinfo.channel, devinfo.target,
 895                        devinfo.lun);
 896                 scbindex = ahc_inb(ahc, SCB_TAG);
 897                 scb = ahc_lookup_scb(ahc, scbindex);
 898                 if (scb != NULL
 899                  && (scb->flags & SCB_RECOVERY_SCB) != 0)
 900                         /*
 901                          * Ensure that we didn't put a second instance of this
 902                          * SCB into the QINFIFO.
 903                          */
 904                         ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
 905                                            SCB_GET_CHANNEL(ahc, scb),
 906                                            SCB_GET_LUN(scb), scb->hscb->tag,
 907                                            ROLE_INITIATOR, /*status*/0,
 908                                            SEARCH_REMOVE);
 909                 break;
 910         }
 911         case NO_FREE_SCB:
 912         {
 913                 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
 914                 ahc_dump_card_state(ahc);
 915                 panic("for safety");
 916                 break;
 917         }
 918         case SCB_MISMATCH:
 919         {
 920                 u_int scbptr;
 921
 922                 scbptr = ahc_inb(ahc, SCBPTR);
 923                 printf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
 924                        scbptr, ahc_inb(ahc, ARG_1),
 925                        ahc->scb_data->hscbs[scbptr].tag);
 926                 ahc_dump_card_state(ahc);
 927                 panic("for safety");
 928                 break;
 929         }
 930         case OUT_OF_RANGE:
 931         {
 932                 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
 933                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
 934                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
 935                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
 936                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
 937                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
 938                        "SINDEX == 0x%x\n, A == 0x%x\n",
 939                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
 940                        ahc_index_busy_tcl(ahc,
 941                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
 942                                       ahc_inb(ahc, SAVED_LUN))),
 943                        ahc_inb(ahc, SINDEX),
 944                        ahc_inb(ahc, ACCUM));
 945                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
 946                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
 947                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
 948                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
 949                        ahc_inb(ahc, SCB_CONTROL));
 950                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
 951                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
 952                 ahc_dump_card_state(ahc);
 953                 panic("for safety");
 954                 break;
 955         }
 956         default:
 957                 printf("ahc_intr: seqint, "
 958                        "intstat == 0x%x, scsisigi = 0x%x\n",
 959                        intstat, ahc_inb(ahc, SCSISIGI));
 960                 break;
 961         }
 962 unpause:
 963         /*
 964          *  The sequencer is paused immediately on
 965          *  a SEQINT, so we should restart it when
 966          *  we're done.
 967          */
 968         ahc_unpause(ahc);
 969 }
 970
 971 void
 972 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
 973 {
 974         u_int   scb_index;
 975         u_int   status0;
 976         u_int   status;
 977         struct  scb *scb;
 978         char    cur_channel;
 979         char    intr_channel;
 980
 981         if ((ahc->features & AHC_TWIN) != 0
 982          && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
 983                 cur_channel = 'B';
 984         else
 985                 cur_channel = 'A';
 986         intr_channel = cur_channel;
 987
 988         if ((ahc->features & AHC_ULTRA2) != 0)
 989                 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
 990         else
 991                 status0 = 0;
 992         status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
 993         if (status == 0 && status0 == 0) {
 994                 if ((ahc->features & AHC_TWIN) != 0) {
 995                         /* Try the other channel */
 996                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
 997                         status = ahc_inb(ahc, SSTAT1)
 998                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
 999                         intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1000                 }
1001                 if (status == 0) {
1002                         printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1003                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1004                         ahc_unpause(ahc);
1005                         return;
1006                 }
1007         }
1008
1009         /* Make sure the sequencer is in a safe location. */
1010         ahc_clear_critical_section(ahc);
1011
1012         scb_index = ahc_inb(ahc, SCB_TAG);
1013         scb = ahc_lookup_scb(ahc, scb_index);
1014         if (scb != NULL
1015          && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1016                 scb = NULL;
1017
1018         if ((ahc->features & AHC_ULTRA2) != 0
1019          && (status0 & IOERR) != 0) {
1020                 int now_lvd;
1021
1022                 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1023                 printf("%s: Transceiver State Has Changed to %s mode\n",
1024                        ahc_name(ahc), now_lvd ? "LVD" : "SE");
1025                 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1026                 /*
1027                  * When transitioning to SE mode, the reset line
1028                  * glitches, triggering an arbitration bug in some
1029                  * Ultra2 controllers.  This bug is cleared when we
1030                  * assert the reset line.  Since a reset glitch has
1031                  * already occurred with this transition and a
1032                  * transceiver state change is handled just like
1033                  * a bus reset anyway, asserting the reset line
1034                  * ourselves is safe.
1035                  */
1036                 ahc_reset_channel(ahc, intr_channel,
1037                                  /*Initiate Reset*/now_lvd == 0);
1038         } else if ((status & SCSIRSTI) != 0) {
1039                 printf("%s: Someone reset channel %c\n",
1040                         ahc_name(ahc), intr_channel);
1041                 if (intr_channel != cur_channel)
1042                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1043                 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1044         } else if ((status & SCSIPERR) != 0) {
1045                 /*
1046                  * Determine the bus phase and queue an appropriate message.
1047                  * SCSIPERR is latched true as soon as a parity error
1048                  * occurs.  If the sequencer acked the transfer that
1049                  * caused the parity error and the currently presented
1050                  * transfer on the bus has correct parity, SCSIPERR will
1051                  * be cleared by CLRSCSIPERR.  Use this to determine if
1052                  * we should look at the last phase the sequencer recorded,
1053                  * or the current phase presented on the bus.
1054                  */
1055                 struct  ahc_devinfo devinfo;
1056                 u_int   mesg_out;
1057                 u_int   curphase;
1058                 u_int   errorphase;
1059                 u_int   lastphase;
1060                 u_int   scsirate;
1061                 u_int   i;
1062                 u_int   sstat2;
1063                 int     silent;
1064
1065                 lastphase = ahc_inb(ahc, LASTPHASE);
1066                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1067                 sstat2 = ahc_inb(ahc, SSTAT2);
1068                 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1069                 /*
1070                  * For all phases save DATA, the sequencer won't
1071                  * automatically ack a byte that has a parity error
1072                  * in it.  So the only way that the current phase
1073                  * could be 'data-in' is if the parity error is for
1074                  * an already acked byte in the data phase.  During
1075                  * synchronous data-in transfers, we may actually
1076                  * ack bytes before latching the current phase in
1077                  * LASTPHASE, leading to the discrepancy between
1078                  * curphase and lastphase.
1079                  */
1080                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1081                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1082                         errorphase = curphase;
1083                 else
1084                         errorphase = lastphase;
1085
1086                 for (i = 0; i < num_phases; i++) {
1087                         if (errorphase == ahc_phase_table[i].phase)
1088                                 break;
1089                 }
1090                 mesg_out = ahc_phase_table[i].mesg_out;
1091                 silent = FALSE;
1092                 if (scb != NULL) {
1093                         if (SCB_IS_SILENT(scb))
1094                                 silent = TRUE;
1095                         else
1096                                 ahc_print_path(ahc, scb);
1097                         scb->flags |= SCB_TRANSMISSION_ERROR;
1098                 } else
1099                         printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1100                                SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1101                 scsirate = ahc_inb(ahc, SCSIRATE);
1102                 if (silent == FALSE) {
1103                         printf("parity error detected %s. "
1104                                "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1105                                ahc_phase_table[i].phasemsg,
1106                                ahc_inw(ahc, SEQADDR0),
1107                                scsirate);
1108                         if ((ahc->features & AHC_DT) != 0) {
1109                                 if ((sstat2 & CRCVALERR) != 0)
1110                                         printf("\tCRC Value Mismatch\n");
1111                                 if ((sstat2 & CRCENDERR) != 0)
1112                                         printf("\tNo terminal CRC packet "
1113                                                "recevied\n");
1114                                 if ((sstat2 & CRCREQERR) != 0)
1115                                         printf("\tIllegal CRC packet "
1116                                                "request\n");
1117                                 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1118                                         printf("\tUnexpected %sDT Data Phase\n",
1119                                                (scsirate & SINGLE_EDGE)
1120                                              ? "" : "non-");
1121                         }
1122                 }
1123
1124                 if ((ahc->features & AHC_DT) != 0
1125                  && (sstat2 & DUAL_EDGE_ERR) != 0) {
1126                         /*
1127                          * This error applies regardless of
1128                          * data direction, so ignore the value
1129                          * in the phase table.
1130                          */
1131                         mesg_out = MSG_INITIATOR_DET_ERR;
1132                 }
1133
1134                 /*
1135                  * We've set the hardware to assert ATN if we
1136                  * get a parity error on "in" phases, so all we
1137                  * need to do is stuff the message buffer with
1138                  * the appropriate message.  "In" phases have set
1139                  * mesg_out to something other than MSG_NOP.
1140                  */
1141                 if (mesg_out != MSG_NOOP) {
1142                         if (ahc->msg_type != MSG_TYPE_NONE)
1143                                 ahc->send_msg_perror = TRUE;
1144                         else
1145                                 ahc_outb(ahc, MSG_OUT, mesg_out);
1146                 }
1147                 /*
1148                  * Force a renegotiation with this target just in
1149                  * case we are out of sync for some external reason
1150                  * unknown (or unreported) by the target.
1151                  */
1152                 ahc_fetch_devinfo(ahc, &devinfo);
1153                 ahc_force_renegotiation(ahc, &devinfo);
1154
1155                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1156                 ahc_unpause(ahc);
1157         } else if ((status & SELTO) != 0) {
1158                 u_int   scbptr;
1159
1160                 /* Stop the selection */
1161                 ahc_outb(ahc, SCSISEQ, 0);
1162
1163                 /* No more pending messages */
1164                 ahc_clear_msg_state(ahc);
1165
1166                 /* Clear interrupt state */
1167                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1168                 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1169
1170                 /*
1171                  * Although the driver does not care about the
1172                  * 'Selection in Progress' status bit, the busy
1173                  * LED does.  SELINGO is only cleared by a successful
1174                  * selection, so we must manually clear it to insure
1175                  * the LED turns off just incase no future successful
1176                  * selections occur (e.g. no devices on the bus).
1177                  */
1178                 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1179
1180                 scbptr = ahc_inb(ahc, WAITING_SCBH);
1181                 ahc_outb(ahc, SCBPTR, scbptr);
1182                 scb_index = ahc_inb(ahc, SCB_TAG);
1183
1184                 scb = ahc_lookup_scb(ahc, scb_index);
1185                 if (scb == NULL) {
1186                         printf("%s: ahc_intr - referenced scb not "
1187                                "valid during SELTO scb(%d, %d)\n",
1188                                ahc_name(ahc), scbptr, scb_index);
1189                         ahc_dump_card_state(ahc);
1190                 } else {
1191                         struct ahc_devinfo devinfo;
1192 #ifdef AHC_DEBUG
1193                         if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1194                                 ahc_print_path(ahc, scb);
1195                                 printf("Saw Selection Timeout for SCB 0x%x\n",
1196                                        scb_index);
1197                         }
1198 #endif
1199                         ahc_scb_devinfo(ahc, &devinfo, scb);
1200                         aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1201                         ahc_freeze_devq(ahc, scb);
1202
1203                         /*
1204                          * Cancel any pending transactions on the device
1205                          * now that it seems to be missing.  This will
1206                          * also revert us to async/narrow transfers until
1207                          * we can renegotiate with the device.
1208                          */
1209                         ahc_handle_devreset(ahc, &devinfo,
1210                                             CAM_SEL_TIMEOUT,
1211                                             "Selection Timeout",
1212                                             /*verbose_level*/1);
1213                 }
1214                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1215                 ahc_restart(ahc);
1216         } else if ((status & BUSFREE) != 0
1217                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1218                 struct  ahc_devinfo devinfo;
1219                 u_int   lastphase;
1220                 u_int   saved_scsiid;
1221                 u_int   saved_lun;
1222                 u_int   target;
1223                 u_int   initiator_role_id;
1224                 char    channel;
1225                 int     printerror;
1226
1227                 /*
1228                  * Clear our selection hardware as soon as possible.
1229                  * We may have an entry in the waiting Q for this target,
1230                  * that is affected by this busfree and we don't want to
1231                  * go about selecting the target while we handle the event.
1232                  */
1233                 ahc_outb(ahc, SCSISEQ,
1234                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1235
1236                 /*
1237                  * Disable busfree interrupts and clear the busfree
1238                  * interrupt status.  We do this here so that several
1239                  * bus transactions occur prior to clearing the SCSIINT
1240                  * latch.  It can take a bit for the clearing to take effect.
1241                  */
1242                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1243                 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1244
1245                 /*
1246                  * Look at what phase we were last in.
1247                  * If its message out, chances are pretty good
1248                  * that the busfree was in response to one of
1249                  * our abort requests.
1250                  */
1251                 lastphase = ahc_inb(ahc, LASTPHASE);
1252                 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1253                 saved_lun = ahc_inb(ahc, SAVED_LUN);
1254                 target = SCSIID_TARGET(ahc, saved_scsiid);
1255                 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1256                 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1257                 ahc_compile_devinfo(&devinfo, initiator_role_id,
1258                                     target, saved_lun, channel, ROLE_INITIATOR);
1259                 printerror = 1;
1260
1261                 if (lastphase == P_MESGOUT) {
1262                         u_int tag;
1263
1264                         tag = SCB_LIST_NULL;
1265                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1266                          || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1267                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
1268                                  == MSG_ABORT_TAG)
1269                                         tag = scb->hscb->tag;
1270                                 ahc_print_path(ahc, scb);
1271                                 printf("SCB %d - Abort%s Completed.\n",
1272                                        scb->hscb->tag, tag == SCB_LIST_NULL ?
1273                                        "" : " Tag");
1274                                 ahc_abort_scbs(ahc, target, channel,
1275                                                saved_lun, tag,
1276                                                ROLE_INITIATOR,
1277                                                CAM_REQ_ABORTED);
1278                                 printerror = 0;
1279                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1280                                                 MSG_BUS_DEV_RESET, TRUE)) {
1281 #ifdef __FreeBSD__
1282                                 /*
1283                                  * Don't mark the user's request for this BDR
1284                                  * as completing with CAM_BDR_SENT.  CAM3
1285                                  * specifies CAM_REQ_CMP.
1286                                  */
1287                                 if (scb != NULL
1288                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1289                                  && ahc_match_scb(ahc, scb, target, channel,
1290                                                   CAM_LUN_WILDCARD,
1291                                                   SCB_LIST_NULL,
1292                                                   ROLE_INITIATOR)) {
1293                                         aic_set_transaction_status(scb, CAM_REQ_CMP);
1294                                 }
1295 #endif
1296                                 ahc_compile_devinfo(&devinfo,
1297                                                     initiator_role_id,
1298                                                     target,
1299                                                     CAM_LUN_WILDCARD,
1300                                                     channel,
1301                                                     ROLE_INITIATOR);
1302                                 ahc_handle_devreset(ahc, &devinfo,
1303                                                     CAM_BDR_SENT,
1304                                                     "Bus Device Reset",
1305                                                     /*verbose_level*/0);
1306                                 printerror = 0;
1307                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1308                                                 MSG_EXT_PPR, FALSE)) {
1309                                 struct ahc_initiator_tinfo *tinfo;
1310                                 struct ahc_tmode_tstate *tstate;
1311
1312                                 /*
1313                                  * PPR Rejected.  Try non-ppr negotiation
1314                                  * and retry command.
1315                                  */
1316                                 tinfo = ahc_fetch_transinfo(ahc,
1317                                                             devinfo.channel,
1318                                                             devinfo.our_scsiid,
1319                                                             devinfo.target,
1320                                                             &tstate);
1321                                 tinfo->curr.transport_version = 2;
1322                                 tinfo->goal.transport_version = 2;
1323                                 tinfo->goal.ppr_options = 0;
1324                                 ahc_qinfifo_requeue_tail(ahc, scb);
1325                                 printerror = 0;
1326                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1327                                                 MSG_EXT_WDTR, FALSE)) {
1328                                 /*
1329                                  * Negotiation Rejected.  Go-narrow and
1330                                  * retry command.
1331                                  */
1332                                 ahc_set_width(ahc, &devinfo,
1333                                               MSG_EXT_WDTR_BUS_8_BIT,
1334                                               AHC_TRANS_CUR|AHC_TRANS_GOAL,
1335                                               /*paused*/TRUE);
1336                                 ahc_qinfifo_requeue_tail(ahc, scb);
1337                                 printerror = 0;
1338                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1339                                                 MSG_EXT_SDTR, FALSE)) {
1340                                 /*
1341                                  * Negotiation Rejected.  Go-async and
1342                                  * retry command.
1343                                  */
1344                                 ahc_set_syncrate(ahc, &devinfo,
1345                                                 /*syncrate*/NULL,
1346                                                 /*period*/0, /*offset*/0,
1347                                                 /*ppr_options*/0,
1348                                                 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1349                                                 /*paused*/TRUE);
1350                                 ahc_qinfifo_requeue_tail(ahc, scb);
1351                                 printerror = 0;
1352                         }
1353                 }
1354                 if (printerror != 0) {
1355                         u_int i;
1356
1357                         if (scb != NULL) {
1358                                 u_int tag;
1359
1360                                 if ((scb->hscb->control & TAG_ENB) != 0)
1361                                         tag = scb->hscb->tag;
1362                                 else
1363                                         tag = SCB_LIST_NULL;
1364                                 ahc_print_path(ahc, scb);
1365                                 ahc_abort_scbs(ahc, target, channel,
1366                                                SCB_GET_LUN(scb), tag,
1367                                                ROLE_INITIATOR,
1368                                                CAM_UNEXP_BUSFREE);
1369                         } else {
1370                                 /*
1371                                  * We had not fully identified this connection,
1372                                  * so we cannot abort anything.
1373                                  */
1374                                 printf("%s: ", ahc_name(ahc));
1375                         }
1376                         for (i = 0; i < num_phases; i++) {
1377                                 if (lastphase == ahc_phase_table[i].phase)
1378                                         break;
1379                         }
1380                         if (lastphase != P_BUSFREE) {
1381                                 /*
1382                                  * Renegotiate with this device at the
1383                                  * next opportunity just in case this busfree
1384                                  * is due to a negotiation mismatch with the
1385                                  * device.
1386                                  */
1387                                 ahc_force_renegotiation(ahc, &devinfo);
1388                         }
1389                         printf("Unexpected busfree %s\n"
1390                                "SEQADDR == 0x%x\n",
1391                                ahc_phase_table[i].phasemsg,
1392                                ahc_inb(ahc, SEQADDR0)
1393                                 | (ahc_inb(ahc, SEQADDR1) << 8));
1394                 }
1395                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1396                 ahc_restart(ahc);
1397         } else {
1398                 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1399                        ahc_name(ahc), status);
1400                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1401         }
1402 }
1403
1404 /*
1405  * Force renegotiation to occur the next time we initiate
1406  * a command to the current device.
1407  */
1408 static void
1409 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1410 {
1411         struct  ahc_initiator_tinfo *targ_info;
1412         struct  ahc_tmode_tstate *tstate;
1413
1414         targ_info = ahc_fetch_transinfo(ahc,
1415                                         devinfo->channel,
1416                                         devinfo->our_scsiid,
1417                                         devinfo->target,
1418                                         &tstate);
1419         ahc_update_neg_request(ahc, devinfo, tstate,
1420                                targ_info, AHC_NEG_IF_NON_ASYNC);
1421 }
1422
1423 #define AHC_MAX_STEPS 2000
1424 void
1425 ahc_clear_critical_section(struct ahc_softc *ahc)
1426 {
1427         int     stepping;
1428         int     steps;
1429         u_int   simode0;
1430         u_int   simode1;
1431
1432         if (ahc->num_critical_sections == 0)
1433                 return;
1434
1435         stepping = FALSE;
1436         steps = 0;
1437         simode0 = 0;
1438         simode1 = 0;
1439         for (;;) {
1440                 struct  cs *cs;
1441                 u_int   seqaddr;
1442                 u_int   i;
1443
1444                 seqaddr = ahc_inb(ahc, SEQADDR0)
1445                         | (ahc_inb(ahc, SEQADDR1) << 8);
1446
1447                 /*
1448                  * Seqaddr represents the next instruction to execute,
1449                  * so we are really executing the instruction just
1450                  * before it.
1451                  */
1452                 cs = ahc->critical_sections;
1453                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1454
1455                         if (cs->begin < seqaddr && cs->end >= seqaddr)
1456                                 break;
1457                 }
1458
1459                 if (i == ahc->num_critical_sections)
1460                         break;
1461
1462                 if (steps > AHC_MAX_STEPS) {
1463                         printf("%s: Infinite loop in critical section\n",
1464                                ahc_name(ahc));
1465                         ahc_dump_card_state(ahc);
1466                         panic("critical section loop");
1467                 }
1468
1469                 steps++;
1470                 if (stepping == FALSE) {
1471                         /*
1472                          * Disable all interrupt sources so that the
1473                          * sequencer will not be stuck by a pausing
1474                          * interrupt condition while we attempt to
1475                          * leave a critical section.
1476                          */
1477                         simode0 = ahc_inb(ahc, SIMODE0);
1478                         ahc_outb(ahc, SIMODE0, 0);
1479                         simode1 = ahc_inb(ahc, SIMODE1);
1480                         if ((ahc->features & AHC_DT) != 0)
1481                                 /*
1482                                  * On DT class controllers, we
1483                                  * use the enhanced busfree logic.
1484                                  * Unfortunately we cannot re-enable
1485                                  * busfree detection within the
1486                                  * current connection, so we must
1487                                  * leave it on while single stepping.
1488                                  */
1489                                 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1490                         else
1491                                 ahc_outb(ahc, SIMODE1, 0);
1492                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1493                         ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1494                         stepping = TRUE;
1495                 }
1496                 if ((ahc->features & AHC_DT) != 0) {
1497                         ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1498                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1499                 }
1500                 ahc_outb(ahc, HCNTRL, ahc->unpause);
1501                 while (!ahc_is_paused(ahc))
1502                         aic_delay(200);
1503         }
1504         if (stepping) {
1505                 ahc_outb(ahc, SIMODE0, simode0);
1506                 ahc_outb(ahc, SIMODE1, simode1);
1507                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1508         }
1509 }
1510
1511 /*
1512  * Clear any pending interrupt status.
1513  */
1514 void
1515 ahc_clear_intstat(struct ahc_softc *ahc)
1516 {
1517         /* Clear any interrupt conditions this may have caused */
1518         ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1519                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1520                                 CLRREQINIT);
1521         ahc_flush_device_writes(ahc);
1522         ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1523         ahc_flush_device_writes(ahc);
1524         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1525         ahc_flush_device_writes(ahc);
1526 }
1527
1528 /**************************** Debugging Routines ******************************/
1529 #ifdef AHC_DEBUG
1530 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1531 #endif
1532
1533 void
1534 ahc_print_scb(struct scb *scb)
1535 {
1536         int i;
1537
1538         struct hardware_scb *hscb = scb->hscb;
1539
1540         printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1541                (void *)scb,
1542                hscb->control,
1543                hscb->scsiid,
1544                hscb->lun,
1545                hscb->cdb_len);
1546         printf("Shared Data: ");
1547         for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1548                 printf("%#02x", hscb->shared_data.cdb[i]);
1549         printf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1550                 aic_le32toh(hscb->dataptr),
1551                 aic_le32toh(hscb->datacnt),
1552                 aic_le32toh(hscb->sgptr),
1553                 hscb->tag);
1554         if (scb->sg_count > 0) {
1555                 for (i = 0; i < scb->sg_count; i++) {
1556                         printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1557                                i,
1558                                (aic_le32toh(scb->sg_list[i].len) >> 24
1559                                 & SG_HIGH_ADDR_BITS),
1560                                aic_le32toh(scb->sg_list[i].addr),
1561                                aic_le32toh(scb->sg_list[i].len));
1562                 }
1563         }
1564 }
1565
1566 /************************* Transfer Negotiation *******************************/
1567 /*
1568  * Allocate per target mode instance (ID we respond to as a target)
1569  * transfer negotiation data structures.
1570  */
1571 static struct ahc_tmode_tstate *
1572 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1573 {
1574         struct ahc_tmode_tstate *master_tstate;
1575         struct ahc_tmode_tstate *tstate;
1576         int i;
1577
1578         master_tstate = ahc->enabled_targets[ahc->our_id];
1579         if (channel == 'B') {
1580                 scsi_id += 8;
1581                 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1582         }
1583         if (ahc->enabled_targets[scsi_id] != NULL
1584          && ahc->enabled_targets[scsi_id] != master_tstate)
1585                 panic("%s: ahc_alloc_tstate - Target already allocated",
1586                       ahc_name(ahc));
1587         tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1588                                                    M_DEVBUF, M_NOWAIT);
1589         if (tstate == NULL)
1590                 return (NULL);
1591
1592         /*
1593          * If we have allocated a master tstate, copy user settings from
1594          * the master tstate (taken from SRAM or the EEPROM) for this
1595          * channel, but reset our current and goal settings to async/narrow
1596          * until an initiator talks to us.
1597          */
1598         if (master_tstate != NULL) {
1599                 memcpy(tstate, master_tstate, sizeof(*tstate));
1600                 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1601                 tstate->ultraenb = 0;
1602                 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1603                         memset(&tstate->transinfo[i].curr, 0,
1604                               sizeof(tstate->transinfo[i].curr));
1605                         memset(&tstate->transinfo[i].goal, 0,
1606                               sizeof(tstate->transinfo[i].goal));
1607                 }
1608         } else
1609                 memset(tstate, 0, sizeof(*tstate));
1610         ahc->enabled_targets[scsi_id] = tstate;
1611         return (tstate);
1612 }
1613
1614 #ifdef AHC_TARGET_MODE
1615 /*
1616  * Free per target mode instance (ID we respond to as a target)
1617  * transfer negotiation data structures.
1618  */
1619 static void
1620 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1621 {
1622         struct ahc_tmode_tstate *tstate;
1623
1624         /*
1625          * Don't clean up our "master" tstate.
1626          * It has our default user settings.
1627          */
1628         if (((channel == 'B' && scsi_id == ahc->our_id_b)
1629           || (channel == 'A' && scsi_id == ahc->our_id))
1630          && force == FALSE)
1631                 return;
1632
1633         if (channel == 'B')
1634                 scsi_id += 8;
1635         tstate = ahc->enabled_targets[scsi_id];
1636         if (tstate != NULL)
1637                 free(tstate, M_DEVBUF);
1638         ahc->enabled_targets[scsi_id] = NULL;
1639 }
1640 #endif
1641
1642 /*
1643  * Called when we have an active connection to a target on the bus,
1644  * this function finds the nearest syncrate to the input period limited
1645  * by the capabilities of the bus connectivity of and sync settings for
1646  * the target.
1647  */
1648 struct ahc_syncrate *
1649 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1650                         struct ahc_initiator_tinfo *tinfo,
1651                         u_int *period, u_int *ppr_options, role_t role)
1652 {
1653         struct  ahc_transinfo *transinfo;
1654         u_int   maxsync;
1655
1656         if ((ahc->features & AHC_ULTRA2) != 0) {
1657                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1658                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1659                         maxsync = AHC_SYNCRATE_DT;
1660                 } else {
1661                         maxsync = AHC_SYNCRATE_ULTRA;
1662                         /* Can't do DT on an SE bus */
1663                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1664                 }
1665         } else if ((ahc->features & AHC_ULTRA) != 0) {
1666                 maxsync = AHC_SYNCRATE_ULTRA;
1667         } else {
1668                 maxsync = AHC_SYNCRATE_FAST;
1669         }
1670         /*
1671          * Never allow a value higher than our current goal
1672          * period otherwise we may allow a target initiated
1673          * negotiation to go above the limit as set by the
1674          * user.  In the case of an initiator initiated
1675          * sync negotiation, we limit based on the user
1676          * setting.  This allows the system to still accept
1677          * incoming negotiations even if target initiated
1678          * negotiation is not performed.
1679          */
1680         if (role == ROLE_TARGET)
1681                 transinfo = &tinfo->user;
1682         else
1683                 transinfo = &tinfo->goal;
1684         *ppr_options &= transinfo->ppr_options;
1685         if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1686                 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1687                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1688         }
1689         if (transinfo->period == 0) {
1690                 *period = 0;
1691                 *ppr_options = 0;
1692                 return (NULL);
1693         }
1694         *period = MAX(*period, transinfo->period);
1695         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1696 }
1697
1698 /*
1699  * Look up the valid period to SCSIRATE conversion in our table.
1700  * Return the period and offset that should be sent to the target
1701  * if this was the beginning of an SDTR.
1702  */
1703 struct ahc_syncrate *
1704 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1705                   u_int *ppr_options, u_int maxsync)
1706 {
1707         struct ahc_syncrate *syncrate;
1708
1709         if ((ahc->features & AHC_DT) == 0)
1710                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1711
1712         /* Skip all DT only entries if DT is not available */
1713         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1714          && maxsync < AHC_SYNCRATE_ULTRA2)
1715                 maxsync = AHC_SYNCRATE_ULTRA2;
1716
1717         for (syncrate = &ahc_syncrates[maxsync];
1718              syncrate->rate != NULL;
1719              syncrate++) {
1720                 /*
1721                  * The Ultra2 table doesn't go as low
1722                  * as for the Fast/Ultra cards.
1723                  */
1724                 if ((ahc->features & AHC_ULTRA2) != 0
1725                  && (syncrate->sxfr_u2 == 0))
1726                         break;
1727
1728                 if (*period <= syncrate->period) {
1729                         /*
1730                          * When responding to a target that requests
1731                          * sync, the requested rate may fall between
1732                          * two rates that we can output, but still be
1733                          * a rate that we can receive.  Because of this,
1734                          * we want to respond to the target with
1735                          * the same rate that it sent to us even
1736                          * if the period we use to send data to it
1737                          * is lower.  Only lower the response period
1738                          * if we must.
1739                          */
1740                         if (syncrate == &ahc_syncrates[maxsync])
1741                                 *period = syncrate->period;
1742
1743                         /*
1744                          * At some speeds, we only support
1745                          * ST transfers.
1746                          */
1747                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1748                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1749                         break;
1750                 }
1751         }
1752
1753         if ((*period == 0)
1754          || (syncrate->rate == NULL)
1755          || ((ahc->features & AHC_ULTRA2) != 0
1756           && (syncrate->sxfr_u2 == 0))) {
1757                 /* Use asynchronous transfers. */
1758                 *period = 0;
1759                 syncrate = NULL;
1760                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1761         }
1762         return (syncrate);
1763 }
1764
1765 /*
1766  * Convert from an entry in our syncrate table to the SCSI equivalent
1767  * sync "period" factor.
1768  */
1769 u_int
1770 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1771 {
1772         struct ahc_syncrate *syncrate;
1773
1774         if ((ahc->features & AHC_ULTRA2) != 0)
1775                 scsirate &= SXFR_ULTRA2;
1776         else
1777                 scsirate &= SXFR;
1778
1779         syncrate = &ahc_syncrates[maxsync];
1780         while (syncrate->rate != NULL) {
1781                 if ((ahc->features & AHC_ULTRA2) != 0) {
1782                         if (syncrate->sxfr_u2 == 0)
1783                                 break;
1784                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1785                                 return (syncrate->period);
1786                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1787                                 return (syncrate->period);
1788                 }
1789                 syncrate++;
1790         }
1791         return (0); /* async */
1792 }
1793
1794 /*
1795  * Truncate the given synchronous offset to a value the
1796  * current adapter type and syncrate are capable of.
1797  */
1798 void
1799 ahc_validate_offset(struct ahc_softc *ahc,
1800                     struct ahc_initiator_tinfo *tinfo,
1801                     struct ahc_syncrate *syncrate,
1802                     u_int *offset, int wide, role_t role)
1803 {
1804         u_int maxoffset;
1805
1806         /* Limit offset to what we can do */
1807         if (syncrate == NULL) {
1808                 maxoffset = 0;
1809         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1810                 maxoffset = MAX_OFFSET_ULTRA2;
1811         } else {
1812                 if (wide)
1813                         maxoffset = MAX_OFFSET_16BIT;
1814                 else
1815                         maxoffset = MAX_OFFSET_8BIT;
1816         }
1817         *offset = MIN(*offset, maxoffset);
1818         if (tinfo != NULL) {
1819                 if (role == ROLE_TARGET)
1820                         *offset = MIN(*offset, tinfo->user.offset);
1821                 else
1822                         *offset = MIN(*offset, tinfo->goal.offset);
1823         }
1824 }
1825
1826 /*
1827  * Truncate the given transfer width parameter to a value the
1828  * current adapter type is capable of.
1829  */
1830 void
1831 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1832                    u_int *bus_width, role_t role)
1833 {
1834         switch (*bus_width) {
1835         default:
1836                 if (ahc->features & AHC_WIDE) {
1837                         /* Respond Wide */
1838                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1839                         break;
1840                 }
1841                 /* FALLTHROUGH */
1842         case MSG_EXT_WDTR_BUS_8_BIT:
1843                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1844                 break;
1845         }
1846         if (tinfo != NULL) {
1847                 if (role == ROLE_TARGET)
1848                         *bus_width = MIN(tinfo->user.width, *bus_width);
1849                 else
1850                         *bus_width = MIN(tinfo->goal.width, *bus_width);
1851         }
1852 }
1853
1854 /*
1855  * Update the bitmask of targets for which the controller should
1856  * negotiate with at the next convenient opportunity.  This currently
1857  * means the next time we send the initial identify messages for
1858  * a new transaction.
1859  */
1860 int
1861 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1862                        struct ahc_tmode_tstate *tstate,
1863                        struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1864 {
1865         u_int auto_negotiate_orig;
1866
1867         auto_negotiate_orig = tstate->auto_negotiate;
1868         if (neg_type == AHC_NEG_ALWAYS) {
1869                 /*
1870                  * Force our "current" settings to be
1871                  * unknown so that unless a bus reset
1872                  * occurs the need to renegotiate is
1873                  * recorded persistently.
1874                  */
1875                 if ((ahc->features & AHC_WIDE) != 0)
1876                         tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1877                 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1878                 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1879         }
1880         if (tinfo->curr.period != tinfo->goal.period
1881          || tinfo->curr.width != tinfo->goal.width
1882          || tinfo->curr.offset != tinfo->goal.offset
1883          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1884          || (neg_type == AHC_NEG_IF_NON_ASYNC
1885           && (tinfo->goal.offset != 0
1886            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1887            || tinfo->goal.ppr_options != 0)))
1888                 tstate->auto_negotiate |= devinfo->target_mask;
1889         else
1890                 tstate->auto_negotiate &= ~devinfo->target_mask;
1891
1892         return (auto_negotiate_orig != tstate->auto_negotiate);
1893 }
1894
1895 /*
1896  * Update the user/goal/curr tables of synchronous negotiation
1897  * parameters as well as, in the case of a current or active update,
1898  * any data structures on the host controller.  In the case of an
1899  * active update, the specified target is currently talking to us on
1900  * the bus, so the transfer parameter update must take effect
1901  * immediately.
1902  */
1903 void
1904 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1905                  struct ahc_syncrate *syncrate, u_int period,
1906                  u_int offset, u_int ppr_options, u_int type, int paused)
1907 {
1908         struct  ahc_initiator_tinfo *tinfo;
1909         struct  ahc_tmode_tstate *tstate;
1910         u_int   old_period;
1911         u_int   old_offset;
1912         u_int   old_ppr;
1913         int     active;
1914         int     update_needed;
1915
1916         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1917         update_needed = 0;
1918
1919         if (syncrate == NULL) {
1920                 period = 0;
1921                 offset = 0;
1922         }
1923
1924         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1925                                     devinfo->target, &tstate);
1926
1927         if ((type & AHC_TRANS_USER) != 0) {
1928                 tinfo->user.period = period;
1929                 tinfo->user.offset = offset;
1930                 tinfo->user.ppr_options = ppr_options;
1931         }
1932
1933         if ((type & AHC_TRANS_GOAL) != 0) {
1934                 tinfo->goal.period = period;
1935                 tinfo->goal.offset = offset;
1936                 tinfo->goal.ppr_options = ppr_options;
1937         }
1938
1939         old_period = tinfo->curr.period;
1940         old_offset = tinfo->curr.offset;
1941         old_ppr    = tinfo->curr.ppr_options;
1942
1943         if ((type & AHC_TRANS_CUR) != 0
1944          && (old_period != period
1945           || old_offset != offset
1946           || old_ppr != ppr_options)) {
1947                 u_int   scsirate;
1948
1949                 update_needed++;
1950                 scsirate = tinfo->scsirate;
1951                 if ((ahc->features & AHC_ULTRA2) != 0) {
1952                         scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1953                         if (syncrate != NULL) {
1954                                 scsirate |= syncrate->sxfr_u2;
1955                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1956                                         scsirate |= ENABLE_CRC;
1957                                 else
1958                                         scsirate |= SINGLE_EDGE;
1959                         }
1960                 } else {
1961                         scsirate &= ~(SXFR|SOFS);
1962                         /*
1963                          * Ensure Ultra mode is set properly for
1964                          * this target.
1965                          */
1966                         tstate->ultraenb &= ~devinfo->target_mask;
1967                         if (syncrate != NULL) {
1968                                 if (syncrate->sxfr & ULTRA_SXFR) {
1969                                         tstate->ultraenb |=
1970                                                 devinfo->target_mask;
1971                                 }
1972                                 scsirate |= syncrate->sxfr & SXFR;
1973                                 scsirate |= offset & SOFS;
1974                         }
1975                         if (active) {
1976                                 u_int sxfrctl0;
1977
1978                                 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1979                                 sxfrctl0 &= ~FAST20;
1980                                 if (tstate->ultraenb & devinfo->target_mask)
1981                                         sxfrctl0 |= FAST20;
1982                                 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1983                         }
1984                 }
1985                 if (active) {
1986                         ahc_outb(ahc, SCSIRATE, scsirate);
1987                         if ((ahc->features & AHC_ULTRA2) != 0)
1988                                 ahc_outb(ahc, SCSIOFFSET, offset);
1989                 }
1990
1991                 tinfo->scsirate = scsirate;
1992                 tinfo->curr.period = period;
1993                 tinfo->curr.offset = offset;
1994                 tinfo->curr.ppr_options = ppr_options;
1995
1996                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1997                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1998                 if (bootverbose) {
1999                         if (offset != 0) {
2000                                 printf("%s: target %d synchronous at %sMHz%s, "
2001                                        "offset = 0x%x\n", ahc_name(ahc),
2002                                        devinfo->target, syncrate->rate,
2003                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
2004                                        ? " DT" : "", offset);
2005                         } else {
2006                                 printf("%s: target %d using "
2007                                        "asynchronous transfers\n",
2008                                        ahc_name(ahc), devinfo->target);
2009                         }
2010                 }
2011         }
2012
2013         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2014                                                 tinfo, AHC_NEG_TO_GOAL);
2015
2016         if (update_needed)
2017                 ahc_update_pending_scbs(ahc);
2018 }
2019
2020 /*
2021  * Update the user/goal/curr tables of wide negotiation
2022  * parameters as well as, in the case of a current or active update,
2023  * any data structures on the host controller.  In the case of an
2024  * active update, the specified target is currently talking to us on
2025  * the bus, so the transfer parameter update must take effect
2026  * immediately.
2027  */
2028 void
2029 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2030               u_int width, u_int type, int paused)
2031 {
2032         struct  ahc_initiator_tinfo *tinfo;
2033         struct  ahc_tmode_tstate *tstate;
2034         u_int   oldwidth;
2035         int     active;
2036         int     update_needed;
2037
2038         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2039         update_needed = 0;
2040         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2041                                     devinfo->target, &tstate);
2042
2043         if ((type & AHC_TRANS_USER) != 0)
2044                 tinfo->user.width = width;
2045
2046         if ((type & AHC_TRANS_GOAL) != 0)
2047                 tinfo->goal.width = width;
2048
2049         oldwidth = tinfo->curr.width;
2050         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2051                 u_int   scsirate;
2052
2053                 update_needed++;
2054                 scsirate =  tinfo->scsirate;
2055                 scsirate &= ~WIDEXFER;
2056                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2057                         scsirate |= WIDEXFER;
2058
2059                 tinfo->scsirate = scsirate;
2060
2061                 if (active)
2062                         ahc_outb(ahc, SCSIRATE, scsirate);
2063
2064                 tinfo->curr.width = width;
2065
2066                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2067                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2068                 if (bootverbose) {
2069                         printf("%s: target %d using %dbit transfers\n",
2070                                ahc_name(ahc), devinfo->target,
2071                                8 * (0x01 << width));
2072                 }
2073         }
2074
2075         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2076                                                 tinfo, AHC_NEG_TO_GOAL);
2077         if (update_needed)
2078                 ahc_update_pending_scbs(ahc);
2079 }
2080
2081 /*
2082  * Update the current state of tagged queuing for a given target.
2083  */
2084 void
2085 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2086              ahc_queue_alg alg)
2087 {
2088         ahc_platform_set_tags(ahc, devinfo, alg);
2089         ahc_send_async(ahc, devinfo->channel, devinfo->target,
2090                        devinfo->lun, AC_TRANSFER_NEG, &alg);
2091 }
2092
2093 /*
2094  * When the transfer settings for a connection change, update any
2095  * in-transit SCBs to contain the new data so the hardware will
2096  * be set correctly during future (re)selections.
2097  */
2098 static void
2099 ahc_update_pending_scbs(struct ahc_softc *ahc)
2100 {
2101         struct  scb *pending_scb;
2102         int     pending_scb_count;
2103         int     i;
2104         int     paused;
2105         u_int   saved_scbptr;
2106
2107         /*
2108          * Traverse the pending SCB list and ensure that all of the
2109          * SCBs there have the proper settings.
2110          */
2111         pending_scb_count = 0;
2112         LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2113                 struct ahc_devinfo devinfo;
2114                 struct hardware_scb *pending_hscb;
2115                 struct ahc_initiator_tinfo *tinfo;
2116                 struct ahc_tmode_tstate *tstate;
2117
2118                 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2119                 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2120                                             devinfo.our_scsiid,
2121                                             devinfo.target, &tstate);
2122                 pending_hscb = pending_scb->hscb;
2123                 pending_hscb->control &= ~ULTRAENB;
2124                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2125                         pending_hscb->control |= ULTRAENB;
2126                 pending_hscb->scsirate = tinfo->scsirate;
2127                 pending_hscb->scsioffset = tinfo->curr.offset;
2128                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2129                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2130                         pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2131                         pending_hscb->control &= ~MK_MESSAGE;
2132                 }
2133                 ahc_sync_scb(ahc, pending_scb,
2134                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2135                 pending_scb_count++;
2136         }
2137
2138         if (pending_scb_count == 0)
2139                 return;
2140
2141         if (ahc_is_paused(ahc)) {
2142                 paused = 1;
2143         } else {
2144                 paused = 0;
2145                 ahc_pause(ahc);
2146         }
2147
2148         saved_scbptr = ahc_inb(ahc, SCBPTR);
2149         /* Ensure that the hscbs down on the card match the new information */
2150         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2151                 struct  hardware_scb *pending_hscb;
2152                 u_int   control;
2153                 u_int   scb_tag;
2154
2155                 ahc_outb(ahc, SCBPTR, i);
2156                 scb_tag = ahc_inb(ahc, SCB_TAG);
2157                 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2158                 if (pending_scb == NULL)
2159                         continue;
2160
2161                 pending_hscb = pending_scb->hscb;
2162                 control = ahc_inb(ahc, SCB_CONTROL);
2163                 control &= ~(ULTRAENB|MK_MESSAGE);
2164                 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2165                 ahc_outb(ahc, SCB_CONTROL, control);
2166                 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2167                 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2168         }
2169         ahc_outb(ahc, SCBPTR, saved_scbptr);
2170
2171         if (paused == 0)
2172                 ahc_unpause(ahc);
2173 }
2174
2175 /**************************** Pathing Information *****************************/
2176 static void
2177 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2178 {
2179         u_int   saved_scsiid;
2180         role_t  role;
2181         int     our_id;
2182
2183         if (ahc_inb(ahc, SSTAT0) & TARGET)
2184                 role = ROLE_TARGET;
2185         else
2186                 role = ROLE_INITIATOR;
2187
2188         if (role == ROLE_TARGET
2189          && (ahc->features & AHC_MULTI_TID) != 0
2190          && (ahc_inb(ahc, SEQ_FLAGS)
2191            & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2192                 /* We were selected, so pull our id from TARGIDIN */
2193                 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2194         } else if ((ahc->features & AHC_ULTRA2) != 0)
2195                 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2196         else
2197                 our_id = ahc_inb(ahc, SCSIID) & OID;
2198
2199         saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2200         ahc_compile_devinfo(devinfo,
2201                             our_id,
2202                             SCSIID_TARGET(ahc, saved_scsiid),
2203                             ahc_inb(ahc, SAVED_LUN),
2204                             SCSIID_CHANNEL(ahc, saved_scsiid),
2205                             role);
2206 }
2207
2208 struct ahc_phase_table_entry*
2209 ahc_lookup_phase_entry(int phase)
2210 {
2211         struct ahc_phase_table_entry *entry;
2212         struct ahc_phase_table_entry *last_entry;
2213
2214         /*
2215          * num_phases doesn't include the default entry which
2216          * will be returned if the phase doesn't match.
2217          */
2218         last_entry = &ahc_phase_table[num_phases];
2219         for (entry = ahc_phase_table; entry < last_entry; entry++) {
2220                 if (phase == entry->phase)
2221                         break;
2222         }
2223         return (entry);
2224 }
2225
2226 void
2227 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2228                     u_int lun, char channel, role_t role)
2229 {
2230         devinfo->our_scsiid = our_id;
2231         devinfo->target = target;
2232         devinfo->lun = lun;
2233         devinfo->target_offset = target;
2234         devinfo->channel = channel;
2235         devinfo->role = role;
2236         if (channel == 'B')
2237                 devinfo->target_offset += 8;
2238         devinfo->target_mask = (0x01 << devinfo->target_offset);
2239 }
2240
2241 void
2242 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2243 {
2244         printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2245                devinfo->target, devinfo->lun);
2246 }
2247
2248 static void
2249 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2250                 struct scb *scb)
2251 {
2252         role_t  role;
2253         int     our_id;
2254
2255         our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2256         role = ROLE_INITIATOR;
2257         if ((scb->flags & SCB_TARGET_SCB) != 0)
2258                 role = ROLE_TARGET;
2259         ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2260                             SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2261 }
2262
2263 /************************ Message Phase Processing ****************************/
2264 static void
2265 ahc_assert_atn(struct ahc_softc *ahc)
2266 {
2267         u_int scsisigo;
2268
2269         scsisigo = ATNO;
2270         if ((ahc->features & AHC_DT) == 0)
2271                 scsisigo |= ahc_inb(ahc, SCSISIGI);
2272         ahc_outb(ahc, SCSISIGO, scsisigo);
2273 }
2274
2275 /*
2276  * When an initiator transaction with the MK_MESSAGE flag either reconnects
2277  * or enters the initial message out phase, we are interrupted.  Fill our
2278  * outgoing message buffer with the appropriate message and beging handing
2279  * the message phase(s) manually.
2280  */
2281 static void
2282 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2283                            struct scb *scb)
2284 {
2285         /*
2286          * To facilitate adding multiple messages together,
2287          * each routine should increment the index and len
2288          * variables instead of setting them explicitly.
2289          */
2290         ahc->msgout_index = 0;
2291         ahc->msgout_len = 0;
2292
2293         if ((scb->flags & SCB_DEVICE_RESET) == 0
2294          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2295                 u_int identify_msg;
2296
2297                 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2298                 if ((scb->hscb->control & DISCENB) != 0)
2299                         identify_msg |= MSG_IDENTIFY_DISCFLAG;
2300                 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2301                 ahc->msgout_len++;
2302
2303                 if ((scb->hscb->control & TAG_ENB) != 0) {
2304                         ahc->msgout_buf[ahc->msgout_index++] =
2305                             scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2306                         ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2307                         ahc->msgout_len += 2;
2308                 }
2309         }
2310
2311         if (scb->flags & SCB_DEVICE_RESET) {
2312                 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2313                 ahc->msgout_len++;
2314                 ahc_print_path(ahc, scb);
2315                 printf("Bus Device Reset Message Sent\n");
2316                 /*
2317                  * Clear our selection hardware in advance of
2318                  * the busfree.  We may have an entry in the waiting
2319                  * Q for this target, and we don't want to go about
2320                  * selecting while we handle the busfree and blow it
2321                  * away.
2322                  */
2323                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2324         } else if ((scb->flags & SCB_ABORT) != 0) {
2325                 if ((scb->hscb->control & TAG_ENB) != 0)
2326                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2327                 else
2328                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2329                 ahc->msgout_len++;
2330                 ahc_print_path(ahc, scb);
2331                 printf("Abort%s Message Sent\n",
2332                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2333                 /*
2334                  * Clear our selection hardware in advance of
2335                  * the busfree.  We may have an entry in the waiting
2336                  * Q for this target, and we don't want to go about
2337                  * selecting while we handle the busfree and blow it
2338                  * away.
2339                  */
2340                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2341         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2342                 ahc_build_transfer_msg(ahc, devinfo);
2343         } else {
2344                 printf("ahc_intr: AWAITING_MSG for an SCB that "
2345                        "does not have a waiting message\n");
2346                 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2347                        devinfo->target_mask);
2348                 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2349                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2350                       ahc_inb(ahc, MSG_OUT), scb->flags);
2351         }
2352
2353         /*
2354          * Clear the MK_MESSAGE flag from the SCB so we aren't
2355          * asked to send this message again.
2356          */
2357         ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2358         scb->hscb->control &= ~MK_MESSAGE;
2359         ahc->msgout_index = 0;
2360         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2361 }
2362
2363 /*
2364  * Build an appropriate transfer negotiation message for the
2365  * currently active target.
2366  */
2367 static void
2368 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2369 {
2370         /*
2371          * We need to initiate transfer negotiations.
2372          * If our current and goal settings are identical,
2373          * we want to renegotiate due to a check condition.
2374          */
2375         struct  ahc_initiator_tinfo *tinfo;
2376         struct  ahc_tmode_tstate *tstate;
2377         struct  ahc_syncrate *rate;
2378         int     dowide;
2379         int     dosync;
2380         int     doppr;
2381         u_int   period;
2382         u_int   ppr_options;
2383         u_int   offset;
2384
2385         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2386                                     devinfo->target, &tstate);
2387         /*
2388          * Filter our period based on the current connection.
2389          * If we can't perform DT transfers on this segment (not in LVD
2390          * mode for instance), then our decision to issue a PPR message
2391          * may change.
2392          */
2393         period = tinfo->goal.period;
2394         offset = tinfo->goal.offset;
2395         ppr_options = tinfo->goal.ppr_options;
2396         /* Target initiated PPR is not allowed in the SCSI spec */
2397         if (devinfo->role == ROLE_TARGET)
2398                 ppr_options = 0;
2399         rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2400                                        &ppr_options, devinfo->role);
2401         dowide = tinfo->curr.width != tinfo->goal.width;
2402         dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2403         /*
2404          * Only use PPR if we have options that need it, even if the device
2405          * claims to support it.  There might be an expander in the way
2406          * that doesn't.
2407          */
2408         doppr = ppr_options != 0;
2409
2410         if (!dowide && !dosync && !doppr) {
2411                 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2412                 dosync = tinfo->goal.offset != 0;
2413         }
2414
2415         if (!dowide && !dosync && !doppr) {
2416                 /*
2417                  * Force async with a WDTR message if we have a wide bus,
2418                  * or just issue an SDTR with a 0 offset.
2419                  */
2420                 if ((ahc->features & AHC_WIDE) != 0)
2421                         dowide = 1;
2422                 else
2423                         dosync = 1;
2424
2425                 if (bootverbose) {
2426                         ahc_print_devinfo(ahc, devinfo);
2427                         printf("Ensuring async\n");
2428                 }
2429         }
2430
2431         /* Target initiated PPR is not allowed in the SCSI spec */
2432         if (devinfo->role == ROLE_TARGET)
2433                 doppr = 0;
2434
2435         /*
2436          * Both the PPR message and SDTR message require the
2437          * goal syncrate to be limited to what the target device
2438          * is capable of handling (based on whether an LVD->SE
2439          * expander is on the bus), so combine these two cases.
2440          * Regardless, guarantee that if we are using WDTR and SDTR
2441          * messages that WDTR comes first.
2442          */
2443         if (doppr || (dosync && !dowide)) {
2444                 offset = tinfo->goal.offset;
2445                 ahc_validate_offset(ahc, tinfo, rate, &offset,
2446                                     doppr ? tinfo->goal.width
2447                                           : tinfo->curr.width,
2448                                     devinfo->role);
2449                 if (doppr) {
2450                         ahc_construct_ppr(ahc, devinfo, period, offset,
2451                                           tinfo->goal.width, ppr_options);
2452                 } else {
2453                         ahc_construct_sdtr(ahc, devinfo, period, offset);
2454                 }
2455         } else {
2456                 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2457         }
2458 }
2459
2460 /*
2461  * Build a synchronous negotiation message in our message
2462  * buffer based on the input parameters.
2463  */
2464 static void
2465 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2466                    u_int period, u_int offset)
2467 {
2468         if (offset == 0)
2469                 period = AHC_ASYNC_XFER_PERIOD;
2470         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2471         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2472         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2473         ahc->msgout_buf[ahc->msgout_index++] = period;
2474         ahc->msgout_buf[ahc->msgout_index++] = offset;
2475         ahc->msgout_len += 5;
2476         if (bootverbose) {
2477                 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2478                        ahc_name(ahc), devinfo->channel, devinfo->target,
2479                        devinfo->lun, period, offset);
2480         }
2481 }
2482
2483 /*
2484  * Build a wide negotiation message in our message
2485  * buffer based on the input parameters.
2486  */
2487 static void
2488 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2489                    u_int bus_width)
2490 {
2491         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2492         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2493         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2494         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2495         ahc->msgout_len += 4;
2496         if (bootverbose) {
2497                 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2498                        ahc_name(ahc), devinfo->channel, devinfo->target,
2499                        devinfo->lun, bus_width);
2500         }
2501 }
2502
2503 /*
2504  * Build a parallel protocol request message in our message
2505  * buffer based on the input parameters.
2506  */
2507 static void
2508 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2509                   u_int period, u_int offset, u_int bus_width,
2510                   u_int ppr_options)
2511 {
2512         if (offset == 0)
2513                 period = AHC_ASYNC_XFER_PERIOD;
2514         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2515         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2516         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2517         ahc->msgout_buf[ahc->msgout_index++] = period;
2518         ahc->msgout_buf[ahc->msgout_index++] = 0;
2519         ahc->msgout_buf[ahc->msgout_index++] = offset;
2520         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2521         ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2522         ahc->msgout_len += 8;
2523         if (bootverbose) {
2524                 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2525                        "offset %x, ppr_options %x\n", ahc_name(ahc),
2526                        devinfo->channel, devinfo->target, devinfo->lun,
2527                        bus_width, period, offset, ppr_options);
2528         }
2529 }
2530
2531 /*
2532  * Clear any active message state.
2533  */
2534 static void
2535 ahc_clear_msg_state(struct ahc_softc *ahc)
2536 {
2537         ahc->msgout_len = 0;
2538         ahc->msgin_index = 0;
2539         ahc->msg_type = MSG_TYPE_NONE;
2540         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2541                 /*
2542                  * The target didn't care to respond to our
2543                  * message request, so clear ATN.
2544                  */
2545                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2546         }
2547         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2548         ahc_outb(ahc, SEQ_FLAGS2,
2549                  ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2550 }
2551
2552 static void
2553 ahc_handle_proto_violation(struct ahc_softc *ahc)
2554 {
2555         struct  ahc_devinfo devinfo;
2556         struct  scb *scb;
2557         u_int   scbid;
2558         u_int   seq_flags;
2559         u_int   curphase;
2560         u_int   lastphase;
2561         int     found;
2562
2563         ahc_fetch_devinfo(ahc, &devinfo);
2564         scbid = ahc_inb(ahc, SCB_TAG);
2565         scb = ahc_lookup_scb(ahc, scbid);
2566         seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2567         curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2568         lastphase = ahc_inb(ahc, LASTPHASE);
2569         if ((seq_flags & NOT_IDENTIFIED) != 0) {
2570                 /*
2571                  * The reconnecting target either did not send an
2572                  * identify message, or did, but we didn't find an SCB
2573                  * to match.
2574                  */
2575                 ahc_print_devinfo(ahc, &devinfo);
2576                 printf("Target did not send an IDENTIFY message. "
2577                        "LASTPHASE = 0x%x.\n", lastphase);
2578                 scb = NULL;
2579         } else if (scb == NULL) {
2580                 /*
2581                  * We don't seem to have an SCB active for this
2582                  * transaction.  Print an error and reset the bus.
2583                  */
2584                 ahc_print_devinfo(ahc, &devinfo);
2585                 printf("No SCB found during protocol violation\n");
2586                 goto proto_violation_reset;
2587         } else {
2588                 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2589                 if ((seq_flags & NO_CDB_SENT) != 0) {
2590                         ahc_print_path(ahc, scb);
2591                         printf("No or incomplete CDB sent to device.\n");
2592                 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2593                         /*
2594                          * The target never bothered to provide status to
2595                          * us prior to completing the command.  Since we don't
2596                          * know the disposition of this command, we must attempt
2597                          * to abort it.  Assert ATN and prepare to send an abort
2598                          * message.
2599                          */
2600                         ahc_print_path(ahc, scb);
2601                         printf("Completed command without status.\n");
2602                 } else {
2603                         ahc_print_path(ahc, scb);
2604                         printf("Unknown protocol violation.\n");
2605                         ahc_dump_card_state(ahc);
2606                 }
2607         }
2608         if ((lastphase & ~P_DATAIN_DT) == 0
2609          || lastphase == P_COMMAND) {
2610 proto_violation_reset:
2611                 /*
2612                  * Target either went directly to data/command
2613                  * phase or didn't respond to our ATN.
2614                  * The only safe thing to do is to blow
2615                  * it away with a bus reset.
2616                  */
2617                 found = ahc_reset_channel(ahc, 'A', TRUE);
2618                 printf("%s: Issued Channel %c Bus Reset. "
2619                        "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2620         } else {
2621                 /*
2622                  * Leave the selection hardware off in case
2623                  * this abort attempt will affect yet to
2624                  * be sent commands.
2625                  */
2626                 ahc_outb(ahc, SCSISEQ,
2627                          ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2628                 ahc_assert_atn(ahc);
2629                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2630                 if (scb == NULL) {
2631                         ahc_print_devinfo(ahc, &devinfo);
2632                         ahc->msgout_buf[0] = MSG_ABORT_TASK;
2633                         ahc->msgout_len = 1;
2634                         ahc->msgout_index = 0;
2635                         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2636                 } else {
2637                         ahc_print_path(ahc, scb);
2638                         scb->flags |= SCB_ABORT;
2639                 }
2640                 printf("Protocol violation %s.  Attempting to abort.\n",
2641                        ahc_lookup_phase_entry(curphase)->phasemsg);
2642         }
2643 }
2644
2645 /*
2646  * Manual message loop handler.
2647  */
2648 static void
2649 ahc_handle_message_phase(struct ahc_softc *ahc)
2650 {
2651         struct  ahc_devinfo devinfo;
2652         u_int   bus_phase;
2653         int     end_session;
2654
2655         ahc_fetch_devinfo(ahc, &devinfo);
2656         end_session = FALSE;
2657         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2658
2659 reswitch:
2660         switch (ahc->msg_type) {
2661         case MSG_TYPE_INITIATOR_MSGOUT:
2662         {
2663                 int lastbyte;
2664                 int phasemis;
2665                 int msgdone;
2666
2667                 if (ahc->msgout_len == 0)
2668                         panic("HOST_MSG_LOOP interrupt with no active message");
2669
2670 #ifdef AHC_DEBUG
2671                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2672                         ahc_print_devinfo(ahc, &devinfo);
2673                         printf("INITIATOR_MSG_OUT");
2674                 }
2675 #endif
2676                 phasemis = bus_phase != P_MESGOUT;
2677                 if (phasemis) {
2678 #ifdef AHC_DEBUG
2679                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2680                                 printf(" PHASEMIS %s\n",
2681                                        ahc_lookup_phase_entry(bus_phase)
2682                                                              ->phasemsg);
2683                         }
2684 #endif
2685                         if (bus_phase == P_MESGIN) {
2686                                 /*
2687                                  * Change gears and see if
2688                                  * this messages is of interest to
2689                                  * us or should be passed back to
2690                                  * the sequencer.
2691                                  */
2692                                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2693                                 ahc->send_msg_perror = FALSE;
2694                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2695                                 ahc->msgin_index = 0;
2696                                 goto reswitch;
2697                         }
2698                         end_session = TRUE;
2699                         break;
2700                 }
2701
2702                 if (ahc->send_msg_perror) {
2703                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2704                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2705 #ifdef AHC_DEBUG
2706                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2707                                 printf(" byte 0x%x\n", ahc->send_msg_perror);
2708 #endif
2709                         ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2710                         break;
2711                 }
2712
2713                 msgdone = ahc->msgout_index == ahc->msgout_len;
2714                 if (msgdone) {
2715                         /*
2716                          * The target has requested a retry.
2717                          * Re-assert ATN, reset our message index to
2718                          * 0, and try again.
2719                          */
2720                         ahc->msgout_index = 0;
2721                         ahc_assert_atn(ahc);
2722                 }
2723
2724                 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2725                 if (lastbyte) {
2726                         /* Last byte is signified by dropping ATN */
2727                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2728                 }
2729
2730                 /*
2731                  * Clear our interrupt status and present
2732                  * the next byte on the bus.
2733                  */
2734                 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2735 #ifdef AHC_DEBUG
2736                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2737                         printf(" byte 0x%x\n",
2738                                ahc->msgout_buf[ahc->msgout_index]);
2739 #endif
2740                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2741                 break;
2742         }
2743         case MSG_TYPE_INITIATOR_MSGIN:
2744         {
2745                 int phasemis;
2746                 int message_done;
2747
2748 #ifdef AHC_DEBUG
2749                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2750                         ahc_print_devinfo(ahc, &devinfo);
2751                         printf("INITIATOR_MSG_IN");
2752                 }
2753 #endif
2754                 phasemis = bus_phase != P_MESGIN;
2755                 if (phasemis) {
2756 #ifdef AHC_DEBUG
2757                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2758                                 printf(" PHASEMIS %s\n",
2759                                        ahc_lookup_phase_entry(bus_phase)
2760                                                              ->phasemsg);
2761                         }
2762 #endif
2763                         ahc->msgin_index = 0;
2764                         if (bus_phase == P_MESGOUT
2765                          && (ahc->send_msg_perror == TRUE
2766                           || (ahc->msgout_len != 0
2767                            && ahc->msgout_index == 0))) {
2768                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2769                                 goto reswitch;
2770                         }
2771                         end_session = TRUE;
2772                         break;
2773                 }
2774
2775                 /* Pull the byte in without acking it */
2776                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2777 #ifdef AHC_DEBUG
2778                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2779                         printf(" byte 0x%x\n",
2780                                ahc->msgin_buf[ahc->msgin_index]);
2781 #endif
2782
2783                 message_done = ahc_parse_msg(ahc, &devinfo);
2784
2785                 if (message_done) {
2786                         /*
2787                          * Clear our incoming message buffer in case there
2788                          * is another message following this one.
2789                          */
2790                         ahc->msgin_index = 0;
2791
2792                         /*
2793                          * If this message illicited a response,
2794                          * assert ATN so the target takes us to the
2795                          * message out phase.
2796                          */
2797                         if (ahc->msgout_len != 0) {
2798 #ifdef AHC_DEBUG
2799                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2800                                         ahc_print_devinfo(ahc, &devinfo);
2801                                         printf("Asserting ATN for response\n");
2802                                 }
2803 #endif
2804                                 ahc_assert_atn(ahc);
2805                         }
2806                 } else
2807                         ahc->msgin_index++;
2808
2809                 if (message_done == MSGLOOP_TERMINATED) {
2810                         end_session = TRUE;
2811                 } else {
2812                         /* Ack the byte */
2813                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2814                         ahc_inb(ahc, SCSIDATL);
2815                 }
2816                 break;
2817         }
2818         case MSG_TYPE_TARGET_MSGIN:
2819         {
2820                 int msgdone;
2821
2822                 if (ahc->msgout_len == 0)
2823                         panic("Target MSGIN with no active message");
2824
2825 #ifdef AHC_DEBUG
2826                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2827                         ahc_print_devinfo(ahc, &devinfo);
2828                         printf("TARGET_MSG_IN");
2829                 }
2830 #endif
2831
2832                 /*
2833                  * If we interrupted a mesgout session, the initiator
2834                  * will not know this until our first REQ.  So, we
2835                  * only honor mesgout requests after we've sent our
2836                  * first byte.
2837                  */
2838                 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2839                  && ahc->msgout_index > 0) {
2840                         /*
2841                          * Change gears and see if this messages is
2842                          * of interest to us or should be passed back
2843                          * to the sequencer.
2844                          */
2845 #ifdef AHC_DEBUG
2846                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2847                                 printf(" Honoring ATN Request.\n");
2848 #endif
2849                         ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2850
2851                         /*
2852                          * Disable SCSI Programmed I/O during the
2853                          * phase change so as to avoid phantom REQs.
2854                          */
2855                         ahc_outb(ahc, SXFRCTL0,
2856                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2857
2858                         /*
2859                          * Since SPIORDY asserts when ACK is asserted
2860                          * for P_MSGOUT, and SPIORDY's assertion triggered
2861                          * our entry into this routine, wait for ACK to
2862                          * *de-assert* before changing phases.
2863                          */
2864                         while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2865                                 ;
2866
2867                         ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2868
2869                         /*
2870                          * All phase line changes require a bus
2871                          * settle delay before REQ is asserted.
2872                          * [SCSI SPI4 10.7.1]
2873                          */
2874                         ahc_flush_device_writes(ahc);
2875                         aic_delay(AHC_BUSSETTLE_DELAY);
2876
2877                         ahc->msgin_index = 0;
2878                         /* Enable SCSI Programmed I/O to REQ for first byte */
2879                         ahc_outb(ahc, SXFRCTL0,
2880                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2881                         break;
2882                 }
2883
2884                 msgdone = ahc->msgout_index == ahc->msgout_len;
2885                 if (msgdone) {
2886                         ahc_outb(ahc, SXFRCTL0,
2887                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2888                         end_session = TRUE;
2889                         break;
2890                 }
2891
2892                 /*
2893                  * Present the next byte on the bus.
2894                  */
2895 #ifdef AHC_DEBUG
2896                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2897                         printf(" byte 0x%x\n",
2898                                ahc->msgout_buf[ahc->msgout_index]);
2899 #endif
2900                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2901                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2902                 break;
2903         }
2904         case MSG_TYPE_TARGET_MSGOUT:
2905         {
2906                 int lastbyte;
2907                 int msgdone;
2908
2909 #ifdef AHC_DEBUG
2910                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2911                         ahc_print_devinfo(ahc, &devinfo);
2912                         printf("TARGET_MSG_OUT");
2913                 }
2914 #endif
2915                 /*
2916                  * The initiator signals that this is
2917                  * the last byte by dropping ATN.
2918                  */
2919                 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2920
2921                 /*
2922                  * Read the latched byte, but turn off SPIOEN first
2923                  * so that we don't inadvertently cause a REQ for the
2924                  * next byte.
2925                  */
2926                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2927                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2928
2929 #ifdef AHC_DEBUG
2930                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2931                         printf(" byte 0x%x\n",
2932                                ahc->msgin_buf[ahc->msgin_index]);
2933 #endif
2934
2935                 msgdone = ahc_parse_msg(ahc, &devinfo);
2936                 if (msgdone == MSGLOOP_TERMINATED) {
2937                         /*
2938                          * The message is *really* done in that it caused
2939                          * us to go to bus free.  The sequencer has already
2940                          * been reset at this point, so pull the ejection
2941                          * handle.
2942                          */
2943                         return;
2944                 }
2945
2946                 ahc->msgin_index++;
2947
2948                 /*
2949                  * XXX Read spec about initiator dropping ATN too soon
2950                  *     and use msgdone to detect it.
2951                  */
2952                 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2953                         ahc->msgin_index = 0;
2954
2955                         /*
2956                          * If this message illicited a response, transition
2957                          * to the Message in phase and send it.
2958                          */
2959                         if (ahc->msgout_len != 0) {
2960 #ifdef AHC_DEBUG
2961                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2962                                         ahc_print_devinfo(ahc, &devinfo);
2963                                         printf(" preparing response.\n");
2964                                 }
2965 #endif
2966                                 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2967
2968                                 /*
2969                                  * All phase line changes require a bus
2970                                  * settle delay before REQ is asserted.
2971                                  * [SCSI SPI4 10.7.1]  When transitioning
2972                                  * from an OUT to an IN phase, we must
2973                                  * also wait a data release delay to allow
2974                                  * the initiator time to release the data
2975                                  * lines. [SCSI SPI4 10.12]
2976                                  */
2977                                 ahc_flush_device_writes(ahc);
2978                                 aic_delay(AHC_BUSSETTLE_DELAY
2979                                         + AHC_DATARELEASE_DELAY);
2980
2981                                 /*
2982                                  * Enable SCSI Programmed I/O.  This will
2983                                  * immediately cause SPIORDY to assert,
2984                                  * and the sequencer will call our message
2985                                  * loop again.
2986                                  */
2987                                 ahc_outb(ahc, SXFRCTL0,
2988                                          ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2989                                 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2990                                 ahc->msgin_index = 0;
2991                                 break;
2992                         }
2993                 }
2994
2995                 if (lastbyte)
2996                         end_session = TRUE;
2997                 else {
2998                         /* Ask for the next byte. */
2999                         ahc_outb(ahc, SXFRCTL0,
3000                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3001                 }
3002
3003                 break;
3004         }
3005         default:
3006                 panic("Unknown REQINIT message type");
3007         }
3008
3009         if (end_session) {
3010                 ahc_clear_msg_state(ahc);
3011                 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3012         } else
3013                 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3014 }
3015
3016 /*
3017  * See if we sent a particular extended message to the target.
3018  * If "full" is true, return true only if the target saw the full
3019  * message.  If "full" is false, return true if the target saw at
3020  * least the first byte of the message.
3021  */
3022 static int
3023 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3024 {
3025         int found;
3026         u_int index;
3027
3028         found = FALSE;
3029         index = 0;
3030
3031         while (index < ahc->msgout_len) {
3032                 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3033                         u_int end_index;
3034
3035                         end_index = index + 1 + ahc->msgout_buf[index + 1];
3036                         if (ahc->msgout_buf[index+2] == msgval
3037                          && type == AHCMSG_EXT) {
3038                                 if (full) {
3039                                         if (ahc->msgout_index > end_index)
3040                                                 found = TRUE;
3041                                 } else if (ahc->msgout_index > index)
3042                                         found = TRUE;
3043                         }
3044                         index = end_index;
3045                 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3046                         && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3047                         /* Skip tag type and tag id or residue param*/
3048                         index += 2;
3049                 } else {
3050                         /* Single byte message */
3051                         if (type == AHCMSG_1B
3052                          && ahc->msgout_buf[index] == msgval
3053                          && ahc->msgout_index > index)
3054                                 found = TRUE;
3055                         index++;
3056                 }
3057
3058                 if (found)
3059                         break;
3060         }
3061         return (found);
3062 }
3063
3064 /*
3065  * Wait for a complete incoming message, parse it, and respond accordingly.
3066  */
3067 static int
3068 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3069 {
3070         struct  ahc_initiator_tinfo *tinfo;
3071         struct  ahc_tmode_tstate *tstate;
3072         int     reject;
3073         int     done;
3074         int     response;
3075         u_int   targ_scsirate;
3076
3077         done = MSGLOOP_IN_PROG;
3078         response = FALSE;
3079         reject = FALSE;
3080         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3081                                     devinfo->target, &tstate);
3082         targ_scsirate = tinfo->scsirate;
3083
3084         /*
3085          * Parse as much of the message as is available,
3086          * rejecting it if we don't support it.  When
3087          * the entire message is available and has been
3088          * handled, return MSGLOOP_MSGCOMPLETE, indicating
3089          * that we have parsed an entire message.
3090          *
3091          * In the case of extended messages, we accept the length
3092          * byte outright and perform more checking once we know the
3093          * extended message type.
3094          */
3095         switch (ahc->msgin_buf[0]) {
3096         case MSG_DISCONNECT:
3097         case MSG_SAVEDATAPOINTER:
3098         case MSG_CMDCOMPLETE:
3099         case MSG_RESTOREPOINTERS:
3100         case MSG_IGN_WIDE_RESIDUE:
3101                 /*
3102                  * End our message loop as these are messages
3103                  * the sequencer handles on its own.
3104                  */
3105                 done = MSGLOOP_TERMINATED;
3106                 break;
3107         case MSG_MESSAGE_REJECT:
3108                 response = ahc_handle_msg_reject(ahc, devinfo);
3109                 /* FALLTHROUGH */
3110         case MSG_NOOP:
3111                 done = MSGLOOP_MSGCOMPLETE;
3112                 break;
3113         case MSG_EXTENDED:
3114         {
3115                 /* Wait for enough of the message to begin validation */
3116                 if (ahc->msgin_index < 2)
3117                         break;
3118                 switch (ahc->msgin_buf[2]) {
3119                 case MSG_EXT_SDTR:
3120                 {
3121                         struct   ahc_syncrate *syncrate;
3122                         u_int    period;
3123                         u_int    ppr_options;
3124                         u_int    offset;
3125                         u_int    saved_offset;
3126
3127                         if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3128                                 reject = TRUE;
3129                                 break;
3130                         }
3131
3132                         /*
3133                          * Wait until we have both args before validating
3134                          * and acting on this message.
3135                          *
3136                          * Add one to MSG_EXT_SDTR_LEN to account for
3137                          * the extended message preamble.
3138                          */
3139                         if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3140                                 break;
3141
3142                         period = ahc->msgin_buf[3];
3143                         ppr_options = 0;
3144                         saved_offset = offset = ahc->msgin_buf[4];
3145                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3146                                                            &ppr_options,
3147                                                            devinfo->role);
3148                         ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3149                                             targ_scsirate & WIDEXFER,
3150                                             devinfo->role);
3151                         if (bootverbose) {
3152                                 printf("(%s:%c:%d:%d): Received "
3153                                        "SDTR period %x, offset %x\n\t"
3154                                        "Filtered to period %x, offset %x\n",
3155                                        ahc_name(ahc), devinfo->channel,
3156                                        devinfo->target, devinfo->lun,
3157                                        ahc->msgin_buf[3], saved_offset,
3158                                        period, offset);
3159                         }
3160                         ahc_set_syncrate(ahc, devinfo,
3161                                          syncrate, period,
3162                                          offset, ppr_options,
3163                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3164                                          /*paused*/TRUE);
3165
3166                         /*
3167                          * See if we initiated Sync Negotiation
3168                          * and didn't have to fall down to async
3169                          * transfers.
3170                          */
3171                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3172                                 /* We started it */
3173                                 if (saved_offset != offset) {
3174                                         /* Went too low - force async */
3175                                         reject = TRUE;
3176                                 }
3177                         } else {
3178                                 /*
3179                                  * Send our own SDTR in reply
3180                                  */
3181                                 if (bootverbose
3182                                  && devinfo->role == ROLE_INITIATOR) {
3183                                         printf("(%s:%c:%d:%d): Target "
3184                                                "Initiated SDTR\n",
3185                                                ahc_name(ahc), devinfo->channel,
3186                                                devinfo->target, devinfo->lun);
3187                                 }
3188                                 ahc->msgout_index = 0;
3189                                 ahc->msgout_len = 0;
3190                                 ahc_construct_sdtr(ahc, devinfo,
3191                                                    period, offset);
3192                                 ahc->msgout_index = 0;
3193                                 response = TRUE;
3194                         }
3195                         done = MSGLOOP_MSGCOMPLETE;
3196                         break;
3197                 }
3198                 case MSG_EXT_WDTR:
3199                 {
3200                         u_int bus_width;
3201                         u_int saved_width;
3202                         u_int sending_reply;
3203
3204                         sending_reply = FALSE;
3205                         if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3206                                 reject = TRUE;
3207                                 break;
3208                         }
3209
3210                         /*
3211                          * Wait until we have our arg before validating
3212                          * and acting on this message.
3213                          *
3214                          * Add one to MSG_EXT_WDTR_LEN to account for
3215                          * the extended message preamble.
3216                          */
3217                         if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3218                                 break;
3219
3220                         bus_width = ahc->msgin_buf[3];
3221                         saved_width = bus_width;
3222                         ahc_validate_width(ahc, tinfo, &bus_width,
3223                                            devinfo->role);
3224                         if (bootverbose) {
3225                                 printf("(%s:%c:%d:%d): Received WDTR "
3226                                        "%x filtered to %x\n",
3227                                        ahc_name(ahc), devinfo->channel,
3228                                        devinfo->target, devinfo->lun,
3229                                        saved_width, bus_width);
3230                         }
3231
3232                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3233                                 /*
3234                                  * Don't send a WDTR back to the
3235                                  * target, since we asked first.
3236                                  * If the width went higher than our
3237                                  * request, reject it.
3238                                  */
3239                                 if (saved_width > bus_width) {
3240                                         reject = TRUE;
3241                                         printf("(%s:%c:%d:%d): requested %dBit "
3242                                                "transfers.  Rejecting...\n",
3243                                                ahc_name(ahc), devinfo->channel,
3244                                                devinfo->target, devinfo->lun,
3245                                                8 * (0x01 << bus_width));
3246                                         bus_width = 0;
3247                                 }
3248                         } else {
3249                                 /*
3250                                  * Send our own WDTR in reply
3251                                  */
3252                                 if (bootverbose
3253                                  && devinfo->role == ROLE_INITIATOR) {
3254                                         printf("(%s:%c:%d:%d): Target "
3255                                                "Initiated WDTR\n",
3256                                                ahc_name(ahc), devinfo->channel,
3257                                                devinfo->target, devinfo->lun);
3258                                 }
3259                                 ahc->msgout_index = 0;
3260                                 ahc->msgout_len = 0;
3261                                 ahc_construct_wdtr(ahc, devinfo, bus_width);
3262                                 ahc->msgout_index = 0;
3263                                 response = TRUE;
3264                                 sending_reply = TRUE;
3265                         }
3266                         /*
3267                          * After a wide message, we are async, but
3268                          * some devices don't seem to honor this portion
3269                          * of the spec.  Force a renegotiation of the
3270                          * sync component of our transfer agreement even
3271                          * if our goal is async.  By updating our width
3272                          * after forcing the negotiation, we avoid
3273                          * renegotiating for width.
3274                          */
3275                         ahc_update_neg_request(ahc, devinfo, tstate,
3276                                                tinfo, AHC_NEG_ALWAYS);
3277                         ahc_set_width(ahc, devinfo, bus_width,
3278                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3279                                       /*paused*/TRUE);
3280                         if (sending_reply == FALSE && reject == FALSE) {
3281                                 /*
3282                                  * We will always have an SDTR to send.
3283                                  */
3284                                 ahc->msgout_index = 0;
3285                                 ahc->msgout_len = 0;
3286                                 ahc_build_transfer_msg(ahc, devinfo);
3287                                 ahc->msgout_index = 0;
3288                                 response = TRUE;
3289                         }
3290                         done = MSGLOOP_MSGCOMPLETE;
3291                         break;
3292                 }
3293                 case MSG_EXT_PPR:
3294                 {
3295                         struct  ahc_syncrate *syncrate;
3296                         u_int   period;
3297                         u_int   offset;
3298                         u_int   bus_width;
3299                         u_int   ppr_options;
3300                         u_int   saved_width;
3301                         u_int   saved_offset;
3302                         u_int   saved_ppr_options;
3303
3304                         if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3305                                 reject = TRUE;
3306                                 break;
3307                         }
3308
3309                         /*
3310                          * Wait until we have all args before validating
3311                          * and acting on this message.
3312                          *
3313                          * Add one to MSG_EXT_PPR_LEN to account for
3314                          * the extended message preamble.
3315                          */
3316                         if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3317                                 break;
3318
3319                         period = ahc->msgin_buf[3];
3320                         offset = ahc->msgin_buf[5];
3321                         bus_width = ahc->msgin_buf[6];
3322                         saved_width = bus_width;
3323                         ppr_options = ahc->msgin_buf[7];
3324                         /*
3325                          * According to the spec, a DT only
3326                          * period factor with no DT option
3327                          * set implies async.
3328                          */
3329                         if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3330                          && period == 9)
3331                                 offset = 0;
3332                         saved_ppr_options = ppr_options;
3333                         saved_offset = offset;
3334
3335                         /*
3336                          * Mask out any options we don't support
3337                          * on any controller.  Transfer options are
3338                          * only available if we are negotiating wide.
3339                          */
3340                         ppr_options &= MSG_EXT_PPR_DT_REQ;
3341                         if (bus_width == 0)
3342                                 ppr_options = 0;
3343
3344                         ahc_validate_width(ahc, tinfo, &bus_width,
3345                                            devinfo->role);
3346                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3347                                                            &ppr_options,
3348                                                            devinfo->role);
3349                         ahc_validate_offset(ahc, tinfo, syncrate,
3350                                             &offset, bus_width,
3351                                             devinfo->role);
3352
3353                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3354                                 /*
3355                                  * If we are unable to do any of the
3356                                  * requested options (we went too low),
3357                                  * then we'll have to reject the message.
3358                                  */
3359                                 if (saved_width > bus_width
3360                                  || saved_offset != offset
3361                                  || saved_ppr_options != ppr_options) {
3362                                         reject = TRUE;
3363                                         period = 0;
3364                                         offset = 0;
3365                                         bus_width = 0;
3366                                         ppr_options = 0;
3367                                         syncrate = NULL;
3368                                 }
3369                         } else {
3370                                 if (devinfo->role != ROLE_TARGET)
3371                                         printf("(%s:%c:%d:%d): Target "
3372                                                "Initiated PPR\n",
3373                                                ahc_name(ahc), devinfo->channel,
3374                                                devinfo->target, devinfo->lun);
3375                                 else
3376                                         printf("(%s:%c:%d:%d): Initiator "
3377                                                "Initiated PPR\n",
3378                                                ahc_name(ahc), devinfo->channel,
3379                                                devinfo->target, devinfo->lun);
3380                                 ahc->msgout_index = 0;
3381                                 ahc->msgout_len = 0;
3382                                 ahc_construct_ppr(ahc, devinfo, period, offset,
3383                                                   bus_width, ppr_options);
3384                                 ahc->msgout_index = 0;
3385                                 response = TRUE;
3386                         }
3387                         if (bootverbose) {
3388                                 printf("(%s:%c:%d:%d): Received PPR width %x, "
3389                                        "period %x, offset %x,options %x\n"
3390                                        "\tFiltered to width %x, period %x, "
3391                                        "offset %x, options %x\n",
3392                                        ahc_name(ahc), devinfo->channel,
3393                                        devinfo->target, devinfo->lun,
3394                                        saved_width, ahc->msgin_buf[3],
3395                                        saved_offset, saved_ppr_options,
3396                                        bus_width, period, offset, ppr_options);
3397                         }
3398                         ahc_set_width(ahc, devinfo, bus_width,
3399                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3400                                       /*paused*/TRUE);
3401                         ahc_set_syncrate(ahc, devinfo,
3402                                          syncrate, period,
3403                                          offset, ppr_options,
3404                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3405                                          /*paused*/TRUE);
3406                         done = MSGLOOP_MSGCOMPLETE;
3407                         break;
3408                 }
3409                 default:
3410                         /* Unknown extended message.  Reject it. */
3411                         reject = TRUE;
3412                         break;
3413                 }
3414                 break;
3415         }
3416 #ifdef AHC_TARGET_MODE
3417         case MSG_BUS_DEV_RESET:
3418                 ahc_handle_devreset(ahc, devinfo,
3419                                     CAM_BDR_SENT,
3420                                     "Bus Device Reset Received",
3421                                     /*verbose_level*/0);
3422                 ahc_restart(ahc);
3423                 done = MSGLOOP_TERMINATED;
3424                 break;
3425         case MSG_ABORT_TAG:
3426         case MSG_ABORT:
3427         case MSG_CLEAR_QUEUE:
3428         {
3429                 int tag;
3430
3431                 /* Target mode messages */
3432                 if (devinfo->role != ROLE_TARGET) {
3433                         reject = TRUE;
3434                         break;
3435                 }
3436                 tag = SCB_LIST_NULL;
3437                 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3438                         tag = ahc_inb(ahc, INITIATOR_TAG);
3439                 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3440                                devinfo->lun, tag, ROLE_TARGET,
3441                                CAM_REQ_ABORTED);
3442
3443                 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3444                 if (tstate != NULL) {
3445                         struct ahc_tmode_lstate* lstate;
3446
3447                         lstate = tstate->enabled_luns[devinfo->lun];
3448                         if (lstate != NULL) {
3449                                 ahc_queue_lstate_event(ahc, lstate,
3450                                                        devinfo->our_scsiid,
3451                                                        ahc->msgin_buf[0],
3452                                                        /*arg*/tag);
3453                                 ahc_send_lstate_events(ahc, lstate);
3454                         }
3455                 }
3456                 ahc_restart(ahc);
3457                 done = MSGLOOP_TERMINATED;
3458                 break;
3459         }
3460 #endif
3461         case MSG_TERM_IO_PROC:
3462         default:
3463                 reject = TRUE;
3464                 break;
3465         }
3466
3467         if (reject) {
3468                 /*
3469                  * Setup to reject the message.
3470                  */
3471                 ahc->msgout_index = 0;
3472                 ahc->msgout_len = 1;
3473                 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3474                 done = MSGLOOP_MSGCOMPLETE;
3475                 response = TRUE;
3476         }
3477
3478         if (done != MSGLOOP_IN_PROG && !response)
3479                 /* Clear the outgoing message buffer */
3480                 ahc->msgout_len = 0;
3481
3482         return (done);
3483 }
3484
3485 /*
3486  * Process a message reject message.
3487  */
3488 static int
3489 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3490 {
3491         /*
3492          * What we care about here is if we had an
3493          * outstanding SDTR or WDTR message for this
3494          * target.  If we did, this is a signal that
3495          * the target is refusing negotiation.
3496          */
3497         struct scb *scb;
3498         struct ahc_initiator_tinfo *tinfo;
3499         struct ahc_tmode_tstate *tstate;
3500         u_int scb_index;
3501         u_int last_msg;
3502         int   response = 0;
3503
3504         scb_index = ahc_inb(ahc, SCB_TAG);
3505         scb = ahc_lookup_scb(ahc, scb_index);
3506         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3507                                     devinfo->our_scsiid,
3508                                     devinfo->target, &tstate);
3509         /* Might be necessary */
3510         last_msg = ahc_inb(ahc, LAST_MSG);
3511
3512         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3513                 /*
3514                  * Target does not support the PPR message.
3515                  * Attempt to negotiate SPI-2 style.
3516                  */
3517                 if (bootverbose) {
3518                         printf("(%s:%c:%d:%d): PPR Rejected. "
3519                                "Trying WDTR/SDTR\n",
3520                                ahc_name(ahc), devinfo->channel,
3521                                devinfo->target, devinfo->lun);
3522                 }
3523                 tinfo->goal.ppr_options = 0;
3524                 tinfo->curr.transport_version = 2;
3525                 tinfo->goal.transport_version = 2;
3526                 ahc->msgout_index = 0;
3527                 ahc->msgout_len = 0;
3528                 ahc_build_transfer_msg(ahc, devinfo);
3529                 ahc->msgout_index = 0;
3530                 response = 1;
3531         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3532                 /* note 8bit xfers */
3533                 printf("(%s:%c:%d:%d): refuses WIDE negotiation.  Using "
3534                        "8bit transfers\n", ahc_name(ahc),
3535                        devinfo->channel, devinfo->target, devinfo->lun);
3536                 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3537                               AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3538                               /*paused*/TRUE);
3539                 /*
3540                  * No need to clear the sync rate.  If the target
3541                  * did not accept the command, our syncrate is
3542                  * unaffected.  If the target started the negotiation,
3543                  * but rejected our response, we already cleared the
3544                  * sync rate before sending our WDTR.
3545                  */
3546                 if (tinfo->goal.offset != tinfo->curr.offset) {
3547                         /* Start the sync negotiation */
3548                         ahc->msgout_index = 0;
3549                         ahc->msgout_len = 0;
3550                         ahc_build_transfer_msg(ahc, devinfo);
3551                         ahc->msgout_index = 0;
3552                         response = 1;
3553                 }
3554         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3555                 /* note asynch xfers and clear flag */
3556                 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3557                                  /*offset*/0, /*ppr_options*/0,
3558                                  AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3559                                  /*paused*/TRUE);
3560                 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3561                        "Using asynchronous transfers\n",
3562                        ahc_name(ahc), devinfo->channel,
3563                        devinfo->target, devinfo->lun);
3564         } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3565                 int tag_type;
3566                 int mask;
3567
3568                 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3569
3570                 if (tag_type == MSG_SIMPLE_TASK) {
3571                         printf("(%s:%c:%d:%d): refuses tagged commands.  "
3572                                "Performing non-tagged I/O\n", ahc_name(ahc),
3573                                devinfo->channel, devinfo->target, devinfo->lun);
3574                         ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3575                         mask = ~0x23;
3576                 } else {
3577                         printf("(%s:%c:%d:%d): refuses %s tagged commands.  "
3578                                "Performing simple queue tagged I/O only\n",
3579                                ahc_name(ahc), devinfo->channel, devinfo->target,
3580                                devinfo->lun, tag_type == MSG_ORDERED_TASK
3581                                ? "ordered" : "head of queue");
3582                         ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3583                         mask = ~0x03;
3584                 }
3585
3586                 /*
3587                  * Resend the identify for this CCB as the target
3588                  * may believe that the selection is invalid otherwise.
3589                  */
3590                 ahc_outb(ahc, SCB_CONTROL,
3591                          ahc_inb(ahc, SCB_CONTROL) & mask);
3592                 scb->hscb->control &= mask;
3593                 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3594                                         /*type*/MSG_SIMPLE_TASK);
3595                 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3596                 ahc_assert_atn(ahc);
3597
3598                 /*
3599                  * This transaction is now at the head of
3600                  * the untagged queue for this target.
3601                  */
3602                 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3603                         struct scb_tailq *untagged_q;
3604
3605                         untagged_q =
3606                             &(ahc->untagged_queues[devinfo->target_offset]);
3607                         TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3608                         scb->flags |= SCB_UNTAGGEDQ;
3609                 }
3610                 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3611                              scb->hscb->tag);
3612
3613                 /*
3614                  * Requeue all tagged commands for this target
3615                  * currently in our possession so they can be
3616                  * converted to untagged commands.
3617                  */
3618                 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3619                                    SCB_GET_CHANNEL(ahc, scb),
3620                                    SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3621                                    ROLE_INITIATOR, CAM_REQUEUE_REQ,
3622                                    SEARCH_COMPLETE);
3623         } else {
3624                 /*
3625                  * Otherwise, we ignore it.
3626                  */
3627                 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3628                        ahc_name(ahc), devinfo->channel, devinfo->target,
3629                        last_msg);
3630         }
3631         return (response);
3632 }
3633
3634 /*
3635  * Process an ingnore wide residue message.
3636  */
3637 static void
3638 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3639 {
3640         u_int scb_index;
3641         struct scb *scb;
3642
3643         scb_index = ahc_inb(ahc, SCB_TAG);
3644         scb = ahc_lookup_scb(ahc, scb_index);
3645         /*
3646          * XXX Actually check data direction in the sequencer?
3647          * Perhaps add datadir to some spare bits in the hscb?
3648          */
3649         if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3650          || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3651                 /*
3652                  * Ignore the message if we haven't
3653                  * seen an appropriate data phase yet.
3654                  */
3655         } else {
3656                 /*
3657                  * If the residual occurred on the last
3658                  * transfer and the transfer request was
3659                  * expected to end on an odd count, do
3660                  * nothing.  Otherwise, subtract a byte
3661                  * and update the residual count accordingly.
3662                  */
3663                 uint32_t sgptr;
3664
3665                 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3666                 if ((sgptr & SG_LIST_NULL) != 0
3667                  && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3668                         /*
3669                          * If the residual occurred on the last
3670                          * transfer and the transfer request was
3671                          * expected to end on an odd count, do
3672                          * nothing.
3673                          */
3674                 } else {
3675                         struct ahc_dma_seg *sg;
3676                         uint32_t data_cnt;
3677                         uint32_t sglen;
3678
3679                         /* Pull in all of the sgptr */
3680                         sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3681                         data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3682
3683                         if ((sgptr & SG_LIST_NULL) != 0) {
3684                                 /*
3685                                  * The residual data count is not updated
3686                                  * for the command run to completion case.
3687                                  * Explicitly zero the count.
3688                                  */
3689                                 data_cnt &= ~AHC_SG_LEN_MASK;
3690                         }
3691
3692                         data_cnt += 1;
3693                         sgptr &= SG_PTR_MASK;
3694
3695                         sg = ahc_sg_bus_to_virt(scb, sgptr);
3696
3697                         /*
3698                          * The residual sg ptr points to the next S/G
3699                          * to load so we must go back one.
3700                          */
3701                         sg--;
3702                         sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3703                         if (sg != scb->sg_list
3704                          && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3705                                 sg--;
3706                                 sglen = aic_le32toh(sg->len);
3707                                 /*
3708                                  * Preserve High Address and SG_LIST bits
3709                                  * while setting the count to 1.
3710                                  */
3711                                 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3712
3713                                 /*
3714                                  * Increment sg so it points to the
3715                                  * "next" sg.
3716                                  */
3717                                 sg++;
3718                                 sgptr = ahc_sg_virt_to_bus(scb, sg);
3719                         }
3720                         ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3721                         ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3722                         /*
3723                          * Toggle the "oddness" of the transfer length
3724                          * to handle this mid-transfer ignore wide
3725                          * residue.  This ensures that the oddness is
3726                          * correct for subsequent data transfers.
3727                          */
3728                         ahc_outb(ahc, SCB_LUN,
3729                                  ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3730                 }
3731         }
3732 }
3733
3734 /*
3735  * Reinitialize the data pointers for the active transfer
3736  * based on its current residual.
3737  */
3738 static void
3739 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3740 {
3741         struct   scb *scb;
3742         struct   ahc_dma_seg *sg;
3743         u_int    scb_index;
3744         uint32_t sgptr;
3745         uint32_t resid;
3746         uint32_t dataptr;
3747
3748         scb_index = ahc_inb(ahc, SCB_TAG);
3749         scb = ahc_lookup_scb(ahc, scb_index);
3750         sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3751               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3752               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3753               | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3754
3755         sgptr &= SG_PTR_MASK;
3756         sg = ahc_sg_bus_to_virt(scb, sgptr);
3757
3758         /* The residual sg_ptr always points to the next sg */
3759         sg--;
3760
3761         resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3762               | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3763               | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3764
3765         dataptr = aic_le32toh(sg->addr)
3766                 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3767                 - resid;
3768         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3769                 u_int dscommand1;
3770
3771                 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3772                 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3773                 ahc_outb(ahc, HADDR,
3774                          (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3775                 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3776         }
3777         ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3778         ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3779         ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3780         ahc_outb(ahc, HADDR, dataptr);
3781         ahc_outb(ahc, HCNT + 2, resid >> 16);
3782         ahc_outb(ahc, HCNT + 1, resid >> 8);
3783         ahc_outb(ahc, HCNT, resid);
3784         if ((ahc->features & AHC_ULTRA2) == 0) {
3785                 ahc_outb(ahc, STCNT + 2, resid >> 16);
3786                 ahc_outb(ahc, STCNT + 1, resid >> 8);
3787                 ahc_outb(ahc, STCNT, resid);
3788         }
3789 }
3790
3791 /*
3792  * Handle the effects of issuing a bus device reset message.
3793  */
3794 static void
3795 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3796                     cam_status status, char *message, int verbose_level)
3797 {
3798 #ifdef AHC_TARGET_MODE
3799         struct ahc_tmode_tstate* tstate;
3800         u_int lun;
3801 #endif
3802         int found;
3803
3804         found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3805                                CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3806                                status);
3807
3808 #ifdef AHC_TARGET_MODE
3809         /*
3810          * Send an immediate notify ccb to all target mord peripheral
3811          * drivers affected by this action.
3812          */
3813         tstate = ahc->enabled_targets[devinfo->our_scsiid];
3814         if (tstate != NULL) {
3815                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3816                         struct ahc_tmode_lstate* lstate;
3817
3818                         lstate = tstate->enabled_luns[lun];
3819                         if (lstate == NULL)
3820                                 continue;
3821
3822                         ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3823                                                MSG_BUS_DEV_RESET, /*arg*/0);
3824                         ahc_send_lstate_events(ahc, lstate);
3825                 }
3826         }
3827 #endif
3828
3829         /*
3830          * Go back to async/narrow transfers and renegotiate.
3831          */
3832         ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3833                       AHC_TRANS_CUR, /*paused*/TRUE);
3834         ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3835                          /*period*/0, /*offset*/0, /*ppr_options*/0,
3836                          AHC_TRANS_CUR, /*paused*/TRUE);
3837
3838         if (status != CAM_SEL_TIMEOUT)
3839                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3840                                CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3841
3842         if (message != NULL
3843          && (verbose_level <= bootverbose))
3844                 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3845                        message, devinfo->channel, devinfo->target, found);
3846 }
3847
3848 #ifdef AHC_TARGET_MODE
3849 static void
3850 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3851                        struct scb *scb)
3852 {
3853
3854         /*
3855          * To facilitate adding multiple messages together,
3856          * each routine should increment the index and len
3857          * variables instead of setting them explicitly.
3858          */
3859         ahc->msgout_index = 0;
3860         ahc->msgout_len = 0;
3861
3862         if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3863                 ahc_build_transfer_msg(ahc, devinfo);
3864         else
3865                 panic("ahc_intr: AWAITING target message with no message");
3866
3867         ahc->msgout_index = 0;
3868         ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3869 }
3870 #endif
3871 /**************************** Initialization **********************************/
3872 /*
3873  * Allocate a controller structure for a new device
3874  * and perform initial initializion.
3875  */
3876 struct ahc_softc *
3877 ahc_alloc(void *platform_arg, char *name)
3878 {
3879         struct  ahc_softc *ahc;
3880         int     i;
3881
3882 #ifndef __FreeBSD__
3883         ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3884         if (!ahc) {
3885                 printf("aic7xxx: cannot malloc softc!\n");
3886                 free(name, M_DEVBUF);
3887                 return NULL;
3888         }
3889 #else
3890         ahc = device_get_softc((device_t)platform_arg);
3891 #endif
3892         memset(ahc, 0, sizeof(*ahc));
3893         ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3894                                   M_DEVBUF, M_NOWAIT);
3895         if (ahc->seep_config == NULL) {
3896 #ifndef __FreeBSD__
3897                 free(ahc, M_DEVBUF);
3898 #endif
3899                 free(name, M_DEVBUF);
3900                 return (NULL);
3901         }
3902         LIST_INIT(&ahc->pending_scbs);
3903         LIST_INIT(&ahc->timedout_scbs);
3904         /* We don't know our unit number until the OSM sets it */
3905         ahc->name = name;
3906         ahc->unit = -1;
3907         ahc->description = NULL;
3908         ahc->channel = 'A';
3909         ahc->channel_b = 'B';
3910         ahc->chip = AHC_NONE;
3911         ahc->features = AHC_FENONE;
3912         ahc->bugs = AHC_BUGNONE;
3913         ahc->flags = AHC_FNONE;
3914         /*
3915          * Default to all error reporting enabled with the
3916          * sequencer operating at its fastest speed.
3917          * The bus attach code may modify this.
3918          */
3919         ahc->seqctl = FASTMODE;
3920
3921         for (i = 0; i < AHC_NUM_TARGETS; i++)
3922                 TAILQ_INIT(&ahc->untagged_queues[i]);
3923         if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3924                 ahc_free(ahc);
3925                 ahc = NULL;
3926         }
3927         ahc_lockinit(ahc);
3928         return (ahc);
3929 }
3930
3931 int
3932 ahc_softc_init(struct ahc_softc *ahc)
3933 {
3934
3935         /* The IRQMS bit is only valid on VL and EISA chips */
3936         if ((ahc->chip & AHC_PCI) == 0)
3937                 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3938         else
3939                 ahc->unpause = 0;
3940         ahc->pause = ahc->unpause | PAUSE;
3941         /* XXX The shared scb data stuff should be deprecated */
3942         if (ahc->scb_data == NULL) {
3943                 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3944                                        M_DEVBUF, M_NOWAIT);
3945                 if (ahc->scb_data == NULL)
3946                         return (ENOMEM);
3947                 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3948         }
3949
3950         return (0);
3951 }
3952
3953 void
3954 ahc_softc_insert(struct ahc_softc *ahc)
3955 {
3956         struct ahc_softc *list_ahc;
3957
3958 #if AIC_PCI_CONFIG > 0
3959         /*
3960          * Second Function PCI devices need to inherit some
3961          * settings from function 0.
3962          */
3963         if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3964          && (ahc->features & AHC_MULTI_FUNC) != 0) {
3965                 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3966                         aic_dev_softc_t list_pci;
3967                         aic_dev_softc_t pci;
3968
3969                         list_pci = list_ahc->dev_softc;
3970                         pci = ahc->dev_softc;
3971                         if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3972                          && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3973                                 struct ahc_softc *master;
3974                                 struct ahc_softc *slave;
3975
3976                                 if (aic_get_pci_function(list_pci) == 0) {
3977                                         master = list_ahc;
3978                                         slave = ahc;
3979                                 } else {
3980                                         master = ahc;
3981                                         slave = list_ahc;
3982                                 }
3983                                 slave->flags &= ~AHC_BIOS_ENABLED;
3984                                 slave->flags |=
3985                                     master->flags & AHC_BIOS_ENABLED;
3986                                 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3987                                 slave->flags |=
3988                                     master->flags & AHC_PRIMARY_CHANNEL;
3989                                 break;
3990                         }
3991                 }
3992         }
3993 #endif
3994
3995         /*
3996          * Insertion sort into our list of softcs.
3997          */
3998         list_ahc = TAILQ_FIRST(&ahc_tailq);
3999         while (list_ahc != NULL
4000             && ahc_softc_comp(ahc, list_ahc) <= 0)
4001                 list_ahc = TAILQ_NEXT(list_ahc, links);
4002         if (list_ahc != NULL)
4003                 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4004         else
4005                 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4006         ahc->init_level++;
4007 }
4008
4009 void
4010 ahc_set_unit(struct ahc_softc *ahc, int unit)
4011 {
4012         ahc->unit = unit;
4013 }
4014
4015 void
4016 ahc_set_name(struct ahc_softc *ahc, char *name)
4017 {
4018         if (ahc->name != NULL)
4019                 free(ahc->name, M_DEVBUF);
4020         ahc->name = name;
4021 }
4022
4023 void
4024 ahc_free(struct ahc_softc *ahc)
4025 {
4026         int i;
4027
4028         ahc_terminate_recovery_thread(ahc);
4029         switch (ahc->init_level) {
4030         default:
4031         case 5:
4032                 ahc_shutdown(ahc);
4033                 /* FALLTHROUGH */
4034         case 4:
4035                 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4036                                   ahc->shared_data_dmamap);
4037                 /* FALLTHROUGH */
4038         case 3:
4039                 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4040                                 ahc->shared_data_dmamap);
4041                 /* FALLTHROUGH */
4042         case 2:
4043                 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4044         case 1:
4045 #ifndef __linux__
4046                 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4047 #endif
4048                 break;
4049         case 0:
4050                 break;
4051         }
4052
4053 #ifndef __linux__
4054         aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4055 #endif
4056         ahc_platform_free(ahc);
4057         ahc_fini_scbdata(ahc);
4058         for (i = 0; i < AHC_NUM_TARGETS; i++) {
4059                 struct ahc_tmode_tstate *tstate;
4060
4061                 tstate = ahc->enabled_targets[i];
4062                 if (tstate != NULL) {
4063 #ifdef AHC_TARGET_MODE
4064                         int j;
4065
4066                         for (j = 0; j < AHC_NUM_LUNS; j++) {
4067                                 struct ahc_tmode_lstate *lstate;
4068
4069                                 lstate = tstate->enabled_luns[j];
4070                                 if (lstate != NULL) {
4071                                         xpt_free_path(lstate->path);
4072                                         free(lstate, M_DEVBUF);
4073                                 }
4074                         }
4075 #endif
4076                         free(tstate, M_DEVBUF);
4077                 }
4078         }
4079 #ifdef AHC_TARGET_MODE
4080         if (ahc->black_hole != NULL) {
4081                 xpt_free_path(ahc->black_hole->path);
4082                 free(ahc->black_hole, M_DEVBUF);
4083         }
4084 #endif
4085         if (ahc->name != NULL)
4086                 free(ahc->name, M_DEVBUF);
4087         if (ahc->seep_config != NULL)
4088                 free(ahc->seep_config, M_DEVBUF);
4089 #ifndef __FreeBSD__
4090         free(ahc, M_DEVBUF);
4091 #endif
4092         return;
4093 }
4094
4095 void
4096 ahc_shutdown(void *arg)
4097 {
4098         struct  ahc_softc *ahc;
4099         int     i;
4100
4101         ahc = (struct ahc_softc *)arg;
4102
4103         /* This will reset most registers to 0, but not all */
4104         ahc_reset(ahc, /*reinit*/FALSE);
4105         ahc_outb(ahc, SCSISEQ, 0);
4106         ahc_outb(ahc, SXFRCTL0, 0);
4107         ahc_outb(ahc, DSPCISTATUS, 0);
4108
4109         for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4110                 ahc_outb(ahc, i, 0);
4111 }
4112
4113 /*
4114  * Reset the controller and record some information about it
4115  * that is only available just after a reset.  If "reinit" is
4116  * non-zero, this reset occurred after initial configuration
4117  * and the caller requests that the chip be fully reinitialized
4118  * to a runable state.  Chip interrupts are *not* enabled after
4119  * a reinitialization.  The caller must enable interrupts via
4120  * ahc_intr_enable().
4121  */
4122 int
4123 ahc_reset(struct ahc_softc *ahc, int reinit)
4124 {
4125         u_int   sblkctl;
4126         u_int   sxfrctl1_a, sxfrctl1_b;
4127         int     error;
4128         int     wait;
4129
4130         /*
4131          * Preserve the value of the SXFRCTL1 register for all channels.
4132          * It contains settings that affect termination and we don't want
4133          * to disturb the integrity of the bus.
4134          */
4135         ahc_pause(ahc);
4136         sxfrctl1_b = 0;
4137         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4138                 u_int sblkctl;
4139
4140                 /*
4141                  * Save channel B's settings in case this chip
4142                  * is setup for TWIN channel operation.
4143                  */
4144                 sblkctl = ahc_inb(ahc, SBLKCTL);
4145                 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4146                 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4147                 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4148         }
4149         sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4150
4151         ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4152
4153         /*
4154          * Ensure that the reset has finished.  We delay 1000us
4155          * prior to reading the register to make sure the chip
4156          * has sufficiently completed its reset to handle register
4157          * accesses.
4158          */
4159         wait = 1000;
4160         do {
4161                 aic_delay(1000);
4162         } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4163
4164         if (wait == 0) {
4165                 printf("%s: WARNING - Failed chip reset!  "
4166                        "Trying to initialize anyway.\n", ahc_name(ahc));
4167         }
4168         ahc_outb(ahc, HCNTRL, ahc->pause);
4169
4170         /* Determine channel configuration */
4171         sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4172         /* No Twin Channel PCI cards */
4173         if ((ahc->chip & AHC_PCI) != 0)
4174                 sblkctl &= ~SELBUSB;
4175         switch (sblkctl) {
4176         case 0:
4177                 /* Single Narrow Channel */
4178                 break;
4179         case 2:
4180                 /* Wide Channel */
4181                 ahc->features |= AHC_WIDE;
4182                 break;
4183         case 8:
4184                 /* Twin Channel */
4185                 ahc->features |= AHC_TWIN;
4186                 break;
4187         default:
4188                 printf(" Unsupported adapter type.  Ignoring\n");
4189                 return(-1);
4190         }
4191
4192         /*
4193          * Reload sxfrctl1.
4194          *
4195          * We must always initialize STPWEN to 1 before we
4196          * restore the saved values.  STPWEN is initialized
4197          * to a tri-state condition which can only be cleared
4198          * by turning it on.
4199          */
4200         if ((ahc->features & AHC_TWIN) != 0) {
4201                 u_int sblkctl;
4202
4203                 sblkctl = ahc_inb(ahc, SBLKCTL);
4204                 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4205                 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4206                 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4207         }
4208         ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4209
4210         error = 0;
4211         if (reinit != 0)
4212                 /*
4213                  * If a recovery action has forced a chip reset,
4214                  * re-initialize the chip to our liking.
4215                  */
4216                 error = ahc->bus_chip_init(ahc);
4217 #ifdef AHC_DUMP_SEQ
4218         else
4219                 ahc_dumpseq(ahc);
4220 #endif
4221
4222         return (error);
4223 }
4224
4225 /*
4226  * Determine the number of SCBs available on the controller
4227  */
4228 int
4229 ahc_probe_scbs(struct ahc_softc *ahc) {
4230         int i;
4231
4232         for (i = 0; i < AHC_SCB_MAX; i++) {
4233                 ahc_outb(ahc, SCBPTR, i);
4234                 ahc_outb(ahc, SCB_BASE, i);
4235                 if (ahc_inb(ahc, SCB_BASE) != i)
4236                         break;
4237                 ahc_outb(ahc, SCBPTR, 0);
4238                 if (ahc_inb(ahc, SCB_BASE) != 0)
4239                         break;
4240         }
4241         return (i);
4242 }
4243
4244 static void
4245 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4246 {
4247         bus_addr_t *baddr;
4248
4249         baddr = (bus_addr_t *)arg;
4250         *baddr = segs->ds_addr;
4251 }
4252
4253 static void
4254 ahc_build_free_scb_list(struct ahc_softc *ahc)
4255 {
4256         int scbsize;
4257         int i;
4258
4259         scbsize = 32;
4260         if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4261                 scbsize = 64;
4262
4263         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4264                 int j;
4265
4266                 ahc_outb(ahc, SCBPTR, i);
4267
4268                 /*
4269                  * Touch all SCB bytes to avoid parity errors
4270                  * should one of our debugging routines read
4271                  * an otherwise uninitiatlized byte.
4272                  */
4273                 for (j = 0; j < scbsize; j++)
4274                         ahc_outb(ahc, SCB_BASE+j, 0xFF);
4275
4276                 /* Clear the control byte. */
4277                 ahc_outb(ahc, SCB_CONTROL, 0);
4278
4279                 /* Set the next pointer */
4280                 if ((ahc->flags & AHC_PAGESCBS) != 0)
4281                         ahc_outb(ahc, SCB_NEXT, i+1);
4282                 else
4283                         ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4284
4285                 /* Make the tag number, SCSIID, and lun invalid */
4286                 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4287                 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4288                 ahc_outb(ahc, SCB_LUN, 0xFF);
4289         }
4290
4291         if ((ahc->flags & AHC_PAGESCBS) != 0) {
4292                 /* SCB 0 heads the free list. */
4293                 ahc_outb(ahc, FREE_SCBH, 0);
4294         } else {
4295                 /* No free list. */
4296                 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4297         }
4298
4299         /* Make sure that the last SCB terminates the free list */
4300         ahc_outb(ahc, SCBPTR, i-1);
4301         ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4302 }
4303
4304 static int
4305 ahc_init_scbdata(struct ahc_softc *ahc)
4306 {
4307         struct scb_data *scb_data;
4308
4309         scb_data = ahc->scb_data;
4310         SLIST_INIT(&scb_data->free_scbs);
4311         SLIST_INIT(&scb_data->sg_maps);
4312
4313         /* Allocate SCB resources */
4314         scb_data->scbarray =
4315             (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4316                                  M_DEVBUF, M_NOWAIT);
4317         if (scb_data->scbarray == NULL)
4318                 return (ENOMEM);
4319         memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4320
4321         /* Determine the number of hardware SCBs and initialize them */
4322
4323         scb_data->maxhscbs = ahc_probe_scbs(ahc);
4324         if (ahc->scb_data->maxhscbs == 0) {
4325                 printf("%s: No SCB space found\n", ahc_name(ahc));
4326                 return (ENXIO);
4327         }
4328
4329         /*
4330          * Create our DMA tags.  These tags define the kinds of device
4331          * accessible memory allocations and memory mappings we will
4332          * need to perform during normal operation.
4333          *
4334          * Unless we need to further restrict the allocation, we rely
4335          * on the restrictions of the parent dmat, hence the common
4336          * use of MAXADDR and MAXSIZE.
4337          */
4338
4339         /* DMA tag for our hardware scb structures */
4340         if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4341                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4342                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4343                                /*highaddr*/BUS_SPACE_MAXADDR,
4344                                /*filter*/NULL, /*filterarg*/NULL,
4345                                AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4346                                /*nsegments*/1,
4347                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4348                                /*flags*/0, &scb_data->hscb_dmat) != 0) {
4349                 goto error_exit;
4350         }
4351
4352         scb_data->init_level++;
4353
4354         /* Allocation for our hscbs */
4355         if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4356                              (void **)&scb_data->hscbs,
4357                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4358                              &scb_data->hscb_dmamap) != 0) {
4359                 goto error_exit;
4360         }
4361
4362         scb_data->init_level++;
4363
4364         /* And permanently map them */
4365         aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4366                         scb_data->hscbs,
4367                         AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4368                         ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4369
4370         scb_data->init_level++;
4371
4372         /* DMA tag for our sense buffers */
4373         if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4374                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4375                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4376                                /*highaddr*/BUS_SPACE_MAXADDR,
4377                                /*filter*/NULL, /*filterarg*/NULL,
4378                                AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4379                                /*nsegments*/1,
4380                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4381                                /*flags*/0, &scb_data->sense_dmat) != 0) {
4382                 goto error_exit;
4383         }
4384
4385         scb_data->init_level++;
4386
4387         /* Allocate them */
4388         if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4389                              (void **)&scb_data->sense,
4390                              BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4391                 goto error_exit;
4392         }
4393
4394         scb_data->init_level++;
4395
4396         /* And permanently map them */
4397         aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4398                         scb_data->sense,
4399                         AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4400                         ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4401
4402         scb_data->init_level++;
4403
4404         /* DMA tag for our S/G structures.  We allocate in page sized chunks */
4405         if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4406                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4407                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4408                                /*highaddr*/BUS_SPACE_MAXADDR,
4409                                /*filter*/NULL, /*filterarg*/NULL,
4410                                PAGE_SIZE, /*nsegments*/1,
4411                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4412                                /*flags*/0, &scb_data->sg_dmat) != 0) {
4413                 goto error_exit;
4414         }
4415
4416         scb_data->init_level++;
4417
4418         /* Perform initial CCB allocation */
4419         memset(scb_data->hscbs, 0,
4420                AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4421         while (ahc_alloc_scbs(ahc) != 0)
4422                 ;
4423
4424         if (scb_data->numscbs == 0) {
4425                 printf("%s: ahc_init_scbdata - "
4426                        "Unable to allocate initial scbs\n",
4427                        ahc_name(ahc));
4428                 goto error_exit;
4429         }
4430
4431         /*
4432          * Reserve the next queued SCB.
4433          */
4434         ahc->next_queued_scb = ahc_get_scb(ahc);
4435
4436         /*
4437          * Note that we were successful
4438          */
4439         return (0);
4440
4441 error_exit:
4442
4443         return (ENOMEM);
4444 }
4445
4446 static void
4447 ahc_fini_scbdata(struct ahc_softc *ahc)
4448 {
4449         struct scb_data *scb_data;
4450
4451         scb_data = ahc->scb_data;
4452         if (scb_data == NULL)
4453                 return;
4454
4455         switch (scb_data->init_level) {
4456         default:
4457         case 7:
4458         {
4459                 struct sg_map_node *sg_map;
4460
4461                 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4462                         SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4463                         aic_dmamap_unload(ahc, scb_data->sg_dmat,
4464                                           sg_map->sg_dmamap);
4465                         aic_dmamem_free(ahc, scb_data->sg_dmat,
4466                                         sg_map->sg_vaddr,
4467                                         sg_map->sg_dmamap);
4468                         free(sg_map, M_DEVBUF);
4469                 }
4470                 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4471         }
4472         case 6:
4473                 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4474                                   scb_data->sense_dmamap);
4475         case 5:
4476                 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4477                                 scb_data->sense_dmamap);
4478         case 4:
4479                 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4480         case 3:
4481                 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4482                                   scb_data->hscb_dmamap);
4483         case 2:
4484                 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4485                                 scb_data->hscb_dmamap);
4486         case 1:
4487                 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4488                 break;
4489         case 0:
4490                 break;
4491         }
4492         if (scb_data->scbarray != NULL)
4493                 free(scb_data->scbarray, M_DEVBUF);
4494 }
4495
4496 int
4497 ahc_alloc_scbs(struct ahc_softc *ahc)
4498 {
4499         struct scb_data *scb_data;
4500         struct scb *next_scb;
4501         struct sg_map_node *sg_map;
4502         bus_addr_t physaddr;
4503         struct ahc_dma_seg *segs;
4504         int newcount;
4505         int i;
4506
4507         scb_data = ahc->scb_data;
4508         if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4509                 /* Can't allocate any more */
4510                 return (0);
4511
4512         next_scb = &scb_data->scbarray[scb_data->numscbs];
4513
4514         sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4515
4516         if (sg_map == NULL)
4517                 return (0);
4518
4519         /* Allocate S/G space for the next batch of SCBS */
4520         if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4521                              (void **)&sg_map->sg_vaddr,
4522                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4523                              &sg_map->sg_dmamap) != 0) {
4524                 free(sg_map, M_DEVBUF);
4525                 return (0);
4526         }
4527
4528         SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4529
4530         aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4531                         sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4532                         &sg_map->sg_physaddr, /*flags*/0);
4533
4534         segs = sg_map->sg_vaddr;
4535         physaddr = sg_map->sg_physaddr;
4536
4537         newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4538         newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4539         for (i = 0; i < newcount; i++) {
4540                 struct scb_platform_data *pdata;
4541 #ifndef __linux__
4542                 int error;
4543 #endif
4544                 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4545                                                            M_DEVBUF, M_NOWAIT);
4546                 if (pdata == NULL)
4547                         break;
4548                 next_scb->platform_data = pdata;
4549                 next_scb->sg_map = sg_map;
4550                 next_scb->sg_list = segs;
4551                 /*
4552                  * The sequencer always starts with the second entry.
4553                  * The first entry is embedded in the scb.
4554                  */
4555                 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4556                 next_scb->ahc_softc = ahc;
4557                 next_scb->flags = SCB_FLAG_NONE;
4558 #ifndef __linux__
4559                 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4560                                           &next_scb->dmamap);
4561                 if (error != 0)
4562                         break;
4563 #endif
4564                 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4565                 next_scb->hscb->tag = ahc->scb_data->numscbs;
4566                 aic_timer_init(&next_scb->io_timer);
4567                 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4568                                   next_scb, links.sle);
4569                 segs += AHC_NSEG;
4570                 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4571                 next_scb++;
4572                 ahc->scb_data->numscbs++;
4573         }
4574         return (i);
4575 }
4576
4577 void
4578 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4579 {
4580         int len;
4581
4582         len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4583         buf += len;
4584         if ((ahc->features & AHC_TWIN) != 0)
4585                 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4586                               "B SCSI Id=%d, primary %c, ",
4587                               ahc->our_id, ahc->our_id_b,
4588                               (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4589         else {
4590                 const char *speed;
4591                 const char *type;
4592
4593                 speed = "";
4594                 if ((ahc->features & AHC_ULTRA) != 0) {
4595                         speed = "Ultra ";
4596                 } else if ((ahc->features & AHC_DT) != 0) {
4597                         speed = "Ultra160 ";
4598                 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4599                         speed = "Ultra2 ";
4600                 }
4601                 if ((ahc->features & AHC_WIDE) != 0) {
4602                         type = "Wide";
4603                 } else {
4604                         type = "Single";
4605                 }
4606                 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4607                               speed, type, ahc->channel, ahc->our_id);
4608         }
4609         buf += len;
4610
4611         if ((ahc->flags & AHC_PAGESCBS) != 0)
4612                 sprintf(buf, "%d/%d SCBs",
4613                         ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4614         else
4615                 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4616 }
4617
4618 int
4619 ahc_chip_init(struct ahc_softc *ahc)
4620 {
4621         int      term;
4622         int      error;
4623         u_int    i;
4624         u_int    scsi_conf;
4625         u_int    scsiseq_template;
4626         uint32_t physaddr;
4627
4628         ahc_outb(ahc, SEQ_FLAGS, 0);
4629         ahc_outb(ahc, SEQ_FLAGS2, 0);
4630
4631         /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4632         if (ahc->features & AHC_TWIN) {
4633                 /*
4634                  * Setup Channel B first.
4635                  */
4636                 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4637                 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4638                 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4639                 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4640                 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4641                                         |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4642                 if ((ahc->features & AHC_ULTRA2) != 0)
4643                         ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4644                 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4645                 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4646
4647                 /* Select Channel A */
4648                 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4649         }
4650         term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4651         if ((ahc->features & AHC_ULTRA2) != 0)
4652                 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4653         else
4654                 ahc_outb(ahc, SCSIID, ahc->our_id);
4655         scsi_conf = ahc_inb(ahc, SCSICONF);
4656         ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4657                                 |term|ahc->seltime
4658                                 |ENSTIMER|ACTNEGEN);
4659         if ((ahc->features & AHC_ULTRA2) != 0)
4660                 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4661         ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4662         ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4663
4664         /* There are no untagged SCBs active yet. */
4665         for (i = 0; i < 16; i++) {
4666                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4667                 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4668                         int lun;
4669
4670                         /*
4671                          * The SCB based BTT allows an entry per
4672                          * target and lun pair.
4673                          */
4674                         for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4675                                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4676                 }
4677         }
4678
4679         /* All of our queues are empty */
4680         for (i = 0; i < 256; i++)
4681                 ahc->qoutfifo[i] = SCB_LIST_NULL;
4682         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4683
4684         for (i = 0; i < 256; i++)
4685                 ahc->qinfifo[i] = SCB_LIST_NULL;
4686
4687         if ((ahc->features & AHC_MULTI_TID) != 0) {
4688                 ahc_outb(ahc, TARGID, 0);
4689                 ahc_outb(ahc, TARGID + 1, 0);
4690         }
4691
4692         /*
4693          * Tell the sequencer where it can find our arrays in memory.
4694          */
4695         physaddr = ahc->scb_data->hscb_busaddr;
4696         ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4697         ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4698         ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4699         ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4700
4701         physaddr = ahc->shared_data_busaddr;
4702         ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4703         ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4704         ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4705         ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4706
4707         /*
4708          * Initialize the group code to command length table.
4709          * This overrides the values in TARG_SCSIRATE, so only
4710          * setup the table after we have processed that information.
4711          */
4712         ahc_outb(ahc, CMDSIZE_TABLE, 5);
4713         ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4714         ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4715         ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4716         ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4717         ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4718         ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4719         ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4720
4721         if ((ahc->features & AHC_HS_MAILBOX) != 0)
4722                 ahc_outb(ahc, HS_MAILBOX, 0);
4723
4724         /* Tell the sequencer of our initial queue positions */
4725         if ((ahc->features & AHC_TARGETMODE) != 0) {
4726                 ahc->tqinfifonext = 1;
4727                 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4728                 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4729         }
4730         ahc->qinfifonext = 0;
4731         ahc->qoutfifonext = 0;
4732         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4733                 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4734                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4735                 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4736                 ahc_outb(ahc, SDSCB_QOFF, 0);
4737         } else {
4738                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4739                 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4740                 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4741         }
4742
4743         /* We don't have any waiting selections */
4744         ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4745
4746         /* Our disconnection list is empty too */
4747         ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4748
4749         /* Message out buffer starts empty */
4750         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4751
4752         /*
4753          * Setup the allowed SCSI Sequences based on operational mode.
4754          * If we are a target, we'll enalbe select in operations once
4755          * we've had a lun enabled.
4756          */
4757         scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4758         if ((ahc->flags & AHC_INITIATORROLE) != 0)
4759                 scsiseq_template |= ENRSELI;
4760         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4761
4762         /* Initialize our list of free SCBs. */
4763         ahc_build_free_scb_list(ahc);
4764
4765         /*
4766          * Tell the sequencer which SCB will be the next one it receives.
4767          */
4768         ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4769
4770         /*
4771          * Load the Sequencer program and Enable the adapter
4772          * in "fast" mode.
4773          */
4774         if (bootverbose)
4775                 printf("%s: Downloading Sequencer Program...",
4776                        ahc_name(ahc));
4777
4778         error = ahc_loadseq(ahc);
4779         if (error != 0)
4780                 return (error);
4781
4782         if ((ahc->features & AHC_ULTRA2) != 0) {
4783                 int wait;
4784
4785                 /*
4786                  * Wait for up to 500ms for our transceivers
4787                  * to settle.  If the adapter does not have
4788                  * a cable attached, the transceivers may
4789                  * never settle, so don't complain if we
4790                  * fail here.
4791                  */
4792                 for (wait = 5000;
4793                      (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4794                      wait--)
4795                         aic_delay(100);
4796         }
4797         ahc_restart(ahc);
4798         return (0);
4799 }
4800
4801 /*
4802  * Start the board, ready for normal operation
4803  */
4804 int
4805 ahc_init(struct ahc_softc *ahc)
4806 {
4807         int      max_targ;
4808         int      error;
4809         u_int    i;
4810         u_int    scsi_conf;
4811         u_int    ultraenb;
4812         u_int    discenable;
4813         u_int    tagenable;
4814         size_t   driver_data_size;
4815
4816 #ifdef AHC_DEBUG
4817         if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4818                 ahc->flags |= AHC_SEQUENCER_DEBUG;
4819 #endif
4820
4821 #ifdef AHC_PRINT_SRAM
4822         printf("Scratch Ram:");
4823         for (i = 0x20; i < 0x5f; i++) {
4824                 if (((i % 8) == 0) && (i != 0)) {
4825                         printf ("\n              ");
4826                 }
4827                 printf (" 0x%x", ahc_inb(ahc, i));
4828         }
4829         if ((ahc->features & AHC_MORE_SRAM) != 0) {
4830                 for (i = 0x70; i < 0x7f; i++) {
4831                         if (((i % 8) == 0) && (i != 0)) {
4832                                 printf ("\n              ");
4833                         }
4834                         printf (" 0x%x", ahc_inb(ahc, i));
4835                 }
4836         }
4837         printf ("\n");
4838         /*
4839          * Reading uninitialized scratch ram may
4840          * generate parity errors.
4841          */
4842         ahc_outb(ahc, CLRINT, CLRPARERR);
4843         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4844 #endif
4845         max_targ = 15;
4846
4847         /*
4848          * Assume we have a board at this stage and it has been reset.
4849          */
4850         if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4851                 ahc->our_id = ahc->our_id_b = 7;
4852
4853         /*
4854          * Default to allowing initiator operations.
4855          */
4856         ahc->flags |= AHC_INITIATORROLE;
4857
4858         /*
4859          * Only allow target mode features if this unit has them enabled.
4860          */
4861         if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4862                 ahc->features &= ~AHC_TARGETMODE;
4863
4864 #ifndef __linux__
4865         /* DMA tag for mapping buffers into device visible space. */
4866         if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4867                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4868                                /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4869                                         ? (bus_addr_t)0x7FFFFFFFFFULL
4870                                         : BUS_SPACE_MAXADDR_32BIT,
4871                                /*highaddr*/BUS_SPACE_MAXADDR,
4872                                /*filter*/NULL, /*filterarg*/NULL,
4873                                /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4874                                /*nsegments*/AHC_NSEG,
4875                                /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4876                                /*flags*/BUS_DMA_ALLOCNOW,
4877                                &ahc->buffer_dmat) != 0) {
4878                 return (ENOMEM);
4879         }
4880 #endif
4881
4882         ahc->init_level++;
4883
4884         /*
4885          * DMA tag for our command fifos and other data in system memory
4886          * the card's sequencer must be able to access.  For initiator
4887          * roles, we need to allocate space for the qinfifo and qoutfifo.
4888          * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4889          * When providing for the target mode role, we must additionally
4890          * provide space for the incoming target command fifo and an extra
4891          * byte to deal with a dma bug in some chip versions.
4892          */
4893         driver_data_size = 2 * 256 * sizeof(uint8_t);
4894         if ((ahc->features & AHC_TARGETMODE) != 0)
4895                 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4896                                  + /*DMA WideOdd Bug Buffer*/1;
4897         if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4898                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4899                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4900                                /*highaddr*/BUS_SPACE_MAXADDR,
4901                                /*filter*/NULL, /*filterarg*/NULL,
4902                                driver_data_size,
4903                                /*nsegments*/1,
4904                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4905                                /*flags*/0, &ahc->shared_data_dmat) != 0) {
4906                 return (ENOMEM);
4907         }
4908
4909         ahc->init_level++;
4910
4911         /* Allocation of driver data */
4912         if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4913                              (void **)&ahc->qoutfifo,
4914                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4915                              &ahc->shared_data_dmamap) != 0) {
4916                 return (ENOMEM);
4917         }
4918
4919         ahc->init_level++;
4920
4921         /* And permanently map it in */
4922         aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4923                         ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4924                         &ahc->shared_data_busaddr, /*flags*/0);
4925
4926         if ((ahc->features & AHC_TARGETMODE) != 0) {
4927                 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4928                 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4929                 ahc->dma_bug_buf = ahc->shared_data_busaddr
4930                                  + driver_data_size - 1;
4931                 /* All target command blocks start out invalid. */
4932                 for (i = 0; i < AHC_TMODE_CMDS; i++)
4933                         ahc->targetcmds[i].cmd_valid = 0;
4934                 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4935                 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4936         }
4937         ahc->qinfifo = &ahc->qoutfifo[256];
4938
4939         ahc->init_level++;
4940
4941         /* Allocate SCB data now that buffer_dmat is initialized */
4942         if (ahc->scb_data->maxhscbs == 0)
4943                 if (ahc_init_scbdata(ahc) != 0)
4944                         return (ENOMEM);
4945
4946         /*
4947          * Allocate a tstate to house information for our
4948          * initiator presence on the bus as well as the user
4949          * data for any target mode initiator.
4950          */
4951         if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4952                 printf("%s: unable to allocate ahc_tmode_tstate.  "
4953                        "Failing attach\n", ahc_name(ahc));
4954                 return (ENOMEM);
4955         }
4956
4957         if ((ahc->features & AHC_TWIN) != 0) {
4958                 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4959                         printf("%s: unable to allocate ahc_tmode_tstate.  "
4960                                "Failing attach\n", ahc_name(ahc));
4961                         return (ENOMEM);
4962                 }
4963         }
4964
4965         /*
4966          * Fire up a recovery thread for this controller.
4967          */
4968         error = ahc_spawn_recovery_thread(ahc);
4969         if (error != 0)
4970                 return (error);
4971
4972         if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4973                 ahc->flags |= AHC_PAGESCBS;
4974         } else {
4975                 ahc->flags &= ~AHC_PAGESCBS;
4976         }
4977
4978 #ifdef AHC_DEBUG
4979         if (ahc_debug & AHC_SHOW_MISC) {
4980                 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4981                        "ahc_dma %u bytes\n",
4982                         ahc_name(ahc),
4983                         (u_int)sizeof(struct hardware_scb),
4984                         (u_int)sizeof(struct scb),
4985                         (u_int)sizeof(struct ahc_dma_seg));
4986         }
4987 #endif /* AHC_DEBUG */
4988
4989         /*
4990          * Look at the information that board initialization or
4991          * the board bios has left us.
4992          */
4993         if (ahc->features & AHC_TWIN) {
4994                 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4995                 if ((scsi_conf & RESET_SCSI) != 0
4996                  && (ahc->flags & AHC_INITIATORROLE) != 0)
4997                         ahc->flags |= AHC_RESET_BUS_B;
4998         }
4999
5000         scsi_conf = ahc_inb(ahc, SCSICONF);
5001         if ((scsi_conf & RESET_SCSI) != 0
5002          && (ahc->flags & AHC_INITIATORROLE) != 0)
5003                 ahc->flags |= AHC_RESET_BUS_A;
5004
5005         ultraenb = 0;
5006         tagenable = ALL_TARGETS_MASK;
5007
5008         /* Grab the disconnection disable table and invert it for our needs */
5009         if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5010                 printf("%s: Host Adapter Bios disabled.  Using default SCSI "
5011                         "device parameters\n", ahc_name(ahc));
5012                 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5013                               AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5014                 discenable = ALL_TARGETS_MASK;
5015                 if ((ahc->features & AHC_ULTRA) != 0)
5016                         ultraenb = ALL_TARGETS_MASK;
5017         } else {
5018                 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5019                            | ahc_inb(ahc, DISC_DSB));
5020                 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5021                         ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5022                                       | ahc_inb(ahc, ULTRA_ENB);
5023         }
5024
5025         if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5026                 max_targ = 7;
5027
5028         for (i = 0; i <= max_targ; i++) {
5029                 struct ahc_initiator_tinfo *tinfo;
5030                 struct ahc_tmode_tstate *tstate;
5031                 u_int our_id;
5032                 u_int target_id;
5033                 char channel;
5034
5035                 channel = 'A';
5036                 our_id = ahc->our_id;
5037                 target_id = i;
5038                 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5039                         channel = 'B';
5040                         our_id = ahc->our_id_b;
5041                         target_id = i % 8;
5042                 }
5043                 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5044                                             target_id, &tstate);
5045                 /* Default to async narrow across the board */
5046                 memset(tinfo, 0, sizeof(*tinfo));
5047                 if (ahc->flags & AHC_USEDEFAULTS) {
5048                         if ((ahc->features & AHC_WIDE) != 0)
5049                                 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5050
5051                         /*
5052                          * These will be truncated when we determine the
5053                          * connection type we have with the target.
5054                          */
5055                         tinfo->user.period = ahc_syncrates->period;
5056                         tinfo->user.offset = MAX_OFFSET;
5057                 } else {
5058                         u_int scsirate;
5059                         uint16_t mask;
5060
5061                         /* Take the settings leftover in scratch RAM. */
5062                         scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5063                         mask = (0x01 << i);
5064                         if ((ahc->features & AHC_ULTRA2) != 0) {
5065                                 u_int offset;
5066                                 u_int maxsync;
5067
5068                                 if ((scsirate & SOFS) == 0x0F) {
5069                                         /*
5070                                          * Haven't negotiated yet,
5071                                          * so the format is different.
5072                                          */
5073                                         scsirate = (scsirate & SXFR) >> 4
5074                                                  | (ultraenb & mask)
5075                                                   ? 0x08 : 0x0
5076                                                  | (scsirate & WIDEXFER);
5077                                         offset = MAX_OFFSET_ULTRA2;
5078                                 } else
5079                                         offset = ahc_inb(ahc, TARG_OFFSET + i);
5080                                 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5081                                         /* Set to the lowest sync rate, 5MHz */
5082                                         scsirate |= 0x1c;
5083                                 maxsync = AHC_SYNCRATE_ULTRA2;
5084                                 if ((ahc->features & AHC_DT) != 0)
5085                                         maxsync = AHC_SYNCRATE_DT;
5086                                 tinfo->user.period =
5087                                     ahc_find_period(ahc, scsirate, maxsync);
5088                                 if (offset == 0)
5089                                         tinfo->user.period = 0;
5090                                 else
5091                                         tinfo->user.offset = MAX_OFFSET;
5092                                 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5093                                  && (ahc->features & AHC_DT) != 0)
5094                                         tinfo->user.ppr_options =
5095                                             MSG_EXT_PPR_DT_REQ;
5096                         } else if ((scsirate & SOFS) != 0) {
5097                                 if ((scsirate & SXFR) == 0x40
5098                                  && (ultraenb & mask) != 0) {
5099                                         /* Treat 10MHz as a non-ultra speed */
5100                                         scsirate &= ~SXFR;
5101                                         ultraenb &= ~mask;
5102                                 }
5103                                 tinfo->user.period =
5104                                     ahc_find_period(ahc, scsirate,
5105                                                     (ultraenb & mask)
5106                                                    ? AHC_SYNCRATE_ULTRA
5107                                                    : AHC_SYNCRATE_FAST);
5108                                 if (tinfo->user.period != 0)
5109                                         tinfo->user.offset = MAX_OFFSET;
5110                         }
5111                         if (tinfo->user.period == 0)
5112                                 tinfo->user.offset = 0;
5113                         if ((scsirate & WIDEXFER) != 0
5114                          && (ahc->features & AHC_WIDE) != 0)
5115                                 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5116                         tinfo->user.protocol_version = 4;
5117                         if ((ahc->features & AHC_DT) != 0)
5118                                 tinfo->user.transport_version = 3;
5119                         else
5120                                 tinfo->user.transport_version = 2;
5121                         tinfo->goal.protocol_version = 2;
5122                         tinfo->goal.transport_version = 2;
5123                         tinfo->curr.protocol_version = 2;
5124                         tinfo->curr.transport_version = 2;
5125                 }
5126                 tstate->ultraenb = 0;
5127         }
5128         ahc->user_discenable = discenable;
5129         ahc->user_tagenable = tagenable;
5130
5131         return (ahc->bus_chip_init(ahc));
5132 }
5133
5134 void
5135 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5136 {
5137         u_int hcntrl;
5138
5139         hcntrl = ahc_inb(ahc, HCNTRL);
5140         hcntrl &= ~INTEN;
5141         ahc->pause &= ~INTEN;
5142         ahc->unpause &= ~INTEN;
5143         if (enable) {
5144                 hcntrl |= INTEN;
5145                 ahc->pause |= INTEN;
5146                 ahc->unpause |= INTEN;
5147         }
5148         ahc_outb(ahc, HCNTRL, hcntrl);
5149 }
5150
5151 /*
5152  * Ensure that the card is paused in a location
5153  * outside of all critical sections and that all
5154  * pending work is completed prior to returning.
5155  * This routine should only be called from outside
5156  * an interrupt context.
5157  */
5158 void
5159 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5160 {
5161         int intstat;
5162         int maxloops;
5163         int paused;
5164
5165         maxloops = 1000;
5166         ahc->flags |= AHC_ALL_INTERRUPTS;
5167         paused = FALSE;
5168         do {
5169                 if (paused) {
5170                         ahc_unpause(ahc);
5171                         /*
5172                          * Give the sequencer some time to service
5173                          * any active selections.
5174                          */
5175                         aic_delay(500);
5176                 }
5177                 ahc_intr(ahc);
5178                 ahc_pause(ahc);
5179                 paused = TRUE;
5180                 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5181                 intstat = ahc_inb(ahc, INTSTAT);
5182                 if ((intstat & INT_PEND) == 0) {
5183                         ahc_clear_critical_section(ahc);
5184                         intstat = ahc_inb(ahc, INTSTAT);
5185                 }
5186         } while (--maxloops
5187               && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5188               && ((intstat & INT_PEND) != 0
5189                || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5190         if (maxloops == 0) {
5191                 printf("Infinite interrupt loop, INTSTAT = %x",
5192                        ahc_inb(ahc, INTSTAT));
5193         }
5194         ahc_platform_flushwork(ahc);
5195         ahc->flags &= ~AHC_ALL_INTERRUPTS;
5196 }
5197
5198 int
5199 ahc_suspend(struct ahc_softc *ahc)
5200 {
5201
5202         ahc_pause_and_flushwork(ahc);
5203
5204         if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5205                 ahc_unpause(ahc);
5206                 return (EBUSY);
5207         }
5208
5209 #ifdef AHC_TARGET_MODE
5210         /*
5211          * XXX What about ATIOs that have not yet been serviced?
5212          * Perhaps we should just refuse to be suspended if we
5213          * are acting in a target role.
5214          */
5215         if (ahc->pending_device != NULL) {
5216                 ahc_unpause(ahc);
5217                 return (EBUSY);
5218         }
5219 #endif
5220         ahc_shutdown(ahc);
5221         return (0);
5222 }
5223
5224 int
5225 ahc_resume(struct ahc_softc *ahc)
5226 {
5227
5228         ahc_reset(ahc, /*reinit*/TRUE);
5229         ahc_intr_enable(ahc, TRUE);
5230         ahc_restart(ahc);
5231         return (0);
5232 }
5233
5234 /************************** Busy Target Table *********************************/
5235 /*
5236  * Return the untagged transaction id for a given target/channel lun.
5237  * Optionally, clear the entry.
5238  */
5239 u_int
5240 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5241 {
5242         u_int scbid;
5243         u_int target_offset;
5244
5245         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5246                 u_int saved_scbptr;
5247
5248                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5249                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5250                 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5251                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5252         } else {
5253                 target_offset = TCL_TARGET_OFFSET(tcl);
5254                 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5255         }
5256
5257         return (scbid);
5258 }
5259
5260 void
5261 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5262 {
5263         u_int target_offset;
5264
5265         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5266                 u_int saved_scbptr;
5267
5268                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5269                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5270                 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5271                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5272         } else {
5273                 target_offset = TCL_TARGET_OFFSET(tcl);
5274                 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5275         }
5276 }
5277
5278 void
5279 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5280 {
5281         u_int target_offset;
5282
5283         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5284                 u_int saved_scbptr;
5285
5286                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5287                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5288                 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5289                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5290         } else {
5291                 target_offset = TCL_TARGET_OFFSET(tcl);
5292                 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5293         }
5294 }
5295
5296 /************************** SCB and SCB queue management **********************/
5297 int
5298 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5299               char channel, int lun, u_int tag, role_t role)
5300 {
5301         int targ = SCB_GET_TARGET(ahc, scb);
5302         char chan = SCB_GET_CHANNEL(ahc, scb);
5303         int slun = SCB_GET_LUN(scb);
5304         int match;
5305
5306         match = ((chan == channel) || (channel == ALL_CHANNELS));
5307         if (match != 0)
5308                 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5309         if (match != 0)
5310                 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5311         if (match != 0) {
5312 #ifdef AHC_TARGET_MODE
5313                 int group;
5314
5315                 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5316                 if (role == ROLE_INITIATOR) {
5317                         match = (group != XPT_FC_GROUP_TMODE)
5318                               && ((tag == scb->hscb->tag)
5319                                || (tag == SCB_LIST_NULL));
5320                 } else if (role == ROLE_TARGET) {
5321                         match = (group == XPT_FC_GROUP_TMODE)
5322                               && ((tag == scb->io_ctx->csio.tag_id)
5323                                || (tag == SCB_LIST_NULL));
5324                 }
5325 #else /* !AHC_TARGET_MODE */
5326                 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5327 #endif /* AHC_TARGET_MODE */
5328         }
5329
5330         return match;
5331 }
5332
5333 void
5334 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5335 {
5336         int     target;
5337         char    channel;
5338         int     lun;
5339
5340         target = SCB_GET_TARGET(ahc, scb);
5341         lun = SCB_GET_LUN(scb);
5342         channel = SCB_GET_CHANNEL(ahc, scb);
5343
5344         ahc_search_qinfifo(ahc, target, channel, lun,
5345                            /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5346                            CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5347
5348         ahc_platform_freeze_devq(ahc, scb);
5349 }
5350
5351 void
5352 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5353 {
5354         struct scb *prev_scb;
5355
5356         prev_scb = NULL;
5357         if (ahc_qinfifo_count(ahc) != 0) {
5358                 u_int prev_tag;
5359                 uint8_t prev_pos;
5360
5361                 prev_pos = ahc->qinfifonext - 1;
5362                 prev_tag = ahc->qinfifo[prev_pos];
5363                 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5364         }
5365         ahc_qinfifo_requeue(ahc, prev_scb, scb);
5366         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5367                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5368         } else {
5369                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5370         }
5371 }
5372
5373 static void
5374 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5375                     struct scb *scb)
5376 {
5377         if (prev_scb == NULL) {
5378                 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5379         } else {
5380                 prev_scb->hscb->next = scb->hscb->tag;
5381                 ahc_sync_scb(ahc, prev_scb,
5382                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5383         }
5384         ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5385         scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5386         ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5387 }
5388
5389 static int
5390 ahc_qinfifo_count(struct ahc_softc *ahc)
5391 {
5392         uint8_t qinpos;
5393         uint8_t diff;
5394
5395         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5396                 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5397                 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5398         } else
5399                 qinpos = ahc_inb(ahc, QINPOS);
5400         diff = ahc->qinfifonext - qinpos;
5401         return (diff);
5402 }
5403
5404 int
5405 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5406                    int lun, u_int tag, role_t role, uint32_t status,
5407                    ahc_search_action action)
5408 {
5409         struct  scb *scb;
5410         struct  scb *prev_scb;
5411         uint8_t qinstart;
5412         uint8_t qinpos;
5413         uint8_t qintail;
5414         uint8_t next;
5415         uint8_t prev;
5416         uint8_t curscbptr;
5417         int     found;
5418         int     have_qregs;
5419
5420         qintail = ahc->qinfifonext;
5421         have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5422         if (have_qregs) {
5423                 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5424                 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5425         } else
5426                 qinstart = ahc_inb(ahc, QINPOS);
5427         qinpos = qinstart;
5428         found = 0;
5429         prev_scb = NULL;
5430
5431         if (action == SEARCH_COMPLETE) {
5432                 /*
5433                  * Don't attempt to run any queued untagged transactions
5434                  * until we are done with the abort process.
5435                  */
5436                 ahc_freeze_untagged_queues(ahc);
5437         }
5438
5439         /*
5440          * Start with an empty queue.  Entries that are not chosen
5441          * for removal will be re-added to the queue as we go.
5442          */
5443         ahc->qinfifonext = qinpos;
5444         ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5445
5446         while (qinpos != qintail) {
5447                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5448                 if (scb == NULL) {
5449                         printf("qinpos = %d, SCB index = %d\n",
5450                                 qinpos, ahc->qinfifo[qinpos]);
5451                         panic("Loop 1\n");
5452                 }
5453
5454                 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5455                         /*
5456                          * We found an scb that needs to be acted on.
5457                          */
5458                         found++;
5459                         switch (action) {
5460                         case SEARCH_COMPLETE:
5461                         {
5462                                 cam_status ostat;
5463                                 cam_status cstat;
5464
5465                                 ostat = aic_get_transaction_status(scb);
5466                                 if (ostat == CAM_REQ_INPROG)
5467                                         aic_set_transaction_status(scb, status);
5468                                 cstat = aic_get_transaction_status(scb);
5469                                 if (cstat != CAM_REQ_CMP)
5470                                         aic_freeze_scb(scb);
5471                                 if ((scb->flags & SCB_ACTIVE) == 0)
5472                                         printf("Inactive SCB in qinfifo\n");
5473                                 ahc_done(ahc, scb);
5474
5475                                 /* FALLTHROUGH */
5476                         }
5477                         case SEARCH_REMOVE:
5478                                 break;
5479                         case SEARCH_COUNT:
5480                                 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5481                                 prev_scb = scb;
5482                                 break;
5483                         }
5484                 } else {
5485                         ahc_qinfifo_requeue(ahc, prev_scb, scb);
5486                         prev_scb = scb;
5487                 }
5488                 qinpos++;
5489         }
5490
5491         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5492                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5493         } else {
5494                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5495         }
5496
5497         if (action != SEARCH_COUNT
5498          && (found != 0)
5499          && (qinstart != ahc->qinfifonext)) {
5500                 /*
5501                  * The sequencer may be in the process of dmaing
5502                  * down the SCB at the beginning of the queue.
5503                  * This could be problematic if either the first,
5504                  * or the second SCB is removed from the queue
5505                  * (the first SCB includes a pointer to the "next"
5506                  * SCB to dma). If we have removed any entries, swap
5507                  * the first element in the queue with the next HSCB
5508                  * so the sequencer will notice that NEXT_QUEUED_SCB
5509                  * has changed during its dma attempt and will retry
5510                  * the DMA.
5511                  */
5512                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5513
5514                 if (scb == NULL) {
5515                         printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5516                                 found, qinstart, ahc->qinfifonext);
5517                         panic("First/Second Qinfifo fixup\n");
5518                 }
5519                 /*
5520                  * ahc_swap_with_next_hscb forces our next pointer to
5521                  * point to the reserved SCB for future commands.  Save
5522                  * and restore our original next pointer to maintain
5523                  * queue integrity.
5524                  */
5525                 next = scb->hscb->next;
5526                 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5527                 ahc_swap_with_next_hscb(ahc, scb);
5528                 scb->hscb->next = next;
5529                 ahc->qinfifo[qinstart] = scb->hscb->tag;
5530
5531                 /* Tell the card about the new head of the qinfifo. */
5532                 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5533
5534                 /* Fixup the tail "next" pointer. */
5535                 qintail = ahc->qinfifonext - 1;
5536                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5537                 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5538         }
5539
5540         /*
5541          * Search waiting for selection list.
5542          */
5543         curscbptr = ahc_inb(ahc, SCBPTR);
5544         next = ahc_inb(ahc, WAITING_SCBH);  /* Start at head of list. */
5545         prev = SCB_LIST_NULL;
5546
5547         while (next != SCB_LIST_NULL) {
5548                 uint8_t scb_index;
5549
5550                 ahc_outb(ahc, SCBPTR, next);
5551                 scb_index = ahc_inb(ahc, SCB_TAG);
5552                 if (scb_index >= ahc->scb_data->numscbs) {
5553                         printf("Waiting List inconsistency. "
5554                                "SCB index == %d, yet numscbs == %d.",
5555                                scb_index, ahc->scb_data->numscbs);
5556                         ahc_dump_card_state(ahc);
5557                         panic("for safety");
5558                 }
5559                 scb = ahc_lookup_scb(ahc, scb_index);
5560                 if (scb == NULL) {
5561                         printf("scb_index = %d, next = %d\n",
5562                                 scb_index, next);
5563                         panic("Waiting List traversal\n");
5564                 }
5565                 if (ahc_match_scb(ahc, scb, target, channel,
5566                                   lun, SCB_LIST_NULL, role)) {
5567                         /*
5568                          * We found an scb that needs to be acted on.
5569                          */
5570                         found++;
5571                         switch (action) {
5572                         case SEARCH_COMPLETE:
5573                         {
5574                                 cam_status ostat;
5575                                 cam_status cstat;
5576
5577                                 ostat = aic_get_transaction_status(scb);
5578                                 if (ostat == CAM_REQ_INPROG)
5579                                         aic_set_transaction_status(scb,
5580                                                                    status);
5581                                 cstat = aic_get_transaction_status(scb);
5582                                 if (cstat != CAM_REQ_CMP)
5583                                         aic_freeze_scb(scb);
5584                                 if ((scb->flags & SCB_ACTIVE) == 0)
5585                                         printf("Inactive SCB in Wait List\n");
5586                                 ahc_done(ahc, scb);
5587                                 /* FALLTHROUGH */
5588                         }
5589                         case SEARCH_REMOVE:
5590                                 next = ahc_rem_wscb(ahc, next, prev);
5591                                 break;
5592                         case SEARCH_COUNT:
5593                                 prev = next;
5594                                 next = ahc_inb(ahc, SCB_NEXT);
5595                                 break;
5596                         }
5597                 } else {
5598
5599                         prev = next;
5600                         next = ahc_inb(ahc, SCB_NEXT);
5601                 }
5602         }
5603         ahc_outb(ahc, SCBPTR, curscbptr);
5604
5605         found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5606                                             channel, lun, status, action);
5607
5608         if (action == SEARCH_COMPLETE)
5609                 ahc_release_untagged_queues(ahc);
5610         return (found);
5611 }
5612
5613 int
5614 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5615                            int target, char channel, int lun, uint32_t status,
5616                            ahc_search_action action)
5617 {
5618         struct  scb *scb;
5619         int     maxtarget;
5620         int     found;
5621         int     i;
5622
5623         if (action == SEARCH_COMPLETE) {
5624                 /*
5625                  * Don't attempt to run any queued untagged transactions
5626                  * until we are done with the abort process.
5627                  */
5628                 ahc_freeze_untagged_queues(ahc);
5629         }
5630
5631         found = 0;
5632         i = 0;
5633         if ((ahc->flags & AHC_SCB_BTT) == 0) {
5634                 maxtarget = 16;
5635                 if (target != CAM_TARGET_WILDCARD) {
5636                         i = target;
5637                         if (channel == 'B')
5638                                 i += 8;
5639                         maxtarget = i + 1;
5640                 }
5641         } else {
5642                 maxtarget = 0;
5643         }
5644
5645         for (; i < maxtarget; i++) {
5646                 struct scb_tailq *untagged_q;
5647                 struct scb *next_scb;
5648
5649                 untagged_q = &(ahc->untagged_queues[i]);
5650                 next_scb = TAILQ_FIRST(untagged_q);
5651                 while (next_scb != NULL) {
5652                         scb = next_scb;
5653                         next_scb = TAILQ_NEXT(scb, links.tqe);
5654
5655                         /*
5656                          * The head of the list may be the currently
5657                          * active untagged command for a device.
5658                          * We're only searching for commands that
5659                          * have not been started.  A transaction
5660                          * marked active but still in the qinfifo
5661                          * is removed by the qinfifo scanning code
5662                          * above.
5663                          */
5664                         if ((scb->flags & SCB_ACTIVE) != 0)
5665                                 continue;
5666
5667                         if (ahc_match_scb(ahc, scb, target, channel, lun,
5668                                           SCB_LIST_NULL, ROLE_INITIATOR) == 0
5669                          || (ctx != NULL && ctx != scb->io_ctx))
5670                                 continue;
5671
5672                         /*
5673                          * We found an scb that needs to be acted on.
5674                          */
5675                         found++;
5676                         switch (action) {
5677                         case SEARCH_COMPLETE:
5678                         {
5679                                 cam_status ostat;
5680                                 cam_status cstat;
5681
5682                                 ostat = aic_get_transaction_status(scb);
5683                                 if (ostat == CAM_REQ_INPROG)
5684                                         aic_set_transaction_status(scb, status);
5685                                 cstat = aic_get_transaction_status(scb);
5686                                 if (cstat != CAM_REQ_CMP)
5687                                         aic_freeze_scb(scb);
5688                                 ahc_done(ahc, scb);
5689                                 break;
5690                         }
5691                         case SEARCH_REMOVE:
5692                                 scb->flags &= ~SCB_UNTAGGEDQ;
5693                                 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5694                                 break;
5695                         case SEARCH_COUNT:
5696                                 break;
5697                         }
5698                 }
5699         }
5700
5701         if (action == SEARCH_COMPLETE)
5702                 ahc_release_untagged_queues(ahc);
5703         return (found);
5704 }
5705
5706 int
5707 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5708                      int lun, u_int tag, int stop_on_first, int remove,
5709                      int save_state)
5710 {
5711         struct  scb *scbp;
5712         u_int   next;
5713         u_int   prev;
5714         u_int   count;
5715         u_int   active_scb;
5716
5717         count = 0;
5718         next = ahc_inb(ahc, DISCONNECTED_SCBH);
5719         prev = SCB_LIST_NULL;
5720
5721         if (save_state) {
5722                 /* restore this when we're done */
5723                 active_scb = ahc_inb(ahc, SCBPTR);
5724         } else
5725                 /* Silence compiler */
5726                 active_scb = SCB_LIST_NULL;
5727
5728         while (next != SCB_LIST_NULL) {
5729                 u_int scb_index;
5730
5731                 ahc_outb(ahc, SCBPTR, next);
5732                 scb_index = ahc_inb(ahc, SCB_TAG);
5733                 if (scb_index >= ahc->scb_data->numscbs) {
5734                         printf("Disconnected List inconsistency. "
5735                                "SCB index == %d, yet numscbs == %d.",
5736                                scb_index, ahc->scb_data->numscbs);
5737                         ahc_dump_card_state(ahc);
5738                         panic("for safety");
5739                 }
5740
5741                 if (next == prev) {
5742                         panic("Disconnected List Loop. "
5743                               "cur SCBPTR == %x, prev SCBPTR == %x.",
5744                               next, prev);
5745                 }
5746                 scbp = ahc_lookup_scb(ahc, scb_index);
5747                 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5748                                   tag, ROLE_INITIATOR)) {
5749                         count++;
5750                         if (remove) {
5751                                 next =
5752                                     ahc_rem_scb_from_disc_list(ahc, prev, next);
5753                         } else {
5754                                 prev = next;
5755                                 next = ahc_inb(ahc, SCB_NEXT);
5756                         }
5757                         if (stop_on_first)
5758                                 break;
5759                 } else {
5760                         prev = next;
5761                         next = ahc_inb(ahc, SCB_NEXT);
5762                 }
5763         }
5764         if (save_state)
5765                 ahc_outb(ahc, SCBPTR, active_scb);
5766         return (count);
5767 }
5768
5769 /*
5770  * Remove an SCB from the on chip list of disconnected transactions.
5771  * This is empty/unused if we are not performing SCB paging.
5772  */
5773 static u_int
5774 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5775 {
5776         u_int next;
5777
5778         ahc_outb(ahc, SCBPTR, scbptr);
5779         next = ahc_inb(ahc, SCB_NEXT);
5780
5781         ahc_outb(ahc, SCB_CONTROL, 0);
5782
5783         ahc_add_curscb_to_free_list(ahc);
5784
5785         if (prev != SCB_LIST_NULL) {
5786                 ahc_outb(ahc, SCBPTR, prev);
5787                 ahc_outb(ahc, SCB_NEXT, next);
5788         } else
5789                 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5790
5791         return (next);
5792 }
5793
5794 /*
5795  * Add the SCB as selected by SCBPTR onto the on chip list of
5796  * free hardware SCBs.  This list is empty/unused if we are not
5797  * performing SCB paging.
5798  */
5799 static void
5800 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5801 {
5802         /*
5803          * Invalidate the tag so that our abort
5804          * routines don't think it's active.
5805          */
5806         ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5807
5808         if ((ahc->flags & AHC_PAGESCBS) != 0) {
5809                 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5810                 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5811         }
5812 }
5813
5814 /*
5815  * Manipulate the waiting for selection list and return the
5816  * scb that follows the one that we remove.
5817  */
5818 static u_int
5819 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5820 {
5821         u_int curscb, next;
5822
5823         /*
5824          * Select the SCB we want to abort and
5825          * pull the next pointer out of it.
5826          */
5827         curscb = ahc_inb(ahc, SCBPTR);
5828         ahc_outb(ahc, SCBPTR, scbpos);
5829         next = ahc_inb(ahc, SCB_NEXT);
5830
5831         /* Clear the necessary fields */
5832         ahc_outb(ahc, SCB_CONTROL, 0);
5833
5834         ahc_add_curscb_to_free_list(ahc);
5835
5836         /* update the waiting list */
5837         if (prev == SCB_LIST_NULL) {
5838                 /* First in the list */
5839                 ahc_outb(ahc, WAITING_SCBH, next);
5840
5841                 /*
5842                  * Ensure we aren't attempting to perform
5843                  * selection for this entry.
5844                  */
5845                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5846         } else {
5847                 /*
5848                  * Select the scb that pointed to us
5849                  * and update its next pointer.
5850                  */
5851                 ahc_outb(ahc, SCBPTR, prev);
5852                 ahc_outb(ahc, SCB_NEXT, next);
5853         }
5854
5855         /*
5856          * Point us back at the original scb position.
5857          */
5858         ahc_outb(ahc, SCBPTR, curscb);
5859         return next;
5860 }
5861
5862 /******************************** Error Handling ******************************/
5863 /*
5864  * Abort all SCBs that match the given description (target/channel/lun/tag),
5865  * setting their status to the passed in status if the status has not already
5866  * been modified from CAM_REQ_INPROG.  This routine assumes that the sequencer
5867  * is paused before it is called.
5868  */
5869 int
5870 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5871                int lun, u_int tag, role_t role, uint32_t status)
5872 {
5873         struct  scb *scbp;
5874         struct  scb *scbp_next;
5875         u_int   active_scb;
5876         int     i, j;
5877         int     maxtarget;
5878         int     minlun;
5879         int     maxlun;
5880
5881         int     found;
5882
5883         /*
5884          * Don't attempt to run any queued untagged transactions
5885          * until we are done with the abort process.
5886          */
5887         ahc_freeze_untagged_queues(ahc);
5888
5889         /* restore this when we're done */
5890         active_scb = ahc_inb(ahc, SCBPTR);
5891
5892         found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5893                                    role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5894
5895         /*
5896          * Clean out the busy target table for any untagged commands.
5897          */
5898         i = 0;
5899         maxtarget = 16;
5900         if (target != CAM_TARGET_WILDCARD) {
5901                 i = target;
5902                 if (channel == 'B')
5903                         i += 8;
5904                 maxtarget = i + 1;
5905         }
5906
5907         if (lun == CAM_LUN_WILDCARD) {
5908                 /*
5909                  * Unless we are using an SCB based
5910                  * busy targets table, there is only
5911                  * one table entry for all luns of
5912                  * a target.
5913                  */
5914                 minlun = 0;
5915                 maxlun = 1;
5916                 if ((ahc->flags & AHC_SCB_BTT) != 0)
5917                         maxlun = AHC_NUM_LUNS;
5918         } else {
5919                 minlun = lun;
5920                 maxlun = lun + 1;
5921         }
5922
5923         if (role != ROLE_TARGET) {
5924                 for (;i < maxtarget; i++) {
5925                         for (j = minlun;j < maxlun; j++) {
5926                                 u_int scbid;
5927                                 u_int tcl;
5928
5929                                 tcl = BUILD_TCL(i << 4, j);
5930                                 scbid = ahc_index_busy_tcl(ahc, tcl);
5931                                 scbp = ahc_lookup_scb(ahc, scbid);
5932                                 if (scbp == NULL
5933                                  || ahc_match_scb(ahc, scbp, target, channel,
5934                                                   lun, tag, role) == 0)
5935                                         continue;
5936                                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5937                         }
5938                 }
5939
5940                 /*
5941                  * Go through the disconnected list and remove any entries we
5942                  * have queued for completion, 0'ing their control byte too.
5943                  * We save the active SCB and restore it ourselves, so there
5944                  * is no reason for this search to restore it too.
5945                  */
5946                 ahc_search_disc_list(ahc, target, channel, lun, tag,
5947                                      /*stop_on_first*/FALSE, /*remove*/TRUE,
5948                                      /*save_state*/FALSE);
5949         }
5950
5951         /*
5952          * Go through the hardware SCB array looking for commands that
5953          * were active but not on any list.  In some cases, these remnants
5954          * might not still have mappings in the scbindex array (e.g. unexpected
5955          * bus free with the same scb queued for an abort).  Don't hold this
5956          * against them.
5957          */
5958         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5959                 u_int scbid;
5960
5961                 ahc_outb(ahc, SCBPTR, i);
5962                 scbid = ahc_inb(ahc, SCB_TAG);
5963                 scbp = ahc_lookup_scb(ahc, scbid);
5964                 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5965                  || (scbp != NULL
5966                   && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5967                         ahc_add_curscb_to_free_list(ahc);
5968         }
5969
5970         /*
5971          * Go through the pending CCB list and look for
5972          * commands for this target that are still active.
5973          * These are other tagged commands that were
5974          * disconnected when the reset occurred.
5975          */
5976         scbp_next = LIST_FIRST(&ahc->pending_scbs);
5977         while (scbp_next != NULL) {
5978                 scbp = scbp_next;
5979                 scbp_next = LIST_NEXT(scbp, pending_links);
5980                 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5981                         cam_status ostat;
5982
5983                         ostat = aic_get_transaction_status(scbp);
5984                         if (ostat == CAM_REQ_INPROG)
5985                                 aic_set_transaction_status(scbp, status);
5986                         if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
5987                                 aic_freeze_scb(scbp);
5988                         if ((scbp->flags & SCB_ACTIVE) == 0)
5989                                 printf("Inactive SCB on pending list\n");
5990                         ahc_done(ahc, scbp);
5991                         found++;
5992                 }
5993         }
5994         ahc_outb(ahc, SCBPTR, active_scb);
5995         ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5996         ahc_release_untagged_queues(ahc);
5997         return found;
5998 }
5999
6000 static void
6001 ahc_reset_current_bus(struct ahc_softc *ahc)
6002 {
6003         uint8_t scsiseq;
6004
6005         ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6006         scsiseq = ahc_inb(ahc, SCSISEQ);
6007         ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6008         ahc_flush_device_writes(ahc);
6009         aic_delay(AHC_BUSRESET_DELAY);
6010         /* Turn off the bus reset */
6011         ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6012
6013         ahc_clear_intstat(ahc);
6014
6015         /* Re-enable reset interrupts */
6016         ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6017 }
6018
6019 int
6020 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6021 {
6022         struct  ahc_devinfo devinfo;
6023         u_int   initiator, target, max_scsiid;
6024         u_int   sblkctl;
6025         u_int   scsiseq;
6026         u_int   simode1;
6027         int     found;
6028         int     restart_needed;
6029         char    cur_channel;
6030
6031         ahc->pending_device = NULL;
6032
6033         ahc_compile_devinfo(&devinfo,
6034                             CAM_TARGET_WILDCARD,
6035                             CAM_TARGET_WILDCARD,
6036                             CAM_LUN_WILDCARD,
6037                             channel, ROLE_UNKNOWN);
6038         ahc_pause(ahc);
6039
6040         /* Make sure the sequencer is in a safe location. */
6041         ahc_clear_critical_section(ahc);
6042
6043         /*
6044          * Run our command complete fifos to ensure that we perform
6045          * completion processing on any commands that 'completed'
6046          * before the reset occurred.
6047          */
6048         ahc_run_qoutfifo(ahc);
6049 #ifdef AHC_TARGET_MODE
6050         /*
6051          * XXX - In Twin mode, the tqinfifo may have commands
6052          *       for an unaffected channel in it.  However, if
6053          *       we have run out of ATIO resources to drain that
6054          *       queue, we may not get them all out here.  Further,
6055          *       the blocked transactions for the reset channel
6056          *       should just be killed off, irrespecitve of whether
6057          *       we are blocked on ATIO resources.  Write a routine
6058          *       to compact the tqinfifo appropriately.
6059          */
6060         if ((ahc->flags & AHC_TARGETROLE) != 0) {
6061                 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6062         }
6063 #endif
6064
6065         /*
6066          * Reset the bus if we are initiating this reset
6067          */
6068         sblkctl = ahc_inb(ahc, SBLKCTL);
6069         cur_channel = 'A';
6070         if ((ahc->features & AHC_TWIN) != 0
6071          && ((sblkctl & SELBUSB) != 0))
6072             cur_channel = 'B';
6073         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6074         if (cur_channel != channel) {
6075                 /* Case 1: Command for another bus is active
6076                  * Stealthily reset the other bus without
6077                  * upsetting the current bus.
6078                  */
6079                 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6080                 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6081 #ifdef AHC_TARGET_MODE
6082                 /*
6083                  * Bus resets clear ENSELI, so we cannot
6084                  * defer re-enabling bus reset interrupts
6085                  * if we are in target mode.
6086                  */
6087                 if ((ahc->flags & AHC_TARGETROLE) != 0)
6088                         simode1 |= ENSCSIRST;
6089 #endif
6090                 ahc_outb(ahc, SIMODE1, simode1);
6091                 if (initiate_reset)
6092                         ahc_reset_current_bus(ahc);
6093                 ahc_clear_intstat(ahc);
6094                 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6095                 ahc_outb(ahc, SBLKCTL, sblkctl);
6096                 restart_needed = FALSE;
6097         } else {
6098                 /* Case 2: A command from this bus is active or we're idle */
6099                 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6100 #ifdef AHC_TARGET_MODE
6101                 /*
6102                  * Bus resets clear ENSELI, so we cannot
6103                  * defer re-enabling bus reset interrupts
6104                  * if we are in target mode.
6105                  */
6106                 if ((ahc->flags & AHC_TARGETROLE) != 0)
6107                         simode1 |= ENSCSIRST;
6108 #endif
6109                 ahc_outb(ahc, SIMODE1, simode1);
6110                 if (initiate_reset)
6111                         ahc_reset_current_bus(ahc);
6112                 ahc_clear_intstat(ahc);
6113                 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6114                 restart_needed = TRUE;
6115         }
6116
6117         /*
6118          * Clean up all the state information for the
6119          * pending transactions on this bus.
6120          */
6121         found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6122                                CAM_LUN_WILDCARD, SCB_LIST_NULL,
6123                                ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6124
6125         max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6126
6127 #ifdef AHC_TARGET_MODE
6128         /*
6129          * Send an immediate notify ccb to all target more peripheral
6130          * drivers affected by this action.
6131          */
6132         for (target = 0; target <= max_scsiid; target++) {
6133                 struct ahc_tmode_tstate* tstate;
6134                 u_int lun;
6135
6136                 tstate = ahc->enabled_targets[target];
6137                 if (tstate == NULL)
6138                         continue;
6139                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6140                         struct ahc_tmode_lstate* lstate;
6141
6142                         lstate = tstate->enabled_luns[lun];
6143                         if (lstate == NULL)
6144                                 continue;
6145
6146                         ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6147                                                EVENT_TYPE_BUS_RESET, /*arg*/0);
6148                         ahc_send_lstate_events(ahc, lstate);
6149                 }
6150         }
6151 #endif
6152         /* Notify the XPT that a bus reset occurred */
6153         ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6154                        CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6155
6156         /*
6157          * Revert to async/narrow transfers until we renegotiate.
6158          */
6159         for (target = 0; target <= max_scsiid; target++) {
6160                 if (ahc->enabled_targets[target] == NULL)
6161                         continue;
6162                 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6163                         struct ahc_devinfo devinfo;
6164
6165                         ahc_compile_devinfo(&devinfo, target, initiator,
6166                                             CAM_LUN_WILDCARD,
6167                                             channel, ROLE_UNKNOWN);
6168                         ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6169                                       AHC_TRANS_CUR, /*paused*/TRUE);
6170                         ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6171                                          /*period*/0, /*offset*/0,
6172                                          /*ppr_options*/0, AHC_TRANS_CUR,
6173                                          /*paused*/TRUE);
6174                 }
6175         }
6176
6177         if (restart_needed)
6178                 ahc_restart(ahc);
6179         else
6180                 ahc_unpause(ahc);
6181         return found;
6182 }
6183
6184 /***************************** Residual Processing ****************************/
6185 /*
6186  * Calculate the residual for a just completed SCB.
6187  */
6188 void
6189 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6190 {
6191         struct hardware_scb *hscb;
6192         struct status_pkt *spkt;
6193         uint32_t sgptr;
6194         uint32_t resid_sgptr;
6195         uint32_t resid;
6196
6197         /*
6198          * 5 cases.
6199          * 1) No residual.
6200          *    SG_RESID_VALID clear in sgptr.
6201          * 2) Transferless command
6202          * 3) Never performed any transfers.
6203          *    sgptr has SG_FULL_RESID set.
6204          * 4) No residual but target did not
6205          *    save data pointers after the
6206          *    last transfer, so sgptr was
6207          *    never updated.
6208          * 5) We have a partial residual.
6209          *    Use residual_sgptr to determine
6210          *    where we are.
6211          */
6212
6213         hscb = scb->hscb;
6214         sgptr = aic_le32toh(hscb->sgptr);
6215         if ((sgptr & SG_RESID_VALID) == 0)
6216                 /* Case 1 */
6217                 return;
6218         sgptr &= ~SG_RESID_VALID;
6219
6220         if ((sgptr & SG_LIST_NULL) != 0)
6221                 /* Case 2 */
6222                 return;
6223
6224         spkt = &hscb->shared_data.status;
6225         resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6226         if ((sgptr & SG_FULL_RESID) != 0) {
6227                 /* Case 3 */
6228                 resid = aic_get_transfer_length(scb);
6229         } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6230                 /* Case 4 */
6231                 return;
6232         } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6233                 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6234                 /* NOTREACHED */
6235                 return;
6236         } else {
6237                 struct ahc_dma_seg *sg;
6238
6239                 /*
6240                  * Remainder of the SG where the transfer
6241                  * stopped.
6242                  */
6243                 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6244                 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6245
6246                 /* The residual sg_ptr always points to the next sg */
6247                 sg--;
6248
6249                 /*
6250                  * Add up the contents of all residual
6251                  * SG segments that are after the SG where
6252                  * the transfer stopped.
6253                  */
6254                 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6255                         sg++;
6256                         resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6257                 }
6258         }
6259         if ((scb->flags & SCB_SENSE) == 0)
6260                 aic_set_residual(scb, resid);
6261         else
6262                 aic_set_sense_residual(scb, resid);
6263
6264 #ifdef AHC_DEBUG
6265         if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6266                 ahc_print_path(ahc, scb);
6267                 printf("Handled %sResidual of %d bytes\n",
6268                        (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6269         }
6270 #endif
6271 }
6272
6273 /******************************* Target Mode **********************************/
6274 #ifdef AHC_TARGET_MODE
6275 /*
6276  * Add a target mode event to this lun's queue
6277  */
6278 static void
6279 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6280                        u_int initiator_id, u_int event_type, u_int event_arg)
6281 {
6282         struct ahc_tmode_event *event;
6283         int pending;
6284
6285         xpt_freeze_devq(lstate->path, /*count*/1);
6286         if (lstate->event_w_idx >= lstate->event_r_idx)
6287                 pending = lstate->event_w_idx - lstate->event_r_idx;
6288         else
6289                 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6290                         - (lstate->event_r_idx - lstate->event_w_idx);
6291
6292         if (event_type == EVENT_TYPE_BUS_RESET
6293          || event_type == MSG_BUS_DEV_RESET) {
6294                 /*
6295                  * Any earlier events are irrelevant, so reset our buffer.
6296                  * This has the effect of allowing us to deal with reset
6297                  * floods (an external device holding down the reset line)
6298                  * without losing the event that is really interesting.
6299                  */
6300                 lstate->event_r_idx = 0;
6301                 lstate->event_w_idx = 0;
6302                 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6303         }
6304
6305         if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6306                 xpt_print_path(lstate->path);
6307                 printf("immediate event %x:%x lost\n",
6308                        lstate->event_buffer[lstate->event_r_idx].event_type,
6309                        lstate->event_buffer[lstate->event_r_idx].event_arg);
6310                 lstate->event_r_idx++;
6311                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6312                         lstate->event_r_idx = 0;
6313                 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6314         }
6315
6316         event = &lstate->event_buffer[lstate->event_w_idx];
6317         event->initiator_id = initiator_id;
6318         event->event_type = event_type;
6319         event->event_arg = event_arg;
6320         lstate->event_w_idx++;
6321         if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6322                 lstate->event_w_idx = 0;
6323 }
6324
6325 /*
6326  * Send any target mode events queued up waiting
6327  * for immediate notify resources.
6328  */
6329 void
6330 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6331 {
6332         struct ccb_hdr *ccbh;
6333         struct ccb_immediate_notify *inot;
6334
6335         while (lstate->event_r_idx != lstate->event_w_idx
6336             && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6337                 struct ahc_tmode_event *event;
6338
6339                 event = &lstate->event_buffer[lstate->event_r_idx];
6340                 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6341                 inot = (struct ccb_immediate_notify *)ccbh;
6342                 switch (event->event_type) {
6343                 case EVENT_TYPE_BUS_RESET:
6344                         ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6345                         break;
6346                 default:
6347                         ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6348                         inot->arg = event->event_type;
6349                         inot->seq_id = event->event_arg;
6350                         break;
6351                 }
6352                 inot->initiator_id = event->initiator_id;
6353                 xpt_done((union ccb *)inot);
6354                 lstate->event_r_idx++;
6355                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6356                         lstate->event_r_idx = 0;
6357         }
6358 }
6359 #endif
6360
6361 /******************** Sequencer Program Patching/Download *********************/
6362
6363 #ifdef AHC_DUMP_SEQ
6364 void
6365 ahc_dumpseq(struct ahc_softc* ahc)
6366 {
6367         int i;
6368
6369         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6370         ahc_outb(ahc, SEQADDR0, 0);
6371         ahc_outb(ahc, SEQADDR1, 0);
6372         for (i = 0; i < ahc->instruction_ram_size; i++) {
6373                 uint8_t ins_bytes[4];
6374
6375                 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6376                 printf("0x%08x\n", ins_bytes[0] << 24
6377                                  | ins_bytes[1] << 16
6378                                  | ins_bytes[2] << 8
6379                                  | ins_bytes[3]);
6380         }
6381 }
6382 #endif
6383
6384 static int
6385 ahc_loadseq(struct ahc_softc *ahc)
6386 {
6387         struct  cs cs_table[num_critical_sections];
6388         u_int   begin_set[num_critical_sections];
6389         u_int   end_set[num_critical_sections];
6390         struct  patch *cur_patch;
6391         u_int   cs_count;
6392         u_int   cur_cs;
6393         u_int   i;
6394         u_int   skip_addr;
6395         u_int   sg_prefetch_cnt;
6396         int     downloaded;
6397         uint8_t download_consts[7];
6398
6399         /*
6400          * Start out with 0 critical sections
6401          * that apply to this firmware load.
6402          */
6403         cs_count = 0;
6404         cur_cs = 0;
6405         memset(begin_set, 0, sizeof(begin_set));
6406         memset(end_set, 0, sizeof(end_set));
6407
6408         /* Setup downloadable constant table */
6409         download_consts[QOUTFIFO_OFFSET] = 0;
6410         if (ahc->targetcmds != NULL)
6411                 download_consts[QOUTFIFO_OFFSET] += 32;
6412         download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6413         download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6414         download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6415         sg_prefetch_cnt = ahc->pci_cachesize;
6416         if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6417                 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6418         download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6419         download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6420         download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6421
6422         cur_patch = patches;
6423         downloaded = 0;
6424         skip_addr = 0;
6425         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6426         ahc_outb(ahc, SEQADDR0, 0);
6427         ahc_outb(ahc, SEQADDR1, 0);
6428
6429         for (i = 0; i < sizeof(seqprog)/4; i++) {
6430                 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6431                         /*
6432                          * Don't download this instruction as it
6433                          * is in a patch that was removed.
6434                          */
6435                         continue;
6436                 }
6437
6438                 if (downloaded == ahc->instruction_ram_size) {
6439                         /*
6440                          * We're about to exceed the instruction
6441                          * storage capacity for this chip.  Fail
6442                          * the load.
6443                          */
6444                         printf("\n%s: Program too large for instruction memory "
6445                                "size of %d!\n", ahc_name(ahc),
6446                                ahc->instruction_ram_size);
6447                         return (ENOMEM);
6448                 }
6449
6450                 /*
6451                  * Move through the CS table until we find a CS
6452                  * that might apply to this instruction.
6453                  */
6454                 for (; cur_cs < num_critical_sections; cur_cs++) {
6455                         if (critical_sections[cur_cs].end <= i) {
6456                                 if (begin_set[cs_count] == TRUE
6457                                  && end_set[cs_count] == FALSE) {
6458                                         cs_table[cs_count].end = downloaded;
6459                                         end_set[cs_count] = TRUE;
6460                                         cs_count++;
6461                                 }
6462                                 continue;
6463                         }
6464                         if (critical_sections[cur_cs].begin <= i
6465                          && begin_set[cs_count] == FALSE) {
6466                                 cs_table[cs_count].begin = downloaded;
6467                                 begin_set[cs_count] = TRUE;
6468                         }
6469                         break;
6470                 }
6471                 ahc_download_instr(ahc, i, download_consts);
6472                 downloaded++;
6473         }
6474
6475         ahc->num_critical_sections = cs_count;
6476         if (cs_count != 0) {
6477                 cs_count *= sizeof(struct cs);
6478                 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6479                 if (ahc->critical_sections == NULL)
6480                         panic("ahc_loadseq: Could not malloc");
6481                 memcpy(ahc->critical_sections, cs_table, cs_count);
6482         }
6483         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6484
6485         if (bootverbose) {
6486                 printf(" %d instructions downloaded\n", downloaded);
6487                 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6488                        ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6489         }
6490         return (0);
6491 }
6492
6493 static int
6494 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6495                 u_int start_instr, u_int *skip_addr)
6496 {
6497         struct  patch *cur_patch;
6498         struct  patch *last_patch;
6499         u_int   num_patches;
6500
6501         num_patches = sizeof(patches)/sizeof(struct patch);
6502         last_patch = &patches[num_patches];
6503         cur_patch = *start_patch;
6504
6505         while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6506                 if (cur_patch->patch_func(ahc) == 0) {
6507                         /* Start rejecting code */
6508                         *skip_addr = start_instr + cur_patch->skip_instr;
6509                         cur_patch += cur_patch->skip_patch;
6510                 } else {
6511                         /* Accepted this patch.  Advance to the next
6512                          * one and wait for our instruction pointer to
6513                          * hit this point.
6514                          */
6515                         cur_patch++;
6516                 }
6517         }
6518
6519         *start_patch = cur_patch;
6520         if (start_instr < *skip_addr)
6521                 /* Still skipping */
6522                 return (0);
6523
6524         return (1);
6525 }
6526
6527 static void
6528 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6529 {
6530         union   ins_formats instr;
6531         struct  ins_format1 *fmt1_ins;
6532         struct  ins_format3 *fmt3_ins;
6533         u_int   opcode;
6534
6535         /*
6536          * The firmware is always compiled into a little endian format.
6537          */
6538         instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6539
6540         fmt1_ins = &instr.format1;
6541         fmt3_ins = NULL;
6542
6543         /* Pull the opcode */
6544         opcode = instr.format1.opcode;
6545         switch (opcode) {
6546         case AIC_OP_JMP:
6547         case AIC_OP_JC:
6548         case AIC_OP_JNC:
6549         case AIC_OP_CALL:
6550         case AIC_OP_JNE:
6551         case AIC_OP_JNZ:
6552         case AIC_OP_JE:
6553         case AIC_OP_JZ:
6554         {
6555                 struct patch *cur_patch;
6556                 int address_offset;
6557                 u_int address;
6558                 u_int skip_addr;
6559                 u_int i;
6560
6561                 fmt3_ins = &instr.format3;
6562                 address_offset = 0;
6563                 address = fmt3_ins->address;
6564                 cur_patch = patches;
6565                 skip_addr = 0;
6566
6567                 for (i = 0; i < address;) {
6568                         ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6569
6570                         if (skip_addr > i) {
6571                                 int end_addr;
6572
6573                                 end_addr = MIN(address, skip_addr);
6574                                 address_offset += end_addr - i;
6575                                 i = skip_addr;
6576                         } else {
6577                                 i++;
6578                         }
6579                 }
6580                 address -= address_offset;
6581                 fmt3_ins->address = address;
6582                 /* FALLTHROUGH */
6583         }
6584         case AIC_OP_OR:
6585         case AIC_OP_AND:
6586         case AIC_OP_XOR:
6587         case AIC_OP_ADD:
6588         case AIC_OP_ADC:
6589         case AIC_OP_BMOV:
6590                 if (fmt1_ins->parity != 0) {
6591                         fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6592                 }
6593                 fmt1_ins->parity = 0;
6594                 if ((ahc->features & AHC_CMD_CHAN) == 0
6595                  && opcode == AIC_OP_BMOV) {
6596                         /*
6597                          * Block move was added at the same time
6598                          * as the command channel.  Verify that
6599                          * this is only a move of a single element
6600                          * and convert the BMOV to a MOV
6601                          * (AND with an immediate of FF).
6602                          */
6603                         if (fmt1_ins->immediate != 1)
6604                                 panic("%s: BMOV not supported\n",
6605                                       ahc_name(ahc));
6606                         fmt1_ins->opcode = AIC_OP_AND;
6607                         fmt1_ins->immediate = 0xff;
6608                 }
6609                 /* FALLTHROUGH */
6610         case AIC_OP_ROL:
6611                 if ((ahc->features & AHC_ULTRA2) != 0) {
6612                         int i, count;
6613
6614                         /* Calculate odd parity for the instruction */
6615                         for (i = 0, count = 0; i < 31; i++) {
6616                                 uint32_t mask;
6617
6618                                 mask = 0x01 << i;
6619                                 if ((instr.integer & mask) != 0)
6620                                         count++;
6621                         }
6622                         if ((count & 0x01) == 0)
6623                                 instr.format1.parity = 1;
6624                 } else {
6625                         /* Compress the instruction for older sequencers */
6626                         if (fmt3_ins != NULL) {
6627                                 instr.integer =
6628                                         fmt3_ins->immediate
6629                                       | (fmt3_ins->source << 8)
6630                                       | (fmt3_ins->address << 16)
6631                                       | (fmt3_ins->opcode << 25);
6632                         } else {
6633                                 instr.integer =
6634                                         fmt1_ins->immediate
6635                                       | (fmt1_ins->source << 8)
6636                                       | (fmt1_ins->destination << 16)
6637                                       | (fmt1_ins->ret << 24)
6638                                       | (fmt1_ins->opcode << 25);
6639                         }
6640                 }
6641                 /* The sequencer is a little endian cpu */
6642                 instr.integer = aic_htole32(instr.integer);
6643                 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6644                 break;
6645         default:
6646                 panic("Unknown opcode encountered in seq program");
6647                 break;
6648         }
6649 }
6650
6651 int
6652 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6653                    const char *name, u_int address, u_int value,
6654                    u_int *cur_column, u_int wrap_point)
6655 {
6656         int     printed;
6657         u_int   printed_mask;
6658         u_int   dummy_column;
6659
6660         if (cur_column == NULL) {
6661                 dummy_column = 0;
6662                 cur_column = &dummy_column;
6663         }
6664
6665         if (*cur_column >= wrap_point) {
6666                 printf("\n");
6667                 *cur_column = 0;
6668         }
6669         printed = printf("%s[0x%x]", name, value);
6670         if (table == NULL) {
6671                 printed += printf(" ");
6672                 *cur_column += printed;
6673                 return (printed);
6674         }
6675         printed_mask = 0;
6676         while (printed_mask != 0xFF) {
6677                 int entry;
6678
6679                 for (entry = 0; entry < num_entries; entry++) {
6680                         if (((value & table[entry].mask)
6681                           != table[entry].value)
6682                          || ((printed_mask & table[entry].mask)
6683                           == table[entry].mask))
6684                                 continue;
6685
6686                         printed += printf("%s%s",
6687                                           printed_mask == 0 ? ":(" : "|",
6688                                           table[entry].name);
6689                         printed_mask |= table[entry].mask;
6690
6691                         break;
6692                 }
6693                 if (entry >= num_entries)
6694                         break;
6695         }
6696         if (printed_mask != 0)
6697                 printed += printf(") ");
6698         else
6699                 printed += printf(" ");
6700         if (cur_column != NULL)
6701                 *cur_column += printed;
6702         return (printed);
6703 }
6704
6705 void
6706 ahc_dump_card_state(struct ahc_softc *ahc)
6707 {
6708         struct  scb *scb;
6709         struct  scb_tailq *untagged_q;
6710         u_int   cur_col;
6711         int     paused;
6712         int     target;
6713         int     maxtarget;
6714         int     i;
6715         uint8_t last_phase;
6716         uint8_t qinpos;
6717         uint8_t qintail;
6718         uint8_t qoutpos;
6719         uint8_t scb_index;
6720         uint8_t saved_scbptr;
6721
6722         if (ahc_is_paused(ahc)) {
6723                 paused = 1;
6724         } else {
6725                 paused = 0;
6726                 ahc_pause(ahc);
6727         }
6728
6729         saved_scbptr = ahc_inb(ahc, SCBPTR);
6730         last_phase = ahc_inb(ahc, LASTPHASE);
6731         printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6732                "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6733                ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6734                ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6735         if (paused)
6736                 printf("Card was paused\n");
6737         printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6738                ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6739                ahc_inb(ahc, ARG_2));
6740         printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6741                ahc_inb(ahc, SCBPTR));
6742         cur_col = 0;
6743         if ((ahc->features & AHC_DT) != 0)
6744                 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6745         ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6746         ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6747         ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6748         ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6749         ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6750         ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6751         ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6752         ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6753         ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6754         ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6755         ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6756         ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6757         ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6758         ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6759         ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6760         ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6761         ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6762         ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6763         if (cur_col != 0)
6764                 printf("\n");
6765         printf("STACK:");
6766         for (i = 0; i < STACK_SIZE; i++)
6767                printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6768         printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6769         printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6770         printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6771         /* QINFIFO */
6772         printf("QINFIFO entries: ");
6773         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6774                 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6775                 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6776         } else
6777                 qinpos = ahc_inb(ahc, QINPOS);
6778         qintail = ahc->qinfifonext;
6779         while (qinpos != qintail) {
6780                 printf("%d ", ahc->qinfifo[qinpos]);
6781                 qinpos++;
6782         }
6783         printf("\n");
6784
6785         printf("Waiting Queue entries: ");
6786         scb_index = ahc_inb(ahc, WAITING_SCBH);
6787         i = 0;
6788         while (scb_index != SCB_LIST_NULL && i++ < 256) {
6789                 ahc_outb(ahc, SCBPTR, scb_index);
6790                 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6791                 scb_index = ahc_inb(ahc, SCB_NEXT);
6792         }
6793         printf("\n");
6794
6795         printf("Disconnected Queue entries: ");
6796         scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6797         i = 0;
6798         while (scb_index != SCB_LIST_NULL && i++ < 256) {
6799                 ahc_outb(ahc, SCBPTR, scb_index);
6800                 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6801                 scb_index = ahc_inb(ahc, SCB_NEXT);
6802         }
6803         printf("\n");
6804
6805         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6806         printf("QOUTFIFO entries: ");
6807         qoutpos = ahc->qoutfifonext;
6808         i = 0;
6809         while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6810                 printf("%d ", ahc->qoutfifo[qoutpos]);
6811                 qoutpos++;
6812         }
6813         printf("\n");
6814
6815         printf("Sequencer Free SCB List: ");
6816         scb_index = ahc_inb(ahc, FREE_SCBH);
6817         i = 0;
6818         while (scb_index != SCB_LIST_NULL && i++ < 256) {
6819                 ahc_outb(ahc, SCBPTR, scb_index);
6820                 printf("%d ", scb_index);
6821                 scb_index = ahc_inb(ahc, SCB_NEXT);
6822         }
6823         printf("\n");
6824
6825         printf("Sequencer SCB Info: ");
6826         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6827                 ahc_outb(ahc, SCBPTR, i);
6828                 cur_col = printf("\n%3d ", i);
6829
6830                 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6831                 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6832                 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6833                 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6834         }
6835         printf("\n");
6836
6837         printf("Pending list: ");
6838         i = 0;
6839         LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6840                 if (i++ > 256)
6841                         break;
6842                 cur_col = printf("\n%3d ", scb->hscb->tag);
6843                 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6844                 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6845                 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6846                 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6847                         ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6848                         printf("(");
6849                         ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6850                                               &cur_col, 60);
6851                         ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6852                         printf(")");
6853                 }
6854         }
6855         printf("\n");
6856
6857         printf("Kernel Free SCB list: ");
6858         i = 0;
6859         SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6860                 if (i++ > 256)
6861                         break;
6862                 printf("%d ", scb->hscb->tag);
6863         }
6864         printf("\n");
6865
6866         maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6867         for (target = 0; target <= maxtarget; target++) {
6868                 untagged_q = &ahc->untagged_queues[target];
6869                 if (TAILQ_FIRST(untagged_q) == NULL)
6870                         continue;
6871                 printf("Untagged Q(%d): ", target);
6872                 i = 0;
6873                 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6874                         if (i++ > 256)
6875                                 break;
6876                         printf("%d ", scb->hscb->tag);
6877                 }
6878                 printf("\n");
6879         }
6880
6881         ahc_platform_dump_card_state(ahc);
6882         printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6883         ahc_outb(ahc, SCBPTR, saved_scbptr);
6884         if (paused == 0)
6885                 ahc_unpause(ahc);
6886 }
6887
6888 /*************************** Timeout Handling *********************************/
6889 void
6890 ahc_timeout(struct scb *scb)
6891 {
6892         struct ahc_softc *ahc;
6893
6894         ahc = scb->ahc_softc;
6895         if ((scb->flags & SCB_ACTIVE) != 0) {
6896                 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6897                         LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6898                                          timedout_links);
6899                         scb->flags |= SCB_TIMEDOUT;
6900                 }
6901                 ahc_wakeup_recovery_thread(ahc);
6902         }
6903 }
6904
6905 /*
6906  * Re-schedule a timeout for the passed in SCB if we determine that some
6907  * other SCB is in the process of recovery or an SCB with a longer
6908  * timeout is still pending.  Limit our search to just "other_scb"
6909  * if it is non-NULL.
6910  */
6911 static int
6912 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6913                       struct scb *other_scb)
6914 {
6915         u_int   newtimeout;
6916         int     found;
6917
6918         ahc_print_path(ahc, scb);
6919         printf("Other SCB Timeout%s",
6920                (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6921                ? " again\n" : "\n");
6922
6923         newtimeout = aic_get_timeout(scb);
6924         scb->flags |= SCB_OTHERTCL_TIMEOUT;
6925         found = 0;
6926         if (other_scb != NULL) {
6927                 if ((other_scb->flags
6928                    & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6929                  || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6930                         found++;
6931                         newtimeout = MAX(aic_get_timeout(other_scb),
6932                                          newtimeout);
6933                 }
6934         } else {
6935                 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6936                         if ((other_scb->flags
6937                            & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6938                          || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6939                                 found++;
6940                                 newtimeout =
6941                                     MAX(aic_get_timeout(other_scb),
6942                                         newtimeout);
6943                         }
6944                 }
6945         }
6946
6947         if (found != 0)
6948                 aic_scb_timer_reset(scb, newtimeout);
6949         else {
6950                 ahc_print_path(ahc, scb);
6951                 printf("No other SCB worth waiting for...\n");
6952         }
6953
6954         return (found != 0);
6955 }
6956
6957 /*
6958  * ahc_recover_commands determines if any of the commands that have currently
6959  * timedout are the root cause for this timeout.  Innocent commands are given
6960  * a new timeout while we wait for the command executing on the bus to timeout.
6961  * This routine is invoked from a thread context so we are allowed to sleep.
6962  * Our lock is not held on entry.
6963  */
6964 void
6965 ahc_recover_commands(struct ahc_softc *ahc)
6966 {
6967         struct  scb *scb;
6968         int     found;
6969         int     restart_needed;
6970         u_int   last_phase;
6971
6972         /*
6973          * Pause the controller and manually flush any
6974          * commands that have just completed but that our
6975          * interrupt handler has yet to see.
6976          */
6977         ahc_pause_and_flushwork(ahc);
6978
6979         if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
6980                 /*
6981                  * The timedout commands have already
6982                  * completed.  This typically means
6983                  * that either the timeout value was on
6984                  * the hairy edge of what the device
6985                  * requires or - more likely - interrupts
6986                  * are not happening.
6987                  */
6988                 printf("%s: Timedout SCBs already complete. "
6989                        "Interrupts may not be functioning.\n", ahc_name(ahc));
6990                 ahc_unpause(ahc);
6991                 return;
6992         }
6993
6994         restart_needed = 0;
6995         printf("%s: Recovery Initiated\n", ahc_name(ahc));
6996         ahc_dump_card_state(ahc);
6997
6998         last_phase = ahc_inb(ahc, LASTPHASE);
6999         while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7000                 u_int   active_scb_index;
7001                 u_int   saved_scbptr;
7002                 int     target;
7003                 int     lun;
7004                 int     i;
7005                 char    channel;
7006
7007                 target = SCB_GET_TARGET(ahc, scb);
7008                 channel = SCB_GET_CHANNEL(ahc, scb);
7009                 lun = SCB_GET_LUN(scb);
7010
7011                 ahc_print_path(ahc, scb);
7012                 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7013                 if (scb->sg_count > 0) {
7014                         for (i = 0; i < scb->sg_count; i++) {
7015                                 printf("sg[%d] - Addr 0x%x : Length %d\n",
7016                                        i,
7017                                        scb->sg_list[i].addr,
7018                                        scb->sg_list[i].len & AHC_SG_LEN_MASK);
7019                         }
7020                 }
7021                 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7022                         /*
7023                          * Been down this road before.
7024                          * Do a full bus reset.
7025                          */
7026                         aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7027 bus_reset:
7028                         found = ahc_reset_channel(ahc, channel,
7029                                                   /*Initiate Reset*/TRUE);
7030                         printf("%s: Issued Channel %c Bus Reset. "
7031                                "%d SCBs aborted\n", ahc_name(ahc), channel,
7032                                found);
7033                         continue;
7034                 }
7035
7036                 /*
7037                  * Remove the command from the timedout list in
7038                  * preparation for requeing it.
7039                  */
7040                 LIST_REMOVE(scb, timedout_links);
7041                 scb->flags &= ~SCB_TIMEDOUT;
7042
7043                 /*
7044                  * If we are a target, transition to bus free and report
7045                  * the timeout.
7046                  *
7047                  * The target/initiator that is holding up the bus may not
7048                  * be the same as the one that triggered this timeout
7049                  * (different commands have different timeout lengths).
7050                  * If the bus is idle and we are actiing as the initiator
7051                  * for this request, queue a BDR message to the timed out
7052                  * target.  Otherwise, if the timed out transaction is
7053                  * active:
7054                  *   Initiator transaction:
7055                  *      Stuff the message buffer with a BDR message and assert
7056                  *      ATN in the hopes that the target will let go of the bus
7057                  *      and go to the mesgout phase.  If this fails, we'll
7058                  *      get another timeout 2 seconds later which will attempt
7059                  *      a bus reset.
7060                  *
7061                  *   Target transaction:
7062                  *      Transition to BUS FREE and report the error.
7063                  *      It's good to be the target!
7064                  */
7065                 saved_scbptr = ahc_inb(ahc, SCBPTR);
7066                 active_scb_index = ahc_inb(ahc, SCB_TAG);
7067
7068                 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7069                   && (active_scb_index < ahc->scb_data->numscbs)) {
7070                         struct scb *active_scb;
7071
7072                         /*
7073                          * If the active SCB is not us, assume that
7074                          * the active SCB has a longer timeout than
7075                          * the timedout SCB, and wait for the active
7076                          * SCB to timeout.
7077                          */
7078                         active_scb = ahc_lookup_scb(ahc, active_scb_index);
7079                         if (active_scb != scb) {
7080                                 if (ahc_other_scb_timeout(ahc, scb,
7081                                                           active_scb) == 0)
7082                                         goto bus_reset;
7083                                 continue;
7084                         }
7085
7086                         /* It's us */
7087                         if ((scb->flags & SCB_TARGET_SCB) != 0) {
7088                                 /*
7089                                  * Send back any queued up transactions
7090                                  * and properly record the error condition.
7091                                  */
7092                                 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7093                                                SCB_GET_CHANNEL(ahc, scb),
7094                                                SCB_GET_LUN(scb),
7095                                                scb->hscb->tag,
7096                                                ROLE_TARGET,
7097                                                CAM_CMD_TIMEOUT);
7098
7099                                 /* Will clear us from the bus */
7100                                 restart_needed = 1;
7101                                 break;
7102                         }
7103
7104                         ahc_set_recoveryscb(ahc, active_scb);
7105                         ahc_outb(ahc, MSG_OUT, HOST_MSG);
7106                         ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7107                         ahc_print_path(ahc, active_scb);
7108                         printf("BDR message in message buffer\n");
7109                         active_scb->flags |= SCB_DEVICE_RESET;
7110                         aic_scb_timer_reset(scb, 2 * 1000);
7111                 } else if (last_phase != P_BUSFREE
7112                         && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7113                         /*
7114                          * SCB is not identified, there
7115                          * is no pending REQ, and the sequencer
7116                          * has not seen a busfree.  Looks like
7117                          * a stuck connection waiting to
7118                          * go busfree.  Reset the bus.
7119                          */
7120                         printf("%s: Connection stuck awaiting busfree or "
7121                                "Identify Msg.\n", ahc_name(ahc));
7122                         goto bus_reset;
7123                 } else {
7124                         int      disconnected;
7125
7126                         if (last_phase != P_BUSFREE
7127                          && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7128                                 /* Hung target selection.  Goto busfree */
7129                                 printf("%s: Hung target selection\n",
7130                                        ahc_name(ahc));
7131                                 restart_needed = 1;
7132                                 break;
7133                         }
7134
7135                         /* XXX Shouldn't panic.  Just punt instead? */
7136                         if ((scb->flags & SCB_TARGET_SCB) != 0)
7137                                 panic("Timed-out target SCB but bus idle");
7138
7139                         if (ahc_search_qinfifo(ahc, target, channel, lun,
7140                                                scb->hscb->tag, ROLE_INITIATOR,
7141                                                /*status*/0, SEARCH_COUNT) > 0) {
7142                                 disconnected = FALSE;
7143                         } else {
7144                                 disconnected = TRUE;
7145                         }
7146
7147                         if (disconnected) {
7148                                 ahc_set_recoveryscb(ahc, scb);
7149                                 /*
7150                                  * Actually re-queue this SCB in an attempt
7151                                  * to select the device before it reconnects.
7152                                  * In either case (selection or reselection),
7153                                  * we will now issue a target reset to the
7154                                  * timed-out device.
7155                                  *
7156                                  * Set the MK_MESSAGE control bit indicating
7157                                  * that we desire to send a message.  We
7158                                  * also set the disconnected flag since
7159                                  * in the paging case there is no guarantee
7160                                  * that our SCB control byte matches the
7161                                  * version on the card.  We don't want the
7162                                  * sequencer to abort the command thinking
7163                                  * an unsolicited reselection occurred.
7164                                  */
7165                                 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7166                                 scb->flags |= SCB_DEVICE_RESET;
7167
7168                                 /*
7169                                  * Remove any cached copy of this SCB in the
7170                                  * disconnected list in preparation for the
7171                                  * queuing of our abort SCB.  We use the
7172                                  * same element in the SCB, SCB_NEXT, for
7173                                  * both the qinfifo and the disconnected list.
7174                                  */
7175                                 ahc_search_disc_list(ahc, target, channel,
7176                                                      lun, scb->hscb->tag,
7177                                                      /*stop_on_first*/TRUE,
7178                                                      /*remove*/TRUE,
7179                                                      /*save_state*/FALSE);
7180
7181                                 /*
7182                                  * In the non-paging case, the sequencer will
7183                                  * never re-reference the in-core SCB.
7184                                  * To make sure we are notified during
7185                                  * reslection, set the MK_MESSAGE flag in
7186                                  * the card's copy of the SCB.
7187                                  */
7188                                 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7189                                         ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7190                                         ahc_outb(ahc, SCB_CONTROL,
7191                                                  ahc_inb(ahc, SCB_CONTROL)
7192                                                 | MK_MESSAGE);
7193                                 }
7194
7195                                 /*
7196                                  * Clear out any entries in the QINFIFO first
7197                                  * so we are the next SCB for this target
7198                                  * to run.
7199                                  */
7200                                 ahc_search_qinfifo(ahc,
7201                                                    SCB_GET_TARGET(ahc, scb),
7202                                                    channel, SCB_GET_LUN(scb),
7203                                                    SCB_LIST_NULL,
7204                                                    ROLE_INITIATOR,
7205                                                    CAM_REQUEUE_REQ,
7206                                                    SEARCH_COMPLETE);
7207                                 ahc_print_path(ahc, scb);
7208                                 printf("Queuing a BDR SCB\n");
7209                                 ahc_qinfifo_requeue_tail(ahc, scb);
7210                                 ahc_outb(ahc, SCBPTR, saved_scbptr);
7211                                 aic_scb_timer_reset(scb, 2 * 1000);
7212                         } else {
7213                                 /* Go "immediately" to the bus reset */
7214                                 /* This shouldn't happen */
7215                                 ahc_set_recoveryscb(ahc, scb);
7216                                 ahc_print_path(ahc, scb);
7217                                 printf("SCB %d: Immediate reset.  "
7218                                         "Flags = 0x%x\n", scb->hscb->tag,
7219                                         scb->flags);
7220                                 goto bus_reset;
7221                         }
7222                 }
7223                 break;
7224         }
7225
7226         /*
7227          * Any remaining SCBs were not the "culprit", so remove
7228          * them from the timeout list.  The timer for these commands
7229          * will be reset once the recovery SCB completes.
7230          */
7231         while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7232                 LIST_REMOVE(scb, timedout_links);
7233                 scb->flags &= ~SCB_TIMEDOUT;
7234         }
7235
7236         if (restart_needed)
7237                 ahc_restart(ahc);
7238         else
7239                 ahc_unpause(ahc);
7240 }
7241
7242 /************************* Target Mode ****************************************/
7243 #ifdef AHC_TARGET_MODE
7244 cam_status
7245 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7246                     struct ahc_tmode_tstate **tstate,
7247                     struct ahc_tmode_lstate **lstate,
7248                     int notfound_failure)
7249 {
7250
7251         if ((ahc->features & AHC_TARGETMODE) == 0)
7252                 return (CAM_REQ_INVALID);
7253
7254         /*
7255          * Handle the 'black hole' device that sucks up
7256          * requests to unattached luns on enabled targets.
7257          */
7258         if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7259          && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7260                 *tstate = NULL;
7261                 *lstate = ahc->black_hole;
7262         } else {
7263                 u_int max_id;
7264
7265                 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7266                 if (ccb->ccb_h.target_id > max_id)
7267                         return (CAM_TID_INVALID);
7268
7269                 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7270                         return (CAM_LUN_INVALID);
7271
7272                 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7273                 *lstate = NULL;
7274                 if (*tstate != NULL)
7275                         *lstate =
7276                             (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7277         }
7278
7279         if (notfound_failure != 0 && *lstate == NULL)
7280                 return (CAM_PATH_INVALID);
7281
7282         return (CAM_REQ_CMP);
7283 }
7284
7285 void
7286 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7287 {
7288         struct     ahc_tmode_tstate *tstate;
7289         struct     ahc_tmode_lstate *lstate;
7290         struct     ccb_en_lun *cel;
7291         cam_status status;
7292         u_int      target;
7293         u_int      lun;
7294         u_int      target_mask;
7295         u_int      our_id;
7296         int        error;
7297         char       channel;
7298
7299         status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7300                                      /*notfound_failure*/FALSE);
7301
7302         if (status != CAM_REQ_CMP) {
7303                 ccb->ccb_h.status = status;
7304                 return;
7305         }
7306
7307         if (cam_sim_bus(sim) == 0)
7308                 our_id = ahc->our_id;
7309         else
7310                 our_id = ahc->our_id_b;
7311
7312         if (ccb->ccb_h.target_id != our_id
7313          && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7314                 /*
7315                  * our_id represents our initiator ID, or
7316                  * the ID of the first target to have an
7317                  * enabled lun in target mode.  There are
7318                  * two cases that may preclude enabling a
7319                  * target id other than our_id.
7320                  *
7321                  *   o our_id is for an active initiator role.
7322                  *     Since the hardware does not support
7323                  *     reselections to the initiator role at
7324                  *     anything other than our_id, and our_id
7325                  *     is used by the hardware to indicate the
7326                  *     ID to use for both select-out and
7327                  *     reselect-out operations, the only target
7328                  *     ID we can support in this mode is our_id.
7329                  *
7330                  *   o The MULTARGID feature is not available and
7331                  *     a previous target mode ID has been enabled.
7332                  */
7333                 if ((ahc->features & AHC_MULTIROLE) != 0) {
7334                         if ((ahc->features & AHC_MULTI_TID) != 0
7335                          && (ahc->flags & AHC_INITIATORROLE) != 0) {
7336                                 /*
7337                                  * Only allow additional targets if
7338                                  * the initiator role is disabled.
7339                                  * The hardware cannot handle a re-select-in
7340                                  * on the initiator id during a re-select-out
7341                                  * on a different target id.
7342                                  */
7343                                 status = CAM_TID_INVALID;
7344                         } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7345                                 || ahc->enabled_luns > 0) {
7346                                 /*
7347                                  * Only allow our target id to change
7348                                  * if the initiator role is not configured
7349                                  * and there are no enabled luns which
7350                                  * are attached to the currently registered
7351                                  * scsi id.
7352                                  */
7353                                 status = CAM_TID_INVALID;
7354                         }
7355                 } else if ((ahc->features & AHC_MULTI_TID) == 0
7356                         && ahc->enabled_luns > 0) {
7357                         status = CAM_TID_INVALID;
7358                 }
7359         }
7360
7361         if (status != CAM_REQ_CMP) {
7362                 ccb->ccb_h.status = status;
7363                 return;
7364         }
7365
7366         /*
7367          * We now have an id that is valid.
7368          * If we aren't in target mode, switch modes.
7369          */
7370         if ((ahc->flags & AHC_TARGETROLE) == 0
7371          && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7372                 ahc_flag saved_flags;
7373
7374                 printf("Configuring Target Mode\n");
7375                 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7376                         ccb->ccb_h.status = CAM_BUSY;
7377                         return;
7378                 }
7379                 saved_flags = ahc->flags;
7380                 ahc->flags |= AHC_TARGETROLE;
7381                 if ((ahc->features & AHC_MULTIROLE) == 0)
7382                         ahc->flags &= ~AHC_INITIATORROLE;
7383                 ahc_pause(ahc);
7384                 error = ahc_loadseq(ahc);
7385                 if (error != 0) {
7386                         /*
7387                          * Restore original configuration and notify
7388                          * the caller that we cannot support target mode.
7389                          * Since the adapter started out in this
7390                          * configuration, the firmware load will succeed,
7391                          * so there is no point in checking ahc_loadseq's
7392                          * return value.
7393                          */
7394                         ahc->flags = saved_flags;
7395                         (void)ahc_loadseq(ahc);
7396                         ahc_restart(ahc);
7397                         ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7398                         return;
7399                 }
7400                 ahc_restart(ahc);
7401         }
7402         cel = &ccb->cel;
7403         target = ccb->ccb_h.target_id;
7404         lun = ccb->ccb_h.target_lun;
7405         channel = SIM_CHANNEL(ahc, sim);
7406         target_mask = 0x01 << target;
7407         if (channel == 'B')
7408                 target_mask <<= 8;
7409
7410         if (cel->enable != 0) {
7411                 u_int scsiseq;
7412
7413                 /* Are we already enabled?? */
7414                 if (lstate != NULL) {
7415                         xpt_print_path(ccb->ccb_h.path);
7416                         printf("Lun already enabled\n");
7417                         ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7418                         return;
7419                 }
7420
7421                 if (cel->grp6_len != 0
7422                  || cel->grp7_len != 0) {
7423                         /*
7424                          * Don't (yet?) support vendor
7425                          * specific commands.
7426                          */
7427                         ccb->ccb_h.status = CAM_REQ_INVALID;
7428                         printf("Non-zero Group Codes\n");
7429                         return;
7430                 }
7431
7432                 /*
7433                  * Seems to be okay.
7434                  * Setup our data structures.
7435                  */
7436                 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7437                         tstate = ahc_alloc_tstate(ahc, target, channel);
7438                         if (tstate == NULL) {
7439                                 xpt_print_path(ccb->ccb_h.path);
7440                                 printf("Couldn't allocate tstate\n");
7441                                 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7442                                 return;
7443                         }
7444                 }
7445                 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7446                 if (lstate == NULL) {
7447                         xpt_print_path(ccb->ccb_h.path);
7448                         printf("Couldn't allocate lstate\n");
7449                         ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7450                         return;
7451                 }
7452                 memset(lstate, 0, sizeof(*lstate));
7453                 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7454                                          xpt_path_path_id(ccb->ccb_h.path),
7455                                          xpt_path_target_id(ccb->ccb_h.path),
7456                                          xpt_path_lun_id(ccb->ccb_h.path));
7457                 if (status != CAM_REQ_CMP) {
7458                         free(lstate, M_DEVBUF);
7459                         xpt_print_path(ccb->ccb_h.path);
7460                         printf("Couldn't allocate path\n");
7461                         ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7462                         return;
7463                 }
7464                 SLIST_INIT(&lstate->accept_tios);
7465                 SLIST_INIT(&lstate->immed_notifies);
7466                 ahc_pause(ahc);
7467                 if (target != CAM_TARGET_WILDCARD) {
7468                         tstate->enabled_luns[lun] = lstate;
7469                         ahc->enabled_luns++;
7470
7471                         if ((ahc->features & AHC_MULTI_TID) != 0) {
7472                                 u_int targid_mask;
7473
7474                                 targid_mask = ahc_inb(ahc, TARGID)
7475                                             | (ahc_inb(ahc, TARGID + 1) << 8);
7476
7477                                 targid_mask |= target_mask;
7478                                 ahc_outb(ahc, TARGID, targid_mask);
7479                                 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7480
7481                                 ahc_update_scsiid(ahc, targid_mask);
7482                         } else {
7483                                 u_int our_id;
7484                                 char  channel;
7485
7486                                 channel = SIM_CHANNEL(ahc, sim);
7487                                 our_id = SIM_SCSI_ID(ahc, sim);
7488
7489                                 /*
7490                                  * This can only happen if selections
7491                                  * are not enabled
7492                                  */
7493                                 if (target != our_id) {
7494                                         u_int sblkctl;
7495                                         char  cur_channel;
7496                                         int   swap;
7497
7498                                         sblkctl = ahc_inb(ahc, SBLKCTL);
7499                                         cur_channel = (sblkctl & SELBUSB)
7500                                                     ? 'B' : 'A';
7501                                         if ((ahc->features & AHC_TWIN) == 0)
7502                                                 cur_channel = 'A';
7503                                         swap = cur_channel != channel;
7504                                         if (channel == 'A')
7505                                                 ahc->our_id = target;
7506                                         else
7507                                                 ahc->our_id_b = target;
7508
7509                                         if (swap)
7510                                                 ahc_outb(ahc, SBLKCTL,
7511                                                          sblkctl ^ SELBUSB);
7512
7513                                         ahc_outb(ahc, SCSIID, target);
7514
7515                                         if (swap)
7516                                                 ahc_outb(ahc, SBLKCTL, sblkctl);
7517                                 }
7518                         }
7519                 } else
7520                         ahc->black_hole = lstate;
7521                 /* Allow select-in operations */
7522                 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7523                         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7524                         scsiseq |= ENSELI;
7525                         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7526                         scsiseq = ahc_inb(ahc, SCSISEQ);
7527                         scsiseq |= ENSELI;
7528                         ahc_outb(ahc, SCSISEQ, scsiseq);
7529                 }
7530                 ahc_unpause(ahc);
7531                 ccb->ccb_h.status = CAM_REQ_CMP;
7532                 xpt_print_path(ccb->ccb_h.path);
7533                 printf("Lun now enabled for target mode\n");
7534         } else {
7535                 struct scb *scb;
7536                 int i, empty;
7537
7538                 if (lstate == NULL) {
7539                         ccb->ccb_h.status = CAM_LUN_INVALID;
7540                         return;
7541                 }
7542
7543                 ccb->ccb_h.status = CAM_REQ_CMP;
7544                 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7545                         struct ccb_hdr *ccbh;
7546
7547                         ccbh = &scb->io_ctx->ccb_h;
7548                         if (ccbh->func_code == XPT_CONT_TARGET_IO
7549                          && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7550                                 printf("CTIO pending\n");
7551                                 ccb->ccb_h.status = CAM_REQ_INVALID;
7552                                 return;
7553                         }
7554                 }
7555
7556                 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7557                         printf("ATIOs pending\n");
7558                         ccb->ccb_h.status = CAM_REQ_INVALID;
7559                 }
7560
7561                 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7562                         printf("INOTs pending\n");
7563                         ccb->ccb_h.status = CAM_REQ_INVALID;
7564                 }
7565
7566                 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7567                         return;
7568                 }
7569
7570                 xpt_print_path(ccb->ccb_h.path);
7571                 printf("Target mode disabled\n");
7572                 xpt_free_path(lstate->path);
7573                 free(lstate, M_DEVBUF);
7574
7575                 ahc_pause(ahc);
7576                 /* Can we clean up the target too? */
7577                 if (target != CAM_TARGET_WILDCARD) {
7578                         tstate->enabled_luns[lun] = NULL;
7579                         ahc->enabled_luns--;
7580                         for (empty = 1, i = 0; i < 8; i++)
7581                                 if (tstate->enabled_luns[i] != NULL) {
7582                                         empty = 0;
7583                                         break;
7584                                 }
7585
7586                         if (empty) {
7587                                 ahc_free_tstate(ahc, target, channel,
7588                                                 /*force*/FALSE);
7589                                 if (ahc->features & AHC_MULTI_TID) {
7590                                         u_int targid_mask;
7591
7592                                         targid_mask = ahc_inb(ahc, TARGID)
7593                                                     | (ahc_inb(ahc, TARGID + 1)
7594                                                        << 8);
7595
7596                                         targid_mask &= ~target_mask;
7597                                         ahc_outb(ahc, TARGID, targid_mask);
7598                                         ahc_outb(ahc, TARGID+1,
7599                                                  (targid_mask >> 8));
7600                                         ahc_update_scsiid(ahc, targid_mask);
7601                                 }
7602                         }
7603                 } else {
7604                         ahc->black_hole = NULL;
7605
7606                         /*
7607                          * We can't allow selections without
7608                          * our black hole device.
7609                          */
7610                         empty = TRUE;
7611                 }
7612                 if (ahc->enabled_luns == 0) {
7613                         /* Disallow select-in */
7614                         u_int scsiseq;
7615
7616                         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7617                         scsiseq &= ~ENSELI;
7618                         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7619                         scsiseq = ahc_inb(ahc, SCSISEQ);
7620                         scsiseq &= ~ENSELI;
7621                         ahc_outb(ahc, SCSISEQ, scsiseq);
7622
7623                         if ((ahc->features & AHC_MULTIROLE) == 0) {
7624                                 printf("Configuring Initiator Mode\n");
7625                                 ahc->flags &= ~AHC_TARGETROLE;
7626                                 ahc->flags |= AHC_INITIATORROLE;
7627                                 /*
7628                                  * Returning to a configuration that
7629                                  * fit previously will always succeed.
7630                                  */
7631                                 (void)ahc_loadseq(ahc);
7632                                 ahc_restart(ahc);
7633                                 /*
7634                                  * Unpaused.  The extra unpause
7635                                  * that follows is harmless.
7636                                  */
7637                         }
7638                 }
7639                 ahc_unpause(ahc);
7640         }
7641 }
7642
7643 static void
7644 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7645 {
7646         u_int scsiid_mask;
7647         u_int scsiid;
7648
7649         if ((ahc->features & AHC_MULTI_TID) == 0)
7650                 panic("ahc_update_scsiid called on non-multitid unit\n");
7651
7652         /*
7653          * Since we will rely on the TARGID mask
7654          * for selection enables, ensure that OID
7655          * in SCSIID is not set to some other ID
7656          * that we don't want to allow selections on.
7657          */
7658         if ((ahc->features & AHC_ULTRA2) != 0)
7659                 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7660         else
7661                 scsiid = ahc_inb(ahc, SCSIID);
7662         scsiid_mask = 0x1 << (scsiid & OID);
7663         if ((targid_mask & scsiid_mask) == 0) {
7664                 u_int our_id;
7665
7666                 /* ffs counts from 1 */
7667                 our_id = ffs(targid_mask);
7668                 if (our_id == 0)
7669                         our_id = ahc->our_id;
7670                 else
7671                         our_id--;
7672                 scsiid &= TID;
7673                 scsiid |= our_id;
7674         }
7675         if ((ahc->features & AHC_ULTRA2) != 0)
7676                 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7677         else
7678                 ahc_outb(ahc, SCSIID, scsiid);
7679 }
7680
7681 void
7682 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7683 {
7684         struct target_cmd *cmd;
7685
7686         /*
7687          * If the card supports auto-access pause,
7688          * we can access the card directly regardless
7689          * of whether it is paused or not.
7690          */
7691         if ((ahc->features & AHC_AUTOPAUSE) != 0)
7692                 paused = TRUE;
7693
7694         ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7695         while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7696                 /*
7697                  * Only advance through the queue if we
7698                  * have the resources to process the command.
7699                  */
7700                 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7701                         break;
7702
7703                 cmd->cmd_valid = 0;
7704                 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7705                                 ahc->shared_data_dmamap,
7706                                 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7707                                 sizeof(struct target_cmd),
7708                                 BUS_DMASYNC_PREREAD);
7709                 ahc->tqinfifonext++;
7710
7711                 /*
7712                  * Lazily update our position in the target mode incoming
7713                  * command queue as seen by the sequencer.
7714                  */
7715                 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7716                         if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7717                                 u_int hs_mailbox;
7718
7719                                 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7720                                 hs_mailbox &= ~HOST_TQINPOS;
7721                                 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7722                                 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7723                         } else {
7724                                 if (!paused)
7725                                         ahc_pause(ahc);
7726                                 ahc_outb(ahc, KERNEL_TQINPOS,
7727                                          ahc->tqinfifonext & HOST_TQINPOS);
7728                                 if (!paused)
7729                                         ahc_unpause(ahc);
7730                         }
7731                 }
7732         }
7733 }
7734
7735 static int
7736 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7737 {
7738         struct    ahc_tmode_tstate *tstate;
7739         struct    ahc_tmode_lstate *lstate;
7740         struct    ccb_accept_tio *atio;
7741         uint8_t *byte;
7742         int       initiator;
7743         int       target;
7744         int       lun;
7745
7746         initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7747         target = SCSIID_OUR_ID(cmd->scsiid);
7748         lun    = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7749
7750         byte = cmd->bytes;
7751         tstate = ahc->enabled_targets[target];
7752         lstate = NULL;
7753         if (tstate != NULL)
7754                 lstate = tstate->enabled_luns[lun];
7755
7756         /*
7757          * Commands for disabled luns go to the black hole driver.
7758          */
7759         if (lstate == NULL)
7760                 lstate = ahc->black_hole;
7761
7762         atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7763         if (atio == NULL) {
7764                 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7765                 /*
7766                  * Wait for more ATIOs from the peripheral driver for this lun.
7767                  */
7768                 if (bootverbose)
7769                         printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7770                 return (1);
7771         } else
7772                 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7773 #ifdef AHC_DEBUG
7774         if (ahc_debug & AHC_SHOW_TQIN) {
7775                 printf("Incoming command from %d for %d:%d%s\n",
7776                        initiator, target, lun,
7777                        lstate == ahc->black_hole ? "(Black Holed)" : "");
7778         }
7779 #endif
7780         SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7781
7782         if (lstate == ahc->black_hole) {
7783                 /* Fill in the wildcards */
7784                 atio->ccb_h.target_id = target;
7785                 atio->ccb_h.target_lun = lun;
7786         }
7787
7788         /*
7789          * Package it up and send it off to
7790          * whomever has this lun enabled.
7791          */
7792         atio->sense_len = 0;
7793         atio->init_id = initiator;
7794         if (byte[0] != 0xFF) {
7795                 /* Tag was included */
7796                 atio->tag_action = *byte++;
7797                 atio->tag_id = *byte++;
7798                 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
7799         } else {
7800                 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
7801         }
7802         byte++;
7803
7804         /* Okay.  Now determine the cdb size based on the command code */
7805         switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7806         case 0:
7807                 atio->cdb_len = 6;
7808                 break;
7809         case 1:
7810         case 2:
7811                 atio->cdb_len = 10;
7812                 break;
7813         case 4:
7814                 atio->cdb_len = 16;
7815                 break;
7816         case 5:
7817                 atio->cdb_len = 12;
7818                 break;
7819         case 3:
7820         default:
7821                 /* Only copy the opcode. */
7822                 atio->cdb_len = 1;
7823                 printf("Reserved or VU command code type encountered\n");
7824                 break;
7825         }
7826
7827         memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7828
7829         atio->ccb_h.status |= CAM_CDB_RECVD;
7830
7831         if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7832                 /*
7833                  * We weren't allowed to disconnect.
7834                  * We're hanging on the bus until a
7835                  * continue target I/O comes in response
7836                  * to this accept tio.
7837                  */
7838 #ifdef AHC_DEBUG
7839                 if (ahc_debug & AHC_SHOW_TQIN) {
7840                         printf("Received Immediate Command %d:%d:%d - %p\n",
7841                                initiator, target, lun, ahc->pending_device);
7842                 }
7843 #endif
7844                 ahc->pending_device = lstate;
7845                 aic_freeze_ccb((union ccb *)atio);
7846                 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7847         }
7848         xpt_done((union ccb*)atio);
7849         return (0);
7850 }
7851
7852 #endif