2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
55 /****************************** Softc Data ************************************/
56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
58 /***************************** Lookup Tables **********************************/
59 char *ahc_chip_names[] =
78 * Hardware error codes.
80 struct ahc_hard_error_entry {
85 static struct ahc_hard_error_entry ahc_hard_errors[] = {
86 { ILLHADDR, "Illegal Host Access" },
87 { ILLSADDR, "Illegal Sequencer Address referrenced" },
88 { ILLOPCODE, "Illegal Opcode in sequencer program" },
89 { SQPARERR, "Sequencer Parity Error" },
90 { DPARERR, "Data-path Parity Error" },
91 { MPARERR, "Scratch or SCB Memory Parity Error" },
92 { PCIERRSTAT, "PCI Error detected" },
93 { CIOPARERR, "CIOBUS Parity Error" },
95 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
97 static struct ahc_phase_table_entry ahc_phase_table[] =
99 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
100 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
101 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
102 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
103 { P_COMMAND, MSG_NOOP, "in Command phase" },
104 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
105 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
106 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
107 { P_BUSFREE, MSG_NOOP, "while idle" },
108 { 0, MSG_NOOP, "in unknown phase" }
112 * In most cases we only wish to itterate over real phases, so
113 * exclude the last element from the count.
115 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
118 * Valid SCSIRATE values. (p. 3-17)
119 * Provides a mapping of tranfer periods in ns to the proper value to
120 * stick in the scsixfer reg.
122 static struct ahc_syncrate ahc_syncrates[] =
124 /* ultra2 fast/ultra period rate */
125 { 0x42, 0x000, 9, "80.0" },
126 { 0x03, 0x000, 10, "40.0" },
127 { 0x04, 0x000, 11, "33.0" },
128 { 0x05, 0x100, 12, "20.0" },
129 { 0x06, 0x110, 15, "16.0" },
130 { 0x07, 0x120, 18, "13.4" },
131 { 0x08, 0x000, 25, "10.0" },
132 { 0x19, 0x010, 31, "8.0" },
133 { 0x1a, 0x020, 37, "6.67" },
134 { 0x1b, 0x030, 43, "5.7" },
135 { 0x1c, 0x040, 50, "5.0" },
136 { 0x00, 0x050, 56, "4.4" },
137 { 0x00, 0x060, 62, "4.0" },
138 { 0x00, 0x070, 68, "3.6" },
139 { 0x00, 0x000, 0, NULL }
142 /* Our Sequencer Program */
143 #include "aic7xxx_seq.h"
145 /**************************** Function Declarations ***************************/
146 static void ahc_force_renegotiation(struct ahc_softc *ahc,
147 struct ahc_devinfo *devinfo);
148 static struct ahc_tmode_tstate*
149 ahc_alloc_tstate(struct ahc_softc *ahc,
150 u_int scsi_id, char channel);
151 #ifdef AHC_TARGET_MODE
152 static void ahc_free_tstate(struct ahc_softc *ahc,
153 u_int scsi_id, char channel, int force);
155 static struct ahc_syncrate*
156 ahc_devlimited_syncrate(struct ahc_softc *ahc,
157 struct ahc_initiator_tinfo *,
161 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
162 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
163 struct ahc_devinfo *devinfo);
164 static void ahc_scb_devinfo(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
167 static void ahc_assert_atn(struct ahc_softc *ahc);
168 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
169 struct ahc_devinfo *devinfo,
171 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
172 struct ahc_devinfo *devinfo);
173 static void ahc_construct_sdtr(struct ahc_softc *ahc,
174 struct ahc_devinfo *devinfo,
175 u_int period, u_int offset);
176 static void ahc_construct_wdtr(struct ahc_softc *ahc,
177 struct ahc_devinfo *devinfo,
179 static void ahc_construct_ppr(struct ahc_softc *ahc,
180 struct ahc_devinfo *devinfo,
181 u_int period, u_int offset,
182 u_int bus_width, u_int ppr_options);
183 static void ahc_clear_msg_state(struct ahc_softc *ahc);
184 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
185 static void ahc_handle_message_phase(struct ahc_softc *ahc);
191 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
192 u_int msgval, int full);
193 static int ahc_parse_msg(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
196 struct ahc_devinfo *devinfo);
197 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
198 struct ahc_devinfo *devinfo);
199 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
200 static void ahc_handle_devreset(struct ahc_softc *ahc,
201 struct ahc_devinfo *devinfo,
202 cam_status status, char *message,
204 #ifdef AHC_TARGET_MODE
205 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
206 struct ahc_devinfo *devinfo,
210 static bus_dmamap_callback_t ahc_dmamap_cb;
211 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
212 static int ahc_init_scbdata(struct ahc_softc *ahc);
213 static void ahc_fini_scbdata(struct ahc_softc *ahc);
214 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
215 struct scb *prev_scb,
217 static int ahc_qinfifo_count(struct ahc_softc *ahc);
218 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
219 u_int prev, u_int scbptr);
220 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
221 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
222 u_int scbpos, u_int prev);
223 static void ahc_reset_current_bus(struct ahc_softc *ahc);
225 static void ahc_dumpseq(struct ahc_softc *ahc);
227 static int ahc_loadseq(struct ahc_softc *ahc);
228 static int ahc_check_patch(struct ahc_softc *ahc,
229 struct patch **start_patch,
230 u_int start_instr, u_int *skip_addr);
231 static void ahc_download_instr(struct ahc_softc *ahc,
232 u_int instrptr, uint8_t *dconsts);
233 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
235 struct scb *other_scb);
236 #ifdef AHC_TARGET_MODE
237 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
238 struct ahc_tmode_lstate *lstate,
242 static void ahc_update_scsiid(struct ahc_softc *ahc,
244 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
245 struct target_cmd *cmd);
247 /************************* Sequencer Execution Control ************************/
249 * Restart the sequencer program from address zero
252 ahc_restart(struct ahc_softc *ahc)
257 /* No more pending messages. */
258 ahc_clear_msg_state(ahc);
260 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
261 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
262 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
263 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
264 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
265 ahc_outb(ahc, SAVED_LUN, 0xFF);
268 * Ensure that the sequencer's idea of TQINPOS
269 * matches our own. The sequencer increments TQINPOS
270 * only after it sees a DMA complete and a reset could
271 * occur before the increment leaving the kernel to believe
272 * the command arrived but the sequencer to not.
274 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
276 /* Always allow reselection */
277 ahc_outb(ahc, SCSISEQ,
278 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
279 if ((ahc->features & AHC_CMD_CHAN) != 0) {
280 /* Ensure that no DMA operations are in progress */
281 ahc_outb(ahc, CCSCBCNT, 0);
282 ahc_outb(ahc, CCSGCTL, 0);
283 ahc_outb(ahc, CCSCBCTL, 0);
286 * If we were in the process of DMA'ing SCB data into
287 * an SCB, replace that SCB on the free list. This prevents
290 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
291 ahc_add_curscb_to_free_list(ahc);
292 ahc_outb(ahc, SEQ_FLAGS2,
293 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
297 * Clear any pending sequencer interrupt. It is no
298 * longer relevant since we're resetting the Program
301 ahc_outb(ahc, CLRINT, CLRSEQINT);
303 ahc_outb(ahc, MWI_RESIDUAL, 0);
304 ahc_outb(ahc, SEQCTL, ahc->seqctl);
305 ahc_outb(ahc, SEQADDR0, 0);
306 ahc_outb(ahc, SEQADDR1, 0);
311 /************************* Input/Output Queues ********************************/
313 ahc_run_qoutfifo(struct ahc_softc *ahc)
318 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
319 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
321 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
322 if ((ahc->qoutfifonext & 0x03) == 0x03) {
326 * Clear 32bits of QOUTFIFO at a time
327 * so that we don't clobber an incoming
328 * byte DMA to the array on architectures
329 * that only support 32bit load and store
332 modnext = ahc->qoutfifonext & ~0x3;
333 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
334 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
335 ahc->shared_data_dmamap,
336 /*offset*/modnext, /*len*/4,
337 BUS_DMASYNC_PREREAD);
341 scb = ahc_lookup_scb(ahc, scb_index);
343 printf("%s: WARNING no command for scb %d "
344 "(cmdcmplt)\nQOUTPOS = %d\n",
345 ahc_name(ahc), scb_index,
346 (ahc->qoutfifonext - 1) & 0xFF);
351 * Save off the residual
354 ahc_update_residual(ahc, scb);
360 ahc_run_untagged_queues(struct ahc_softc *ahc)
364 for (i = 0; i < 16; i++)
365 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
369 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
373 if (ahc->untagged_queue_lock != 0)
376 if ((scb = TAILQ_FIRST(queue)) != NULL
377 && (scb->flags & SCB_ACTIVE) == 0) {
378 scb->flags |= SCB_ACTIVE;
380 * Timers are disabled while recovery is in progress.
382 aic_scb_timer_start(scb);
383 ahc_queue_scb(ahc, scb);
387 /************************* Interrupt Handling *********************************/
389 ahc_handle_brkadrint(struct ahc_softc *ahc)
392 * We upset the sequencer :-(
393 * Lookup the error message
398 error = ahc_inb(ahc, ERROR);
399 for (i = 0; error != 1 && i < num_errors; i++)
401 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
402 ahc_name(ahc), ahc_hard_errors[i].errmesg,
403 ahc_inb(ahc, SEQADDR0) |
404 (ahc_inb(ahc, SEQADDR1) << 8));
406 ahc_dump_card_state(ahc);
408 /* Tell everyone that this HBA is no longer available */
409 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
410 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
413 /* Disable all interrupt sources by resetting the controller */
418 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
421 struct ahc_devinfo devinfo;
423 ahc_fetch_devinfo(ahc, &devinfo);
426 * Clear the upper byte that holds SEQINT status
427 * codes and clear the SEQINT bit. We will unpause
428 * the sequencer, if appropriate, after servicing
431 ahc_outb(ahc, CLRINT, CLRSEQINT);
432 switch (intstat & SEQINT_MASK) {
436 struct hardware_scb *hscb;
439 * Set the default return value to 0 (don't
440 * send sense). The sense code will change
443 ahc_outb(ahc, RETURN_1, 0);
446 * The sequencer will notify us when a command
447 * has an error that would be of interest to
448 * the kernel. This allows us to leave the sequencer
449 * running in the common case of command completes
450 * without error. The sequencer will already have
451 * dma'd the SCB back up to us, so we can reference
452 * the in kernel copy directly.
454 scb_index = ahc_inb(ahc, SCB_TAG);
455 scb = ahc_lookup_scb(ahc, scb_index);
457 ahc_print_devinfo(ahc, &devinfo);
458 printf("ahc_intr - referenced scb "
459 "not valid during seqint 0x%x scb(%d)\n",
461 ahc_dump_card_state(ahc);
468 /* Don't want to clobber the original sense code */
469 if ((scb->flags & SCB_SENSE) != 0) {
471 * Clear the SCB_SENSE Flag and have
472 * the sequencer do a normal command
475 scb->flags &= ~SCB_SENSE;
476 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
479 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
480 /* Freeze the queue until the client sees the error. */
481 ahc_freeze_devq(ahc, scb);
483 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
484 switch (hscb->shared_data.status.scsi_status) {
486 printf("%s: Interrupted for staus of 0???\n",
489 case SCSI_STATUS_CMD_TERMINATED:
490 case SCSI_STATUS_CHECK_COND:
492 struct ahc_dma_seg *sg;
493 struct scsi_sense *sc;
494 struct ahc_initiator_tinfo *targ_info;
495 struct ahc_tmode_tstate *tstate;
496 struct ahc_transinfo *tinfo;
498 if (ahc_debug & AHC_SHOW_SENSE) {
499 ahc_print_path(ahc, scb);
500 printf("SCB %d: requests Check Status\n",
505 if (aic_perform_autosense(scb) == 0)
508 targ_info = ahc_fetch_transinfo(ahc,
513 tinfo = &targ_info->curr;
515 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
517 * Save off the residual if there is one.
519 ahc_update_residual(ahc, scb);
521 if (ahc_debug & AHC_SHOW_SENSE) {
522 ahc_print_path(ahc, scb);
523 printf("Sending Sense\n");
526 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
527 sg->len = aic_get_sense_bufsize(ahc, scb);
528 sg->len |= AHC_DMA_LAST_SEG;
530 /* Fixup byte order */
531 sg->addr = aic_htole32(sg->addr);
532 sg->len = aic_htole32(sg->len);
534 sc->opcode = REQUEST_SENSE;
536 if (tinfo->protocol_version <= SCSI_REV_2
537 && SCB_GET_LUN(scb) < 8)
538 sc->byte2 = SCB_GET_LUN(scb) << 5;
541 sc->length = sg->len;
545 * We can't allow the target to disconnect.
546 * This will be an untagged transaction and
547 * having the target disconnect will make this
548 * transaction indestinguishable from outstanding
549 * tagged transactions.
554 * This request sense could be because the
555 * the device lost power or in some other
556 * way has lost our transfer negotiations.
557 * Renegotiate if appropriate. Unit attention
558 * errors will be reported before any data
561 if (aic_get_residual(scb)
562 == aic_get_transfer_length(scb)) {
563 ahc_update_neg_request(ahc, &devinfo,
565 AHC_NEG_IF_NON_ASYNC);
567 if (tstate->auto_negotiate & devinfo.target_mask) {
568 hscb->control |= MK_MESSAGE;
569 scb->flags &= ~SCB_NEGOTIATE;
570 scb->flags |= SCB_AUTO_NEGOTIATE;
572 hscb->cdb_len = sizeof(*sc);
573 hscb->dataptr = sg->addr;
574 hscb->datacnt = sg->len;
575 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
576 hscb->sgptr = aic_htole32(hscb->sgptr);
578 scb->flags |= SCB_SENSE;
579 ahc_qinfifo_requeue_tail(ahc, scb);
580 ahc_outb(ahc, RETURN_1, SEND_SENSE);
582 * Ensure we have enough time to actually
583 * retrieve the sense, but only schedule
584 * the timer if we are not in recovery or
585 * this is a recovery SCB that is allowed
586 * to have an active timer.
588 if (ahc->scb_data->recovery_scbs == 0
589 || (scb->flags & SCB_RECOVERY_SCB) != 0)
590 aic_scb_timer_reset(scb, 5 * 1000);
600 /* Ensure we don't leave the selection hardware on */
601 ahc_outb(ahc, SCSISEQ,
602 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
604 printf("%s:%c:%d: no active SCB for reconnecting "
605 "target - issuing BUS DEVICE RESET\n",
606 ahc_name(ahc), devinfo.channel, devinfo.target);
607 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
608 "ARG_1 == 0x%x ACCUM = 0x%x\n",
609 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
610 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
611 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
613 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
614 ahc_index_busy_tcl(ahc,
615 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
616 ahc_inb(ahc, SAVED_LUN))),
617 ahc_inb(ahc, SINDEX));
618 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
619 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
620 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
621 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
622 ahc_inb(ahc, SCB_CONTROL));
623 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
624 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
625 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
626 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
627 ahc_dump_card_state(ahc);
628 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
630 ahc->msgout_index = 0;
631 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
632 ahc_outb(ahc, MSG_OUT, HOST_MSG);
638 u_int rejbyte = ahc_inb(ahc, ACCUM);
639 printf("%s:%c:%d: Warning - unknown message received from "
640 "target (0x%x). Rejecting\n",
641 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
644 case PROTO_VIOLATION:
646 ahc_handle_proto_violation(ahc);
650 ahc_handle_ign_wide_residue(ahc, &devinfo);
653 ahc_reinitialize_dataptrs(ahc);
659 lastphase = ahc_inb(ahc, LASTPHASE);
660 printf("%s:%c:%d: unknown scsi bus phase %x, "
661 "lastphase = 0x%x. Attempting to continue\n",
662 ahc_name(ahc), devinfo.channel, devinfo.target,
663 lastphase, ahc_inb(ahc, SCSISIGI));
670 lastphase = ahc_inb(ahc, LASTPHASE);
671 printf("%s:%c:%d: Missed busfree. "
672 "Lastphase = 0x%x, Curphase = 0x%x\n",
673 ahc_name(ahc), devinfo.channel, devinfo.target,
674 lastphase, ahc_inb(ahc, SCSISIGI));
681 * The sequencer has encountered a message phase
682 * that requires host assistance for completion.
683 * While handling the message phase(s), we will be
684 * notified by the sequencer after each byte is
685 * transfered so we can track bus phase changes.
687 * If this is the first time we've seen a HOST_MSG_LOOP
688 * interrupt, initialize the state of the host message
691 if (ahc->msg_type == MSG_TYPE_NONE) {
696 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
697 if (bus_phase != P_MESGIN
698 && bus_phase != P_MESGOUT) {
699 printf("ahc_intr: HOST_MSG_LOOP bad "
703 * Probably transitioned to bus free before
704 * we got here. Just punt the message.
706 ahc_clear_intstat(ahc);
711 scb_index = ahc_inb(ahc, SCB_TAG);
712 scb = ahc_lookup_scb(ahc, scb_index);
713 if (devinfo.role == ROLE_INITIATOR) {
715 panic("HOST_MSG_LOOP with "
716 "invalid SCB %x\n", scb_index);
718 if (bus_phase == P_MESGOUT)
719 ahc_setup_initiator_msgout(ahc,
724 MSG_TYPE_INITIATOR_MSGIN;
725 ahc->msgin_index = 0;
728 #ifdef AHC_TARGET_MODE
730 if (bus_phase == P_MESGOUT) {
732 MSG_TYPE_TARGET_MSGOUT;
733 ahc->msgin_index = 0;
736 ahc_setup_target_msgin(ahc,
743 ahc_handle_message_phase(ahc);
749 * If we've cleared the parity error interrupt
750 * but the sequencer still believes that SCSIPERR
751 * is true, it must be that the parity error is
752 * for the currently presented byte on the bus,
753 * and we are not in a phase (data-in) where we will
754 * eventually ack this byte. Ack the byte and
755 * throw it away in the hope that the target will
756 * take us to message out to deliver the appropriate
759 if ((intstat & SCSIINT) == 0
760 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
762 if ((ahc->features & AHC_DT) == 0) {
766 * The hardware will only let you ack bytes
767 * if the expected phase in SCSISIGO matches
768 * the current phase. Make sure this is
769 * currently the case.
771 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
772 ahc_outb(ahc, LASTPHASE, curphase);
773 ahc_outb(ahc, SCSISIGO, curphase);
775 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
779 * In a data phase. Faster to bitbucket
780 * the data than to individually ack each
781 * byte. This is also the only strategy
782 * that will work with AUTOACK enabled.
784 ahc_outb(ahc, SXFRCTL1,
785 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
787 while (--wait != 0) {
788 if ((ahc_inb(ahc, SCSISIGI)
793 ahc_outb(ahc, SXFRCTL1,
794 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
799 ahc_print_devinfo(ahc, &devinfo);
800 printf("Unable to clear parity error. "
802 scb_index = ahc_inb(ahc, SCB_TAG);
803 scb = ahc_lookup_scb(ahc, scb_index);
805 aic_set_transaction_status(scb,
807 ahc_reset_channel(ahc, devinfo.channel,
811 ahc_inb(ahc, SCSIDATL);
819 * When the sequencer detects an overrun, it
820 * places the controller in "BITBUCKET" mode
821 * and allows the target to complete its transfer.
822 * Unfortunately, none of the counters get updated
823 * when the controller is in this mode, so we have
824 * no way of knowing how large the overrun was.
826 u_int scbindex = ahc_inb(ahc, SCB_TAG);
827 u_int lastphase = ahc_inb(ahc, LASTPHASE);
830 scb = ahc_lookup_scb(ahc, scbindex);
831 for (i = 0; i < num_phases; i++) {
832 if (lastphase == ahc_phase_table[i].phase)
835 ahc_print_path(ahc, scb);
836 printf("data overrun detected %s."
838 ahc_phase_table[i].phasemsg,
840 ahc_print_path(ahc, scb);
841 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
842 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
843 aic_get_transfer_length(scb), scb->sg_count);
844 if (scb->sg_count > 0) {
845 for (i = 0; i < scb->sg_count; i++) {
847 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
849 (aic_le32toh(scb->sg_list[i].len) >> 24
850 & SG_HIGH_ADDR_BITS),
851 aic_le32toh(scb->sg_list[i].addr),
852 aic_le32toh(scb->sg_list[i].len)
857 * Set this and it will take effect when the
858 * target does a command complete.
860 ahc_freeze_devq(ahc, scb);
861 if ((scb->flags & SCB_SENSE) == 0) {
862 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
864 scb->flags &= ~SCB_SENSE;
865 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
869 if ((ahc->features & AHC_ULTRA2) != 0) {
871 * Clear the channel in case we return
872 * to data phase later.
874 ahc_outb(ahc, SXFRCTL0,
875 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
876 ahc_outb(ahc, SXFRCTL0,
877 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
879 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
882 /* Ensure HHADDR is 0 for future DMA operations. */
883 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
884 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
885 ahc_outb(ahc, HADDR, 0);
886 ahc_outb(ahc, DSCOMMAND1, dscommand1);
894 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
895 ahc_name(ahc), devinfo.channel, devinfo.target,
897 scbindex = ahc_inb(ahc, SCB_TAG);
898 scb = ahc_lookup_scb(ahc, scbindex);
900 && (scb->flags & SCB_RECOVERY_SCB) != 0)
902 * Ensure that we didn't put a second instance of this
903 * SCB into the QINFIFO.
905 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
906 SCB_GET_CHANNEL(ahc, scb),
907 SCB_GET_LUN(scb), scb->hscb->tag,
908 ROLE_INITIATOR, /*status*/0,
914 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
915 ahc_dump_card_state(ahc);
923 scbptr = ahc_inb(ahc, SCBPTR);
924 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
925 scbptr, ahc_inb(ahc, ARG_1),
926 ahc->scb_data->hscbs[scbptr].tag);
927 ahc_dump_card_state(ahc);
933 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
934 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
935 "ARG_1 == 0x%x ACCUM = 0x%x\n",
936 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
937 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
938 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
939 "SINDEX == 0x%x\n, A == 0x%x\n",
940 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
941 ahc_index_busy_tcl(ahc,
942 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
943 ahc_inb(ahc, SAVED_LUN))),
944 ahc_inb(ahc, SINDEX),
945 ahc_inb(ahc, ACCUM));
946 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
947 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
948 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
949 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
950 ahc_inb(ahc, SCB_CONTROL));
951 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
952 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
953 ahc_dump_card_state(ahc);
958 printf("ahc_intr: seqint, "
959 "intstat == 0x%x, scsisigi = 0x%x\n",
960 intstat, ahc_inb(ahc, SCSISIGI));
965 * The sequencer is paused immediately on
966 * a SEQINT, so we should restart it when
973 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
982 if ((ahc->features & AHC_TWIN) != 0
983 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
987 intr_channel = cur_channel;
989 if ((ahc->features & AHC_ULTRA2) != 0)
990 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
993 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
994 if (status == 0 && status0 == 0) {
995 if ((ahc->features & AHC_TWIN) != 0) {
996 /* Try the other channel */
997 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
998 status = ahc_inb(ahc, SSTAT1)
999 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1000 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1003 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1004 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1010 /* Make sure the sequencer is in a safe location. */
1011 ahc_clear_critical_section(ahc);
1013 scb_index = ahc_inb(ahc, SCB_TAG);
1014 scb = ahc_lookup_scb(ahc, scb_index);
1016 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1019 if ((ahc->features & AHC_ULTRA2) != 0
1020 && (status0 & IOERR) != 0) {
1023 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1024 printf("%s: Transceiver State Has Changed to %s mode\n",
1025 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1026 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1028 * When transitioning to SE mode, the reset line
1029 * glitches, triggering an arbitration bug in some
1030 * Ultra2 controllers. This bug is cleared when we
1031 * assert the reset line. Since a reset glitch has
1032 * already occurred with this transition and a
1033 * transceiver state change is handled just like
1034 * a bus reset anyway, asserting the reset line
1035 * ourselves is safe.
1037 ahc_reset_channel(ahc, intr_channel,
1038 /*Initiate Reset*/now_lvd == 0);
1039 } else if ((status & SCSIRSTI) != 0) {
1040 printf("%s: Someone reset channel %c\n",
1041 ahc_name(ahc), intr_channel);
1042 if (intr_channel != cur_channel)
1043 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1044 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1045 } else if ((status & SCSIPERR) != 0) {
1047 * Determine the bus phase and queue an appropriate message.
1048 * SCSIPERR is latched true as soon as a parity error
1049 * occurs. If the sequencer acked the transfer that
1050 * caused the parity error and the currently presented
1051 * transfer on the bus has correct parity, SCSIPERR will
1052 * be cleared by CLRSCSIPERR. Use this to determine if
1053 * we should look at the last phase the sequencer recorded,
1054 * or the current phase presented on the bus.
1056 struct ahc_devinfo devinfo;
1066 lastphase = ahc_inb(ahc, LASTPHASE);
1067 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1068 sstat2 = ahc_inb(ahc, SSTAT2);
1069 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1071 * For all phases save DATA, the sequencer won't
1072 * automatically ack a byte that has a parity error
1073 * in it. So the only way that the current phase
1074 * could be 'data-in' is if the parity error is for
1075 * an already acked byte in the data phase. During
1076 * synchronous data-in transfers, we may actually
1077 * ack bytes before latching the current phase in
1078 * LASTPHASE, leading to the discrepancy between
1079 * curphase and lastphase.
1081 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1082 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1083 errorphase = curphase;
1085 errorphase = lastphase;
1087 for (i = 0; i < num_phases; i++) {
1088 if (errorphase == ahc_phase_table[i].phase)
1091 mesg_out = ahc_phase_table[i].mesg_out;
1094 if (SCB_IS_SILENT(scb))
1097 ahc_print_path(ahc, scb);
1098 scb->flags |= SCB_TRANSMISSION_ERROR;
1100 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1101 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1102 scsirate = ahc_inb(ahc, SCSIRATE);
1103 if (silent == FALSE) {
1104 printf("parity error detected %s. "
1105 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1106 ahc_phase_table[i].phasemsg,
1107 ahc_inw(ahc, SEQADDR0),
1109 if ((ahc->features & AHC_DT) != 0) {
1110 if ((sstat2 & CRCVALERR) != 0)
1111 printf("\tCRC Value Mismatch\n");
1112 if ((sstat2 & CRCENDERR) != 0)
1113 printf("\tNo terminal CRC packet "
1115 if ((sstat2 & CRCREQERR) != 0)
1116 printf("\tIllegal CRC packet "
1118 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1119 printf("\tUnexpected %sDT Data Phase\n",
1120 (scsirate & SINGLE_EDGE)
1125 if ((ahc->features & AHC_DT) != 0
1126 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1128 * This error applies regardless of
1129 * data direction, so ignore the value
1130 * in the phase table.
1132 mesg_out = MSG_INITIATOR_DET_ERR;
1136 * We've set the hardware to assert ATN if we
1137 * get a parity error on "in" phases, so all we
1138 * need to do is stuff the message buffer with
1139 * the appropriate message. "In" phases have set
1140 * mesg_out to something other than MSG_NOP.
1142 if (mesg_out != MSG_NOOP) {
1143 if (ahc->msg_type != MSG_TYPE_NONE)
1144 ahc->send_msg_perror = TRUE;
1146 ahc_outb(ahc, MSG_OUT, mesg_out);
1149 * Force a renegotiation with this target just in
1150 * case we are out of sync for some external reason
1151 * unknown (or unreported) by the target.
1153 ahc_fetch_devinfo(ahc, &devinfo);
1154 ahc_force_renegotiation(ahc, &devinfo);
1156 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1158 } else if ((status & SELTO) != 0) {
1161 /* Stop the selection */
1162 ahc_outb(ahc, SCSISEQ, 0);
1164 /* No more pending messages */
1165 ahc_clear_msg_state(ahc);
1167 /* Clear interrupt state */
1168 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1169 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1172 * Although the driver does not care about the
1173 * 'Selection in Progress' status bit, the busy
1174 * LED does. SELINGO is only cleared by a sucessfull
1175 * selection, so we must manually clear it to insure
1176 * the LED turns off just incase no future successful
1177 * selections occur (e.g. no devices on the bus).
1179 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1181 scbptr = ahc_inb(ahc, WAITING_SCBH);
1182 ahc_outb(ahc, SCBPTR, scbptr);
1183 scb_index = ahc_inb(ahc, SCB_TAG);
1185 scb = ahc_lookup_scb(ahc, scb_index);
1187 printf("%s: ahc_intr - referenced scb not "
1188 "valid during SELTO scb(%d, %d)\n",
1189 ahc_name(ahc), scbptr, scb_index);
1190 ahc_dump_card_state(ahc);
1192 struct ahc_devinfo devinfo;
1194 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1195 ahc_print_path(ahc, scb);
1196 printf("Saw Selection Timeout for SCB 0x%x\n",
1200 ahc_scb_devinfo(ahc, &devinfo, scb);
1201 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1202 ahc_freeze_devq(ahc, scb);
1205 * Cancel any pending transactions on the device
1206 * now that it seems to be missing. This will
1207 * also revert us to async/narrow transfers until
1208 * we can renegotiate with the device.
1210 ahc_handle_devreset(ahc, &devinfo,
1212 "Selection Timeout",
1213 /*verbose_level*/1);
1215 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1217 } else if ((status & BUSFREE) != 0
1218 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1219 struct ahc_devinfo devinfo;
1224 u_int initiator_role_id;
1229 * Clear our selection hardware as soon as possible.
1230 * We may have an entry in the waiting Q for this target,
1231 * that is affected by this busfree and we don't want to
1232 * go about selecting the target while we handle the event.
1234 ahc_outb(ahc, SCSISEQ,
1235 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1238 * Disable busfree interrupts and clear the busfree
1239 * interrupt status. We do this here so that several
1240 * bus transactions occur prior to clearing the SCSIINT
1241 * latch. It can take a bit for the clearing to take effect.
1243 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1244 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1247 * Look at what phase we were last in.
1248 * If its message out, chances are pretty good
1249 * that the busfree was in response to one of
1250 * our abort requests.
1252 lastphase = ahc_inb(ahc, LASTPHASE);
1253 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1254 saved_lun = ahc_inb(ahc, SAVED_LUN);
1255 target = SCSIID_TARGET(ahc, saved_scsiid);
1256 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1257 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1258 ahc_compile_devinfo(&devinfo, initiator_role_id,
1259 target, saved_lun, channel, ROLE_INITIATOR);
1262 if (lastphase == P_MESGOUT) {
1265 tag = SCB_LIST_NULL;
1266 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1267 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1268 if (ahc->msgout_buf[ahc->msgout_index - 1]
1270 tag = scb->hscb->tag;
1271 ahc_print_path(ahc, scb);
1272 printf("SCB %d - Abort%s Completed.\n",
1273 scb->hscb->tag, tag == SCB_LIST_NULL ?
1275 ahc_abort_scbs(ahc, target, channel,
1280 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1281 MSG_BUS_DEV_RESET, TRUE)) {
1284 * Don't mark the user's request for this BDR
1285 * as completing with CAM_BDR_SENT. CAM3
1286 * specifies CAM_REQ_CMP.
1289 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1290 && ahc_match_scb(ahc, scb, target, channel,
1294 aic_set_transaction_status(scb, CAM_REQ_CMP);
1297 ahc_compile_devinfo(&devinfo,
1303 ahc_handle_devreset(ahc, &devinfo,
1306 /*verbose_level*/0);
1308 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1309 MSG_EXT_PPR, FALSE)) {
1310 struct ahc_initiator_tinfo *tinfo;
1311 struct ahc_tmode_tstate *tstate;
1314 * PPR Rejected. Try non-ppr negotiation
1315 * and retry command.
1317 tinfo = ahc_fetch_transinfo(ahc,
1322 tinfo->curr.transport_version = 2;
1323 tinfo->goal.transport_version = 2;
1324 tinfo->goal.ppr_options = 0;
1325 ahc_qinfifo_requeue_tail(ahc, scb);
1327 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1328 MSG_EXT_WDTR, FALSE)) {
1330 * Negotiation Rejected. Go-narrow and
1333 ahc_set_width(ahc, &devinfo,
1334 MSG_EXT_WDTR_BUS_8_BIT,
1335 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1337 ahc_qinfifo_requeue_tail(ahc, scb);
1339 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1340 MSG_EXT_SDTR, FALSE)) {
1342 * Negotiation Rejected. Go-async and
1345 ahc_set_syncrate(ahc, &devinfo,
1347 /*period*/0, /*offset*/0,
1349 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1351 ahc_qinfifo_requeue_tail(ahc, scb);
1355 if (printerror != 0) {
1361 if ((scb->hscb->control & TAG_ENB) != 0)
1362 tag = scb->hscb->tag;
1364 tag = SCB_LIST_NULL;
1365 ahc_print_path(ahc, scb);
1366 ahc_abort_scbs(ahc, target, channel,
1367 SCB_GET_LUN(scb), tag,
1372 * We had not fully identified this connection,
1373 * so we cannot abort anything.
1375 printf("%s: ", ahc_name(ahc));
1377 for (i = 0; i < num_phases; i++) {
1378 if (lastphase == ahc_phase_table[i].phase)
1381 if (lastphase != P_BUSFREE) {
1383 * Renegotiate with this device at the
1384 * next oportunity just in case this busfree
1385 * is due to a negotiation mismatch with the
1388 ahc_force_renegotiation(ahc, &devinfo);
1390 printf("Unexpected busfree %s\n"
1391 "SEQADDR == 0x%x\n",
1392 ahc_phase_table[i].phasemsg,
1393 ahc_inb(ahc, SEQADDR0)
1394 | (ahc_inb(ahc, SEQADDR1) << 8));
1396 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1399 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1400 ahc_name(ahc), status);
1401 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1406 * Force renegotiation to occur the next time we initiate
1407 * a command to the current device.
1410 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1412 struct ahc_initiator_tinfo *targ_info;
1413 struct ahc_tmode_tstate *tstate;
1415 targ_info = ahc_fetch_transinfo(ahc,
1417 devinfo->our_scsiid,
1420 ahc_update_neg_request(ahc, devinfo, tstate,
1421 targ_info, AHC_NEG_IF_NON_ASYNC);
1424 #define AHC_MAX_STEPS 2000
1426 ahc_clear_critical_section(struct ahc_softc *ahc)
1433 if (ahc->num_critical_sections == 0)
1445 seqaddr = ahc_inb(ahc, SEQADDR0)
1446 | (ahc_inb(ahc, SEQADDR1) << 8);
1449 * Seqaddr represents the next instruction to execute,
1450 * so we are really executing the instruction just
1453 cs = ahc->critical_sections;
1454 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1456 if (cs->begin < seqaddr && cs->end >= seqaddr)
1460 if (i == ahc->num_critical_sections)
1463 if (steps > AHC_MAX_STEPS) {
1464 printf("%s: Infinite loop in critical section\n",
1466 ahc_dump_card_state(ahc);
1467 panic("critical section loop");
1471 if (stepping == FALSE) {
1474 * Disable all interrupt sources so that the
1475 * sequencer will not be stuck by a pausing
1476 * interrupt condition while we attempt to
1477 * leave a critical section.
1479 simode0 = ahc_inb(ahc, SIMODE0);
1480 ahc_outb(ahc, SIMODE0, 0);
1481 simode1 = ahc_inb(ahc, SIMODE1);
1482 if ((ahc->features & AHC_DT) != 0)
1484 * On DT class controllers, we
1485 * use the enhanced busfree logic.
1486 * Unfortunately we cannot re-enable
1487 * busfree detection within the
1488 * current connection, so we must
1489 * leave it on while single stepping.
1491 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1493 ahc_outb(ahc, SIMODE1, 0);
1494 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1495 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1498 if ((ahc->features & AHC_DT) != 0) {
1499 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1500 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1502 ahc_outb(ahc, HCNTRL, ahc->unpause);
1503 while (!ahc_is_paused(ahc))
1507 ahc_outb(ahc, SIMODE0, simode0);
1508 ahc_outb(ahc, SIMODE1, simode1);
1509 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1514 * Clear any pending interrupt status.
1517 ahc_clear_intstat(struct ahc_softc *ahc)
1519 /* Clear any interrupt conditions this may have caused */
1520 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1521 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1523 ahc_flush_device_writes(ahc);
1524 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1525 ahc_flush_device_writes(ahc);
1526 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1527 ahc_flush_device_writes(ahc);
1530 /**************************** Debugging Routines ******************************/
1532 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1536 ahc_print_scb(struct scb *scb)
1540 struct hardware_scb *hscb = scb->hscb;
1542 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1548 printf("Shared Data: ");
1549 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1550 printf("%#02x", hscb->shared_data.cdb[i]);
1551 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1552 aic_le32toh(hscb->dataptr),
1553 aic_le32toh(hscb->datacnt),
1554 aic_le32toh(hscb->sgptr),
1556 if (scb->sg_count > 0) {
1557 for (i = 0; i < scb->sg_count; i++) {
1558 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1560 (aic_le32toh(scb->sg_list[i].len) >> 24
1561 & SG_HIGH_ADDR_BITS),
1562 aic_le32toh(scb->sg_list[i].addr),
1563 aic_le32toh(scb->sg_list[i].len));
1568 /************************* Transfer Negotiation *******************************/
1570 * Allocate per target mode instance (ID we respond to as a target)
1571 * transfer negotiation data structures.
1573 static struct ahc_tmode_tstate *
1574 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1576 struct ahc_tmode_tstate *master_tstate;
1577 struct ahc_tmode_tstate *tstate;
1580 master_tstate = ahc->enabled_targets[ahc->our_id];
1581 if (channel == 'B') {
1583 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1585 if (ahc->enabled_targets[scsi_id] != NULL
1586 && ahc->enabled_targets[scsi_id] != master_tstate)
1587 panic("%s: ahc_alloc_tstate - Target already allocated",
1589 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1590 M_DEVBUF, M_NOWAIT);
1595 * If we have allocated a master tstate, copy user settings from
1596 * the master tstate (taken from SRAM or the EEPROM) for this
1597 * channel, but reset our current and goal settings to async/narrow
1598 * until an initiator talks to us.
1600 if (master_tstate != NULL) {
1601 memcpy(tstate, master_tstate, sizeof(*tstate));
1602 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1603 tstate->ultraenb = 0;
1604 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1605 memset(&tstate->transinfo[i].curr, 0,
1606 sizeof(tstate->transinfo[i].curr));
1607 memset(&tstate->transinfo[i].goal, 0,
1608 sizeof(tstate->transinfo[i].goal));
1611 memset(tstate, 0, sizeof(*tstate));
1612 ahc->enabled_targets[scsi_id] = tstate;
1616 #ifdef AHC_TARGET_MODE
1618 * Free per target mode instance (ID we respond to as a target)
1619 * transfer negotiation data structures.
1622 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1624 struct ahc_tmode_tstate *tstate;
1627 * Don't clean up our "master" tstate.
1628 * It has our default user settings.
1630 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1631 || (channel == 'A' && scsi_id == ahc->our_id))
1637 tstate = ahc->enabled_targets[scsi_id];
1639 free(tstate, M_DEVBUF);
1640 ahc->enabled_targets[scsi_id] = NULL;
1645 * Called when we have an active connection to a target on the bus,
1646 * this function finds the nearest syncrate to the input period limited
1647 * by the capabilities of the bus connectivity of and sync settings for
1650 struct ahc_syncrate *
1651 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1652 struct ahc_initiator_tinfo *tinfo,
1653 u_int *period, u_int *ppr_options, role_t role)
1655 struct ahc_transinfo *transinfo;
1658 if ((ahc->features & AHC_ULTRA2) != 0) {
1659 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1660 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1661 maxsync = AHC_SYNCRATE_DT;
1663 maxsync = AHC_SYNCRATE_ULTRA;
1664 /* Can't do DT on an SE bus */
1665 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1667 } else if ((ahc->features & AHC_ULTRA) != 0) {
1668 maxsync = AHC_SYNCRATE_ULTRA;
1670 maxsync = AHC_SYNCRATE_FAST;
1673 * Never allow a value higher than our current goal
1674 * period otherwise we may allow a target initiated
1675 * negotiation to go above the limit as set by the
1676 * user. In the case of an initiator initiated
1677 * sync negotiation, we limit based on the user
1678 * setting. This allows the system to still accept
1679 * incoming negotiations even if target initiated
1680 * negotiation is not performed.
1682 if (role == ROLE_TARGET)
1683 transinfo = &tinfo->user;
1685 transinfo = &tinfo->goal;
1686 *ppr_options &= transinfo->ppr_options;
1687 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1688 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1689 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1691 if (transinfo->period == 0) {
1696 *period = MAX(*period, transinfo->period);
1697 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1701 * Look up the valid period to SCSIRATE conversion in our table.
1702 * Return the period and offset that should be sent to the target
1703 * if this was the beginning of an SDTR.
1705 struct ahc_syncrate *
1706 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1707 u_int *ppr_options, u_int maxsync)
1709 struct ahc_syncrate *syncrate;
1711 if ((ahc->features & AHC_DT) == 0)
1712 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1714 /* Skip all DT only entries if DT is not available */
1715 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1716 && maxsync < AHC_SYNCRATE_ULTRA2)
1717 maxsync = AHC_SYNCRATE_ULTRA2;
1719 for (syncrate = &ahc_syncrates[maxsync];
1720 syncrate->rate != NULL;
1724 * The Ultra2 table doesn't go as low
1725 * as for the Fast/Ultra cards.
1727 if ((ahc->features & AHC_ULTRA2) != 0
1728 && (syncrate->sxfr_u2 == 0))
1731 if (*period <= syncrate->period) {
1733 * When responding to a target that requests
1734 * sync, the requested rate may fall between
1735 * two rates that we can output, but still be
1736 * a rate that we can receive. Because of this,
1737 * we want to respond to the target with
1738 * the same rate that it sent to us even
1739 * if the period we use to send data to it
1740 * is lower. Only lower the response period
1743 if (syncrate == &ahc_syncrates[maxsync])
1744 *period = syncrate->period;
1747 * At some speeds, we only support
1750 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1751 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1757 || (syncrate->rate == NULL)
1758 || ((ahc->features & AHC_ULTRA2) != 0
1759 && (syncrate->sxfr_u2 == 0))) {
1760 /* Use asynchronous transfers. */
1763 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1769 * Convert from an entry in our syncrate table to the SCSI equivalent
1770 * sync "period" factor.
1773 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1775 struct ahc_syncrate *syncrate;
1777 if ((ahc->features & AHC_ULTRA2) != 0)
1778 scsirate &= SXFR_ULTRA2;
1782 syncrate = &ahc_syncrates[maxsync];
1783 while (syncrate->rate != NULL) {
1785 if ((ahc->features & AHC_ULTRA2) != 0) {
1786 if (syncrate->sxfr_u2 == 0)
1788 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1789 return (syncrate->period);
1790 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1791 return (syncrate->period);
1795 return (0); /* async */
1799 * Truncate the given synchronous offset to a value the
1800 * current adapter type and syncrate are capable of.
1803 ahc_validate_offset(struct ahc_softc *ahc,
1804 struct ahc_initiator_tinfo *tinfo,
1805 struct ahc_syncrate *syncrate,
1806 u_int *offset, int wide, role_t role)
1810 /* Limit offset to what we can do */
1811 if (syncrate == NULL) {
1813 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1814 maxoffset = MAX_OFFSET_ULTRA2;
1817 maxoffset = MAX_OFFSET_16BIT;
1819 maxoffset = MAX_OFFSET_8BIT;
1821 *offset = MIN(*offset, maxoffset);
1822 if (tinfo != NULL) {
1823 if (role == ROLE_TARGET)
1824 *offset = MIN(*offset, tinfo->user.offset);
1826 *offset = MIN(*offset, tinfo->goal.offset);
1831 * Truncate the given transfer width parameter to a value the
1832 * current adapter type is capable of.
1835 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1836 u_int *bus_width, role_t role)
1838 switch (*bus_width) {
1840 if (ahc->features & AHC_WIDE) {
1842 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1846 case MSG_EXT_WDTR_BUS_8_BIT:
1847 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1850 if (tinfo != NULL) {
1851 if (role == ROLE_TARGET)
1852 *bus_width = MIN(tinfo->user.width, *bus_width);
1854 *bus_width = MIN(tinfo->goal.width, *bus_width);
1859 * Update the bitmask of targets for which the controller should
1860 * negotiate with at the next convenient oportunity. This currently
1861 * means the next time we send the initial identify messages for
1862 * a new transaction.
1865 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1866 struct ahc_tmode_tstate *tstate,
1867 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1869 u_int auto_negotiate_orig;
1871 auto_negotiate_orig = tstate->auto_negotiate;
1872 if (neg_type == AHC_NEG_ALWAYS) {
1874 * Force our "current" settings to be
1875 * unknown so that unless a bus reset
1876 * occurs the need to renegotiate is
1877 * recorded persistently.
1879 if ((ahc->features & AHC_WIDE) != 0)
1880 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1881 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1882 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1884 if (tinfo->curr.period != tinfo->goal.period
1885 || tinfo->curr.width != tinfo->goal.width
1886 || tinfo->curr.offset != tinfo->goal.offset
1887 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1888 || (neg_type == AHC_NEG_IF_NON_ASYNC
1889 && (tinfo->goal.offset != 0
1890 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1891 || tinfo->goal.ppr_options != 0)))
1892 tstate->auto_negotiate |= devinfo->target_mask;
1894 tstate->auto_negotiate &= ~devinfo->target_mask;
1896 return (auto_negotiate_orig != tstate->auto_negotiate);
1900 * Update the user/goal/curr tables of synchronous negotiation
1901 * parameters as well as, in the case of a current or active update,
1902 * any data structures on the host controller. In the case of an
1903 * active update, the specified target is currently talking to us on
1904 * the bus, so the transfer parameter update must take effect
1908 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1909 struct ahc_syncrate *syncrate, u_int period,
1910 u_int offset, u_int ppr_options, u_int type, int paused)
1912 struct ahc_initiator_tinfo *tinfo;
1913 struct ahc_tmode_tstate *tstate;
1920 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1923 if (syncrate == NULL) {
1928 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1929 devinfo->target, &tstate);
1931 if ((type & AHC_TRANS_USER) != 0) {
1932 tinfo->user.period = period;
1933 tinfo->user.offset = offset;
1934 tinfo->user.ppr_options = ppr_options;
1937 if ((type & AHC_TRANS_GOAL) != 0) {
1938 tinfo->goal.period = period;
1939 tinfo->goal.offset = offset;
1940 tinfo->goal.ppr_options = ppr_options;
1943 old_period = tinfo->curr.period;
1944 old_offset = tinfo->curr.offset;
1945 old_ppr = tinfo->curr.ppr_options;
1947 if ((type & AHC_TRANS_CUR) != 0
1948 && (old_period != period
1949 || old_offset != offset
1950 || old_ppr != ppr_options)) {
1954 scsirate = tinfo->scsirate;
1955 if ((ahc->features & AHC_ULTRA2) != 0) {
1957 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1958 if (syncrate != NULL) {
1959 scsirate |= syncrate->sxfr_u2;
1960 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1961 scsirate |= ENABLE_CRC;
1963 scsirate |= SINGLE_EDGE;
1967 scsirate &= ~(SXFR|SOFS);
1969 * Ensure Ultra mode is set properly for
1972 tstate->ultraenb &= ~devinfo->target_mask;
1973 if (syncrate != NULL) {
1974 if (syncrate->sxfr & ULTRA_SXFR) {
1976 devinfo->target_mask;
1978 scsirate |= syncrate->sxfr & SXFR;
1979 scsirate |= offset & SOFS;
1984 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1985 sxfrctl0 &= ~FAST20;
1986 if (tstate->ultraenb & devinfo->target_mask)
1988 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1992 ahc_outb(ahc, SCSIRATE, scsirate);
1993 if ((ahc->features & AHC_ULTRA2) != 0)
1994 ahc_outb(ahc, SCSIOFFSET, offset);
1997 tinfo->scsirate = scsirate;
1998 tinfo->curr.period = period;
1999 tinfo->curr.offset = offset;
2000 tinfo->curr.ppr_options = ppr_options;
2002 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2003 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2006 printf("%s: target %d synchronous at %sMHz%s, "
2007 "offset = 0x%x\n", ahc_name(ahc),
2008 devinfo->target, syncrate->rate,
2009 (ppr_options & MSG_EXT_PPR_DT_REQ)
2010 ? " DT" : "", offset);
2012 printf("%s: target %d using "
2013 "asynchronous transfers\n",
2014 ahc_name(ahc), devinfo->target);
2019 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2020 tinfo, AHC_NEG_TO_GOAL);
2023 ahc_update_pending_scbs(ahc);
2027 * Update the user/goal/curr tables of wide negotiation
2028 * parameters as well as, in the case of a current or active update,
2029 * any data structures on the host controller. In the case of an
2030 * active update, the specified target is currently talking to us on
2031 * the bus, so the transfer parameter update must take effect
2035 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2036 u_int width, u_int type, int paused)
2038 struct ahc_initiator_tinfo *tinfo;
2039 struct ahc_tmode_tstate *tstate;
2044 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2046 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2047 devinfo->target, &tstate);
2049 if ((type & AHC_TRANS_USER) != 0)
2050 tinfo->user.width = width;
2052 if ((type & AHC_TRANS_GOAL) != 0)
2053 tinfo->goal.width = width;
2055 oldwidth = tinfo->curr.width;
2056 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2060 scsirate = tinfo->scsirate;
2061 scsirate &= ~WIDEXFER;
2062 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2063 scsirate |= WIDEXFER;
2065 tinfo->scsirate = scsirate;
2068 ahc_outb(ahc, SCSIRATE, scsirate);
2070 tinfo->curr.width = width;
2072 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2073 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2075 printf("%s: target %d using %dbit transfers\n",
2076 ahc_name(ahc), devinfo->target,
2077 8 * (0x01 << width));
2081 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2082 tinfo, AHC_NEG_TO_GOAL);
2084 ahc_update_pending_scbs(ahc);
2088 * Update the current state of tagged queuing for a given target.
2091 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2094 ahc_platform_set_tags(ahc, devinfo, alg);
2095 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2096 devinfo->lun, AC_TRANSFER_NEG, &alg);
2100 * When the transfer settings for a connection change, update any
2101 * in-transit SCBs to contain the new data so the hardware will
2102 * be set correctly during future (re)selections.
2105 ahc_update_pending_scbs(struct ahc_softc *ahc)
2107 struct scb *pending_scb;
2108 int pending_scb_count;
2114 * Traverse the pending SCB list and ensure that all of the
2115 * SCBs there have the proper settings.
2117 pending_scb_count = 0;
2118 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2119 struct ahc_devinfo devinfo;
2120 struct hardware_scb *pending_hscb;
2121 struct ahc_initiator_tinfo *tinfo;
2122 struct ahc_tmode_tstate *tstate;
2124 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2125 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2127 devinfo.target, &tstate);
2128 pending_hscb = pending_scb->hscb;
2129 pending_hscb->control &= ~ULTRAENB;
2130 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2131 pending_hscb->control |= ULTRAENB;
2132 pending_hscb->scsirate = tinfo->scsirate;
2133 pending_hscb->scsioffset = tinfo->curr.offset;
2134 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2135 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2136 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2137 pending_hscb->control &= ~MK_MESSAGE;
2139 ahc_sync_scb(ahc, pending_scb,
2140 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2141 pending_scb_count++;
2144 if (pending_scb_count == 0)
2147 if (ahc_is_paused(ahc)) {
2154 saved_scbptr = ahc_inb(ahc, SCBPTR);
2155 /* Ensure that the hscbs down on the card match the new information */
2156 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2157 struct hardware_scb *pending_hscb;
2161 ahc_outb(ahc, SCBPTR, i);
2162 scb_tag = ahc_inb(ahc, SCB_TAG);
2163 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2164 if (pending_scb == NULL)
2167 pending_hscb = pending_scb->hscb;
2168 control = ahc_inb(ahc, SCB_CONTROL);
2169 control &= ~(ULTRAENB|MK_MESSAGE);
2170 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2171 ahc_outb(ahc, SCB_CONTROL, control);
2172 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2173 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2175 ahc_outb(ahc, SCBPTR, saved_scbptr);
2181 /**************************** Pathing Information *****************************/
2183 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2189 if (ahc_inb(ahc, SSTAT0) & TARGET)
2192 role = ROLE_INITIATOR;
2194 if (role == ROLE_TARGET
2195 && (ahc->features & AHC_MULTI_TID) != 0
2196 && (ahc_inb(ahc, SEQ_FLAGS)
2197 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2198 /* We were selected, so pull our id from TARGIDIN */
2199 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2200 } else if ((ahc->features & AHC_ULTRA2) != 0)
2201 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2203 our_id = ahc_inb(ahc, SCSIID) & OID;
2205 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2206 ahc_compile_devinfo(devinfo,
2208 SCSIID_TARGET(ahc, saved_scsiid),
2209 ahc_inb(ahc, SAVED_LUN),
2210 SCSIID_CHANNEL(ahc, saved_scsiid),
2214 struct ahc_phase_table_entry*
2215 ahc_lookup_phase_entry(int phase)
2217 struct ahc_phase_table_entry *entry;
2218 struct ahc_phase_table_entry *last_entry;
2221 * num_phases doesn't include the default entry which
2222 * will be returned if the phase doesn't match.
2224 last_entry = &ahc_phase_table[num_phases];
2225 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2226 if (phase == entry->phase)
2233 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2234 u_int lun, char channel, role_t role)
2236 devinfo->our_scsiid = our_id;
2237 devinfo->target = target;
2239 devinfo->target_offset = target;
2240 devinfo->channel = channel;
2241 devinfo->role = role;
2243 devinfo->target_offset += 8;
2244 devinfo->target_mask = (0x01 << devinfo->target_offset);
2248 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2250 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2251 devinfo->target, devinfo->lun);
2255 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2261 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2262 role = ROLE_INITIATOR;
2263 if ((scb->flags & SCB_TARGET_SCB) != 0)
2265 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2266 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2270 /************************ Message Phase Processing ****************************/
2272 ahc_assert_atn(struct ahc_softc *ahc)
2277 if ((ahc->features & AHC_DT) == 0)
2278 scsisigo |= ahc_inb(ahc, SCSISIGI);
2279 ahc_outb(ahc, SCSISIGO, scsisigo);
2283 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2284 * or enters the initial message out phase, we are interrupted. Fill our
2285 * outgoing message buffer with the appropriate message and beging handing
2286 * the message phase(s) manually.
2289 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2293 * To facilitate adding multiple messages together,
2294 * each routine should increment the index and len
2295 * variables instead of setting them explicitly.
2297 ahc->msgout_index = 0;
2298 ahc->msgout_len = 0;
2300 if ((scb->flags & SCB_DEVICE_RESET) == 0
2301 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2304 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2305 if ((scb->hscb->control & DISCENB) != 0)
2306 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2307 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2310 if ((scb->hscb->control & TAG_ENB) != 0) {
2311 ahc->msgout_buf[ahc->msgout_index++] =
2312 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2313 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2314 ahc->msgout_len += 2;
2318 if (scb->flags & SCB_DEVICE_RESET) {
2319 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2321 ahc_print_path(ahc, scb);
2322 printf("Bus Device Reset Message Sent\n");
2324 * Clear our selection hardware in advance of
2325 * the busfree. We may have an entry in the waiting
2326 * Q for this target, and we don't want to go about
2327 * selecting while we handle the busfree and blow it
2330 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2331 } else if ((scb->flags & SCB_ABORT) != 0) {
2332 if ((scb->hscb->control & TAG_ENB) != 0)
2333 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2335 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2337 ahc_print_path(ahc, scb);
2338 printf("Abort%s Message Sent\n",
2339 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2341 * Clear our selection hardware in advance of
2342 * the busfree. We may have an entry in the waiting
2343 * Q for this target, and we don't want to go about
2344 * selecting while we handle the busfree and blow it
2347 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2348 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2349 ahc_build_transfer_msg(ahc, devinfo);
2351 printf("ahc_intr: AWAITING_MSG for an SCB that "
2352 "does not have a waiting message\n");
2353 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2354 devinfo->target_mask);
2355 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2356 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2357 ahc_inb(ahc, MSG_OUT), scb->flags);
2361 * Clear the MK_MESSAGE flag from the SCB so we aren't
2362 * asked to send this message again.
2364 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2365 scb->hscb->control &= ~MK_MESSAGE;
2366 ahc->msgout_index = 0;
2367 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2371 * Build an appropriate transfer negotiation message for the
2372 * currently active target.
2375 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2378 * We need to initiate transfer negotiations.
2379 * If our current and goal settings are identical,
2380 * we want to renegotiate due to a check condition.
2382 struct ahc_initiator_tinfo *tinfo;
2383 struct ahc_tmode_tstate *tstate;
2384 struct ahc_syncrate *rate;
2392 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2393 devinfo->target, &tstate);
2395 * Filter our period based on the current connection.
2396 * If we can't perform DT transfers on this segment (not in LVD
2397 * mode for instance), then our decision to issue a PPR message
2400 period = tinfo->goal.period;
2401 offset = tinfo->goal.offset;
2402 ppr_options = tinfo->goal.ppr_options;
2403 /* Target initiated PPR is not allowed in the SCSI spec */
2404 if (devinfo->role == ROLE_TARGET)
2406 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2407 &ppr_options, devinfo->role);
2408 dowide = tinfo->curr.width != tinfo->goal.width;
2409 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2411 * Only use PPR if we have options that need it, even if the device
2412 * claims to support it. There might be an expander in the way
2415 doppr = ppr_options != 0;
2417 if (!dowide && !dosync && !doppr) {
2418 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2419 dosync = tinfo->goal.offset != 0;
2422 if (!dowide && !dosync && !doppr) {
2424 * Force async with a WDTR message if we have a wide bus,
2425 * or just issue an SDTR with a 0 offset.
2427 if ((ahc->features & AHC_WIDE) != 0)
2433 ahc_print_devinfo(ahc, devinfo);
2434 printf("Ensuring async\n");
2438 /* Target initiated PPR is not allowed in the SCSI spec */
2439 if (devinfo->role == ROLE_TARGET)
2443 * Both the PPR message and SDTR message require the
2444 * goal syncrate to be limited to what the target device
2445 * is capable of handling (based on whether an LVD->SE
2446 * expander is on the bus), so combine these two cases.
2447 * Regardless, guarantee that if we are using WDTR and SDTR
2448 * messages that WDTR comes first.
2450 if (doppr || (dosync && !dowide)) {
2452 offset = tinfo->goal.offset;
2453 ahc_validate_offset(ahc, tinfo, rate, &offset,
2454 doppr ? tinfo->goal.width
2455 : tinfo->curr.width,
2458 ahc_construct_ppr(ahc, devinfo, period, offset,
2459 tinfo->goal.width, ppr_options);
2461 ahc_construct_sdtr(ahc, devinfo, period, offset);
2464 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2469 * Build a synchronous negotiation message in our message
2470 * buffer based on the input parameters.
2473 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2474 u_int period, u_int offset)
2477 period = AHC_ASYNC_XFER_PERIOD;
2478 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2479 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2481 ahc->msgout_buf[ahc->msgout_index++] = period;
2482 ahc->msgout_buf[ahc->msgout_index++] = offset;
2483 ahc->msgout_len += 5;
2485 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2486 ahc_name(ahc), devinfo->channel, devinfo->target,
2487 devinfo->lun, period, offset);
2492 * Build a wide negotiation message in our message
2493 * buffer based on the input parameters.
2496 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2499 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2500 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2501 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2502 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2503 ahc->msgout_len += 4;
2505 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2506 ahc_name(ahc), devinfo->channel, devinfo->target,
2507 devinfo->lun, bus_width);
2512 * Build a parallel protocol request message in our message
2513 * buffer based on the input parameters.
2516 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2517 u_int period, u_int offset, u_int bus_width,
2521 period = AHC_ASYNC_XFER_PERIOD;
2522 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2523 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2524 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2525 ahc->msgout_buf[ahc->msgout_index++] = period;
2526 ahc->msgout_buf[ahc->msgout_index++] = 0;
2527 ahc->msgout_buf[ahc->msgout_index++] = offset;
2528 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2529 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2530 ahc->msgout_len += 8;
2532 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2533 "offset %x, ppr_options %x\n", ahc_name(ahc),
2534 devinfo->channel, devinfo->target, devinfo->lun,
2535 bus_width, period, offset, ppr_options);
2540 * Clear any active message state.
2543 ahc_clear_msg_state(struct ahc_softc *ahc)
2545 ahc->msgout_len = 0;
2546 ahc->msgin_index = 0;
2547 ahc->msg_type = MSG_TYPE_NONE;
2548 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2550 * The target didn't care to respond to our
2551 * message request, so clear ATN.
2553 ahc_outb(ahc, CLRSINT1, CLRATNO);
2555 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2556 ahc_outb(ahc, SEQ_FLAGS2,
2557 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2561 ahc_handle_proto_violation(struct ahc_softc *ahc)
2563 struct ahc_devinfo devinfo;
2571 ahc_fetch_devinfo(ahc, &devinfo);
2572 scbid = ahc_inb(ahc, SCB_TAG);
2573 scb = ahc_lookup_scb(ahc, scbid);
2574 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2575 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2576 lastphase = ahc_inb(ahc, LASTPHASE);
2577 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2580 * The reconnecting target either did not send an
2581 * identify message, or did, but we didn't find an SCB
2584 ahc_print_devinfo(ahc, &devinfo);
2585 printf("Target did not send an IDENTIFY message. "
2586 "LASTPHASE = 0x%x.\n", lastphase);
2588 } else if (scb == NULL) {
2590 * We don't seem to have an SCB active for this
2591 * transaction. Print an error and reset the bus.
2593 ahc_print_devinfo(ahc, &devinfo);
2594 printf("No SCB found during protocol violation\n");
2595 goto proto_violation_reset;
2597 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2598 if ((seq_flags & NO_CDB_SENT) != 0) {
2599 ahc_print_path(ahc, scb);
2600 printf("No or incomplete CDB sent to device.\n");
2601 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2603 * The target never bothered to provide status to
2604 * us prior to completing the command. Since we don't
2605 * know the disposition of this command, we must attempt
2606 * to abort it. Assert ATN and prepare to send an abort
2609 ahc_print_path(ahc, scb);
2610 printf("Completed command without status.\n");
2612 ahc_print_path(ahc, scb);
2613 printf("Unknown protocol violation.\n");
2614 ahc_dump_card_state(ahc);
2617 if ((lastphase & ~P_DATAIN_DT) == 0
2618 || lastphase == P_COMMAND) {
2619 proto_violation_reset:
2621 * Target either went directly to data/command
2622 * phase or didn't respond to our ATN.
2623 * The only safe thing to do is to blow
2624 * it away with a bus reset.
2626 found = ahc_reset_channel(ahc, 'A', TRUE);
2627 printf("%s: Issued Channel %c Bus Reset. "
2628 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2631 * Leave the selection hardware off in case
2632 * this abort attempt will affect yet to
2635 ahc_outb(ahc, SCSISEQ,
2636 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2637 ahc_assert_atn(ahc);
2638 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2640 ahc_print_devinfo(ahc, &devinfo);
2641 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2642 ahc->msgout_len = 1;
2643 ahc->msgout_index = 0;
2644 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2646 ahc_print_path(ahc, scb);
2647 scb->flags |= SCB_ABORT;
2649 printf("Protocol violation %s. Attempting to abort.\n",
2650 ahc_lookup_phase_entry(curphase)->phasemsg);
2655 * Manual message loop handler.
2658 ahc_handle_message_phase(struct ahc_softc *ahc)
2660 struct ahc_devinfo devinfo;
2664 ahc_fetch_devinfo(ahc, &devinfo);
2665 end_session = FALSE;
2666 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2669 switch (ahc->msg_type) {
2670 case MSG_TYPE_INITIATOR_MSGOUT:
2676 if (ahc->msgout_len == 0)
2677 panic("HOST_MSG_LOOP interrupt with no active message");
2680 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2681 ahc_print_devinfo(ahc, &devinfo);
2682 printf("INITIATOR_MSG_OUT");
2685 phasemis = bus_phase != P_MESGOUT;
2688 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2689 printf(" PHASEMIS %s\n",
2690 ahc_lookup_phase_entry(bus_phase)
2694 if (bus_phase == P_MESGIN) {
2696 * Change gears and see if
2697 * this messages is of interest to
2698 * us or should be passed back to
2701 ahc_outb(ahc, CLRSINT1, CLRATNO);
2702 ahc->send_msg_perror = FALSE;
2703 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2704 ahc->msgin_index = 0;
2711 if (ahc->send_msg_perror) {
2712 ahc_outb(ahc, CLRSINT1, CLRATNO);
2713 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2715 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2716 printf(" byte 0x%x\n", ahc->send_msg_perror);
2718 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2722 msgdone = ahc->msgout_index == ahc->msgout_len;
2725 * The target has requested a retry.
2726 * Re-assert ATN, reset our message index to
2729 ahc->msgout_index = 0;
2730 ahc_assert_atn(ahc);
2733 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2735 /* Last byte is signified by dropping ATN */
2736 ahc_outb(ahc, CLRSINT1, CLRATNO);
2740 * Clear our interrupt status and present
2741 * the next byte on the bus.
2743 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2745 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2746 printf(" byte 0x%x\n",
2747 ahc->msgout_buf[ahc->msgout_index]);
2749 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2752 case MSG_TYPE_INITIATOR_MSGIN:
2758 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2759 ahc_print_devinfo(ahc, &devinfo);
2760 printf("INITIATOR_MSG_IN");
2763 phasemis = bus_phase != P_MESGIN;
2766 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2767 printf(" PHASEMIS %s\n",
2768 ahc_lookup_phase_entry(bus_phase)
2772 ahc->msgin_index = 0;
2773 if (bus_phase == P_MESGOUT
2774 && (ahc->send_msg_perror == TRUE
2775 || (ahc->msgout_len != 0
2776 && ahc->msgout_index == 0))) {
2777 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2784 /* Pull the byte in without acking it */
2785 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2787 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2788 printf(" byte 0x%x\n",
2789 ahc->msgin_buf[ahc->msgin_index]);
2792 message_done = ahc_parse_msg(ahc, &devinfo);
2796 * Clear our incoming message buffer in case there
2797 * is another message following this one.
2799 ahc->msgin_index = 0;
2802 * If this message illicited a response,
2803 * assert ATN so the target takes us to the
2804 * message out phase.
2806 if (ahc->msgout_len != 0) {
2808 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2809 ahc_print_devinfo(ahc, &devinfo);
2810 printf("Asserting ATN for response\n");
2813 ahc_assert_atn(ahc);
2818 if (message_done == MSGLOOP_TERMINATED) {
2822 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2823 ahc_inb(ahc, SCSIDATL);
2827 case MSG_TYPE_TARGET_MSGIN:
2831 if (ahc->msgout_len == 0)
2832 panic("Target MSGIN with no active message");
2835 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2836 ahc_print_devinfo(ahc, &devinfo);
2837 printf("TARGET_MSG_IN");
2842 * If we interrupted a mesgout session, the initiator
2843 * will not know this until our first REQ. So, we
2844 * only honor mesgout requests after we've sent our
2847 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2848 && ahc->msgout_index > 0) {
2851 * Change gears and see if this messages is
2852 * of interest to us or should be passed back
2856 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2857 printf(" Honoring ATN Request.\n");
2859 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2862 * Disable SCSI Programmed I/O during the
2863 * phase change so as to avoid phantom REQs.
2865 ahc_outb(ahc, SXFRCTL0,
2866 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2869 * Since SPIORDY asserts when ACK is asserted
2870 * for P_MSGOUT, and SPIORDY's assertion triggered
2871 * our entry into this routine, wait for ACK to
2872 * *de-assert* before changing phases.
2874 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2877 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2880 * All phase line changes require a bus
2881 * settle delay before REQ is asserted.
2882 * [SCSI SPI4 10.7.1]
2884 ahc_flush_device_writes(ahc);
2885 aic_delay(AHC_BUSSETTLE_DELAY);
2887 ahc->msgin_index = 0;
2888 /* Enable SCSI Programmed I/O to REQ for first byte */
2889 ahc_outb(ahc, SXFRCTL0,
2890 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2894 msgdone = ahc->msgout_index == ahc->msgout_len;
2896 ahc_outb(ahc, SXFRCTL0,
2897 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2903 * Present the next byte on the bus.
2906 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2907 printf(" byte 0x%x\n",
2908 ahc->msgout_buf[ahc->msgout_index]);
2910 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2911 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2914 case MSG_TYPE_TARGET_MSGOUT:
2920 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2921 ahc_print_devinfo(ahc, &devinfo);
2922 printf("TARGET_MSG_OUT");
2926 * The initiator signals that this is
2927 * the last byte by dropping ATN.
2929 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2932 * Read the latched byte, but turn off SPIOEN first
2933 * so that we don't inadvertently cause a REQ for the
2936 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2937 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2940 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2941 printf(" byte 0x%x\n",
2942 ahc->msgin_buf[ahc->msgin_index]);
2945 msgdone = ahc_parse_msg(ahc, &devinfo);
2946 if (msgdone == MSGLOOP_TERMINATED) {
2948 * The message is *really* done in that it caused
2949 * us to go to bus free. The sequencer has already
2950 * been reset at this point, so pull the ejection
2959 * XXX Read spec about initiator dropping ATN too soon
2960 * and use msgdone to detect it.
2962 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2963 ahc->msgin_index = 0;
2966 * If this message illicited a response, transition
2967 * to the Message in phase and send it.
2969 if (ahc->msgout_len != 0) {
2971 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2972 ahc_print_devinfo(ahc, &devinfo);
2973 printf(" preparing response.\n");
2976 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2979 * All phase line changes require a bus
2980 * settle delay before REQ is asserted.
2981 * [SCSI SPI4 10.7.1] When transitioning
2982 * from an OUT to an IN phase, we must
2983 * also wait a data release delay to allow
2984 * the initiator time to release the data
2985 * lines. [SCSI SPI4 10.12]
2987 ahc_flush_device_writes(ahc);
2988 aic_delay(AHC_BUSSETTLE_DELAY
2989 + AHC_DATARELEASE_DELAY);
2992 * Enable SCSI Programmed I/O. This will
2993 * immediately cause SPIORDY to assert,
2994 * and the sequencer will call our message
2997 ahc_outb(ahc, SXFRCTL0,
2998 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2999 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3000 ahc->msgin_index = 0;
3008 /* Ask for the next byte. */
3009 ahc_outb(ahc, SXFRCTL0,
3010 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3016 panic("Unknown REQINIT message type");
3020 ahc_clear_msg_state(ahc);
3021 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3023 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3027 * See if we sent a particular extended message to the target.
3028 * If "full" is true, return true only if the target saw the full
3029 * message. If "full" is false, return true if the target saw at
3030 * least the first byte of the message.
3033 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3041 while (index < ahc->msgout_len) {
3042 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3045 end_index = index + 1 + ahc->msgout_buf[index + 1];
3046 if (ahc->msgout_buf[index+2] == msgval
3047 && type == AHCMSG_EXT) {
3050 if (ahc->msgout_index > end_index)
3052 } else if (ahc->msgout_index > index)
3056 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3057 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3059 /* Skip tag type and tag id or residue param*/
3062 /* Single byte message */
3063 if (type == AHCMSG_1B
3064 && ahc->msgout_buf[index] == msgval
3065 && ahc->msgout_index > index)
3077 * Wait for a complete incoming message, parse it, and respond accordingly.
3080 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3082 struct ahc_initiator_tinfo *tinfo;
3083 struct ahc_tmode_tstate *tstate;
3087 u_int targ_scsirate;
3089 done = MSGLOOP_IN_PROG;
3092 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3093 devinfo->target, &tstate);
3094 targ_scsirate = tinfo->scsirate;
3097 * Parse as much of the message as is available,
3098 * rejecting it if we don't support it. When
3099 * the entire message is available and has been
3100 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3101 * that we have parsed an entire message.
3103 * In the case of extended messages, we accept the length
3104 * byte outright and perform more checking once we know the
3105 * extended message type.
3107 switch (ahc->msgin_buf[0]) {
3108 case MSG_DISCONNECT:
3109 case MSG_SAVEDATAPOINTER:
3110 case MSG_CMDCOMPLETE:
3111 case MSG_RESTOREPOINTERS:
3112 case MSG_IGN_WIDE_RESIDUE:
3114 * End our message loop as these are messages
3115 * the sequencer handles on its own.
3117 done = MSGLOOP_TERMINATED;
3119 case MSG_MESSAGE_REJECT:
3120 response = ahc_handle_msg_reject(ahc, devinfo);
3123 done = MSGLOOP_MSGCOMPLETE;
3127 /* Wait for enough of the message to begin validation */
3128 if (ahc->msgin_index < 2)
3130 switch (ahc->msgin_buf[2]) {
3133 struct ahc_syncrate *syncrate;
3139 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3145 * Wait until we have both args before validating
3146 * and acting on this message.
3148 * Add one to MSG_EXT_SDTR_LEN to account for
3149 * the extended message preamble.
3151 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3154 period = ahc->msgin_buf[3];
3156 saved_offset = offset = ahc->msgin_buf[4];
3157 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3160 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3161 targ_scsirate & WIDEXFER,
3164 printf("(%s:%c:%d:%d): Received "
3165 "SDTR period %x, offset %x\n\t"
3166 "Filtered to period %x, offset %x\n",
3167 ahc_name(ahc), devinfo->channel,
3168 devinfo->target, devinfo->lun,
3169 ahc->msgin_buf[3], saved_offset,
3172 ahc_set_syncrate(ahc, devinfo,
3174 offset, ppr_options,
3175 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3179 * See if we initiated Sync Negotiation
3180 * and didn't have to fall down to async
3183 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3185 if (saved_offset != offset) {
3186 /* Went too low - force async */
3191 * Send our own SDTR in reply
3194 && devinfo->role == ROLE_INITIATOR) {
3195 printf("(%s:%c:%d:%d): Target "
3197 ahc_name(ahc), devinfo->channel,
3198 devinfo->target, devinfo->lun);
3200 ahc->msgout_index = 0;
3201 ahc->msgout_len = 0;
3202 ahc_construct_sdtr(ahc, devinfo,
3204 ahc->msgout_index = 0;
3207 done = MSGLOOP_MSGCOMPLETE;
3214 u_int sending_reply;
3216 sending_reply = FALSE;
3217 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3223 * Wait until we have our arg before validating
3224 * and acting on this message.
3226 * Add one to MSG_EXT_WDTR_LEN to account for
3227 * the extended message preamble.
3229 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3232 bus_width = ahc->msgin_buf[3];
3233 saved_width = bus_width;
3234 ahc_validate_width(ahc, tinfo, &bus_width,
3237 printf("(%s:%c:%d:%d): Received WDTR "
3238 "%x filtered to %x\n",
3239 ahc_name(ahc), devinfo->channel,
3240 devinfo->target, devinfo->lun,
3241 saved_width, bus_width);
3244 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3246 * Don't send a WDTR back to the
3247 * target, since we asked first.
3248 * If the width went higher than our
3249 * request, reject it.
3251 if (saved_width > bus_width) {
3253 printf("(%s:%c:%d:%d): requested %dBit "
3254 "transfers. Rejecting...\n",
3255 ahc_name(ahc), devinfo->channel,
3256 devinfo->target, devinfo->lun,
3257 8 * (0x01 << bus_width));
3262 * Send our own WDTR in reply
3265 && devinfo->role == ROLE_INITIATOR) {
3266 printf("(%s:%c:%d:%d): Target "
3268 ahc_name(ahc), devinfo->channel,
3269 devinfo->target, devinfo->lun);
3271 ahc->msgout_index = 0;
3272 ahc->msgout_len = 0;
3273 ahc_construct_wdtr(ahc, devinfo, bus_width);
3274 ahc->msgout_index = 0;
3276 sending_reply = TRUE;
3279 * After a wide message, we are async, but
3280 * some devices don't seem to honor this portion
3281 * of the spec. Force a renegotiation of the
3282 * sync component of our transfer agreement even
3283 * if our goal is async. By updating our width
3284 * after forcing the negotiation, we avoid
3285 * renegotiating for width.
3287 ahc_update_neg_request(ahc, devinfo, tstate,
3288 tinfo, AHC_NEG_ALWAYS);
3289 ahc_set_width(ahc, devinfo, bus_width,
3290 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3292 if (sending_reply == FALSE && reject == FALSE) {
3295 * We will always have an SDTR to send.
3297 ahc->msgout_index = 0;
3298 ahc->msgout_len = 0;
3299 ahc_build_transfer_msg(ahc, devinfo);
3300 ahc->msgout_index = 0;
3303 done = MSGLOOP_MSGCOMPLETE;
3308 struct ahc_syncrate *syncrate;
3315 u_int saved_ppr_options;
3317 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3323 * Wait until we have all args before validating
3324 * and acting on this message.
3326 * Add one to MSG_EXT_PPR_LEN to account for
3327 * the extended message preamble.
3329 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3332 period = ahc->msgin_buf[3];
3333 offset = ahc->msgin_buf[5];
3334 bus_width = ahc->msgin_buf[6];
3335 saved_width = bus_width;
3336 ppr_options = ahc->msgin_buf[7];
3338 * According to the spec, a DT only
3339 * period factor with no DT option
3340 * set implies async.
3342 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3345 saved_ppr_options = ppr_options;
3346 saved_offset = offset;
3349 * Mask out any options we don't support
3350 * on any controller. Transfer options are
3351 * only available if we are negotiating wide.
3353 ppr_options &= MSG_EXT_PPR_DT_REQ;
3357 ahc_validate_width(ahc, tinfo, &bus_width,
3359 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3362 ahc_validate_offset(ahc, tinfo, syncrate,
3366 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3368 * If we are unable to do any of the
3369 * requested options (we went too low),
3370 * then we'll have to reject the message.
3372 if (saved_width > bus_width
3373 || saved_offset != offset
3374 || saved_ppr_options != ppr_options) {
3383 if (devinfo->role != ROLE_TARGET)
3384 printf("(%s:%c:%d:%d): Target "
3386 ahc_name(ahc), devinfo->channel,
3387 devinfo->target, devinfo->lun);
3389 printf("(%s:%c:%d:%d): Initiator "
3391 ahc_name(ahc), devinfo->channel,
3392 devinfo->target, devinfo->lun);
3393 ahc->msgout_index = 0;
3394 ahc->msgout_len = 0;
3395 ahc_construct_ppr(ahc, devinfo, period, offset,
3396 bus_width, ppr_options);
3397 ahc->msgout_index = 0;
3401 printf("(%s:%c:%d:%d): Received PPR width %x, "
3402 "period %x, offset %x,options %x\n"
3403 "\tFiltered to width %x, period %x, "
3404 "offset %x, options %x\n",
3405 ahc_name(ahc), devinfo->channel,
3406 devinfo->target, devinfo->lun,
3407 saved_width, ahc->msgin_buf[3],
3408 saved_offset, saved_ppr_options,
3409 bus_width, period, offset, ppr_options);
3411 ahc_set_width(ahc, devinfo, bus_width,
3412 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3414 ahc_set_syncrate(ahc, devinfo,
3416 offset, ppr_options,
3417 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3419 done = MSGLOOP_MSGCOMPLETE;
3423 /* Unknown extended message. Reject it. */
3429 #ifdef AHC_TARGET_MODE
3430 case MSG_BUS_DEV_RESET:
3431 ahc_handle_devreset(ahc, devinfo,
3433 "Bus Device Reset Received",
3434 /*verbose_level*/0);
3436 done = MSGLOOP_TERMINATED;
3440 case MSG_CLEAR_QUEUE:
3444 /* Target mode messages */
3445 if (devinfo->role != ROLE_TARGET) {
3449 tag = SCB_LIST_NULL;
3450 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3451 tag = ahc_inb(ahc, INITIATOR_TAG);
3452 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3453 devinfo->lun, tag, ROLE_TARGET,
3456 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3457 if (tstate != NULL) {
3458 struct ahc_tmode_lstate* lstate;
3460 lstate = tstate->enabled_luns[devinfo->lun];
3461 if (lstate != NULL) {
3462 ahc_queue_lstate_event(ahc, lstate,
3463 devinfo->our_scsiid,
3466 ahc_send_lstate_events(ahc, lstate);
3470 done = MSGLOOP_TERMINATED;
3474 case MSG_TERM_IO_PROC:
3482 * Setup to reject the message.
3484 ahc->msgout_index = 0;
3485 ahc->msgout_len = 1;
3486 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3487 done = MSGLOOP_MSGCOMPLETE;
3491 if (done != MSGLOOP_IN_PROG && !response)
3492 /* Clear the outgoing message buffer */
3493 ahc->msgout_len = 0;
3499 * Process a message reject message.
3502 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3505 * What we care about here is if we had an
3506 * outstanding SDTR or WDTR message for this
3507 * target. If we did, this is a signal that
3508 * the target is refusing negotiation.
3511 struct ahc_initiator_tinfo *tinfo;
3512 struct ahc_tmode_tstate *tstate;
3517 scb_index = ahc_inb(ahc, SCB_TAG);
3518 scb = ahc_lookup_scb(ahc, scb_index);
3519 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3520 devinfo->our_scsiid,
3521 devinfo->target, &tstate);
3522 /* Might be necessary */
3523 last_msg = ahc_inb(ahc, LAST_MSG);
3525 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3527 * Target does not support the PPR message.
3528 * Attempt to negotiate SPI-2 style.
3531 printf("(%s:%c:%d:%d): PPR Rejected. "
3532 "Trying WDTR/SDTR\n",
3533 ahc_name(ahc), devinfo->channel,
3534 devinfo->target, devinfo->lun);
3536 tinfo->goal.ppr_options = 0;
3537 tinfo->curr.transport_version = 2;
3538 tinfo->goal.transport_version = 2;
3539 ahc->msgout_index = 0;
3540 ahc->msgout_len = 0;
3541 ahc_build_transfer_msg(ahc, devinfo);
3542 ahc->msgout_index = 0;
3544 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3546 /* note 8bit xfers */
3547 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3548 "8bit transfers\n", ahc_name(ahc),
3549 devinfo->channel, devinfo->target, devinfo->lun);
3550 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3551 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3554 * No need to clear the sync rate. If the target
3555 * did not accept the command, our syncrate is
3556 * unaffected. If the target started the negotiation,
3557 * but rejected our response, we already cleared the
3558 * sync rate before sending our WDTR.
3560 if (tinfo->goal.offset != tinfo->curr.offset) {
3562 /* Start the sync negotiation */
3563 ahc->msgout_index = 0;
3564 ahc->msgout_len = 0;
3565 ahc_build_transfer_msg(ahc, devinfo);
3566 ahc->msgout_index = 0;
3569 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3570 /* note asynch xfers and clear flag */
3571 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3572 /*offset*/0, /*ppr_options*/0,
3573 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3575 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3576 "Using asynchronous transfers\n",
3577 ahc_name(ahc), devinfo->channel,
3578 devinfo->target, devinfo->lun);
3579 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3583 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3585 if (tag_type == MSG_SIMPLE_TASK) {
3586 printf("(%s:%c:%d:%d): refuses tagged commands. "
3587 "Performing non-tagged I/O\n", ahc_name(ahc),
3588 devinfo->channel, devinfo->target, devinfo->lun);
3589 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3592 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3593 "Performing simple queue tagged I/O only\n",
3594 ahc_name(ahc), devinfo->channel, devinfo->target,
3595 devinfo->lun, tag_type == MSG_ORDERED_TASK
3596 ? "ordered" : "head of queue");
3597 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3602 * Resend the identify for this CCB as the target
3603 * may believe that the selection is invalid otherwise.
3605 ahc_outb(ahc, SCB_CONTROL,
3606 ahc_inb(ahc, SCB_CONTROL) & mask);
3607 scb->hscb->control &= mask;
3608 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3609 /*type*/MSG_SIMPLE_TASK);
3610 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3611 ahc_assert_atn(ahc);
3614 * This transaction is now at the head of
3615 * the untagged queue for this target.
3617 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3618 struct scb_tailq *untagged_q;
3621 &(ahc->untagged_queues[devinfo->target_offset]);
3622 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3623 scb->flags |= SCB_UNTAGGEDQ;
3625 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3629 * Requeue all tagged commands for this target
3630 * currently in our posession so they can be
3631 * converted to untagged commands.
3633 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3634 SCB_GET_CHANNEL(ahc, scb),
3635 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3636 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3640 * Otherwise, we ignore it.
3642 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3643 ahc_name(ahc), devinfo->channel, devinfo->target,
3650 * Process an ingnore wide residue message.
3653 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3658 scb_index = ahc_inb(ahc, SCB_TAG);
3659 scb = ahc_lookup_scb(ahc, scb_index);
3661 * XXX Actually check data direction in the sequencer?
3662 * Perhaps add datadir to some spare bits in the hscb?
3664 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3665 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3667 * Ignore the message if we haven't
3668 * seen an appropriate data phase yet.
3672 * If the residual occurred on the last
3673 * transfer and the transfer request was
3674 * expected to end on an odd count, do
3675 * nothing. Otherwise, subtract a byte
3676 * and update the residual count accordingly.
3680 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3681 if ((sgptr & SG_LIST_NULL) != 0
3682 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3684 * If the residual occurred on the last
3685 * transfer and the transfer request was
3686 * expected to end on an odd count, do
3690 struct ahc_dma_seg *sg;
3695 /* Pull in all of the sgptr */
3696 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3697 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3699 if ((sgptr & SG_LIST_NULL) != 0) {
3701 * The residual data count is not updated
3702 * for the command run to completion case.
3703 * Explicitly zero the count.
3705 data_cnt &= ~AHC_SG_LEN_MASK;
3708 data_addr = ahc_inl(ahc, SHADDR);
3712 sgptr &= SG_PTR_MASK;
3714 sg = ahc_sg_bus_to_virt(scb, sgptr);
3717 * The residual sg ptr points to the next S/G
3718 * to load so we must go back one.
3721 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3722 if (sg != scb->sg_list
3723 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3726 sglen = aic_le32toh(sg->len);
3728 * Preserve High Address and SG_LIST bits
3729 * while setting the count to 1.
3731 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3732 data_addr = aic_le32toh(sg->addr)
3733 + (sglen & AHC_SG_LEN_MASK) - 1;
3736 * Increment sg so it points to the
3740 sgptr = ahc_sg_virt_to_bus(scb, sg);
3742 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3743 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3745 * Toggle the "oddness" of the transfer length
3746 * to handle this mid-transfer ignore wide
3747 * residue. This ensures that the oddness is
3748 * correct for subsequent data transfers.
3750 ahc_outb(ahc, SCB_LUN,
3751 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3758 * Reinitialize the data pointers for the active transfer
3759 * based on its current residual.
3762 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3765 struct ahc_dma_seg *sg;
3771 scb_index = ahc_inb(ahc, SCB_TAG);
3772 scb = ahc_lookup_scb(ahc, scb_index);
3773 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3774 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3775 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3776 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3778 sgptr &= SG_PTR_MASK;
3779 sg = ahc_sg_bus_to_virt(scb, sgptr);
3781 /* The residual sg_ptr always points to the next sg */
3784 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3785 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3786 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3788 dataptr = aic_le32toh(sg->addr)
3789 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3791 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3794 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3795 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3796 ahc_outb(ahc, HADDR,
3797 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3798 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3800 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3801 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3802 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3803 ahc_outb(ahc, HADDR, dataptr);
3804 ahc_outb(ahc, HCNT + 2, resid >> 16);
3805 ahc_outb(ahc, HCNT + 1, resid >> 8);
3806 ahc_outb(ahc, HCNT, resid);
3807 if ((ahc->features & AHC_ULTRA2) == 0) {
3808 ahc_outb(ahc, STCNT + 2, resid >> 16);
3809 ahc_outb(ahc, STCNT + 1, resid >> 8);
3810 ahc_outb(ahc, STCNT, resid);
3815 * Handle the effects of issuing a bus device reset message.
3818 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3819 cam_status status, char *message, int verbose_level)
3821 #ifdef AHC_TARGET_MODE
3822 struct ahc_tmode_tstate* tstate;
3827 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3828 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3831 #ifdef AHC_TARGET_MODE
3833 * Send an immediate notify ccb to all target mord peripheral
3834 * drivers affected by this action.
3836 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3837 if (tstate != NULL) {
3838 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3839 struct ahc_tmode_lstate* lstate;
3841 lstate = tstate->enabled_luns[lun];
3845 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3846 MSG_BUS_DEV_RESET, /*arg*/0);
3847 ahc_send_lstate_events(ahc, lstate);
3853 * Go back to async/narrow transfers and renegotiate.
3855 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3856 AHC_TRANS_CUR, /*paused*/TRUE);
3857 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3858 /*period*/0, /*offset*/0, /*ppr_options*/0,
3859 AHC_TRANS_CUR, /*paused*/TRUE);
3861 if (status != CAM_SEL_TIMEOUT)
3862 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3863 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3866 && (verbose_level <= bootverbose))
3867 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3868 message, devinfo->channel, devinfo->target, found);
3871 #ifdef AHC_TARGET_MODE
3873 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3878 * To facilitate adding multiple messages together,
3879 * each routine should increment the index and len
3880 * variables instead of setting them explicitly.
3882 ahc->msgout_index = 0;
3883 ahc->msgout_len = 0;
3885 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3886 ahc_build_transfer_msg(ahc, devinfo);
3888 panic("ahc_intr: AWAITING target message with no message");
3890 ahc->msgout_index = 0;
3891 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3894 /**************************** Initialization **********************************/
3896 * Allocate a controller structure for a new device
3897 * and perform initial initializion.
3900 ahc_alloc(void *platform_arg, char *name)
3902 struct ahc_softc *ahc;
3906 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3908 printf("aic7xxx: cannot malloc softc!\n");
3909 free(name, M_DEVBUF);
3913 ahc = device_get_softc((device_t)platform_arg);
3915 memset(ahc, 0, sizeof(*ahc));
3916 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3917 M_DEVBUF, M_NOWAIT);
3918 if (ahc->seep_config == NULL) {
3920 free(ahc, M_DEVBUF);
3922 free(name, M_DEVBUF);
3925 LIST_INIT(&ahc->pending_scbs);
3926 LIST_INIT(&ahc->timedout_scbs);
3927 /* We don't know our unit number until the OSM sets it */
3930 ahc->description = NULL;
3932 ahc->channel_b = 'B';
3933 ahc->chip = AHC_NONE;
3934 ahc->features = AHC_FENONE;
3935 ahc->bugs = AHC_BUGNONE;
3936 ahc->flags = AHC_FNONE;
3938 * Default to all error reporting enabled with the
3939 * sequencer operating at its fastest speed.
3940 * The bus attach code may modify this.
3942 ahc->seqctl = FASTMODE;
3944 for (i = 0; i < AHC_NUM_TARGETS; i++)
3945 TAILQ_INIT(&ahc->untagged_queues[i]);
3946 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3955 ahc_softc_init(struct ahc_softc *ahc)
3958 /* The IRQMS bit is only valid on VL and EISA chips */
3959 if ((ahc->chip & AHC_PCI) == 0)
3960 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3963 ahc->pause = ahc->unpause | PAUSE;
3964 /* XXX The shared scb data stuff should be deprecated */
3965 if (ahc->scb_data == NULL) {
3966 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3967 M_DEVBUF, M_NOWAIT);
3968 if (ahc->scb_data == NULL)
3970 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3977 ahc_softc_insert(struct ahc_softc *ahc)
3979 struct ahc_softc *list_ahc;
3981 #if AIC_PCI_CONFIG > 0
3983 * Second Function PCI devices need to inherit some
3984 * settings from function 0.
3986 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3987 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3988 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3989 aic_dev_softc_t list_pci;
3990 aic_dev_softc_t pci;
3992 list_pci = list_ahc->dev_softc;
3993 pci = ahc->dev_softc;
3994 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3995 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3996 struct ahc_softc *master;
3997 struct ahc_softc *slave;
3999 if (aic_get_pci_function(list_pci) == 0) {
4006 slave->flags &= ~AHC_BIOS_ENABLED;
4008 master->flags & AHC_BIOS_ENABLED;
4009 slave->flags &= ~AHC_PRIMARY_CHANNEL;
4011 master->flags & AHC_PRIMARY_CHANNEL;
4019 * Insertion sort into our list of softcs.
4021 list_ahc = TAILQ_FIRST(&ahc_tailq);
4022 while (list_ahc != NULL
4023 && ahc_softc_comp(ahc, list_ahc) <= 0)
4024 list_ahc = TAILQ_NEXT(list_ahc, links);
4025 if (list_ahc != NULL)
4026 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4028 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4033 ahc_set_unit(struct ahc_softc *ahc, int unit)
4039 ahc_set_name(struct ahc_softc *ahc, char *name)
4041 if (ahc->name != NULL)
4042 free(ahc->name, M_DEVBUF);
4047 ahc_free(struct ahc_softc *ahc)
4051 ahc_terminate_recovery_thread(ahc);
4052 switch (ahc->init_level) {
4058 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4059 ahc->shared_data_dmamap);
4062 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4063 ahc->shared_data_dmamap);
4066 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4069 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4077 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4079 ahc_platform_free(ahc);
4080 ahc_fini_scbdata(ahc);
4081 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4082 struct ahc_tmode_tstate *tstate;
4084 tstate = ahc->enabled_targets[i];
4085 if (tstate != NULL) {
4086 #ifdef AHC_TARGET_MODE
4089 for (j = 0; j < AHC_NUM_LUNS; j++) {
4090 struct ahc_tmode_lstate *lstate;
4092 lstate = tstate->enabled_luns[j];
4093 if (lstate != NULL) {
4094 xpt_free_path(lstate->path);
4095 free(lstate, M_DEVBUF);
4099 free(tstate, M_DEVBUF);
4102 #ifdef AHC_TARGET_MODE
4103 if (ahc->black_hole != NULL) {
4104 xpt_free_path(ahc->black_hole->path);
4105 free(ahc->black_hole, M_DEVBUF);
4108 if (ahc->name != NULL)
4109 free(ahc->name, M_DEVBUF);
4110 if (ahc->seep_config != NULL)
4111 free(ahc->seep_config, M_DEVBUF);
4113 free(ahc, M_DEVBUF);
4119 ahc_shutdown(void *arg)
4121 struct ahc_softc *ahc;
4124 ahc = (struct ahc_softc *)arg;
4126 /* This will reset most registers to 0, but not all */
4127 ahc_reset(ahc, /*reinit*/FALSE);
4128 ahc_outb(ahc, SCSISEQ, 0);
4129 ahc_outb(ahc, SXFRCTL0, 0);
4130 ahc_outb(ahc, DSPCISTATUS, 0);
4132 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4133 ahc_outb(ahc, i, 0);
4137 * Reset the controller and record some information about it
4138 * that is only available just after a reset. If "reinit" is
4139 * non-zero, this reset occured after initial configuration
4140 * and the caller requests that the chip be fully reinitialized
4141 * to a runable state. Chip interrupts are *not* enabled after
4142 * a reinitialization. The caller must enable interrupts via
4143 * ahc_intr_enable().
4146 ahc_reset(struct ahc_softc *ahc, int reinit)
4149 u_int sxfrctl1_a, sxfrctl1_b;
4154 * Preserve the value of the SXFRCTL1 register for all channels.
4155 * It contains settings that affect termination and we don't want
4156 * to disturb the integrity of the bus.
4160 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4164 * Save channel B's settings in case this chip
4165 * is setup for TWIN channel operation.
4167 sblkctl = ahc_inb(ahc, SBLKCTL);
4168 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4169 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4170 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4172 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4174 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4177 * Ensure that the reset has finished. We delay 1000us
4178 * prior to reading the register to make sure the chip
4179 * has sufficiently completed its reset to handle register
4185 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4188 printf("%s: WARNING - Failed chip reset! "
4189 "Trying to initialize anyway.\n", ahc_name(ahc));
4191 ahc_outb(ahc, HCNTRL, ahc->pause);
4193 /* Determine channel configuration */
4194 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4195 /* No Twin Channel PCI cards */
4196 if ((ahc->chip & AHC_PCI) != 0)
4197 sblkctl &= ~SELBUSB;
4200 /* Single Narrow Channel */
4204 ahc->features |= AHC_WIDE;
4208 ahc->features |= AHC_TWIN;
4211 printf(" Unsupported adapter type. Ignoring\n");
4218 * We must always initialize STPWEN to 1 before we
4219 * restore the saved values. STPWEN is initialized
4220 * to a tri-state condition which can only be cleared
4223 if ((ahc->features & AHC_TWIN) != 0) {
4226 sblkctl = ahc_inb(ahc, SBLKCTL);
4227 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4228 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4229 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4231 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4236 * If a recovery action has forced a chip reset,
4237 * re-initialize the chip to our liking.
4239 error = ahc->bus_chip_init(ahc);
4249 * Determine the number of SCBs available on the controller
4252 ahc_probe_scbs(struct ahc_softc *ahc) {
4255 for (i = 0; i < AHC_SCB_MAX; i++) {
4257 ahc_outb(ahc, SCBPTR, i);
4258 ahc_outb(ahc, SCB_BASE, i);
4259 if (ahc_inb(ahc, SCB_BASE) != i)
4261 ahc_outb(ahc, SCBPTR, 0);
4262 if (ahc_inb(ahc, SCB_BASE) != 0)
4269 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4273 baddr = (bus_addr_t *)arg;
4274 *baddr = segs->ds_addr;
4278 ahc_build_free_scb_list(struct ahc_softc *ahc)
4284 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4287 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4290 ahc_outb(ahc, SCBPTR, i);
4293 * Touch all SCB bytes to avoid parity errors
4294 * should one of our debugging routines read
4295 * an otherwise uninitiatlized byte.
4297 for (j = 0; j < scbsize; j++)
4298 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4300 /* Clear the control byte. */
4301 ahc_outb(ahc, SCB_CONTROL, 0);
4303 /* Set the next pointer */
4304 if ((ahc->flags & AHC_PAGESCBS) != 0)
4305 ahc_outb(ahc, SCB_NEXT, i+1);
4307 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4309 /* Make the tag number, SCSIID, and lun invalid */
4310 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4311 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4312 ahc_outb(ahc, SCB_LUN, 0xFF);
4315 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4316 /* SCB 0 heads the free list. */
4317 ahc_outb(ahc, FREE_SCBH, 0);
4320 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4323 /* Make sure that the last SCB terminates the free list */
4324 ahc_outb(ahc, SCBPTR, i-1);
4325 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4329 ahc_init_scbdata(struct ahc_softc *ahc)
4331 struct scb_data *scb_data;
4333 scb_data = ahc->scb_data;
4334 SLIST_INIT(&scb_data->free_scbs);
4335 SLIST_INIT(&scb_data->sg_maps);
4337 /* Allocate SCB resources */
4338 scb_data->scbarray =
4339 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4340 M_DEVBUF, M_NOWAIT);
4341 if (scb_data->scbarray == NULL)
4343 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4345 /* Determine the number of hardware SCBs and initialize them */
4347 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4348 if (ahc->scb_data->maxhscbs == 0) {
4349 printf("%s: No SCB space found\n", ahc_name(ahc));
4354 * Create our DMA tags. These tags define the kinds of device
4355 * accessible memory allocations and memory mappings we will
4356 * need to perform during normal operation.
4358 * Unless we need to further restrict the allocation, we rely
4359 * on the restrictions of the parent dmat, hence the common
4360 * use of MAXADDR and MAXSIZE.
4363 /* DMA tag for our hardware scb structures */
4364 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4365 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4366 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4367 /*highaddr*/BUS_SPACE_MAXADDR,
4368 /*filter*/NULL, /*filterarg*/NULL,
4369 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4371 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4372 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4376 scb_data->init_level++;
4378 /* Allocation for our hscbs */
4379 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4380 (void **)&scb_data->hscbs,
4381 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4382 &scb_data->hscb_dmamap) != 0) {
4386 scb_data->init_level++;
4388 /* And permanently map them */
4389 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4391 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4392 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4394 scb_data->init_level++;
4396 /* DMA tag for our sense buffers */
4397 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4398 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4399 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4400 /*highaddr*/BUS_SPACE_MAXADDR,
4401 /*filter*/NULL, /*filterarg*/NULL,
4402 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4404 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4405 /*flags*/0, &scb_data->sense_dmat) != 0) {
4409 scb_data->init_level++;
4412 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4413 (void **)&scb_data->sense,
4414 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4418 scb_data->init_level++;
4420 /* And permanently map them */
4421 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4423 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4424 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4426 scb_data->init_level++;
4428 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4429 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4430 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4431 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4432 /*highaddr*/BUS_SPACE_MAXADDR,
4433 /*filter*/NULL, /*filterarg*/NULL,
4434 PAGE_SIZE, /*nsegments*/1,
4435 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4436 /*flags*/0, &scb_data->sg_dmat) != 0) {
4440 scb_data->init_level++;
4442 /* Perform initial CCB allocation */
4443 memset(scb_data->hscbs, 0,
4444 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4445 while (ahc_alloc_scbs(ahc) != 0)
4448 if (scb_data->numscbs == 0) {
4449 printf("%s: ahc_init_scbdata - "
4450 "Unable to allocate initial scbs\n",
4456 * Reserve the next queued SCB.
4458 ahc->next_queued_scb = ahc_get_scb(ahc);
4461 * Note that we were successfull
4471 ahc_fini_scbdata(struct ahc_softc *ahc)
4473 struct scb_data *scb_data;
4475 scb_data = ahc->scb_data;
4476 if (scb_data == NULL)
4479 switch (scb_data->init_level) {
4483 struct sg_map_node *sg_map;
4485 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4486 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4487 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4489 aic_dmamem_free(ahc, scb_data->sg_dmat,
4492 free(sg_map, M_DEVBUF);
4494 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4497 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4498 scb_data->sense_dmamap);
4500 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4501 scb_data->sense_dmamap);
4503 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4505 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4506 scb_data->hscb_dmamap);
4508 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4509 scb_data->hscb_dmamap);
4511 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4516 if (scb_data->scbarray != NULL)
4517 free(scb_data->scbarray, M_DEVBUF);
4521 ahc_alloc_scbs(struct ahc_softc *ahc)
4523 struct scb_data *scb_data;
4524 struct scb *next_scb;
4525 struct sg_map_node *sg_map;
4526 bus_addr_t physaddr;
4527 struct ahc_dma_seg *segs;
4531 scb_data = ahc->scb_data;
4532 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4533 /* Can't allocate any more */
4536 next_scb = &scb_data->scbarray[scb_data->numscbs];
4538 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4543 /* Allocate S/G space for the next batch of SCBS */
4544 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4545 (void **)&sg_map->sg_vaddr,
4546 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4547 &sg_map->sg_dmamap) != 0) {
4548 free(sg_map, M_DEVBUF);
4552 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4554 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4555 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4556 &sg_map->sg_physaddr, /*flags*/0);
4558 segs = sg_map->sg_vaddr;
4559 physaddr = sg_map->sg_physaddr;
4561 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4562 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4563 for (i = 0; i < newcount; i++) {
4564 struct scb_platform_data *pdata;
4568 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4569 M_DEVBUF, M_NOWAIT);
4572 next_scb->platform_data = pdata;
4573 next_scb->sg_map = sg_map;
4574 next_scb->sg_list = segs;
4576 * The sequencer always starts with the second entry.
4577 * The first entry is embedded in the scb.
4579 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4580 next_scb->ahc_softc = ahc;
4581 next_scb->flags = SCB_FLAG_NONE;
4583 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4588 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4589 next_scb->hscb->tag = ahc->scb_data->numscbs;
4590 aic_timer_init(&next_scb->io_timer);
4591 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4592 next_scb, links.sle);
4594 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4596 ahc->scb_data->numscbs++;
4602 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4606 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4608 if ((ahc->features & AHC_TWIN) != 0)
4609 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4610 "B SCSI Id=%d, primary %c, ",
4611 ahc->our_id, ahc->our_id_b,
4612 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4618 if ((ahc->features & AHC_ULTRA) != 0) {
4620 } else if ((ahc->features & AHC_DT) != 0) {
4621 speed = "Ultra160 ";
4622 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4625 if ((ahc->features & AHC_WIDE) != 0) {
4630 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4631 speed, type, ahc->channel, ahc->our_id);
4635 if ((ahc->flags & AHC_PAGESCBS) != 0)
4636 sprintf(buf, "%d/%d SCBs",
4637 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4639 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4643 ahc_chip_init(struct ahc_softc *ahc)
4649 u_int scsiseq_template;
4652 ahc_outb(ahc, SEQ_FLAGS, 0);
4653 ahc_outb(ahc, SEQ_FLAGS2, 0);
4655 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4656 if (ahc->features & AHC_TWIN) {
4659 * Setup Channel B first.
4661 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4662 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4663 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4664 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4665 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4666 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4667 if ((ahc->features & AHC_ULTRA2) != 0)
4668 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4669 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4670 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4672 /* Select Channel A */
4673 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4675 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4676 if ((ahc->features & AHC_ULTRA2) != 0)
4677 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4679 ahc_outb(ahc, SCSIID, ahc->our_id);
4680 scsi_conf = ahc_inb(ahc, SCSICONF);
4681 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4683 |ENSTIMER|ACTNEGEN);
4684 if ((ahc->features & AHC_ULTRA2) != 0)
4685 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4686 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4687 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4689 /* There are no untagged SCBs active yet. */
4690 for (i = 0; i < 16; i++) {
4691 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4692 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4696 * The SCB based BTT allows an entry per
4697 * target and lun pair.
4699 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4700 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4704 /* All of our queues are empty */
4705 for (i = 0; i < 256; i++)
4706 ahc->qoutfifo[i] = SCB_LIST_NULL;
4707 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4709 for (i = 0; i < 256; i++)
4710 ahc->qinfifo[i] = SCB_LIST_NULL;
4712 if ((ahc->features & AHC_MULTI_TID) != 0) {
4713 ahc_outb(ahc, TARGID, 0);
4714 ahc_outb(ahc, TARGID + 1, 0);
4718 * Tell the sequencer where it can find our arrays in memory.
4720 physaddr = ahc->scb_data->hscb_busaddr;
4721 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4722 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4723 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4724 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4726 physaddr = ahc->shared_data_busaddr;
4727 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4728 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4729 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4730 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4733 * Initialize the group code to command length table.
4734 * This overrides the values in TARG_SCSIRATE, so only
4735 * setup the table after we have processed that information.
4737 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4738 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4739 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4740 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4741 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4742 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4743 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4744 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4746 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4747 ahc_outb(ahc, HS_MAILBOX, 0);
4749 /* Tell the sequencer of our initial queue positions */
4750 if ((ahc->features & AHC_TARGETMODE) != 0) {
4751 ahc->tqinfifonext = 1;
4752 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4753 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4755 ahc->qinfifonext = 0;
4756 ahc->qoutfifonext = 0;
4757 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4758 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4759 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4760 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4761 ahc_outb(ahc, SDSCB_QOFF, 0);
4763 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4764 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4765 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4768 /* We don't have any waiting selections */
4769 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4771 /* Our disconnection list is empty too */
4772 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4774 /* Message out buffer starts empty */
4775 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4778 * Setup the allowed SCSI Sequences based on operational mode.
4779 * If we are a target, we'll enalbe select in operations once
4780 * we've had a lun enabled.
4782 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4783 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4784 scsiseq_template |= ENRSELI;
4785 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4787 /* Initialize our list of free SCBs. */
4788 ahc_build_free_scb_list(ahc);
4791 * Tell the sequencer which SCB will be the next one it receives.
4793 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4796 * Load the Sequencer program and Enable the adapter
4800 printf("%s: Downloading Sequencer Program...",
4803 error = ahc_loadseq(ahc);
4807 if ((ahc->features & AHC_ULTRA2) != 0) {
4811 * Wait for up to 500ms for our transceivers
4812 * to settle. If the adapter does not have
4813 * a cable attached, the transceivers may
4814 * never settle, so don't complain if we
4818 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4827 * Start the board, ready for normal operation
4830 ahc_init(struct ahc_softc *ahc)
4839 size_t driver_data_size;
4842 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4843 ahc->flags |= AHC_SEQUENCER_DEBUG;
4846 #ifdef AHC_PRINT_SRAM
4847 printf("Scratch Ram:");
4848 for (i = 0x20; i < 0x5f; i++) {
4849 if (((i % 8) == 0) && (i != 0)) {
4852 printf (" 0x%x", ahc_inb(ahc, i));
4854 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4855 for (i = 0x70; i < 0x7f; i++) {
4856 if (((i % 8) == 0) && (i != 0)) {
4859 printf (" 0x%x", ahc_inb(ahc, i));
4864 * Reading uninitialized scratch ram may
4865 * generate parity errors.
4867 ahc_outb(ahc, CLRINT, CLRPARERR);
4868 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4873 * Assume we have a board at this stage and it has been reset.
4875 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4876 ahc->our_id = ahc->our_id_b = 7;
4879 * Default to allowing initiator operations.
4881 ahc->flags |= AHC_INITIATORROLE;
4884 * Only allow target mode features if this unit has them enabled.
4886 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4887 ahc->features &= ~AHC_TARGETMODE;
4890 /* DMA tag for mapping buffers into device visible space. */
4891 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4892 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4893 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4894 ? (bus_addr_t)0x7FFFFFFFFFULL
4895 : BUS_SPACE_MAXADDR_32BIT,
4896 /*highaddr*/BUS_SPACE_MAXADDR,
4897 /*filter*/NULL, /*filterarg*/NULL,
4898 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4899 /*nsegments*/AHC_NSEG,
4900 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4901 /*flags*/BUS_DMA_ALLOCNOW,
4902 &ahc->buffer_dmat) != 0) {
4910 * DMA tag for our command fifos and other data in system memory
4911 * the card's sequencer must be able to access. For initiator
4912 * roles, we need to allocate space for the qinfifo and qoutfifo.
4913 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4914 * When providing for the target mode role, we must additionally
4915 * provide space for the incoming target command fifo and an extra
4916 * byte to deal with a dma bug in some chip versions.
4918 driver_data_size = 2 * 256 * sizeof(uint8_t);
4919 if ((ahc->features & AHC_TARGETMODE) != 0)
4920 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4921 + /*DMA WideOdd Bug Buffer*/1;
4922 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4923 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4924 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4925 /*highaddr*/BUS_SPACE_MAXADDR,
4926 /*filter*/NULL, /*filterarg*/NULL,
4929 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4930 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4936 /* Allocation of driver data */
4937 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4938 (void **)&ahc->qoutfifo,
4939 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4940 &ahc->shared_data_dmamap) != 0) {
4946 /* And permanently map it in */
4947 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4948 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4949 &ahc->shared_data_busaddr, /*flags*/0);
4951 if ((ahc->features & AHC_TARGETMODE) != 0) {
4952 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4953 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4954 ahc->dma_bug_buf = ahc->shared_data_busaddr
4955 + driver_data_size - 1;
4956 /* All target command blocks start out invalid. */
4957 for (i = 0; i < AHC_TMODE_CMDS; i++)
4958 ahc->targetcmds[i].cmd_valid = 0;
4959 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4960 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4962 ahc->qinfifo = &ahc->qoutfifo[256];
4966 /* Allocate SCB data now that buffer_dmat is initialized */
4967 if (ahc->scb_data->maxhscbs == 0)
4968 if (ahc_init_scbdata(ahc) != 0)
4972 * Allocate a tstate to house information for our
4973 * initiator presence on the bus as well as the user
4974 * data for any target mode initiator.
4976 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4977 printf("%s: unable to allocate ahc_tmode_tstate. "
4978 "Failing attach\n", ahc_name(ahc));
4982 if ((ahc->features & AHC_TWIN) != 0) {
4983 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4984 printf("%s: unable to allocate ahc_tmode_tstate. "
4985 "Failing attach\n", ahc_name(ahc));
4991 * Fire up a recovery thread for this controller.
4993 error = ahc_spawn_recovery_thread(ahc);
4997 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4998 ahc->flags |= AHC_PAGESCBS;
5000 ahc->flags &= ~AHC_PAGESCBS;
5004 if (ahc_debug & AHC_SHOW_MISC) {
5005 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
5006 "ahc_dma %u bytes\n",
5008 (u_int)sizeof(struct hardware_scb),
5009 (u_int)sizeof(struct scb),
5010 (u_int)sizeof(struct ahc_dma_seg));
5012 #endif /* AHC_DEBUG */
5015 * Look at the information that board initialization or
5016 * the board bios has left us.
5018 if (ahc->features & AHC_TWIN) {
5019 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5020 if ((scsi_conf & RESET_SCSI) != 0
5021 && (ahc->flags & AHC_INITIATORROLE) != 0)
5022 ahc->flags |= AHC_RESET_BUS_B;
5025 scsi_conf = ahc_inb(ahc, SCSICONF);
5026 if ((scsi_conf & RESET_SCSI) != 0
5027 && (ahc->flags & AHC_INITIATORROLE) != 0)
5028 ahc->flags |= AHC_RESET_BUS_A;
5031 tagenable = ALL_TARGETS_MASK;
5033 /* Grab the disconnection disable table and invert it for our needs */
5034 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5035 printf("%s: Host Adapter Bios disabled. Using default SCSI "
5036 "device parameters\n", ahc_name(ahc));
5037 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5038 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5039 discenable = ALL_TARGETS_MASK;
5040 if ((ahc->features & AHC_ULTRA) != 0)
5041 ultraenb = ALL_TARGETS_MASK;
5043 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5044 | ahc_inb(ahc, DISC_DSB));
5045 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5046 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5047 | ahc_inb(ahc, ULTRA_ENB);
5050 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5053 for (i = 0; i <= max_targ; i++) {
5054 struct ahc_initiator_tinfo *tinfo;
5055 struct ahc_tmode_tstate *tstate;
5061 our_id = ahc->our_id;
5063 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5065 our_id = ahc->our_id_b;
5068 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5069 target_id, &tstate);
5070 /* Default to async narrow across the board */
5071 memset(tinfo, 0, sizeof(*tinfo));
5072 if (ahc->flags & AHC_USEDEFAULTS) {
5073 if ((ahc->features & AHC_WIDE) != 0)
5074 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5077 * These will be truncated when we determine the
5078 * connection type we have with the target.
5080 tinfo->user.period = ahc_syncrates->period;
5081 tinfo->user.offset = MAX_OFFSET;
5086 /* Take the settings leftover in scratch RAM. */
5087 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5089 if ((ahc->features & AHC_ULTRA2) != 0) {
5093 if ((scsirate & SOFS) == 0x0F) {
5095 * Haven't negotiated yet,
5096 * so the format is different.
5098 scsirate = (scsirate & SXFR) >> 4
5101 | (scsirate & WIDEXFER);
5102 offset = MAX_OFFSET_ULTRA2;
5104 offset = ahc_inb(ahc, TARG_OFFSET + i);
5105 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5106 /* Set to the lowest sync rate, 5MHz */
5108 maxsync = AHC_SYNCRATE_ULTRA2;
5109 if ((ahc->features & AHC_DT) != 0)
5110 maxsync = AHC_SYNCRATE_DT;
5111 tinfo->user.period =
5112 ahc_find_period(ahc, scsirate, maxsync);
5114 tinfo->user.period = 0;
5116 tinfo->user.offset = MAX_OFFSET;
5117 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5118 && (ahc->features & AHC_DT) != 0)
5119 tinfo->user.ppr_options =
5121 } else if ((scsirate & SOFS) != 0) {
5122 if ((scsirate & SXFR) == 0x40
5123 && (ultraenb & mask) != 0) {
5124 /* Treat 10MHz as a non-ultra speed */
5128 tinfo->user.period =
5129 ahc_find_period(ahc, scsirate,
5131 ? AHC_SYNCRATE_ULTRA
5132 : AHC_SYNCRATE_FAST);
5133 if (tinfo->user.period != 0)
5134 tinfo->user.offset = MAX_OFFSET;
5136 if (tinfo->user.period == 0)
5137 tinfo->user.offset = 0;
5138 if ((scsirate & WIDEXFER) != 0
5139 && (ahc->features & AHC_WIDE) != 0)
5140 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5141 tinfo->user.protocol_version = 4;
5142 if ((ahc->features & AHC_DT) != 0)
5143 tinfo->user.transport_version = 3;
5145 tinfo->user.transport_version = 2;
5146 tinfo->goal.protocol_version = 2;
5147 tinfo->goal.transport_version = 2;
5148 tinfo->curr.protocol_version = 2;
5149 tinfo->curr.transport_version = 2;
5151 tstate->ultraenb = 0;
5153 ahc->user_discenable = discenable;
5154 ahc->user_tagenable = tagenable;
5156 return (ahc->bus_chip_init(ahc));
5160 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5164 hcntrl = ahc_inb(ahc, HCNTRL);
5166 ahc->pause &= ~INTEN;
5167 ahc->unpause &= ~INTEN;
5170 ahc->pause |= INTEN;
5171 ahc->unpause |= INTEN;
5173 ahc_outb(ahc, HCNTRL, hcntrl);
5177 * Ensure that the card is paused in a location
5178 * outside of all critical sections and that all
5179 * pending work is completed prior to returning.
5180 * This routine should only be called from outside
5181 * an interrupt context.
5184 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5191 ahc->flags |= AHC_ALL_INTERRUPTS;
5197 * Give the sequencer some time to service
5198 * any active selections.
5205 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5206 intstat = ahc_inb(ahc, INTSTAT);
5207 if ((intstat & INT_PEND) == 0) {
5208 ahc_clear_critical_section(ahc);
5209 intstat = ahc_inb(ahc, INTSTAT);
5212 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5213 && ((intstat & INT_PEND) != 0
5214 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5215 if (maxloops == 0) {
5216 printf("Infinite interrupt loop, INTSTAT = %x",
5217 ahc_inb(ahc, INTSTAT));
5219 ahc_platform_flushwork(ahc);
5220 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5224 ahc_suspend(struct ahc_softc *ahc)
5227 ahc_pause_and_flushwork(ahc);
5229 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5234 #ifdef AHC_TARGET_MODE
5236 * XXX What about ATIOs that have not yet been serviced?
5237 * Perhaps we should just refuse to be suspended if we
5238 * are acting in a target role.
5240 if (ahc->pending_device != NULL) {
5250 ahc_resume(struct ahc_softc *ahc)
5253 ahc_reset(ahc, /*reinit*/TRUE);
5254 ahc_intr_enable(ahc, TRUE);
5259 /************************** Busy Target Table *********************************/
5261 * Return the untagged transaction id for a given target/channel lun.
5262 * Optionally, clear the entry.
5265 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5268 u_int target_offset;
5270 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5273 saved_scbptr = ahc_inb(ahc, SCBPTR);
5274 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5275 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5276 ahc_outb(ahc, SCBPTR, saved_scbptr);
5278 target_offset = TCL_TARGET_OFFSET(tcl);
5279 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5286 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5288 u_int target_offset;
5290 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5293 saved_scbptr = ahc_inb(ahc, SCBPTR);
5294 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5295 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5296 ahc_outb(ahc, SCBPTR, saved_scbptr);
5298 target_offset = TCL_TARGET_OFFSET(tcl);
5299 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5304 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5306 u_int target_offset;
5308 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5311 saved_scbptr = ahc_inb(ahc, SCBPTR);
5312 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5313 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5314 ahc_outb(ahc, SCBPTR, saved_scbptr);
5316 target_offset = TCL_TARGET_OFFSET(tcl);
5317 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5321 /************************** SCB and SCB queue management **********************/
5323 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5324 char channel, int lun, u_int tag, role_t role)
5326 int targ = SCB_GET_TARGET(ahc, scb);
5327 char chan = SCB_GET_CHANNEL(ahc, scb);
5328 int slun = SCB_GET_LUN(scb);
5331 match = ((chan == channel) || (channel == ALL_CHANNELS));
5333 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5335 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5337 #ifdef AHC_TARGET_MODE
5340 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5341 if (role == ROLE_INITIATOR) {
5342 match = (group != XPT_FC_GROUP_TMODE)
5343 && ((tag == scb->hscb->tag)
5344 || (tag == SCB_LIST_NULL));
5345 } else if (role == ROLE_TARGET) {
5346 match = (group == XPT_FC_GROUP_TMODE)
5347 && ((tag == scb->io_ctx->csio.tag_id)
5348 || (tag == SCB_LIST_NULL));
5350 #else /* !AHC_TARGET_MODE */
5351 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5352 #endif /* AHC_TARGET_MODE */
5359 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5365 target = SCB_GET_TARGET(ahc, scb);
5366 lun = SCB_GET_LUN(scb);
5367 channel = SCB_GET_CHANNEL(ahc, scb);
5369 ahc_search_qinfifo(ahc, target, channel, lun,
5370 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5371 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5373 ahc_platform_freeze_devq(ahc, scb);
5377 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5379 struct scb *prev_scb;
5382 if (ahc_qinfifo_count(ahc) != 0) {
5386 prev_pos = ahc->qinfifonext - 1;
5387 prev_tag = ahc->qinfifo[prev_pos];
5388 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5390 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5391 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5392 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5394 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5399 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5402 if (prev_scb == NULL) {
5403 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5405 prev_scb->hscb->next = scb->hscb->tag;
5406 ahc_sync_scb(ahc, prev_scb,
5407 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5409 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5410 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5411 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5415 ahc_qinfifo_count(struct ahc_softc *ahc)
5420 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5421 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5422 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5424 qinpos = ahc_inb(ahc, QINPOS);
5425 diff = ahc->qinfifonext - qinpos;
5430 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5431 int lun, u_int tag, role_t role, uint32_t status,
5432 ahc_search_action action)
5435 struct scb *prev_scb;
5445 qintail = ahc->qinfifonext;
5446 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5448 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5449 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5451 qinstart = ahc_inb(ahc, QINPOS);
5456 if (action == SEARCH_COMPLETE) {
5458 * Don't attempt to run any queued untagged transactions
5459 * until we are done with the abort process.
5461 ahc_freeze_untagged_queues(ahc);
5465 * Start with an empty queue. Entries that are not chosen
5466 * for removal will be re-added to the queue as we go.
5468 ahc->qinfifonext = qinpos;
5469 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5471 while (qinpos != qintail) {
5472 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5474 printf("qinpos = %d, SCB index = %d\n",
5475 qinpos, ahc->qinfifo[qinpos]);
5479 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5481 * We found an scb that needs to be acted on.
5485 case SEARCH_COMPLETE:
5490 ostat = aic_get_transaction_status(scb);
5491 if (ostat == CAM_REQ_INPROG)
5492 aic_set_transaction_status(scb, status);
5493 cstat = aic_get_transaction_status(scb);
5494 if (cstat != CAM_REQ_CMP)
5495 aic_freeze_scb(scb);
5496 if ((scb->flags & SCB_ACTIVE) == 0)
5497 printf("Inactive SCB in qinfifo\n");
5505 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5510 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5516 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5517 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5519 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5522 if (action != SEARCH_COUNT
5524 && (qinstart != ahc->qinfifonext)) {
5526 * The sequencer may be in the process of dmaing
5527 * down the SCB at the beginning of the queue.
5528 * This could be problematic if either the first,
5529 * or the second SCB is removed from the queue
5530 * (the first SCB includes a pointer to the "next"
5531 * SCB to dma). If we have removed any entries, swap
5532 * the first element in the queue with the next HSCB
5533 * so the sequencer will notice that NEXT_QUEUED_SCB
5534 * has changed during its dma attempt and will retry
5537 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5540 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5541 found, qinstart, ahc->qinfifonext);
5542 panic("First/Second Qinfifo fixup\n");
5545 * ahc_swap_with_next_hscb forces our next pointer to
5546 * point to the reserved SCB for future commands. Save
5547 * and restore our original next pointer to maintain
5550 next = scb->hscb->next;
5551 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5552 ahc_swap_with_next_hscb(ahc, scb);
5553 scb->hscb->next = next;
5554 ahc->qinfifo[qinstart] = scb->hscb->tag;
5556 /* Tell the card about the new head of the qinfifo. */
5557 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5559 /* Fixup the tail "next" pointer. */
5560 qintail = ahc->qinfifonext - 1;
5561 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5562 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5566 * Search waiting for selection list.
5568 curscbptr = ahc_inb(ahc, SCBPTR);
5569 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5570 prev = SCB_LIST_NULL;
5572 while (next != SCB_LIST_NULL) {
5575 ahc_outb(ahc, SCBPTR, next);
5576 scb_index = ahc_inb(ahc, SCB_TAG);
5577 if (scb_index >= ahc->scb_data->numscbs) {
5578 printf("Waiting List inconsistency. "
5579 "SCB index == %d, yet numscbs == %d.",
5580 scb_index, ahc->scb_data->numscbs);
5581 ahc_dump_card_state(ahc);
5582 panic("for safety");
5584 scb = ahc_lookup_scb(ahc, scb_index);
5586 printf("scb_index = %d, next = %d\n",
5588 panic("Waiting List traversal\n");
5590 if (ahc_match_scb(ahc, scb, target, channel,
5591 lun, SCB_LIST_NULL, role)) {
5593 * We found an scb that needs to be acted on.
5597 case SEARCH_COMPLETE:
5602 ostat = aic_get_transaction_status(scb);
5603 if (ostat == CAM_REQ_INPROG)
5604 aic_set_transaction_status(scb,
5606 cstat = aic_get_transaction_status(scb);
5607 if (cstat != CAM_REQ_CMP)
5608 aic_freeze_scb(scb);
5609 if ((scb->flags & SCB_ACTIVE) == 0)
5610 printf("Inactive SCB in Wait List\n");
5615 next = ahc_rem_wscb(ahc, next, prev);
5619 next = ahc_inb(ahc, SCB_NEXT);
5625 next = ahc_inb(ahc, SCB_NEXT);
5628 ahc_outb(ahc, SCBPTR, curscbptr);
5630 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5631 channel, lun, status, action);
5633 if (action == SEARCH_COMPLETE)
5634 ahc_release_untagged_queues(ahc);
5639 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5640 int target, char channel, int lun, uint32_t status,
5641 ahc_search_action action)
5648 if (action == SEARCH_COMPLETE) {
5650 * Don't attempt to run any queued untagged transactions
5651 * until we are done with the abort process.
5653 ahc_freeze_untagged_queues(ahc);
5658 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5661 if (target != CAM_TARGET_WILDCARD) {
5672 for (; i < maxtarget; i++) {
5673 struct scb_tailq *untagged_q;
5674 struct scb *next_scb;
5676 untagged_q = &(ahc->untagged_queues[i]);
5677 next_scb = TAILQ_FIRST(untagged_q);
5678 while (next_scb != NULL) {
5681 next_scb = TAILQ_NEXT(scb, links.tqe);
5684 * The head of the list may be the currently
5685 * active untagged command for a device.
5686 * We're only searching for commands that
5687 * have not been started. A transaction
5688 * marked active but still in the qinfifo
5689 * is removed by the qinfifo scanning code
5692 if ((scb->flags & SCB_ACTIVE) != 0)
5695 if (ahc_match_scb(ahc, scb, target, channel, lun,
5696 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5697 || (ctx != NULL && ctx != scb->io_ctx))
5701 * We found an scb that needs to be acted on.
5705 case SEARCH_COMPLETE:
5710 ostat = aic_get_transaction_status(scb);
5711 if (ostat == CAM_REQ_INPROG)
5712 aic_set_transaction_status(scb, status);
5713 cstat = aic_get_transaction_status(scb);
5714 if (cstat != CAM_REQ_CMP)
5715 aic_freeze_scb(scb);
5720 scb->flags &= ~SCB_UNTAGGEDQ;
5721 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5729 if (action == SEARCH_COMPLETE)
5730 ahc_release_untagged_queues(ahc);
5735 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5736 int lun, u_int tag, int stop_on_first, int remove,
5746 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5747 prev = SCB_LIST_NULL;
5750 /* restore this when we're done */
5751 active_scb = ahc_inb(ahc, SCBPTR);
5753 /* Silence compiler */
5754 active_scb = SCB_LIST_NULL;
5756 while (next != SCB_LIST_NULL) {
5759 ahc_outb(ahc, SCBPTR, next);
5760 scb_index = ahc_inb(ahc, SCB_TAG);
5761 if (scb_index >= ahc->scb_data->numscbs) {
5762 printf("Disconnected List inconsistency. "
5763 "SCB index == %d, yet numscbs == %d.",
5764 scb_index, ahc->scb_data->numscbs);
5765 ahc_dump_card_state(ahc);
5766 panic("for safety");
5770 panic("Disconnected List Loop. "
5771 "cur SCBPTR == %x, prev SCBPTR == %x.",
5774 scbp = ahc_lookup_scb(ahc, scb_index);
5775 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5776 tag, ROLE_INITIATOR)) {
5780 ahc_rem_scb_from_disc_list(ahc, prev, next);
5783 next = ahc_inb(ahc, SCB_NEXT);
5789 next = ahc_inb(ahc, SCB_NEXT);
5793 ahc_outb(ahc, SCBPTR, active_scb);
5798 * Remove an SCB from the on chip list of disconnected transactions.
5799 * This is empty/unused if we are not performing SCB paging.
5802 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5806 ahc_outb(ahc, SCBPTR, scbptr);
5807 next = ahc_inb(ahc, SCB_NEXT);
5809 ahc_outb(ahc, SCB_CONTROL, 0);
5811 ahc_add_curscb_to_free_list(ahc);
5813 if (prev != SCB_LIST_NULL) {
5814 ahc_outb(ahc, SCBPTR, prev);
5815 ahc_outb(ahc, SCB_NEXT, next);
5817 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5823 * Add the SCB as selected by SCBPTR onto the on chip list of
5824 * free hardware SCBs. This list is empty/unused if we are not
5825 * performing SCB paging.
5828 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5831 * Invalidate the tag so that our abort
5832 * routines don't think it's active.
5834 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5836 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5837 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5838 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5843 * Manipulate the waiting for selection list and return the
5844 * scb that follows the one that we remove.
5847 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5852 * Select the SCB we want to abort and
5853 * pull the next pointer out of it.
5855 curscb = ahc_inb(ahc, SCBPTR);
5856 ahc_outb(ahc, SCBPTR, scbpos);
5857 next = ahc_inb(ahc, SCB_NEXT);
5859 /* Clear the necessary fields */
5860 ahc_outb(ahc, SCB_CONTROL, 0);
5862 ahc_add_curscb_to_free_list(ahc);
5864 /* update the waiting list */
5865 if (prev == SCB_LIST_NULL) {
5866 /* First in the list */
5867 ahc_outb(ahc, WAITING_SCBH, next);
5870 * Ensure we aren't attempting to perform
5871 * selection for this entry.
5873 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5876 * Select the scb that pointed to us
5877 * and update its next pointer.
5879 ahc_outb(ahc, SCBPTR, prev);
5880 ahc_outb(ahc, SCB_NEXT, next);
5884 * Point us back at the original scb position.
5886 ahc_outb(ahc, SCBPTR, curscb);
5890 /******************************** Error Handling ******************************/
5892 * Abort all SCBs that match the given description (target/channel/lun/tag),
5893 * setting their status to the passed in status if the status has not already
5894 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5895 * is paused before it is called.
5898 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5899 int lun, u_int tag, role_t role, uint32_t status)
5902 struct scb *scbp_next;
5912 * Don't attempt to run any queued untagged transactions
5913 * until we are done with the abort process.
5915 ahc_freeze_untagged_queues(ahc);
5917 /* restore this when we're done */
5918 active_scb = ahc_inb(ahc, SCBPTR);
5920 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5921 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5924 * Clean out the busy target table for any untagged commands.
5928 if (target != CAM_TARGET_WILDCARD) {
5935 if (lun == CAM_LUN_WILDCARD) {
5938 * Unless we are using an SCB based
5939 * busy targets table, there is only
5940 * one table entry for all luns of
5945 if ((ahc->flags & AHC_SCB_BTT) != 0)
5946 maxlun = AHC_NUM_LUNS;
5952 if (role != ROLE_TARGET) {
5953 for (;i < maxtarget; i++) {
5954 for (j = minlun;j < maxlun; j++) {
5958 tcl = BUILD_TCL(i << 4, j);
5959 scbid = ahc_index_busy_tcl(ahc, tcl);
5960 scbp = ahc_lookup_scb(ahc, scbid);
5962 || ahc_match_scb(ahc, scbp, target, channel,
5963 lun, tag, role) == 0)
5965 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5970 * Go through the disconnected list and remove any entries we
5971 * have queued for completion, 0'ing their control byte too.
5972 * We save the active SCB and restore it ourselves, so there
5973 * is no reason for this search to restore it too.
5975 ahc_search_disc_list(ahc, target, channel, lun, tag,
5976 /*stop_on_first*/FALSE, /*remove*/TRUE,
5977 /*save_state*/FALSE);
5981 * Go through the hardware SCB array looking for commands that
5982 * were active but not on any list. In some cases, these remnants
5983 * might not still have mappings in the scbindex array (e.g. unexpected
5984 * bus free with the same scb queued for an abort). Don't hold this
5987 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5990 ahc_outb(ahc, SCBPTR, i);
5991 scbid = ahc_inb(ahc, SCB_TAG);
5992 scbp = ahc_lookup_scb(ahc, scbid);
5993 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5995 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5996 ahc_add_curscb_to_free_list(ahc);
6000 * Go through the pending CCB list and look for
6001 * commands for this target that are still active.
6002 * These are other tagged commands that were
6003 * disconnected when the reset occurred.
6005 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6006 while (scbp_next != NULL) {
6008 scbp_next = LIST_NEXT(scbp, pending_links);
6009 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6012 ostat = aic_get_transaction_status(scbp);
6013 if (ostat == CAM_REQ_INPROG)
6014 aic_set_transaction_status(scbp, status);
6015 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
6016 aic_freeze_scb(scbp);
6017 if ((scbp->flags & SCB_ACTIVE) == 0)
6018 printf("Inactive SCB on pending list\n");
6019 ahc_done(ahc, scbp);
6023 ahc_outb(ahc, SCBPTR, active_scb);
6024 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6025 ahc_release_untagged_queues(ahc);
6030 ahc_reset_current_bus(struct ahc_softc *ahc)
6034 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6035 scsiseq = ahc_inb(ahc, SCSISEQ);
6036 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6037 ahc_flush_device_writes(ahc);
6038 aic_delay(AHC_BUSRESET_DELAY);
6039 /* Turn off the bus reset */
6040 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6042 ahc_clear_intstat(ahc);
6044 /* Re-enable reset interrupts */
6045 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6049 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6051 struct ahc_devinfo devinfo;
6052 u_int initiator, target, max_scsiid;
6060 ahc->pending_device = NULL;
6062 ahc_compile_devinfo(&devinfo,
6063 CAM_TARGET_WILDCARD,
6064 CAM_TARGET_WILDCARD,
6066 channel, ROLE_UNKNOWN);
6069 /* Make sure the sequencer is in a safe location. */
6070 ahc_clear_critical_section(ahc);
6073 * Run our command complete fifos to ensure that we perform
6074 * completion processing on any commands that 'completed'
6075 * before the reset occurred.
6077 ahc_run_qoutfifo(ahc);
6078 #ifdef AHC_TARGET_MODE
6080 * XXX - In Twin mode, the tqinfifo may have commands
6081 * for an unaffected channel in it. However, if
6082 * we have run out of ATIO resources to drain that
6083 * queue, we may not get them all out here. Further,
6084 * the blocked transactions for the reset channel
6085 * should just be killed off, irrespecitve of whether
6086 * we are blocked on ATIO resources. Write a routine
6087 * to compact the tqinfifo appropriately.
6089 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6090 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6095 * Reset the bus if we are initiating this reset
6097 sblkctl = ahc_inb(ahc, SBLKCTL);
6099 if ((ahc->features & AHC_TWIN) != 0
6100 && ((sblkctl & SELBUSB) != 0))
6102 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6103 if (cur_channel != channel) {
6104 /* Case 1: Command for another bus is active
6105 * Stealthily reset the other bus without
6106 * upsetting the current bus.
6108 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6109 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6110 #ifdef AHC_TARGET_MODE
6112 * Bus resets clear ENSELI, so we cannot
6113 * defer re-enabling bus reset interrupts
6114 * if we are in target mode.
6116 if ((ahc->flags & AHC_TARGETROLE) != 0)
6117 simode1 |= ENSCSIRST;
6119 ahc_outb(ahc, SIMODE1, simode1);
6121 ahc_reset_current_bus(ahc);
6122 ahc_clear_intstat(ahc);
6123 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6124 ahc_outb(ahc, SBLKCTL, sblkctl);
6125 restart_needed = FALSE;
6127 /* Case 2: A command from this bus is active or we're idle */
6128 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6129 #ifdef AHC_TARGET_MODE
6131 * Bus resets clear ENSELI, so we cannot
6132 * defer re-enabling bus reset interrupts
6133 * if we are in target mode.
6135 if ((ahc->flags & AHC_TARGETROLE) != 0)
6136 simode1 |= ENSCSIRST;
6138 ahc_outb(ahc, SIMODE1, simode1);
6140 ahc_reset_current_bus(ahc);
6141 ahc_clear_intstat(ahc);
6142 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6143 restart_needed = TRUE;
6147 * Clean up all the state information for the
6148 * pending transactions on this bus.
6150 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6151 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6152 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6154 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6156 #ifdef AHC_TARGET_MODE
6158 * Send an immediate notify ccb to all target more peripheral
6159 * drivers affected by this action.
6161 for (target = 0; target <= max_scsiid; target++) {
6162 struct ahc_tmode_tstate* tstate;
6165 tstate = ahc->enabled_targets[target];
6168 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6169 struct ahc_tmode_lstate* lstate;
6171 lstate = tstate->enabled_luns[lun];
6175 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6176 EVENT_TYPE_BUS_RESET, /*arg*/0);
6177 ahc_send_lstate_events(ahc, lstate);
6181 /* Notify the XPT that a bus reset occurred */
6182 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6183 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6186 * Revert to async/narrow transfers until we renegotiate.
6188 for (target = 0; target <= max_scsiid; target++) {
6190 if (ahc->enabled_targets[target] == NULL)
6192 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6193 struct ahc_devinfo devinfo;
6195 ahc_compile_devinfo(&devinfo, target, initiator,
6197 channel, ROLE_UNKNOWN);
6198 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6199 AHC_TRANS_CUR, /*paused*/TRUE);
6200 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6201 /*period*/0, /*offset*/0,
6202 /*ppr_options*/0, AHC_TRANS_CUR,
6215 /***************************** Residual Processing ****************************/
6217 * Calculate the residual for a just completed SCB.
6220 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6222 struct hardware_scb *hscb;
6223 struct status_pkt *spkt;
6225 uint32_t resid_sgptr;
6231 * SG_RESID_VALID clear in sgptr.
6232 * 2) Transferless command
6233 * 3) Never performed any transfers.
6234 * sgptr has SG_FULL_RESID set.
6235 * 4) No residual but target did not
6236 * save data pointers after the
6237 * last transfer, so sgptr was
6239 * 5) We have a partial residual.
6240 * Use residual_sgptr to determine
6245 sgptr = aic_le32toh(hscb->sgptr);
6246 if ((sgptr & SG_RESID_VALID) == 0)
6249 sgptr &= ~SG_RESID_VALID;
6251 if ((sgptr & SG_LIST_NULL) != 0)
6255 spkt = &hscb->shared_data.status;
6256 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6257 if ((sgptr & SG_FULL_RESID) != 0) {
6259 resid = aic_get_transfer_length(scb);
6260 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6263 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6264 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6268 struct ahc_dma_seg *sg;
6271 * Remainder of the SG where the transfer
6274 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6275 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6277 /* The residual sg_ptr always points to the next sg */
6281 * Add up the contents of all residual
6282 * SG segments that are after the SG where
6283 * the transfer stopped.
6285 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6287 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6290 if ((scb->flags & SCB_SENSE) == 0)
6291 aic_set_residual(scb, resid);
6293 aic_set_sense_residual(scb, resid);
6296 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6297 ahc_print_path(ahc, scb);
6298 printf("Handled %sResidual of %d bytes\n",
6299 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6304 /******************************* Target Mode **********************************/
6305 #ifdef AHC_TARGET_MODE
6307 * Add a target mode event to this lun's queue
6310 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6311 u_int initiator_id, u_int event_type, u_int event_arg)
6313 struct ahc_tmode_event *event;
6316 xpt_freeze_devq(lstate->path, /*count*/1);
6317 if (lstate->event_w_idx >= lstate->event_r_idx)
6318 pending = lstate->event_w_idx - lstate->event_r_idx;
6320 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6321 - (lstate->event_r_idx - lstate->event_w_idx);
6323 if (event_type == EVENT_TYPE_BUS_RESET
6324 || event_type == MSG_BUS_DEV_RESET) {
6326 * Any earlier events are irrelevant, so reset our buffer.
6327 * This has the effect of allowing us to deal with reset
6328 * floods (an external device holding down the reset line)
6329 * without losing the event that is really interesting.
6331 lstate->event_r_idx = 0;
6332 lstate->event_w_idx = 0;
6333 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6336 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6337 xpt_print_path(lstate->path);
6338 printf("immediate event %x:%x lost\n",
6339 lstate->event_buffer[lstate->event_r_idx].event_type,
6340 lstate->event_buffer[lstate->event_r_idx].event_arg);
6341 lstate->event_r_idx++;
6342 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6343 lstate->event_r_idx = 0;
6344 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6347 event = &lstate->event_buffer[lstate->event_w_idx];
6348 event->initiator_id = initiator_id;
6349 event->event_type = event_type;
6350 event->event_arg = event_arg;
6351 lstate->event_w_idx++;
6352 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6353 lstate->event_w_idx = 0;
6357 * Send any target mode events queued up waiting
6358 * for immediate notify resources.
6361 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6363 struct ccb_hdr *ccbh;
6364 struct ccb_immediate_notify *inot;
6366 while (lstate->event_r_idx != lstate->event_w_idx
6367 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6368 struct ahc_tmode_event *event;
6370 event = &lstate->event_buffer[lstate->event_r_idx];
6371 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6372 inot = (struct ccb_immediate_notify *)ccbh;
6373 switch (event->event_type) {
6374 case EVENT_TYPE_BUS_RESET:
6375 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6378 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6379 inot->arg = event->event_type;
6380 inot->seq_id = event->event_arg;
6383 inot->initiator_id = event->initiator_id;
6384 xpt_done((union ccb *)inot);
6385 lstate->event_r_idx++;
6386 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6387 lstate->event_r_idx = 0;
6392 /******************** Sequencer Program Patching/Download *********************/
6396 ahc_dumpseq(struct ahc_softc* ahc)
6400 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6401 ahc_outb(ahc, SEQADDR0, 0);
6402 ahc_outb(ahc, SEQADDR1, 0);
6403 for (i = 0; i < ahc->instruction_ram_size; i++) {
6404 uint8_t ins_bytes[4];
6406 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6407 printf("0x%08x\n", ins_bytes[0] << 24
6408 | ins_bytes[1] << 16
6416 ahc_loadseq(struct ahc_softc *ahc)
6418 struct cs cs_table[num_critical_sections];
6419 u_int begin_set[num_critical_sections];
6420 u_int end_set[num_critical_sections];
6421 struct patch *cur_patch;
6426 u_int sg_prefetch_cnt;
6428 uint8_t download_consts[7];
6431 * Start out with 0 critical sections
6432 * that apply to this firmware load.
6436 memset(begin_set, 0, sizeof(begin_set));
6437 memset(end_set, 0, sizeof(end_set));
6439 /* Setup downloadable constant table */
6440 download_consts[QOUTFIFO_OFFSET] = 0;
6441 if (ahc->targetcmds != NULL)
6442 download_consts[QOUTFIFO_OFFSET] += 32;
6443 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6444 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6445 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6446 sg_prefetch_cnt = ahc->pci_cachesize;
6447 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6448 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6449 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6450 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6451 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6453 cur_patch = patches;
6456 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6457 ahc_outb(ahc, SEQADDR0, 0);
6458 ahc_outb(ahc, SEQADDR1, 0);
6460 for (i = 0; i < sizeof(seqprog)/4; i++) {
6461 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6463 * Don't download this instruction as it
6464 * is in a patch that was removed.
6469 if (downloaded == ahc->instruction_ram_size) {
6471 * We're about to exceed the instruction
6472 * storage capacity for this chip. Fail
6475 printf("\n%s: Program too large for instruction memory "
6476 "size of %d!\n", ahc_name(ahc),
6477 ahc->instruction_ram_size);
6482 * Move through the CS table until we find a CS
6483 * that might apply to this instruction.
6485 for (; cur_cs < num_critical_sections; cur_cs++) {
6486 if (critical_sections[cur_cs].end <= i) {
6487 if (begin_set[cs_count] == TRUE
6488 && end_set[cs_count] == FALSE) {
6489 cs_table[cs_count].end = downloaded;
6490 end_set[cs_count] = TRUE;
6495 if (critical_sections[cur_cs].begin <= i
6496 && begin_set[cs_count] == FALSE) {
6497 cs_table[cs_count].begin = downloaded;
6498 begin_set[cs_count] = TRUE;
6502 ahc_download_instr(ahc, i, download_consts);
6506 ahc->num_critical_sections = cs_count;
6507 if (cs_count != 0) {
6509 cs_count *= sizeof(struct cs);
6510 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6511 if (ahc->critical_sections == NULL)
6512 panic("ahc_loadseq: Could not malloc");
6513 memcpy(ahc->critical_sections, cs_table, cs_count);
6515 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6518 printf(" %d instructions downloaded\n", downloaded);
6519 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6520 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6526 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6527 u_int start_instr, u_int *skip_addr)
6529 struct patch *cur_patch;
6530 struct patch *last_patch;
6533 num_patches = sizeof(patches)/sizeof(struct patch);
6534 last_patch = &patches[num_patches];
6535 cur_patch = *start_patch;
6537 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6539 if (cur_patch->patch_func(ahc) == 0) {
6541 /* Start rejecting code */
6542 *skip_addr = start_instr + cur_patch->skip_instr;
6543 cur_patch += cur_patch->skip_patch;
6545 /* Accepted this patch. Advance to the next
6546 * one and wait for our intruction pointer to
6553 *start_patch = cur_patch;
6554 if (start_instr < *skip_addr)
6555 /* Still skipping */
6562 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6564 union ins_formats instr;
6565 struct ins_format1 *fmt1_ins;
6566 struct ins_format3 *fmt3_ins;
6570 * The firmware is always compiled into a little endian format.
6572 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6574 fmt1_ins = &instr.format1;
6577 /* Pull the opcode */
6578 opcode = instr.format1.opcode;
6589 struct patch *cur_patch;
6595 fmt3_ins = &instr.format3;
6597 address = fmt3_ins->address;
6598 cur_patch = patches;
6601 for (i = 0; i < address;) {
6603 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6605 if (skip_addr > i) {
6608 end_addr = MIN(address, skip_addr);
6609 address_offset += end_addr - i;
6615 address -= address_offset;
6616 fmt3_ins->address = address;
6625 if (fmt1_ins->parity != 0) {
6626 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6628 fmt1_ins->parity = 0;
6629 if ((ahc->features & AHC_CMD_CHAN) == 0
6630 && opcode == AIC_OP_BMOV) {
6632 * Block move was added at the same time
6633 * as the command channel. Verify that
6634 * this is only a move of a single element
6635 * and convert the BMOV to a MOV
6636 * (AND with an immediate of FF).
6638 if (fmt1_ins->immediate != 1)
6639 panic("%s: BMOV not supported\n",
6641 fmt1_ins->opcode = AIC_OP_AND;
6642 fmt1_ins->immediate = 0xff;
6646 if ((ahc->features & AHC_ULTRA2) != 0) {
6649 /* Calculate odd parity for the instruction */
6650 for (i = 0, count = 0; i < 31; i++) {
6654 if ((instr.integer & mask) != 0)
6657 if ((count & 0x01) == 0)
6658 instr.format1.parity = 1;
6660 /* Compress the instruction for older sequencers */
6661 if (fmt3_ins != NULL) {
6664 | (fmt3_ins->source << 8)
6665 | (fmt3_ins->address << 16)
6666 | (fmt3_ins->opcode << 25);
6670 | (fmt1_ins->source << 8)
6671 | (fmt1_ins->destination << 16)
6672 | (fmt1_ins->ret << 24)
6673 | (fmt1_ins->opcode << 25);
6676 /* The sequencer is a little endian cpu */
6677 instr.integer = aic_htole32(instr.integer);
6678 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6681 panic("Unknown opcode encountered in seq program");
6687 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6688 const char *name, u_int address, u_int value,
6689 u_int *cur_column, u_int wrap_point)
6695 if (cur_column == NULL) {
6697 cur_column = &dummy_column;
6700 if (*cur_column >= wrap_point) {
6704 printed = printf("%s[0x%x]", name, value);
6705 if (table == NULL) {
6706 printed += printf(" ");
6707 *cur_column += printed;
6711 while (printed_mask != 0xFF) {
6714 for (entry = 0; entry < num_entries; entry++) {
6715 if (((value & table[entry].mask)
6716 != table[entry].value)
6717 || ((printed_mask & table[entry].mask)
6718 == table[entry].mask))
6721 printed += printf("%s%s",
6722 printed_mask == 0 ? ":(" : "|",
6724 printed_mask |= table[entry].mask;
6728 if (entry >= num_entries)
6731 if (printed_mask != 0)
6732 printed += printf(") ");
6734 printed += printf(" ");
6735 if (cur_column != NULL)
6736 *cur_column += printed;
6741 ahc_dump_card_state(struct ahc_softc *ahc)
6744 struct scb_tailq *untagged_q;
6755 uint8_t saved_scbptr;
6757 if (ahc_is_paused(ahc)) {
6764 saved_scbptr = ahc_inb(ahc, SCBPTR);
6765 last_phase = ahc_inb(ahc, LASTPHASE);
6766 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6767 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6768 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6769 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6771 printf("Card was paused\n");
6772 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6773 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6774 ahc_inb(ahc, ARG_2));
6775 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6776 ahc_inb(ahc, SCBPTR));
6778 if ((ahc->features & AHC_DT) != 0)
6779 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6780 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6781 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6782 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6783 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6784 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6785 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6786 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6787 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6788 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6789 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6790 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6791 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6792 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6793 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6794 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6795 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6796 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6797 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6801 for (i = 0; i < STACK_SIZE; i++)
6802 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6803 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6804 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6805 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6807 printf("QINFIFO entries: ");
6808 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6809 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6810 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6812 qinpos = ahc_inb(ahc, QINPOS);
6813 qintail = ahc->qinfifonext;
6814 while (qinpos != qintail) {
6815 printf("%d ", ahc->qinfifo[qinpos]);
6820 printf("Waiting Queue entries: ");
6821 scb_index = ahc_inb(ahc, WAITING_SCBH);
6823 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6824 ahc_outb(ahc, SCBPTR, scb_index);
6825 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6826 scb_index = ahc_inb(ahc, SCB_NEXT);
6830 printf("Disconnected Queue entries: ");
6831 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6833 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6834 ahc_outb(ahc, SCBPTR, scb_index);
6835 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6836 scb_index = ahc_inb(ahc, SCB_NEXT);
6840 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6841 printf("QOUTFIFO entries: ");
6842 qoutpos = ahc->qoutfifonext;
6844 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6845 printf("%d ", ahc->qoutfifo[qoutpos]);
6850 printf("Sequencer Free SCB List: ");
6851 scb_index = ahc_inb(ahc, FREE_SCBH);
6853 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6854 ahc_outb(ahc, SCBPTR, scb_index);
6855 printf("%d ", scb_index);
6856 scb_index = ahc_inb(ahc, SCB_NEXT);
6860 printf("Sequencer SCB Info: ");
6861 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6862 ahc_outb(ahc, SCBPTR, i);
6863 cur_col = printf("\n%3d ", i);
6865 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6866 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6867 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6868 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6872 printf("Pending list: ");
6874 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6877 cur_col = printf("\n%3d ", scb->hscb->tag);
6878 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6879 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6880 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6881 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6882 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6884 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6886 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6892 printf("Kernel Free SCB list: ");
6894 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6897 printf("%d ", scb->hscb->tag);
6901 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6902 for (target = 0; target <= maxtarget; target++) {
6903 untagged_q = &ahc->untagged_queues[target];
6904 if (TAILQ_FIRST(untagged_q) == NULL)
6906 printf("Untagged Q(%d): ", target);
6908 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6911 printf("%d ", scb->hscb->tag);
6916 ahc_platform_dump_card_state(ahc);
6917 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6918 ahc_outb(ahc, SCBPTR, saved_scbptr);
6923 /*************************** Timeout Handling *********************************/
6925 ahc_timeout(struct scb *scb)
6927 struct ahc_softc *ahc;
6929 ahc = scb->ahc_softc;
6930 if ((scb->flags & SCB_ACTIVE) != 0) {
6931 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6932 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6934 scb->flags |= SCB_TIMEDOUT;
6936 ahc_wakeup_recovery_thread(ahc);
6941 * Re-schedule a timeout for the passed in SCB if we determine that some
6942 * other SCB is in the process of recovery or an SCB with a longer
6943 * timeout is still pending. Limit our search to just "other_scb"
6944 * if it is non-NULL.
6947 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6948 struct scb *other_scb)
6953 ahc_print_path(ahc, scb);
6954 printf("Other SCB Timeout%s",
6955 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6956 ? " again\n" : "\n");
6958 newtimeout = aic_get_timeout(scb);
6959 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6961 if (other_scb != NULL) {
6962 if ((other_scb->flags
6963 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6964 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6966 newtimeout = MAX(aic_get_timeout(other_scb),
6970 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6971 if ((other_scb->flags
6972 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6973 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6976 MAX(aic_get_timeout(other_scb),
6983 aic_scb_timer_reset(scb, newtimeout);
6985 ahc_print_path(ahc, scb);
6986 printf("No other SCB worth waiting for...\n");
6989 return (found != 0);
6993 * ahc_recover_commands determines if any of the commands that have currently
6994 * timedout are the root cause for this timeout. Innocent commands are given
6995 * a new timeout while we wait for the command executing on the bus to timeout.
6996 * This routine is invoked from a thread context so we are allowed to sleep.
6997 * Our lock is not held on entry.
7000 ahc_recover_commands(struct ahc_softc *ahc)
7008 * Pause the controller and manually flush any
7009 * commands that have just completed but that our
7010 * interrupt handler has yet to see.
7012 ahc_pause_and_flushwork(ahc);
7014 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
7016 * The timedout commands have already
7017 * completed. This typically means
7018 * that either the timeout value was on
7019 * the hairy edge of what the device
7020 * requires or - more likely - interrupts
7021 * are not happening.
7023 printf("%s: Timedout SCBs already complete. "
7024 "Interrupts may not be functioning.\n", ahc_name(ahc));
7030 printf("%s: Recovery Initiated\n", ahc_name(ahc));
7031 ahc_dump_card_state(ahc);
7033 last_phase = ahc_inb(ahc, LASTPHASE);
7034 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7035 u_int active_scb_index;
7042 target = SCB_GET_TARGET(ahc, scb);
7043 channel = SCB_GET_CHANNEL(ahc, scb);
7044 lun = SCB_GET_LUN(scb);
7046 ahc_print_path(ahc, scb);
7047 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7048 if (scb->sg_count > 0) {
7049 for (i = 0; i < scb->sg_count; i++) {
7050 printf("sg[%d] - Addr 0x%x : Length %d\n",
7052 scb->sg_list[i].addr,
7053 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7056 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7058 * Been down this road before.
7059 * Do a full bus reset.
7061 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7063 found = ahc_reset_channel(ahc, channel,
7064 /*Initiate Reset*/TRUE);
7065 printf("%s: Issued Channel %c Bus Reset. "
7066 "%d SCBs aborted\n", ahc_name(ahc), channel,
7072 * Remove the command from the timedout list in
7073 * preparation for requeing it.
7075 LIST_REMOVE(scb, timedout_links);
7076 scb->flags &= ~SCB_TIMEDOUT;
7079 * If we are a target, transition to bus free and report
7082 * The target/initiator that is holding up the bus may not
7083 * be the same as the one that triggered this timeout
7084 * (different commands have different timeout lengths).
7085 * If the bus is idle and we are actiing as the initiator
7086 * for this request, queue a BDR message to the timed out
7087 * target. Otherwise, if the timed out transaction is
7089 * Initiator transaction:
7090 * Stuff the message buffer with a BDR message and assert
7091 * ATN in the hopes that the target will let go of the bus
7092 * and go to the mesgout phase. If this fails, we'll
7093 * get another timeout 2 seconds later which will attempt
7096 * Target transaction:
7097 * Transition to BUS FREE and report the error.
7098 * It's good to be the target!
7100 saved_scbptr = ahc_inb(ahc, SCBPTR);
7101 active_scb_index = ahc_inb(ahc, SCB_TAG);
7103 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7104 && (active_scb_index < ahc->scb_data->numscbs)) {
7105 struct scb *active_scb;
7108 * If the active SCB is not us, assume that
7109 * the active SCB has a longer timeout than
7110 * the timedout SCB, and wait for the active
7113 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7114 if (active_scb != scb) {
7115 if (ahc_other_scb_timeout(ahc, scb,
7122 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7125 * Send back any queued up transactions
7126 * and properly record the error condition.
7128 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7129 SCB_GET_CHANNEL(ahc, scb),
7135 /* Will clear us from the bus */
7140 ahc_set_recoveryscb(ahc, active_scb);
7141 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7142 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7143 ahc_print_path(ahc, active_scb);
7144 printf("BDR message in message buffer\n");
7145 active_scb->flags |= SCB_DEVICE_RESET;
7146 aic_scb_timer_reset(scb, 2 * 1000);
7147 } else if (last_phase != P_BUSFREE
7148 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7150 * SCB is not identified, there
7151 * is no pending REQ, and the sequencer
7152 * has not seen a busfree. Looks like
7153 * a stuck connection waiting to
7154 * go busfree. Reset the bus.
7156 printf("%s: Connection stuck awaiting busfree or "
7157 "Identify Msg.\n", ahc_name(ahc));
7162 if (last_phase != P_BUSFREE
7163 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7164 /* Hung target selection. Goto busfree */
7165 printf("%s: Hung target selection\n",
7171 /* XXX Shouldn't panic. Just punt instead? */
7172 if ((scb->flags & SCB_TARGET_SCB) != 0)
7173 panic("Timed-out target SCB but bus idle");
7175 if (ahc_search_qinfifo(ahc, target, channel, lun,
7176 scb->hscb->tag, ROLE_INITIATOR,
7177 /*status*/0, SEARCH_COUNT) > 0) {
7178 disconnected = FALSE;
7180 disconnected = TRUE;
7185 ahc_set_recoveryscb(ahc, scb);
7187 * Actually re-queue this SCB in an attempt
7188 * to select the device before it reconnects.
7189 * In either case (selection or reselection),
7190 * we will now issue a target reset to the
7193 * Set the MK_MESSAGE control bit indicating
7194 * that we desire to send a message. We
7195 * also set the disconnected flag since
7196 * in the paging case there is no guarantee
7197 * that our SCB control byte matches the
7198 * version on the card. We don't want the
7199 * sequencer to abort the command thinking
7200 * an unsolicited reselection occurred.
7202 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7203 scb->flags |= SCB_DEVICE_RESET;
7206 * Remove any cached copy of this SCB in the
7207 * disconnected list in preparation for the
7208 * queuing of our abort SCB. We use the
7209 * same element in the SCB, SCB_NEXT, for
7210 * both the qinfifo and the disconnected list.
7212 ahc_search_disc_list(ahc, target, channel,
7213 lun, scb->hscb->tag,
7214 /*stop_on_first*/TRUE,
7216 /*save_state*/FALSE);
7219 * In the non-paging case, the sequencer will
7220 * never re-reference the in-core SCB.
7221 * To make sure we are notified during
7222 * reslection, set the MK_MESSAGE flag in
7223 * the card's copy of the SCB.
7225 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7226 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7227 ahc_outb(ahc, SCB_CONTROL,
7228 ahc_inb(ahc, SCB_CONTROL)
7233 * Clear out any entries in the QINFIFO first
7234 * so we are the next SCB for this target
7237 ahc_search_qinfifo(ahc,
7238 SCB_GET_TARGET(ahc, scb),
7239 channel, SCB_GET_LUN(scb),
7244 ahc_print_path(ahc, scb);
7245 printf("Queuing a BDR SCB\n");
7246 ahc_qinfifo_requeue_tail(ahc, scb);
7247 ahc_outb(ahc, SCBPTR, saved_scbptr);
7248 aic_scb_timer_reset(scb, 2 * 1000);
7250 /* Go "immediatly" to the bus reset */
7251 /* This shouldn't happen */
7252 ahc_set_recoveryscb(ahc, scb);
7253 ahc_print_path(ahc, scb);
7254 printf("SCB %d: Immediate reset. "
7255 "Flags = 0x%x\n", scb->hscb->tag,
7264 * Any remaining SCBs were not the "culprit", so remove
7265 * them from the timeout list. The timer for these commands
7266 * will be reset once the recovery SCB completes.
7268 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7270 LIST_REMOVE(scb, timedout_links);
7271 scb->flags &= ~SCB_TIMEDOUT;
7280 /************************* Target Mode ****************************************/
7281 #ifdef AHC_TARGET_MODE
7283 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7284 struct ahc_tmode_tstate **tstate,
7285 struct ahc_tmode_lstate **lstate,
7286 int notfound_failure)
7289 if ((ahc->features & AHC_TARGETMODE) == 0)
7290 return (CAM_REQ_INVALID);
7293 * Handle the 'black hole' device that sucks up
7294 * requests to unattached luns on enabled targets.
7296 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7297 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7299 *lstate = ahc->black_hole;
7303 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7304 if (ccb->ccb_h.target_id > max_id)
7305 return (CAM_TID_INVALID);
7307 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7308 return (CAM_LUN_INVALID);
7310 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7312 if (*tstate != NULL)
7314 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7317 if (notfound_failure != 0 && *lstate == NULL)
7318 return (CAM_PATH_INVALID);
7320 return (CAM_REQ_CMP);
7324 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7326 struct ahc_tmode_tstate *tstate;
7327 struct ahc_tmode_lstate *lstate;
7328 struct ccb_en_lun *cel;
7337 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7338 /*notfound_failure*/FALSE);
7340 if (status != CAM_REQ_CMP) {
7341 ccb->ccb_h.status = status;
7345 if (cam_sim_bus(sim) == 0)
7346 our_id = ahc->our_id;
7348 our_id = ahc->our_id_b;
7350 if (ccb->ccb_h.target_id != our_id) {
7352 * our_id represents our initiator ID, or
7353 * the ID of the first target to have an
7354 * enabled lun in target mode. There are
7355 * two cases that may preclude enabling a
7356 * target id other than our_id.
7358 * o our_id is for an active initiator role.
7359 * Since the hardware does not support
7360 * reselections to the initiator role at
7361 * anything other than our_id, and our_id
7362 * is used by the hardware to indicate the
7363 * ID to use for both select-out and
7364 * reselect-out operations, the only target
7365 * ID we can support in this mode is our_id.
7367 * o The MULTARGID feature is not available and
7368 * a previous target mode ID has been enabled.
7370 if ((ahc->features & AHC_MULTIROLE) != 0) {
7372 if ((ahc->features & AHC_MULTI_TID) != 0
7373 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7375 * Only allow additional targets if
7376 * the initiator role is disabled.
7377 * The hardware cannot handle a re-select-in
7378 * on the initiator id during a re-select-out
7379 * on a different target id.
7381 status = CAM_TID_INVALID;
7382 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7383 || ahc->enabled_luns > 0) {
7385 * Only allow our target id to change
7386 * if the initiator role is not configured
7387 * and there are no enabled luns which
7388 * are attached to the currently registered
7391 status = CAM_TID_INVALID;
7393 } else if ((ahc->features & AHC_MULTI_TID) == 0
7394 && ahc->enabled_luns > 0) {
7396 status = CAM_TID_INVALID;
7400 if (status != CAM_REQ_CMP) {
7401 ccb->ccb_h.status = status;
7406 * We now have an id that is valid.
7407 * If we aren't in target mode, switch modes.
7409 if ((ahc->flags & AHC_TARGETROLE) == 0
7410 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7411 ahc_flag saved_flags;
7413 printf("Configuring Target Mode\n");
7414 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7415 ccb->ccb_h.status = CAM_BUSY;
7418 saved_flags = ahc->flags;
7419 ahc->flags |= AHC_TARGETROLE;
7420 if ((ahc->features & AHC_MULTIROLE) == 0)
7421 ahc->flags &= ~AHC_INITIATORROLE;
7423 error = ahc_loadseq(ahc);
7426 * Restore original configuration and notify
7427 * the caller that we cannot support target mode.
7428 * Since the adapter started out in this
7429 * configuration, the firmware load will succeed,
7430 * so there is no point in checking ahc_loadseq's
7433 ahc->flags = saved_flags;
7434 (void)ahc_loadseq(ahc);
7436 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7442 target = ccb->ccb_h.target_id;
7443 lun = ccb->ccb_h.target_lun;
7444 channel = SIM_CHANNEL(ahc, sim);
7445 target_mask = 0x01 << target;
7449 if (cel->enable != 0) {
7452 /* Are we already enabled?? */
7453 if (lstate != NULL) {
7454 xpt_print_path(ccb->ccb_h.path);
7455 printf("Lun already enabled\n");
7456 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7460 if (cel->grp6_len != 0
7461 || cel->grp7_len != 0) {
7463 * Don't (yet?) support vendor
7464 * specific commands.
7466 ccb->ccb_h.status = CAM_REQ_INVALID;
7467 printf("Non-zero Group Codes\n");
7473 * Setup our data structures.
7475 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7476 tstate = ahc_alloc_tstate(ahc, target, channel);
7477 if (tstate == NULL) {
7478 xpt_print_path(ccb->ccb_h.path);
7479 printf("Couldn't allocate tstate\n");
7480 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7484 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7485 if (lstate == NULL) {
7486 xpt_print_path(ccb->ccb_h.path);
7487 printf("Couldn't allocate lstate\n");
7488 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7491 memset(lstate, 0, sizeof(*lstate));
7492 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7493 xpt_path_path_id(ccb->ccb_h.path),
7494 xpt_path_target_id(ccb->ccb_h.path),
7495 xpt_path_lun_id(ccb->ccb_h.path));
7496 if (status != CAM_REQ_CMP) {
7497 free(lstate, M_DEVBUF);
7498 xpt_print_path(ccb->ccb_h.path);
7499 printf("Couldn't allocate path\n");
7500 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7503 SLIST_INIT(&lstate->accept_tios);
7504 SLIST_INIT(&lstate->immed_notifies);
7506 if (target != CAM_TARGET_WILDCARD) {
7507 tstate->enabled_luns[lun] = lstate;
7508 ahc->enabled_luns++;
7510 if ((ahc->features & AHC_MULTI_TID) != 0) {
7513 targid_mask = ahc_inb(ahc, TARGID)
7514 | (ahc_inb(ahc, TARGID + 1) << 8);
7516 targid_mask |= target_mask;
7517 ahc_outb(ahc, TARGID, targid_mask);
7518 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7520 ahc_update_scsiid(ahc, targid_mask);
7525 channel = SIM_CHANNEL(ahc, sim);
7526 our_id = SIM_SCSI_ID(ahc, sim);
7529 * This can only happen if selections
7532 if (target != our_id) {
7537 sblkctl = ahc_inb(ahc, SBLKCTL);
7538 cur_channel = (sblkctl & SELBUSB)
7540 if ((ahc->features & AHC_TWIN) == 0)
7542 swap = cur_channel != channel;
7544 ahc->our_id = target;
7546 ahc->our_id_b = target;
7549 ahc_outb(ahc, SBLKCTL,
7552 ahc_outb(ahc, SCSIID, target);
7555 ahc_outb(ahc, SBLKCTL, sblkctl);
7559 ahc->black_hole = lstate;
7560 /* Allow select-in operations */
7561 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7562 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7564 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7565 scsiseq = ahc_inb(ahc, SCSISEQ);
7567 ahc_outb(ahc, SCSISEQ, scsiseq);
7570 ccb->ccb_h.status = CAM_REQ_CMP;
7571 xpt_print_path(ccb->ccb_h.path);
7572 printf("Lun now enabled for target mode\n");
7577 if (lstate == NULL) {
7578 ccb->ccb_h.status = CAM_LUN_INVALID;
7582 ccb->ccb_h.status = CAM_REQ_CMP;
7583 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7584 struct ccb_hdr *ccbh;
7586 ccbh = &scb->io_ctx->ccb_h;
7587 if (ccbh->func_code == XPT_CONT_TARGET_IO
7588 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7589 printf("CTIO pending\n");
7590 ccb->ccb_h.status = CAM_REQ_INVALID;
7595 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7596 printf("ATIOs pending\n");
7597 ccb->ccb_h.status = CAM_REQ_INVALID;
7600 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7601 printf("INOTs pending\n");
7602 ccb->ccb_h.status = CAM_REQ_INVALID;
7605 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7609 xpt_print_path(ccb->ccb_h.path);
7610 printf("Target mode disabled\n");
7611 xpt_free_path(lstate->path);
7612 free(lstate, M_DEVBUF);
7615 /* Can we clean up the target too? */
7616 if (target != CAM_TARGET_WILDCARD) {
7617 tstate->enabled_luns[lun] = NULL;
7618 ahc->enabled_luns--;
7619 for (empty = 1, i = 0; i < 8; i++)
7620 if (tstate->enabled_luns[i] != NULL) {
7626 ahc_free_tstate(ahc, target, channel,
7628 if (ahc->features & AHC_MULTI_TID) {
7631 targid_mask = ahc_inb(ahc, TARGID)
7632 | (ahc_inb(ahc, TARGID + 1)
7635 targid_mask &= ~target_mask;
7636 ahc_outb(ahc, TARGID, targid_mask);
7637 ahc_outb(ahc, TARGID+1,
7638 (targid_mask >> 8));
7639 ahc_update_scsiid(ahc, targid_mask);
7644 ahc->black_hole = NULL;
7647 * We can't allow selections without
7648 * our black hole device.
7652 if (ahc->enabled_luns == 0) {
7653 /* Disallow select-in */
7656 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7658 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7659 scsiseq = ahc_inb(ahc, SCSISEQ);
7661 ahc_outb(ahc, SCSISEQ, scsiseq);
7663 if ((ahc->features & AHC_MULTIROLE) == 0) {
7664 printf("Configuring Initiator Mode\n");
7665 ahc->flags &= ~AHC_TARGETROLE;
7666 ahc->flags |= AHC_INITIATORROLE;
7668 * Returning to a configuration that
7669 * fit previously will always succeed.
7671 (void)ahc_loadseq(ahc);
7674 * Unpaused. The extra unpause
7675 * that follows is harmless.
7684 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7689 if ((ahc->features & AHC_MULTI_TID) == 0)
7690 panic("ahc_update_scsiid called on non-multitid unit\n");
7693 * Since we will rely on the TARGID mask
7694 * for selection enables, ensure that OID
7695 * in SCSIID is not set to some other ID
7696 * that we don't want to allow selections on.
7698 if ((ahc->features & AHC_ULTRA2) != 0)
7699 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7701 scsiid = ahc_inb(ahc, SCSIID);
7702 scsiid_mask = 0x1 << (scsiid & OID);
7703 if ((targid_mask & scsiid_mask) == 0) {
7706 /* ffs counts from 1 */
7707 our_id = ffs(targid_mask);
7709 our_id = ahc->our_id;
7715 if ((ahc->features & AHC_ULTRA2) != 0)
7716 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7718 ahc_outb(ahc, SCSIID, scsiid);
7722 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7724 struct target_cmd *cmd;
7727 * If the card supports auto-access pause,
7728 * we can access the card directly regardless
7729 * of whether it is paused or not.
7731 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7734 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7735 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7738 * Only advance through the queue if we
7739 * have the resources to process the command.
7741 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7745 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7746 ahc->shared_data_dmamap,
7747 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7748 sizeof(struct target_cmd),
7749 BUS_DMASYNC_PREREAD);
7750 ahc->tqinfifonext++;
7753 * Lazily update our position in the target mode incoming
7754 * command queue as seen by the sequencer.
7756 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7757 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7760 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7761 hs_mailbox &= ~HOST_TQINPOS;
7762 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7763 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7767 ahc_outb(ahc, KERNEL_TQINPOS,
7768 ahc->tqinfifonext & HOST_TQINPOS);
7777 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7779 struct ahc_tmode_tstate *tstate;
7780 struct ahc_tmode_lstate *lstate;
7781 struct ccb_accept_tio *atio;
7787 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7788 target = SCSIID_OUR_ID(cmd->scsiid);
7789 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7792 tstate = ahc->enabled_targets[target];
7795 lstate = tstate->enabled_luns[lun];
7798 * Commands for disabled luns go to the black hole driver.
7801 lstate = ahc->black_hole;
7803 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7805 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7807 * Wait for more ATIOs from the peripheral driver for this lun.
7810 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7813 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7815 if (ahc_debug & AHC_SHOW_TQIN) {
7816 printf("Incoming command from %d for %d:%d%s\n",
7817 initiator, target, lun,
7818 lstate == ahc->black_hole ? "(Black Holed)" : "");
7821 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7823 if (lstate == ahc->black_hole) {
7824 /* Fill in the wildcards */
7825 atio->ccb_h.target_id = target;
7826 atio->ccb_h.target_lun = lun;
7830 * Package it up and send it off to
7831 * whomever has this lun enabled.
7833 atio->sense_len = 0;
7834 atio->init_id = initiator;
7835 if (byte[0] != 0xFF) {
7836 /* Tag was included */
7837 atio->tag_action = *byte++;
7838 atio->tag_id = *byte++;
7839 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
7841 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
7845 /* Okay. Now determine the cdb size based on the command code */
7846 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7862 /* Only copy the opcode. */
7864 printf("Reserved or VU command code type encountered\n");
7868 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7870 atio->ccb_h.status |= CAM_CDB_RECVD;
7872 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7874 * We weren't allowed to disconnect.
7875 * We're hanging on the bus until a
7876 * continue target I/O comes in response
7877 * to this accept tio.
7880 if (ahc_debug & AHC_SHOW_TQIN) {
7881 printf("Received Immediate Command %d:%d:%d - %p\n",
7882 initiator, target, lun, ahc->pending_device);
7885 ahc->pending_device = lstate;
7886 aic_freeze_ccb((union ccb *)atio);
7887 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7889 xpt_done((union ccb*)atio);