2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
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15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#50 $"
44 PATCH_ARG_LIST = "struct ahc_softc *ahc"
47 #include "aic7xxx.reg"
48 #include "scsi_message.h"
51 * A few words on the waiting SCB list:
52 * After starting the selection hardware, we check for reconnecting targets
53 * as well as for our selection to complete just in case the reselection wins
54 * bus arbitration. The problem with this is that we must keep track of the
55 * SCB that we've already pulled from the QINFIFO and started the selection
56 * on just in case the reselection wins so that we can retry the selection at
57 * a later time. This problem cannot be resolved by holding a single entry
58 * in scratch ram since a reconnecting target can request sense and this will
59 * create yet another SCB waiting for selection. The solution used here is to
60 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list
61 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
62 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
63 * this list everytime a request sense occurs or after completing a non-tagged
64 * command for which a second SCB has been queued. The sequencer will
65 * automatically consume the entries.
70 * Turn off the selection hardware. We need to reset the
71 * selection request in order to perform a new selection.
73 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
74 and SIMODE1, ~ENBUSFREE;
76 call clear_target_state;
77 and SXFRCTL0, ~SPIOEN;
78 if ((ahc->features & AHC_ULTRA2) != 0) {
81 test SCSISEQ, ENSELO jnz poll_for_selection;
82 if ((ahc->features & AHC_TWIN) != 0) {
83 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
84 test SCSISEQ, ENSELO jnz poll_for_selection;
86 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
88 if ((ahc->features & AHC_TWIN) != 0) {
89 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
91 test SSTAT0, SELDO|SELDI jnz selection;
93 /* Has the driver posted any work for us? */
95 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
96 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
99 cmp KERNEL_QINPOS, A je poll_for_work_loop;
101 mov ARG_1, NEXT_QUEUED_SCB;
104 * We have at least one queued SCB now and we don't have any
105 * SCBs in the list of SCBs awaiting selection. Allocate a
106 * card SCB for the host's SCB and get to work on it.
108 if ((ahc->flags & AHC_PAGESCBS) != 0) {
109 mov ALLZEROS call get_free_or_disc_scb;
111 /* In the non-paging case, the SCBID == hardware SCB index */
114 or SEQ_FLAGS2, SCB_DMA;
118 * DMA the SCB from host ram into the current SCB location.
120 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
121 mov ARG_1 call dma_scb;
123 * Check one last time to see if this SCB was canceled
124 * before we completed the DMA operation. If it was,
125 * the QINFIFO next pointer will not match our saved
130 cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
131 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
132 cmp SCB_TAG, A je . + 2;
133 mvi SCB_MISMATCH call set_seqint;
135 mov NEXT_QUEUED_SCB, SCB_NEXT;
136 mov SCB_NEXT,WAITING_SCBH;
137 mov WAITING_SCBH, SCBPTR;
138 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
139 mov NONE, SNSCB_QOFF;
143 and SEQ_FLAGS2, ~SCB_DMA;
147 * Start the first entry on the waiting SCB list.
149 mov SCBPTR, WAITING_SCBH;
150 call start_selection;
154 * Twin channel devices cannot handle things like SELTO
155 * interrupts on the "background" channel. So, while
156 * selecting, keep polling the current channel until
157 * either a selection or reselection occurs.
159 test SSTAT0, SELDO|SELDI jz poll_for_selection;
163 * We aren't expecting a bus free, so interrupt
164 * the kernel driver if it happens.
166 mvi CLRSINT1,CLRBUSFREE;
167 if ((ahc->features & AHC_DT) == 0) {
168 or SIMODE1, ENBUSFREE;
172 * Guard against a bus free after (re)selection
173 * but prior to enabling the busfree interrupt. SELDI
174 * and SELDO will be cleared in that case.
176 test SSTAT0, SELDI|SELDO jz bus_free_sel;
177 test SSTAT0,SELDO jnz select_out;
179 if ((ahc->flags & AHC_TARGETROLE) != 0) {
180 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
181 test SSTAT0, TARGET jz initiator_reselect;
183 mvi CLRSINT0, CLRSELDI;
186 * We've just been selected. Assert BSY and
187 * setup the phase for receiving messages
190 mvi SCSISIGO, P_MESGOUT|BSYO;
193 * Setup the DMA for sending the identify and
194 * command information.
196 or SEQ_FLAGS, CMDPHASE_PENDING;
199 if ((ahc->features & AHC_CMD_CHAN) != 0) {
201 mvi SHARED_DATA_ADDR call set_32byte_addr;
202 mvi CCSCBCTL, CCSCBRESET;
205 mvi SHARED_DATA_ADDR call set_32byte_addr;
206 mvi DFCNTRL, FIFORESET;
209 /* Initiator that selected us */
210 and SAVED_SCSIID, SELID_MASK, SELID;
211 /* The Target ID we were selected at */
212 if ((ahc->features & AHC_MULTI_TID) != 0) {
213 and A, OID, TARGIDIN;
214 } else if ((ahc->features & AHC_ULTRA2) != 0) {
215 and A, OID, SCSIID_ULTRA2;
220 if ((ahc->features & AHC_TWIN) != 0) {
221 test SBLKCTL, SELBUSB jz . + 2;
222 or SAVED_SCSIID, TWIN_CHNLB;
224 if ((ahc->features & AHC_CMD_CHAN) != 0) {
225 mov CCSCBRAM, SAVED_SCSIID;
227 mov DFDAT, SAVED_SCSIID;
231 * If ATN isn't asserted, the target isn't interested
232 * in talking to us. Go directly to bus free.
233 * XXX SCSI-1 may require us to assume lun 0 if
236 test SCSISIGI, ATNI jz target_busfree;
239 * Watch ATN closely now as we pull in messages from the
240 * initiator. We follow the guidlines from section 6.5
241 * of the SCSI-2 spec for what messages are allowed when.
246 * Our first message must be one of IDENTIFY, ABORT, or
249 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
251 if ((ahc->features & AHC_CMD_CHAN) != 0) {
252 mov CCSCBRAM, DINDEX;
256 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
258 /* Remember for disconnection decision */
259 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
260 /* XXX Honor per target settings too */
261 or SEQ_FLAGS, NO_DISCONNECT;
263 test SCSISIGI, ATNI jz ident_messages_done;
266 * If this is a tagged request, the tagged message must
267 * immediately follow the identify. We test for a valid
268 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
269 * < MSG_IGN_WIDE_RESIDUE.
271 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
272 jnc ident_messages_done_msg_pending;
273 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
274 jc ident_messages_done_msg_pending;
277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
278 mov CCSCBRAM, DINDEX;
284 * If the initiator doesn't feel like providing a tag number,
285 * we've got a failed selection and must transition to bus
288 test SCSISIGI, ATNI jz target_busfree;
291 * Store the tag for the host.
294 if ((ahc->features & AHC_CMD_CHAN) != 0) {
295 mov CCSCBRAM, DINDEX;
299 mov INITIATOR_TAG, DINDEX;
300 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
303 /* Terminate the ident list */
304 if ((ahc->features & AHC_CMD_CHAN) != 0) {
305 mvi CCSCBRAM, SCB_LIST_NULL;
307 mvi DFDAT, SCB_LIST_NULL;
309 or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN;
310 test SEQ_FLAGS2, TARGET_MSG_PENDING
311 jnz target_mesgout_pending;
312 test SCSISIGI, ATNI jnz target_mesgout_continue;
316 ident_messages_done_msg_pending:
317 or SEQ_FLAGS2, TARGET_MSG_PENDING;
318 jmp ident_messages_done;
321 * Pushed message loop to allow the kernel to
322 * run it's own target mode message state engine.
324 host_target_message_loop:
325 mvi HOST_MSG_LOOP call set_seqint;
326 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
327 test SSTAT0, SPIORDY jz .;
328 jmp host_target_message_loop;
331 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
333 * Reselection has been initiated by a target. Make a note that we've been
334 * reselected, but haven't seen an IDENTIFY message from the target yet.
337 /* XXX test for and handle ONE BIT condition */
338 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
339 and SAVED_SCSIID, SELID_MASK, SELID;
340 if ((ahc->features & AHC_ULTRA2) != 0) {
341 and A, OID, SCSIID_ULTRA2;
346 if ((ahc->features & AHC_TWIN) != 0) {
347 test SBLKCTL, SELBUSB jz . + 2;
348 or SAVED_SCSIID, TWIN_CHNLB;
350 mvi CLRSINT0, CLRSELDI;
355 call add_scb_to_free_list;
356 jmp poll_for_work_loop;
360 * If bus reset interrupts have been disabled (from a previous
361 * reset), re-enable them now. Resets are only of interest
362 * when we have outstanding transactions, so we can safely
363 * defer re-enabling the interrupt until, as an initiator,
364 * we start sending out transactions again.
366 test SIMODE1, ENSCSIRST jnz . + 3;
367 mvi CLRSINT1, CLRSCSIRSTI;
368 or SIMODE1, ENSCSIRST;
369 if ((ahc->features & AHC_TWIN) != 0) {
370 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
371 test SCB_SCSIID, TWIN_CHNLB jz . + 2;
373 mov SBLKCTL,SINDEX; /* select channel */
376 if ((ahc->features & AHC_ULTRA2) != 0) {
377 mov SCSIID_ULTRA2, SCB_SCSIID;
378 } else if ((ahc->features & AHC_TWIN) != 0) {
379 and SCSIID, TWIN_TID|OID, SCB_SCSIID;
381 mov SCSIID, SCB_SCSIID;
383 if ((ahc->flags & AHC_TARGETROLE) != 0) {
384 mov SINDEX, SCSISEQ_TEMPLATE;
385 test SCB_CONTROL, TARGET_SCB jz . + 2;
387 mov SCSISEQ, SINDEX ret;
389 mov SCSISEQ, SCSISEQ_TEMPLATE ret;
393 * Initialize transfer settings with SCB provided settings.
395 set_transfer_settings:
396 if ((ahc->features & AHC_ULTRA) != 0) {
397 test SCB_CONTROL, ULTRAENB jz . + 2;
401 * Initialize SCSIRATE with the appropriate value for this target.
403 if ((ahc->features & AHC_ULTRA2) != 0) {
404 bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
406 mov SCSIRATE, SCB_SCSIRATE ret;
409 if ((ahc->flags & AHC_TARGETROLE) != 0) {
411 * We carefully toggle SPIOEN to allow us to return the
412 * message byte we receive so it can be checked prior to
413 * driving REQ on the bus for the next byte.
417 * Drive REQ on the bus by enabling SCSI PIO.
420 /* Wait for the byte */
421 test SSTAT0, SPIORDY jz .;
422 /* Prevent our read from triggering another REQ */
423 and SXFRCTL0, ~SPIOEN;
424 /* Save latched contents */
425 mov DINDEX, SCSIDATL ret;
429 * After the selection, remove this SCB from the "waiting SCB"
430 * list. This is achieved by simply moving our "next" pointer into
431 * WAITING_SCBH. Our next pointer will be set to null the next time this
432 * SCB is used, so don't bother with it now.
435 /* Turn off the selection hardware */
436 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
437 mov SCBPTR, WAITING_SCBH;
438 mov WAITING_SCBH,SCB_NEXT;
439 mov SAVED_SCSIID, SCB_SCSIID;
440 mov SAVED_LUN, SCB_LUN;
441 call set_transfer_settings;
442 if ((ahc->flags & AHC_TARGETROLE) != 0) {
443 test SSTAT0, TARGET jz initiator_select;
445 or SXFRCTL0, CLRSTCNT|CLRCHN;
448 * Put tag in connonical location since not
449 * all connections have an SCB.
451 mov INITIATOR_TAG, SCB_TARGET_ITAG;
454 * We've just re-selected an initiator.
455 * Assert BSY and setup the phase for
456 * sending our identify messages.
458 mvi P_MESGIN|BSYO call change_phase;
459 mvi CLRSINT0, CLRSELDO;
462 * Start out with a simple identify message.
464 or SCB_LUN, MSG_IDENTIFYFLAG call target_outb;
467 * If we are the result of a tagged command, send
468 * a simple Q tag and the tag id.
470 test SCB_CONTROL, TAG_ENB jz . + 3;
471 mvi MSG_SIMPLE_Q_TAG call target_outb;
472 mov SCB_TARGET_ITAG call target_outb;
475 * Now determine what phases the host wants us
478 mov SEQ_FLAGS, SCB_TARGET_PHASES;
480 test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
481 mvi P_MESGIN|BSYO call change_phase;
482 jmp host_target_message_loop;
485 * Start honoring ATN signals now that
486 * we properly identified ourselves.
488 test SCSISIGI, ATNI jnz target_mesgout;
489 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
490 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
491 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
494 * No more work to do. Either disconnect or not depending
495 * on the state of NO_DISCONNECT.
497 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
498 mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL;
499 call complete_target_cmd;
500 if ((ahc->flags & AHC_PAGESCBS) != 0) {
501 mov ALLZEROS call get_free_or_disc_scb;
503 cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .;
504 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
505 mov TARG_IMMEDIATE_SCB call dma_scb;
506 call set_transfer_settings;
507 or SXFRCTL0, CLRSTCNT|CLRCHN;
511 mvi SCSISIGO, P_MESGOUT|BSYO;
512 target_mesgout_continue:
514 target_mesgout_pending:
515 /* Local Processing goes here... */
516 jmp host_target_message_loop;
519 mvi P_MESGIN|BSYO call change_phase;
520 test SEQ_FLAGS, DPHASE jz . + 2;
521 mvi MSG_SAVEDATAPOINTER call target_outb;
522 mvi MSG_DISCONNECT call target_outb;
525 /* Wait for preceding I/O session to complete. */
526 test SCSISIGI, ACKI jnz .;
528 and SIMODE1, ~ENBUSFREE;
529 if ((ahc->features & AHC_ULTRA2) != 0) {
533 mvi LASTPHASE, P_BUSFREE;
534 call complete_target_cmd;
539 * The target has dropped ATN (doesn't want to abort or BDR)
540 * and we believe this selection to be valid. If the ring
541 * buffer for new commands is full, return busy or queue full.
543 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
544 and A, HOST_TQINPOS, HS_MAILBOX;
546 mov A, KERNEL_TQINPOS;
548 cmp TQINPOS, A jne tqinfifo_has_space;
549 mvi P_STATUS|BSYO call change_phase;
550 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
551 mvi STATUS_QUEUE_FULL call target_outb;
552 jmp target_busfree_wait;
553 mvi STATUS_BUSY call target_outb;
554 jmp target_busfree_wait;
556 mvi P_COMMAND|BSYO call change_phase;
560 if ((ahc->features & AHC_CMD_CHAN) != 0) {
567 * Determine the number of bytes to read
568 * based on the command group code via table lookup.
569 * We reuse the first 8 bytes of the TARG_SCSIRATE
570 * BIOS array for this table. Count is one less than
571 * the total for the command since we've already fetched
574 shr A, CMD_GROUP_CODE_SHIFT;
575 add SINDEX, CMDSIZE_TABLE, A;
578 test A, 0xFF jz command_phase_done;
581 test SSTAT0, SPIORDY jz .;
583 and SXFRCTL0, ~SPIOEN; /* Last Byte */
584 if ((ahc->features & AHC_CMD_CHAN) != 0) {
585 mov CCSCBRAM, SCSIDATL;
590 test A, 0xFF jnz command_loop;
593 and SEQ_FLAGS, ~CMDPHASE_PENDING;
598 * Data phases on the bus are from the
599 * perspective of the initiator. The dma
600 * code looks at LASTPHASE to determine the
601 * data direction of the DMA. Toggle it for
604 xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
605 or SCB_TARGET_DATA_DIR, BSYO call change_phase;
609 mvi P_STATUS|BSYO call change_phase;
610 mvi LASTPHASE, P_STATUS;
611 mov SCB_SCSI_STATUS call target_outb;
612 /* XXX Watch for ATN or parity errors??? */
613 mvi SCSISIGO, P_MESGIN|BSYO;
614 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
615 mov ALLZEROS call target_outb;
616 jmp target_busfree_wait;
619 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
620 mov SCB_TAG jmp complete_post;
621 if ((ahc->features & AHC_CMD_CHAN) != 0) {
622 /* Set the valid byte */
624 mov CCSCBRAM, ALLONES;
626 or CCSCBCTL, CCSCBEN|CCSCBRESET;
627 test CCSCBCTL, CCSCBDONE jz .;
630 /* Set the valid byte */
631 or DFCNTRL, FIFORESET;
632 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
634 mvi 28 call set_hcnt;
635 or DFCNTRL, HDMAEN|FIFOFLUSH;
639 mvi INTSTAT,CMDCMPLT ret;
642 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
644 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
646 * As soon as we get a successful selection, the target
647 * should go into the message out phase since we have ATN
650 mvi MSG_OUT, MSG_IDENTIFYFLAG;
651 or SEQ_FLAGS, IDENTIFY_SEEN;
652 mvi CLRSINT0, CLRSELDO;
655 * Main loop for information transfer phases. Wait for the
656 * target to assert REQ before checking MSG, C/D and I/O for
665 test A, ~P_DATAIN jz p_data;
666 cmp A,P_COMMAND je p_command;
667 cmp A,P_MESGOUT je p_mesgout;
668 cmp A,P_STATUS je p_status;
669 cmp A,P_MESGIN je p_mesgin;
671 mvi BAD_PHASE call set_seqint;
672 jmp ITloop; /* Try reading the bus again. */
675 and SIMODE1, ~ENBUSFREE;
676 mov NONE, SCSIDATL; /* Ack the last byte */
677 if ((ahc->features & AHC_ULTRA2) != 0) {
678 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
680 and SXFRCTL0, ~SPIOEN;
681 test SSTAT1,REQINIT|BUSFREE jz .;
682 test SSTAT1, BUSFREE jnz poll_for_work;
683 mvi MISSED_BUSFREE call set_seqint;
688 * We assume that the kernel driver may reset us
689 * at any time, even in the middle of a DMA, so
693 or SXFRCTL0, CLRSTCNT|CLRCHN;
696 * We don't know the target we will connect to,
697 * so default to narrow transfers to avoid
700 if ((ahc->features & AHC_ULTRA2) != 0) {
701 bmov SCSIRATE, ALLZEROS, 2;
704 if ((ahc->features & AHC_ULTRA) != 0) {
705 and SXFRCTL0, ~(FAST20);
708 mvi LASTPHASE, P_BUSFREE;
709 /* clear target specific flags */
713 clr A; /* add sizeof(struct scatter) */
714 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
715 adc SCB_RESIDUAL_SGPTR[1],A;
716 adc SCB_RESIDUAL_SGPTR[2],A;
717 adc SCB_RESIDUAL_SGPTR[3],A ret;
719 if ((ahc->features & AHC_CMD_CHAN) != 0) {
721 test CCSGCTL, CCSGEN jz return;
722 test CCSGCTL, CCSGDONE jz .;
723 disable_ccsgen_fetch_done:
725 test CCSGCTL, CCSGEN jnz .;
729 * Do we need any more segments for this transfer?
731 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
733 /* Did we just finish fetching segs? */
734 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
736 /* Are we actively fetching segments? */
737 test CCSGCTL, CCSGEN jnz return;
740 * Do we have any prefetch left???
742 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
745 * Need to fetch segments, but we can only do that
746 * if the command channel is completely idle. Make
747 * sure we don't have an SCB prefetch going on.
749 test CCSCBCTL, CCSCBEN jnz return;
752 * We fetch a "cacheline aligned" and sized amount of data
753 * so we don't end up referencing a non-existant page.
754 * Cacheline aligned is in quotes because the kernel will
755 * set the prefetch amount to a reasonable level if the
756 * cacheline size is unknown.
758 mvi CCHCNT, SG_PREFETCH_CNT;
759 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
760 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
761 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
762 idle_sgfetch_complete:
763 call disable_ccsgen_fetch_done;
764 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
766 if ((ahc->features & AHC_ULTRA2) != 0) {
767 /* Does the hardware have space for another SG entry? */
768 test DFSTATUS, PRELOAD_AVAIL jz return;
769 bmov HADDR, CCSGRAM, 7;
770 test HCNT[0], 0x1 jz . + 2;
771 xor DATA_COUNT_ODD, 0x1;
772 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
773 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
774 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
777 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
778 test DATA_COUNT_ODD, 0x1 jz . + 2;
780 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
782 mov SG_CACHE_PRE, SINDEX;
783 /* Load the segment */
784 or DFCNTRL, PRELOADEN;
789 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
791 * Calculate the trailing portion of this S/G segment that cannot
792 * be transferred using memory write and invalidate PCI transactions.
793 * XXX Can we optimize this for PCI writes only???
797 * If the ending address is on a cacheline boundary,
798 * there is no need for an extra segment.
802 and A, CACHESIZE_MASK;
803 test A, 0xFF jz return;
806 * If the transfer is less than a cachline,
807 * there is no need for an extra segment.
809 test HCNT[1], 0xFF jnz calc_mwi_residual_final;
810 test HCNT[2], 0xFF jnz calc_mwi_residual_final;
811 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
814 calc_mwi_residual_final:
824 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_data_okay;
825 mvi NO_IDENT jmp set_seqint;
827 if ((ahc->features & AHC_ULTRA2) != 0) {
828 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
830 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
832 test LASTPHASE, IOI jnz . + 2;
833 or DMAPARAMS, DIRECTION;
834 if ((ahc->features & AHC_CMD_CHAN) != 0) {
835 /* We don't have any valid S/G elements */
836 mvi CCSGADDR, SG_PREFETCH_CNT;
838 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
841 * If we re-enter the data phase after going through another
842 * phase, our transfer location has almost certainly been
843 * corrupted by the interveining, non-data, transfers. Ask
844 * the host driver to fix us up based on the transfer residual.
846 mvi PDATA_REINIT call set_seqint;
849 data_phase_initialize:
850 /* We have seen a data phase for the first time */
851 or SEQ_FLAGS, DPHASE;
854 * Initialize the DMA address and counter from the SCB.
855 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
856 * flag in the highest byte of the data count. We cannot
857 * modify the saved values in the SCB until we see a save
858 * data pointers message.
860 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
861 /* The lowest address byte must be loaded last. */
862 mov SCB_DATACNT[3] call set_hhaddr;
864 if ((ahc->features & AHC_CMD_CHAN) != 0) {
865 bmov HADDR, SCB_DATAPTR, 7;
866 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
869 mvi SCB_DATAPTR call bcopy_7;
870 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
871 mvi SCB_DATACNT + 3 call bcopy_5;
873 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
874 call calc_mwi_residual;
876 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
877 and DATA_COUNT_ODD, 0x1, HCNT[0];
879 if ((ahc->features & AHC_ULTRA2) == 0) {
880 if ((ahc->features & AHC_CMD_CHAN) != 0) {
883 call set_stcnt_from_hcnt;
888 /* Guard against overruns */
889 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
892 * Turn on `Bit Bucket' mode, wait until the target takes
893 * us to another phase, and then notify the host.
895 and DMAPARAMS, DIRECTION;
896 mov DFCNTRL, DMAPARAMS;
897 or SXFRCTL1,BITBUCKET;
898 if ((ahc->features & AHC_DT) == 0) {
899 test SSTAT1,PHASEMIS jz .;
901 test SCSIPHASE, DATA_PHASE_MASK jnz .;
903 and SXFRCTL1, ~BITBUCKET;
904 mvi DATA_OVERRUN call set_seqint;
908 if ((ahc->features & AHC_ULTRA2) != 0) {
909 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
910 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
912 test DATA_COUNT_ODD, 0x1 jz . + 2;
914 mov SG_CACHE_PRE, SINDEX;
915 mov DFCNTRL, DMAPARAMS;
919 * The transfer is complete if either the last segment
920 * completes or the target changes phase.
922 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
923 if ((ahc->features & AHC_DT) == 0) {
924 if ((ahc->flags & AHC_TARGETROLE) != 0) {
926 * As a target, we control the phases,
927 * so ignore PHASEMIS.
929 test SSTAT0, TARGET jnz ultra2_dma_loop;
931 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
932 test SSTAT1,PHASEMIS jz ultra2_dma_loop;
935 test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
940 * The transfer has terminated either due to a phase
941 * change, and/or the completion of the last segment.
942 * We have two goals here. Do as much other work
943 * as possible while the data fifo drains on a read
944 * and respond as quickly as possible to the standard
945 * messages (save data pointers/disconnect and command
946 * complete) that usually follow a data phase.
948 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
950 * On chips with broken auto-flush, start
951 * the flushing process now. We'll poke
952 * the chip from time to time to keep the
953 * flush process going as we complete the
956 or DFCNTRL, FIFOFLUSH;
959 * We assume that, even though data may still be
960 * transferring to the host, that the SCSI side of
961 * the DMA engine is now in a static state. This
962 * allows us to update our notion of where we are
965 * If, by chance, we stopped before being able
966 * to fetch additional segments for this transfer,
967 * yet the last S/G was completely exhausted,
968 * call our idle loop until it is able to load
969 * another segment. This will allow us to immediately
970 * pickup on the next segment on the next data phase.
972 * If we happened to stop on the last segment, then
973 * our residual information is still correct from
974 * the idle loop and there is no need to perform
978 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
979 /* Record if we've consumed all S/G entries */
980 test SSTAT2, SHVALID jnz residuals_correct;
981 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
982 jmp residuals_correct;
985 test SSTAT2, SHVALID jnz sgptr_fixup;
987 jmp ultra2_ensure_sg;
991 * Fixup the residual next S/G pointer. The S/G preload
992 * feature of the chip allows us to load two elements
993 * in addition to the currently active element. We
994 * store the bottom byte of the next S/G pointer in
995 * the SG_CACEPTR register so we can restore the
996 * correct value when the DMA completes. If the next
997 * sg ptr value has advanced to the point where higher
998 * bytes in the address have been affected, fix them
1001 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1002 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1003 add SCB_RESIDUAL_SGPTR[1], -1;
1004 adc SCB_RESIDUAL_SGPTR[2], -1;
1005 adc SCB_RESIDUAL_SGPTR[3], -1;
1007 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1009 test SG_CACHE_SHADOW, ODD_SEG jz . + 2;
1010 or DATA_COUNT_ODD, 0x1;
1011 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1014 * Go ahead and shut down the DMA engine now.
1015 * In the future, we'll want to handle end of
1016 * transfer messages prior to doing this, but this
1017 * requires similar restructuring for pre-ULTRA2
1020 test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
1022 if ((ahc->features & AHC_DT) == 0) {
1023 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1025 * On Rev A of the aic7890, the autoflush
1026 * feature doesn't function correctly.
1027 * Perform an explicit manual flush. During
1028 * a manual flush, the FIFOEMP bit becomes
1029 * true every time the PCI FIFO empties
1030 * regardless of the state of the SCSI FIFO.
1031 * It can take up to 4 clock cycles for the
1032 * SCSI FIFO to get data into the PCI FIFO
1033 * and for FIFOEMP to de-assert. Here we
1034 * guard against this condition by making
1035 * sure the FIFOEMP bit stays on for 5 full
1038 or DFCNTRL, FIFOFLUSH;
1039 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1040 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1041 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1042 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1044 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1047 * We enable the auto-ack feature on DT capable
1048 * controllers. This means that the controller may
1049 * have already transferred some overrun bytes into
1050 * the data FIFO and acked them on the bus. The only
1051 * way to detect this situation is to wait for
1052 * LAST_SEG_DONE to come true on a completed transfer
1053 * and then test to see if the data FIFO is non-empty.
1055 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 4;
1056 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1057 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1059 jmp data_phase_loop;
1060 test DFSTATUS, FIFOEMP jz .;
1063 /* Don't clobber an inprogress host data transfer */
1064 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1066 and DFCNTRL, ~(SCSIEN|HDMAEN);
1067 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1068 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1070 * Keep HHADDR cleared for future, 32bit addressed
1071 * only, DMA operations.
1073 * Due to bayonette style S/G handling, our residual
1074 * data must be "fixed up" once the transfer is halted.
1075 * Here we fixup the HSHADDR stored in the high byte
1076 * of the residual data cnt. By postponing the fixup,
1077 * we can batch the clearing of HADDR with the fixup.
1078 * If we halted on the last segment, the residual is
1079 * already correct. If we are not on the last
1080 * segment, copy the high address directly from HSHADDR.
1081 * We don't need to worry about maintaining the
1082 * SG_LAST_SEG flag as it will always be false in the
1083 * case where an update is required.
1085 or DSCOMMAND1, HADDLDSEL0;
1086 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1087 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1089 and DSCOMMAND1, ~HADDLDSEL0;
1092 /* If we are the last SG block, tell the hardware. */
1093 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1094 && ahc->pci_cachesize != 0) {
1095 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1097 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1098 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1099 test SSTAT0, TARGET jz dma_last_sg;
1100 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) {
1101 test DMAPARAMS, DIRECTION jz dma_mid_sg;
1105 and DMAPARAMS, ~WIDEODD;
1107 /* Start DMA data transfer. */
1108 mov DFCNTRL, DMAPARAMS;
1110 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1113 test SSTAT0,DMADONE jnz dma_dmadone;
1114 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1117 * We will be "done" DMAing when the transfer count goes to
1118 * zero, or the target changes the phase (in light of this,
1119 * it makes sense that the DMA circuitry doesn't ACK when
1120 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1121 * the data FIFO should be flushed auto-magically on STCNT=0
1122 * or a phase change, so just wait for FIFO empty status.
1125 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1127 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1129 /* Don't clobber an inprogress host data transfer */
1130 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1133 * Now shut off the DMA and make sure that the DMA
1134 * hardware has actually stopped. Touching the DMA
1135 * counters, etc. while a DMA is active will result
1136 * in an ILLSADDR exception.
1139 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1142 * Some revisions of the aic78XX have a problem where, if the
1143 * data fifo is full, but the PCI input latch is not empty,
1144 * HDMAEN cannot be cleared. The fix used here is to drain
1145 * the prefetched but unused data from the data fifo until
1146 * there is space for the input latch to drain.
1148 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1151 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1153 /* See if we have completed this last segment */
1154 test STCNT[0], 0xff jnz data_phase_finish;
1155 test STCNT[1], 0xff jnz data_phase_finish;
1156 test STCNT[2], 0xff jnz data_phase_finish;
1159 * Advance the scatter-gather pointers if needed
1161 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1162 && ahc->pci_cachesize != 0) {
1163 test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
1165 * Reload HADDR from SHADDR and setup the
1166 * count to be the size of our residual.
1168 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1169 bmov HADDR, SHADDR, 4;
1170 mov HCNT, MWI_RESIDUAL;
1171 bmov HCNT[1], ALLZEROS, 2;
1174 mvi SHADDR call bcopy_4;
1175 mov MWI_RESIDUAL call set_hcnt;
1181 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
1182 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
1183 jmp data_phase_finish;
1186 * Load the next SG element's data address and length
1187 * into the DMA engine. If we don't have hardware
1188 * to perform a prefetch, we'll have to fetch the
1189 * segment from host memory first.
1191 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1192 /* Wait for the idle loop to complete */
1193 test CCSGCTL, CCSGEN jz . + 3;
1195 test CCSGCTL, CCSGEN jnz . - 1;
1196 bmov HADDR, CCSGRAM, 7;
1198 * Workaround for flaky external SCB RAM
1199 * on certain aic7895 setups. It seems
1200 * unable to handle direct transfers from
1201 * S/G ram to certain SCB locations.
1203 mov SINDEX, CCSGRAM;
1204 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1206 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1207 mov ALLZEROS call set_hhaddr;
1210 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1212 mvi SG_SIZEOF call set_hcnt;
1214 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1220 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1223 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1224 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1227 * The lowest address byte must be loaded
1228 * last as it triggers the computation of
1229 * some items in the PCI block. The ULTRA2
1230 * chips do this on PRELOAD.
1234 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1235 && ahc->pci_cachesize != 0) {
1236 call calc_mwi_residual;
1239 /* Point to the new next sg in memory */
1243 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1244 bmov STCNT, HCNT, 3;
1246 call set_stcnt_from_hcnt;
1248 /* Track odd'ness */
1249 test HCNT[0], 0x1 jz . + 2;
1250 xor DATA_COUNT_ODD, 0x1;
1252 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1253 test SSTAT0, TARGET jnz data_phase_loop;
1258 * If the target has left us in data phase, loop through
1259 * the dma code again. In the case of ULTRA2 adapters,
1260 * we should only loop if there is a data overrun. For
1261 * all other adapters, we'll loop after each S/G element
1262 * is loaded as well as if there is an overrun.
1264 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1265 test SSTAT0, TARGET jnz data_phase_done;
1267 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1268 test SSTAT1, REQINIT jz .;
1269 if ((ahc->features & AHC_DT) == 0) {
1270 test SSTAT1,PHASEMIS jz data_phase_loop;
1272 test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
1278 * After a DMA finishes, save the SG and STCNT residuals back into
1279 * the SCB. We use STCNT instead of HCNT, since it's a reflection
1280 * of how many bytes were transferred on the SCSI (as opposed to the
1283 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1284 /* Kill off any pending prefetch */
1285 call disable_ccsgen;
1288 if ((ahc->features & AHC_ULTRA2) == 0) {
1290 * Clear the high address byte so that all other DMA
1291 * operations, which use 32bit addressing, can assume
1294 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1295 mov ALLZEROS call set_hhaddr;
1300 * Update our residual information before the information is
1301 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1302 * transferred all data, no update is needed.
1305 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1306 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1307 && ahc->pci_cachesize != 0) {
1308 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1309 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1311 mov A, MWI_RESIDUAL;
1312 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1314 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
1315 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
1317 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1320 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1322 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1323 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1325 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1326 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1327 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1329 residual_update_done:
1331 * Since we've been through a data phase, the SCB_RESID* fields
1332 * are now initialized. Clear the full residual flag.
1334 and SCB_SGPTR[0], ~SG_FULL_RESID;
1336 if ((ahc->features & AHC_ULTRA2) != 0) {
1337 /* Clear the channel in case we return to data phase later */
1338 or SXFRCTL0, CLRSTCNT|CLRCHN;
1339 or SXFRCTL0, CLRSTCNT|CLRCHN;
1342 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1343 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1344 and SEQ_FLAGS, ~DPHASE_PENDING;
1346 * For data-in phases, wait for any pending acks from the
1347 * initiator before changing phase. We only need to
1348 * send Ignore Wide Residue messages for data-in phases.
1350 test DFCNTRL, DIRECTION jz target_ITloop;
1351 test SSTAT1, REQINIT jnz .;
1352 test DATA_COUNT_ODD, 0x1 jz target_ITloop;
1353 test SCSIRATE, WIDEXFER jz target_ITloop;
1355 * Issue an Ignore Wide Residue Message.
1357 mvi P_MESGIN|BSYO call change_phase;
1358 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1359 mvi 1 call target_outb;
1365 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1367 * Command phase. Set up the DMA registers and let 'er rip.
1370 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_command_okay;
1371 mvi NO_IDENT jmp set_seqint;
1374 if ((ahc->features & AHC_ULTRA2) != 0) {
1375 bmov HCNT[0], SCB_CDB_LEN, 1;
1376 bmov HCNT[1], ALLZEROS, 2;
1377 mvi SG_CACHE_PRE, LAST_SEG;
1378 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1379 bmov STCNT[0], SCB_CDB_LEN, 1;
1380 bmov STCNT[1], ALLZEROS, 2;
1382 mov STCNT[0], SCB_CDB_LEN;
1386 add NONE, -13, SCB_CDB_LEN;
1387 mvi SCB_CDB_STORE jnc p_command_embedded;
1388 p_command_from_host:
1389 if ((ahc->features & AHC_ULTRA2) != 0) {
1390 bmov HADDR[0], SCB_CDB_PTR, 4;
1391 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
1393 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1394 bmov HADDR[0], SCB_CDB_PTR, 4;
1395 bmov HCNT, STCNT, 3;
1398 mvi SCB_CDB_PTR call bcopy_4;
1399 mov SCB_CDB_LEN call set_hcnt;
1401 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
1406 * The data fifo seems to require 4 byte aligned
1407 * transfers from the sequencer. Force this to
1408 * be the case by clearing HADDR[0] even though
1409 * we aren't going to touch host memory.
1412 if ((ahc->features & AHC_ULTRA2) != 0) {
1413 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
1414 bmov DFDAT, SCB_CDB_STORE, 12;
1415 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1416 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1418 * On the 7895 the data FIFO will
1419 * get corrupted if you try to dump
1420 * data from external SCB memory into
1421 * the FIFO while it is enabled. So,
1422 * fill the fifo and then enable SCSI
1425 mvi DFCNTRL, (DIRECTION|FIFORESET);
1427 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1429 bmov DFDAT, SCB_CDB_STORE, 12;
1430 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1431 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
1433 or DFCNTRL, FIFOFLUSH;
1436 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1437 call copy_to_fifo_6;
1438 call copy_to_fifo_6;
1439 or DFCNTRL, FIFOFLUSH;
1442 if ((ahc->features & AHC_DT) == 0) {
1443 test SSTAT0, SDONE jnz . + 2;
1444 test SSTAT1, PHASEMIS jz p_command_loop;
1446 * Wait for our ACK to go-away on it's own
1447 * instead of being killed by SCSIEN getting cleared.
1449 test SCSISIGI, ACKI jnz .;
1451 test DFCNTRL, SCSIEN jnz p_command_loop;
1453 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1454 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
1455 if ((ahc->features & AHC_ULTRA2) != 0) {
1456 /* Drop any residual from the S/G Preload queue */
1457 or SXFRCTL0, CLRSTCNT;
1462 * Status phase. Wait for the data byte to appear, then read it
1463 * and store it into the SCB.
1466 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_status_okay;
1467 mvi NO_IDENT jmp set_seqint;
1469 mov SCB_SCSI_STATUS, SCSIDATL;
1473 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1474 * indentify message sequence and send it to the target. The host may
1475 * override this behavior by setting the MK_MESSAGE bit in the SCB
1476 * control byte. This will cause us to interrupt the host and allow
1477 * it to handle the message phase completely on its own. If the bit
1478 * associated with this target is set, we will also interrupt the host,
1479 * thereby allowing it to send a message on the next selection regardless
1480 * of the transaction being sent.
1482 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
1483 * This is done to allow the host to send messages outside of an identify
1484 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
1485 * on an SCB that might not be for the current nexus. (For example, a
1486 * BDR message in responce to a bad reselection would leave us pointed to
1487 * an SCB that doesn't have anything to do with the current target).
1489 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
1490 * bus device reset).
1492 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
1493 * in case the target decides to put us in this phase for some strange
1497 /* Turn on ATN for the retry */
1498 if ((ahc->features & AHC_DT) == 0) {
1499 or SCSISIGO, ATNO, LASTPHASE;
1504 mov SINDEX, MSG_OUT;
1505 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
1506 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
1508 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
1509 test SCB_CONTROL, DISCENB jnz . + 2;
1510 and SINDEX, ~DISCENB;
1512 * Send a tag message if TAG_ENB is set in the SCB control block.
1513 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
1516 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
1517 mov SCSIDATL, SINDEX; /* Send the identify message */
1519 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1520 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
1522 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1523 mov SCB_TAG jmp p_mesgout_onebyte;
1525 * Interrupt the driver, and allow it to handle this message
1526 * phase and any required retries.
1528 p_mesgout_from_host:
1529 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1530 jmp host_message_loop;
1533 mvi CLRSINT1, CLRATNO;
1534 mov SCSIDATL, SINDEX;
1537 * If the next bus phase after ATN drops is message out, it means
1538 * that the target is requesting that the last message(s) be resent.
1541 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1544 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1545 mov LAST_MSG, MSG_OUT;
1546 mvi MSG_OUT, MSG_NOOP; /* No message left */
1550 * Message in phase. Bytes are read using Automatic PIO mode.
1553 mvi ACCUM call inb_first; /* read the 1st message byte */
1555 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1556 cmp A,MSG_DISCONNECT je mesgin_disconnect;
1557 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1558 cmp ALLZEROS,A je mesgin_complete;
1559 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1560 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1561 cmp A,MSG_NOOP je mesgin_done;
1564 * Pushed message loop to allow the kernel to
1565 * run it's own message state engine. To avoid an
1566 * extra nop instruction after signaling the kernel,
1567 * we perform the phase_lock before checking to see
1568 * if we should exit the loop and skip the phase_lock
1569 * in the ITloop. Performing back to back phase_locks
1570 * shouldn't hurt, but why do it twice...
1573 mvi HOST_MSG_LOOP call set_seqint;
1575 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
1576 jmp host_message_loop;
1578 mesgin_ign_wide_residue:
1579 if ((ahc->features & AHC_WIDE) != 0) {
1580 test SCSIRATE, WIDEXFER jz mesgin_reject;
1581 /* Pull the residue byte */
1582 mvi ARG_1 call inb_next;
1583 cmp ARG_1, 0x01 jne mesgin_reject;
1584 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1585 test DATA_COUNT_ODD, 0x1 jz mesgin_done;
1586 mvi IGN_WIDE_RES call set_seqint;
1591 mvi MSG_MESSAGE_REJECT call mk_mesg;
1593 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1598 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
1599 * and trigger a completion interrupt. Before doing so, check to see if there
1600 * is a residual or the status byte is something other than STATUS_GOOD (0).
1601 * In either of these conditions, we upload the SCB back to the host so it can
1602 * process this information. In the case of a non zero status byte, we
1603 * additionally interrupt the kernel driver synchronously, allowing it to
1604 * decide if sense should be retrieved. If the kernel driver wishes to request
1605 * sense, it will fill the kernel SCB with a request sense command, requeue
1606 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1607 * RETURN_1 to SEND_SENSE.
1611 * If ATN is raised, we still want to give the target a message.
1612 * Perhaps there was a parity error on this last message byte.
1613 * Either way, the target should take us to message out phase
1614 * and then attempt to complete the command again. We should use a
1615 * critical section here to guard against a timeout triggering
1616 * for this command and setting ATN while we are still processing
1618 test SCSISIGI, ATNI jnz mesgin_done;
1622 * See if we attempted to deliver a message but the target ingnored us.
1624 test SCB_CONTROL, MK_MESSAGE jz . + 2;
1625 mvi MKMSG_FAILED call set_seqint;
1628 * Check for residuals
1630 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
1631 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1632 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1634 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */
1636 or SCB_SGPTR, SG_RESID_VALID;
1637 mvi DMAPARAMS, FIFORESET;
1638 mov SCB_TAG call dma_scb;
1639 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */
1640 mvi BAD_STATUS call set_seqint; /* let driver know */
1641 cmp RETURN_1, SEND_SENSE jne complete;
1642 call add_scb_to_free_list;
1645 mov SCB_TAG call complete_post;
1650 /* Post the SCBID in SINDEX and issue an interrupt */
1651 call add_scb_to_free_list;
1653 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1658 mvi QOUTFIFO_OFFSET call post_byte_setup;
1659 mov ARG_1 call post_byte;
1660 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1663 mvi INTSTAT,CMDCMPLT ret;
1665 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1667 * Is it a disconnect message? Set a flag in the SCB to remind us
1668 * and await the bus going free. If this is an untagged transaction
1669 * store the SCB id for it in our untagged target table for lookup on
1674 * If ATN is raised, we still want to give the target a message.
1675 * Perhaps there was a parity error on this last message byte
1676 * or we want to abort this command. Either way, the target
1677 * should take us to message out phase and then attempt to
1679 * XXX - Wait for more testing.
1680 test SCSISIGI, ATNI jnz mesgin_done;
1683 or SCB_CONTROL,DISCONNECTED;
1684 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1685 call add_scb_to_disc_list;
1687 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1689 mov SAVED_LUN, SCB_LUN;
1690 mov SCB_SCSIID call set_busy_target;
1694 * Save data pointers message:
1695 * Copying RAM values back to SCB, for Save Data Pointers message, but
1696 * only if we've actually been into a data phase to change them. This
1697 * protects against bogus data in scratch ram and the residual counts
1698 * since they are only initialized when we go into data_in or data_out.
1699 * Ack the message as soon as possible. For chips without S/G pipelining,
1700 * we can only ack the message after SHADDR has been saved. On these
1701 * chips, SHADDR increments with every bus transaction, even PIO.
1704 if ((ahc->features & AHC_ULTRA2) != 0) {
1705 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1706 test SEQ_FLAGS, DPHASE jz ITloop;
1708 test SEQ_FLAGS, DPHASE jz mesgin_done;
1712 * If we are asked to save our position at the end of the
1713 * transfer, just mark us at the end rather than perform a
1716 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1717 or SCB_SGPTR, SG_LIST_NULL;
1718 if ((ahc->features & AHC_ULTRA2) != 0) {
1727 * The SCB_SGPTR becomes the next one we'll download,
1728 * and the SCB_DATAPTR becomes the current SHADDR.
1729 * Use the residual number since STCNT is corrupted by
1730 * any message transfer.
1732 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1733 bmov SCB_DATAPTR, SHADDR, 4;
1734 if ((ahc->features & AHC_ULTRA2) == 0) {
1735 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1737 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
1739 mvi DINDEX, SCB_DATAPTR;
1740 mvi SHADDR call bcopy_4;
1741 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1742 mvi SCB_RESIDUAL_DATACNT call bcopy_8;
1747 * Restore pointers message? Data pointers are recopied from the
1748 * SCB anytime we enter a data phase for the first time, so all
1749 * we need to do is clear the DPHASE flag and let the data phase
1753 and SEQ_FLAGS, ~DPHASE; /*
1755 * the next time through
1761 * Index into our Busy Target table. SINDEX and DINDEX are modified
1762 * upon return. SCBPTR may be modified by this action.
1765 shr DINDEX, 4, SINDEX;
1766 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1767 mov SCBPTR, SAVED_LUN;
1768 add DINDEX, SCB_64_BTT;
1770 add DINDEX, BUSY_TARGETS;
1772 mov DINDIR, ARG_1 ret;
1775 * Identify message? For a reconnecting target, this tells us the lun
1776 * that the reconnection is for - find the correct SCB and switch to it,
1777 * clearing the "disconnected" bit so we don't "find" it by accident later.
1781 * Determine whether a target is using tagged or non-tagged
1782 * transactions by first looking at the transaction stored in
1783 * the busy target array. If there is no untagged transaction
1784 * for this target or the transaction is for a different lun, then
1785 * this must be a tagged transaction.
1787 shr SINDEX, 4, SAVED_SCSIID;
1788 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1789 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1790 add SINDEX, SCB_64_BTT;
1791 mov SCBPTR, SAVED_LUN;
1792 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1793 add NONE, -SCB_64_BTT, SINDEX;
1795 mvi INTSTAT, OUT_OF_RANGE;
1797 add NONE, -(SCB_64_BTT + 16), SINDEX;
1799 mvi INTSTAT, OUT_OF_RANGE;
1803 add SINDEX, BUSY_TARGETS;
1804 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1805 add NONE, -BUSY_TARGETS, SINDEX;
1807 mvi INTSTAT, OUT_OF_RANGE;
1809 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1811 mvi INTSTAT, OUT_OF_RANGE;
1816 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
1817 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1818 mov ARG_1 call findSCB;
1822 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1823 jmp setup_SCB_id_lun_okay;
1826 * We only allow one untagged command per-target
1827 * at a time. So, if the lun doesn't match, look
1828 * for a tag message.
1831 cmp SAVED_LUN, A je setup_SCB_id_lun_okay;
1832 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1834 * findSCB removes the SCB from the
1835 * disconnected list, so we must replace
1836 * it there should this SCB be for another
1844 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1845 * If we get one, we use the tag returned to find the proper
1846 * SCB. With SCB paging, we must search for non-tagged
1847 * transactions since the SCB may exist in any slot. If we're not
1848 * using SCB paging, we can use the tag as the direct index to the
1852 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1855 mov NONE,SCSIDATL; /* ACK Identify MSG */
1857 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1860 cmp LASTPHASE, P_MESGIN jne not_found;
1861 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1864 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
1866 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1867 mvi ARG_1 call inb_next; /* tag value */
1868 mov ARG_1 call findSCB;
1870 mvi ARG_1 call inb_next; /* tag value */
1875 * Ensure that the SCB the tag points to is for
1876 * an SCB transaction to the reconnecting target.
1879 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1883 cmp SAVED_SCSIID, A jne not_found_cleanup_scb;
1884 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1889 cmp SAVED_LUN, A jne not_found_cleanup_scb;
1890 setup_SCB_id_lun_okay:
1891 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1894 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
1895 and SCB_CONTROL,~DISCONNECTED;
1896 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged;
1897 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1900 mvi ARG_1, SCB_LIST_NULL;
1901 mov SAVED_SCSIID call set_busy_target;
1902 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1906 mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */
1907 call set_transfer_settings;
1908 /* See if the host wants to send a message upon reconnection */
1909 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1910 mvi HOST_MSG call mk_mesg;
1913 not_found_cleanup_scb:
1914 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1918 mvi NO_MATCH call set_seqint;
1922 if ((ahc->features & AHC_DT) == 0) {
1923 or SCSISIGO, ATNO, LASTPHASE;
1927 mov MSG_OUT,SINDEX ret;
1930 * Functions to read data in Automatic PIO mode.
1932 * According to Adaptec's documentation, an ACK is not sent on input from
1933 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1934 * latched (the usual way), then read the data byte directly off the bus
1935 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1936 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1937 * spec guarantees that the target will hold the data byte on the bus until
1940 * The assumption here is that these are called in a particular sequence,
1941 * and that REQ is already set when inb_first is called. inb_{first,next}
1942 * use the same calling convention as inb.
1945 mvi PERR_DETECTED call set_seqint;
1948 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1951 * If there is a parity error, wait for the kernel to
1952 * see the interrupt and prepare our message response
1953 * before continuing.
1955 test SSTAT1, REQINIT jz inb_next_wait;
1956 test SSTAT1, SCSIPERR jnz inb_next_wait_perr;
1957 inb_next_check_phase:
1958 and LASTPHASE, PHASE_MASK, SCSISIGI;
1959 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1962 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1964 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1967 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1969 * Change to a new phase. If we are changing the state of the I/O signal,
1970 * from out to in, wait an additional data release delay before continuing.
1973 /* Wait for preceeding I/O session to complete. */
1974 test SCSISIGI, ACKI jnz .;
1976 /* Change the phase */
1977 and DINDEX, IOI, SCSISIGI;
1978 mov SCSISIGO, SINDEX;
1982 * If the data direction has changed, from
1983 * out (initiator driving) to in (target driving),
1984 * we must wait at least a data release delay plus
1985 * the normal bus settle delay. [SCSI III SPI 10.11.0]
1987 cmp DINDEX, A je change_phase_wait;
1988 test SINDEX, IOI jz change_phase_wait;
1989 call change_phase_wait;
1997 * Send a byte to an initiator in Automatic PIO mode.
2000 or SXFRCTL0, SPIOEN;
2001 test SSTAT0, SPIORDY jz .;
2002 mov SCSIDATL, SINDEX;
2003 test SSTAT0, SPIORDY jz .;
2004 and SXFRCTL0, ~SPIOEN ret;
2008 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
2009 * be set to the position of the SCB. If the SCB cannot be found locally,
2010 * it will be paged in from host memory. RETURN_2 stores the address of the
2011 * preceding SCB in the disconnected list which can be used to speed up
2012 * removal of the found SCB from the disconnected list.
2014 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2017 mov A, SINDEX; /* Tag passed in SINDEX */
2018 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
2019 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */
2020 mvi ARG_2, SCB_LIST_NULL; /* Head of list */
2023 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
2025 mov SCBPTR,SCB_NEXT;
2027 cmp SCB_TAG, A jne findSCB_next;
2028 rem_scb_from_disc_list:
2029 cmp ARG_2, SCB_LIST_NULL je rHead;
2030 mov DINDEX, SCB_NEXT;
2033 mov SCB_NEXT, DINDEX;
2034 mov SCBPTR, SINDEX ret;
2036 mov DISCONNECTED_SCBH,SCB_NEXT ret;
2040 * We didn't find it. Page in the SCB.
2042 mov ARG_1, A; /* Save tag */
2043 mov ALLZEROS call get_free_or_disc_scb;
2044 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
2045 mov ARG_1 jmp dma_scb;
2049 * Prepare the hardware to post a byte to host memory given an
2050 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
2054 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2055 mvi DINDEX, CCHADDR;
2056 mvi SHARED_DATA_ADDR call set_1byte_addr;
2058 mvi CCSCBCTL, CCSCBRESET ret;
2061 mvi SHARED_DATA_ADDR call set_1byte_addr;
2062 mvi 1 call set_hcnt;
2063 mvi DFCNTRL, FIFORESET ret;
2067 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2068 bmov CCSCBRAM, SINDEX, 1;
2069 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2070 test CCSCBCTL, CCSCBDONE jz .;
2074 or DFCNTRL, HDMAEN|FIFOFLUSH;
2079 mvi PERR_DETECTED call set_seqint;
2082 * If there is a parity error, wait for the kernel to
2083 * see the interrupt and prepare our message response
2084 * before continuing.
2086 test SSTAT1, REQINIT jz phase_lock;
2087 test SSTAT1, SCSIPERR jnz phase_lock_perr;
2088 phase_lock_latch_phase:
2089 if ((ahc->features & AHC_DT) == 0) {
2090 and SCSISIGO, PHASE_MASK, SCSISIGI;
2092 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
2094 if ((ahc->features & AHC_CMD_CHAN) == 0) {
2096 mov HCNT[0], SINDEX;
2101 set_stcnt_from_hcnt:
2102 mov STCNT[0], HCNT[0];
2103 mov STCNT[1], HCNT[1];
2104 mov STCNT[2], HCNT[2] ret;
2118 mov DINDIR, SINDIR ret;
2121 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2123 * Setup addr assuming that A is an index into
2124 * an array of 32byte objects, SINDEX contains
2125 * the base address of that array, and DINDEX
2126 * contains the base address of the location
2127 * to store the indexed address.
2136 * Setup addr assuming that A is an index into
2137 * an array of 64byte objects, SINDEX contains
2138 * the base address of that array, and DINDEX
2139 * contains the base address of the location
2140 * to store the indexed address.
2147 * Setup addr assuming that A + (ARG_2 * 256) is an
2148 * index into an array of 1byte objects, SINDEX contains
2149 * the base address of that array, and DINDEX contains
2150 * the base address of the location to store the computed
2154 add DINDIR, A, SINDIR;
2156 adc DINDIR, A, SINDIR;
2158 adc DINDIR, A, SINDIR;
2159 adc DINDIR, A, SINDIR ret;
2162 * Either post or fetch an SCB from host memory based on the
2163 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
2167 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2168 mvi DINDEX, CCHADDR;
2169 mvi HSCB_ADDR call set_64byte_addr;
2170 mov CCSCBPTR, SCBPTR;
2171 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
2172 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2173 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64;
2175 mvi CCHCNT, SCB_DOWNLOAD_SIZE;
2177 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
2178 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
2181 mvi CCHCNT, SCB_UPLOAD_SIZE;
2182 if ((ahc->features & AHC_ULTRA2) == 0) {
2183 mvi CCSCBCTL, CCSCBRESET;
2184 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
2185 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2186 test CCSCBCTL, CCSCBDONE jz .;
2187 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2188 mvi CCSCBCTL, CCARREN|CCSCBRESET;
2189 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
2190 mvi CCHCNT, SCB_UPLOAD_SIZE;
2191 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
2192 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
2194 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
2195 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
2199 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
2203 mvi HSCB_ADDR call set_64byte_addr;
2204 mvi SCB_DOWNLOAD_SIZE call set_hcnt;
2205 mov DFCNTRL, DMAPARAMS;
2206 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
2207 /* Fill it with the SCB data */
2209 mvi SINDEX, SCB_BASE;
2210 add A, SCB_DOWNLOAD_SIZE, SINDEX;
2211 copy_scb_tofifo_loop:
2212 call copy_to_fifo_8;
2213 cmp SINDEX, A jne copy_scb_tofifo_loop;
2214 or DFCNTRL, HDMAEN|FIFOFLUSH;
2217 mvi DINDEX, SCB_BASE;
2218 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2220 * The PCI module will only issue a PCI
2221 * retry if the data FIFO is empty. If the
2222 * host disconnects in the middle of a
2223 * transfer, we must empty the fifo of all
2224 * available data to force the chip to
2225 * continue the transfer. This does not
2226 * happen for SCSI transfers as the SCSI module
2227 * will drain the FIFO as data are made available.
2228 * When the hang occurs, we know that a multiple
2229 * of 8 bytes is in the FIFO because the PCI
2230 * module has an 8 byte input latch that only
2231 * dumps to the FIFO when HCNT == 0 or the
2235 /* Wait for at least 8 bytes of data to arrive. */
2237 test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
2239 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
2240 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2241 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2242 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2244 * The PCI module no longer intends to perform
2245 * a PCI transaction. Drain the fifo.
2247 dma_scb_hang_dma_drain_fifo:
2249 add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
2252 cmp DINDEX, A jne . - 1;
2253 cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
2254 je dma_finish_nowait;
2255 /* Restore A as the lines left to transfer. */
2256 add A, -SCB_BASE, DINDEX;
2258 jmp dma_scb_hang_fifo;
2259 dma_scb_hang_dma_done:
2260 and DFCNTRL, ~HDMAEN;
2261 test DFCNTRL, HDMAEN jnz .;
2279 mov DINDIR,DFDAT ret;
2293 mov DFDAT,SINDIR ret;
2296 * Wait for DMA from host memory to data FIFO to complete, then disable
2297 * DMA and wait for it to acknowledge that it's off.
2300 test DFSTATUS,HDONE jz dma_finish;
2303 and DFCNTRL, ~HDMAEN;
2304 test DFCNTRL, HDMAEN jnz .;
2308 * Restore an SCB that failed to match an incoming reselection
2309 * to the correct/safe state. If the SCB is for a disconnected
2310 * transaction, it must be returned to the disconnected list.
2311 * If it is not in the disconnected state, it must be free.
2314 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2315 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
2317 add_scb_to_free_list:
2318 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2320 mov SCB_NEXT, FREE_SCBH;
2321 mvi SCB_TAG, SCB_LIST_NULL;
2322 mov FREE_SCBH, SCBPTR ret;
2325 mvi SCB_TAG, SCB_LIST_NULL ret;
2328 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2330 or DSCOMMAND1, HADDLDSEL0;
2331 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2332 and DSCOMMAND1, ~HADDLDSEL0 ret;
2335 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2336 get_free_or_disc_scb:
2338 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2339 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2341 mvi NO_FREE_SCB call set_seqint;
2342 mvi SINDEX, SCB_LIST_NULL ret;
2344 mov SCBPTR, DISCONNECTED_SCBH;
2345 mov DISCONNECTED_SCBH, SCB_NEXT;
2347 mvi DMAPARAMS, FIFORESET;
2348 mov SCB_TAG jmp dma_scb;
2351 mov SCBPTR, FREE_SCBH;
2352 mov FREE_SCBH, SCB_NEXT ret;
2355 add_scb_to_disc_list:
2357 * Link this SCB into the DISCONNECTED list. This list holds the
2358 * candidates for paging out an SCB if one is needed for a new command.
2359 * Modifying the disconnected list is a critical(pause dissabled) section.
2362 mov SCB_NEXT, DISCONNECTED_SCBH;
2363 mov DISCONNECTED_SCBH, SCBPTR ret;
2367 mov INTSTAT, SINDEX;