2 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * without modification.
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15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#40 $"
44 PATCH_ARG_LIST = "struct ahc_softc *ahc"
46 #include "aic7xxx.reg"
47 #include "scsi_message.h"
50 * A few words on the waiting SCB list:
51 * After starting the selection hardware, we check for reconnecting targets
52 * as well as for our selection to complete just in case the reselection wins
53 * bus arbitration. The problem with this is that we must keep track of the
54 * SCB that we've already pulled from the QINFIFO and started the selection
55 * on just in case the reselection wins so that we can retry the selection at
56 * a later time. This problem cannot be resolved by holding a single entry
57 * in scratch ram since a reconnecting target can request sense and this will
58 * create yet another SCB waiting for selection. The solution used here is to
59 * use byte 27 of the SCB as a psuedo-next pointer and to thread a list
60 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
61 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
62 * this list everytime a request sense occurs or after completing a non-tagged
63 * command for which a second SCB has been queued. The sequencer will
64 * automatically consume the entries.
69 * Turn off the selection hardware. We need to reset the
70 * selection request in order to perform a new selection.
72 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
73 and SIMODE1, ~ENBUSFREE;
75 call clear_target_state;
76 and SXFRCTL0, ~SPIOEN;
77 if ((ahc->features & AHC_ULTRA2) != 0) {
80 test SCSISEQ, ENSELO jnz poll_for_selection;
81 if ((ahc->features & AHC_TWIN) != 0) {
82 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
83 test SCSISEQ, ENSELO jnz poll_for_selection;
85 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
87 if ((ahc->features & AHC_TWIN) != 0) {
88 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
90 test SSTAT0, SELDO|SELDI jnz selection;
92 /* Has the driver posted any work for us? */
94 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
95 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
98 cmp KERNEL_QINPOS, A je poll_for_work_loop;
100 mov ARG_1, NEXT_QUEUED_SCB;
103 * We have at least one queued SCB now and we don't have any
104 * SCBs in the list of SCBs awaiting selection. Allocate a
105 * card SCB for the host's SCB and get to work on it.
107 if ((ahc->flags & AHC_PAGESCBS) != 0) {
108 mov ALLZEROS call get_free_or_disc_scb;
110 /* In the non-paging case, the SCBID == hardware SCB index */
113 or SEQ_FLAGS2, SCB_DMA;
117 * DMA the SCB from host ram into the current SCB location.
119 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
120 mov ARG_1 call dma_scb;
122 * Check one last time to see if this SCB was canceled
123 * before we completed the DMA operation. If it was,
124 * the QINFIFO next pointer will not match our saved
129 cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
130 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
131 cmp SCB_TAG, A je . + 2;
132 mvi SCB_MISMATCH call set_seqint;
134 mov NEXT_QUEUED_SCB, SCB_NEXT;
135 mov SCB_NEXT,WAITING_SCBH;
136 mov WAITING_SCBH, SCBPTR;
137 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
138 mov NONE, SNSCB_QOFF;
142 and SEQ_FLAGS2, ~SCB_DMA;
146 * Start the first entry on the waiting SCB list.
148 mov SCBPTR, WAITING_SCBH;
149 call start_selection;
153 * Twin channel devices cannot handle things like SELTO
154 * interrupts on the "background" channel. So, while
155 * selecting, keep polling the current channel until
156 * either a selection or reselection occurs.
158 test SSTAT0, SELDO|SELDI jz poll_for_selection;
162 * We aren't expecting a bus free, so interrupt
163 * the kernel driver if it happens.
165 mvi CLRSINT1,CLRBUSFREE;
166 if ((ahc->features & AHC_DT) == 0) {
167 or SIMODE1, ENBUSFREE;
171 * Guard against a bus free after (re)selection
172 * but prior to enabling the busfree interrupt. SELDI
173 * and SELDO will be cleared in that case.
175 test SSTAT0, SELDI|SELDO jz bus_free_sel;
176 test SSTAT0,SELDO jnz select_out;
178 if ((ahc->flags & AHC_TARGETROLE) != 0) {
179 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
180 test SSTAT0, TARGET jz initiator_reselect;
182 mvi CLRSINT0, CLRSELDI;
185 * We've just been selected. Assert BSY and
186 * setup the phase for receiving messages
189 mvi SCSISIGO, P_MESGOUT|BSYO;
192 * Setup the DMA for sending the identify and
193 * command information.
195 or SEQ_FLAGS, CMDPHASE_PENDING;
198 if ((ahc->features & AHC_CMD_CHAN) != 0) {
200 mvi SHARED_DATA_ADDR call set_32byte_addr;
201 mvi CCSCBCTL, CCSCBRESET;
204 mvi SHARED_DATA_ADDR call set_32byte_addr;
205 mvi DFCNTRL, FIFORESET;
208 /* Initiator that selected us */
209 and SAVED_SCSIID, SELID_MASK, SELID;
210 /* The Target ID we were selected at */
211 if ((ahc->features & AHC_MULTI_TID) != 0) {
212 and A, OID, TARGIDIN;
213 } else if ((ahc->features & AHC_ULTRA2) != 0) {
214 and A, OID, SCSIID_ULTRA2;
219 if ((ahc->features & AHC_TWIN) != 0) {
220 test SBLKCTL, SELBUSB jz . + 2;
221 or SAVED_SCSIID, TWIN_CHNLB;
223 if ((ahc->features & AHC_CMD_CHAN) != 0) {
224 mov CCSCBRAM, SAVED_SCSIID;
226 mov DFDAT, SAVED_SCSIID;
230 * If ATN isn't asserted, the target isn't interested
231 * in talking to us. Go directly to bus free.
232 * XXX SCSI-1 may require us to assume lun 0 if
235 test SCSISIGI, ATNI jz target_busfree;
238 * Watch ATN closely now as we pull in messages from the
239 * initiator. We follow the guidlines from section 6.5
240 * of the SCSI-2 spec for what messages are allowed when.
245 * Our first message must be one of IDENTIFY, ABORT, or
248 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
250 if ((ahc->features & AHC_CMD_CHAN) != 0) {
251 mov CCSCBRAM, DINDEX;
255 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
257 /* Remember for disconnection decision */
258 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
259 /* XXX Honor per target settings too */
260 or SEQ_FLAGS, NO_DISCONNECT;
262 test SCSISIGI, ATNI jz ident_messages_done;
265 * If this is a tagged request, the tagged message must
266 * immediately follow the identify. We test for a valid
267 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
268 * < MSG_IGN_WIDE_RESIDUE.
270 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
271 jnc ident_messages_done_msg_pending;
272 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
273 jc ident_messages_done_msg_pending;
276 if ((ahc->features & AHC_CMD_CHAN) != 0) {
277 mov CCSCBRAM, DINDEX;
283 * If the initiator doesn't feel like providing a tag number,
284 * we've got a failed selection and must transition to bus
287 test SCSISIGI, ATNI jz target_busfree;
290 * Store the tag for the host.
293 if ((ahc->features & AHC_CMD_CHAN) != 0) {
294 mov CCSCBRAM, DINDEX;
298 mov INITIATOR_TAG, DINDEX;
299 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
302 /* Terminate the ident list */
303 if ((ahc->features & AHC_CMD_CHAN) != 0) {
304 mvi CCSCBRAM, SCB_LIST_NULL;
306 mvi DFDAT, SCB_LIST_NULL;
308 or SEQ_FLAGS, TARG_CMD_PENDING|IDENTIFY_SEEN;
309 test SEQ_FLAGS2, TARGET_MSG_PENDING
310 jnz target_mesgout_pending;
311 test SCSISIGI, ATNI jnz target_mesgout_continue;
315 ident_messages_done_msg_pending:
316 or SEQ_FLAGS2, TARGET_MSG_PENDING;
317 jmp ident_messages_done;
320 * Pushed message loop to allow the kernel to
321 * run it's own target mode message state engine.
323 host_target_message_loop:
324 mvi HOST_MSG_LOOP call set_seqint;
325 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
326 test SSTAT0, SPIORDY jz .;
327 jmp host_target_message_loop;
330 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
332 * Reselection has been initiated by a target. Make a note that we've been
333 * reselected, but haven't seen an IDENTIFY message from the target yet.
336 /* XXX test for and handle ONE BIT condition */
337 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
338 and SAVED_SCSIID, SELID_MASK, SELID;
339 if ((ahc->features & AHC_ULTRA2) != 0) {
340 and A, OID, SCSIID_ULTRA2;
345 if ((ahc->features & AHC_TWIN) != 0) {
346 test SBLKCTL, SELBUSB jz . + 2;
347 or SAVED_SCSIID, TWIN_CHNLB;
349 mvi CLRSINT0, CLRSELDI;
354 call add_scb_to_free_list;
355 jmp poll_for_work_loop;
359 * If bus reset interrupts have been disabled (from a previous
360 * reset), re-enable them now. Resets are only of interest
361 * when we have outstanding transactions, so we can safely
362 * defer re-enabling the interrupt until, as an initiator,
363 * we start sending out transactions again.
365 test SIMODE1, ENSCSIRST jnz . + 3;
366 mvi CLRSINT1, CLRSCSIRSTI;
367 or SIMODE1, ENSCSIRST;
368 if ((ahc->features & AHC_TWIN) != 0) {
369 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
370 test SCB_SCSIID, TWIN_CHNLB jz . + 2;
372 mov SBLKCTL,SINDEX; /* select channel */
375 if ((ahc->features & AHC_ULTRA2) != 0) {
376 mov SCSIID_ULTRA2, SCB_SCSIID;
377 } else if ((ahc->features & AHC_TWIN) != 0) {
378 and SCSIID, TWIN_TID|OID, SCB_SCSIID;
380 mov SCSIID, SCB_SCSIID;
382 if ((ahc->flags & AHC_TARGETROLE) != 0) {
383 mov SINDEX, SCSISEQ_TEMPLATE;
384 test SCB_CONTROL, TARGET_SCB jz . + 2;
386 mov SCSISEQ, SINDEX ret;
388 mov SCSISEQ, SCSISEQ_TEMPLATE ret;
392 * Initialize transfer settings and clear the SCSI channel.
393 * SINDEX should contain any additional bit's the client wants
394 * set in SXFRCTL0. We also assume that the current SCB is
395 * a valid SCB for the target we wish to talk to.
398 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
399 set_transfer_settings:
400 if ((ahc->features & AHC_ULTRA) != 0) {
401 test SCB_CONTROL, ULTRAENB jz . + 2;
405 * Initialize SCSIRATE with the appropriate value for this target.
407 if ((ahc->features & AHC_ULTRA2) != 0) {
408 bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
410 mov SCSIRATE, SCB_SCSIRATE ret;
413 if ((ahc->flags & AHC_TARGETROLE) != 0) {
415 * We carefully toggle SPIOEN to allow us to return the
416 * message byte we receive so it can be checked prior to
417 * driving REQ on the bus for the next byte.
421 * Drive REQ on the bus by enabling SCSI PIO.
424 /* Wait for the byte */
425 test SSTAT0, SPIORDY jz .;
426 /* Prevent our read from triggering another REQ */
427 and SXFRCTL0, ~SPIOEN;
428 /* Save latched contents */
429 mov DINDEX, SCSIDATL ret;
433 * After the selection, remove this SCB from the "waiting SCB"
434 * list. This is achieved by simply moving our "next" pointer into
435 * WAITING_SCBH. Our next pointer will be set to null the next time this
436 * SCB is used, so don't bother with it now.
439 /* Turn off the selection hardware */
440 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
441 mvi CLRSINT0, CLRSELDO;
442 mov SCBPTR, WAITING_SCBH;
443 mov WAITING_SCBH,SCB_NEXT;
444 mov SAVED_SCSIID, SCB_SCSIID;
445 mov SAVED_LUN, SCB_LUN;
446 call initialize_channel;
447 if ((ahc->flags & AHC_TARGETROLE) != 0) {
448 test SSTAT0, TARGET jz initiator_select;
451 * We've just re-selected an initiator.
452 * Assert BSY and setup the phase for
453 * sending our identify messages.
455 mvi P_MESGIN|BSYO call change_phase;
458 * Start out with a simple identify message.
460 or SCB_LUN, MSG_IDENTIFYFLAG call target_outb;
463 * If we are the result of a tagged command, send
464 * a simple Q tag and the tag id.
466 test SCB_CONTROL, TAG_ENB jz . + 3;
467 mvi MSG_SIMPLE_Q_TAG call target_outb;
468 mov SCB_TARGET_ITAG call target_outb;
471 * Now determine what phases the host wants us
474 mov SEQ_FLAGS, SCB_TARGET_PHASES;
476 test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
477 mvi P_MESGIN|BSYO call change_phase;
478 jmp host_target_message_loop;
481 * Start honoring ATN signals now that
482 * we properly identified ourselves.
484 test SCSISIGI, ATNI jnz target_mesgout;
485 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
486 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
487 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
490 * No more work to do. Either disconnect or not depending
491 * on the state of NO_DISCONNECT.
493 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
494 mov RETURN_1, ALLZEROS;
495 call complete_target_cmd;
496 cmp RETURN_1, CONT_MSG_LOOP jne .;
497 if ((ahc->flags & AHC_PAGESCBS) != 0) {
498 mov ALLZEROS call get_free_or_disc_scb;
500 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
501 mov SCB_TAG call dma_scb;
502 call set_transfer_settings;
506 mvi SCSISIGO, P_MESGOUT|BSYO;
507 target_mesgout_continue:
509 target_mesgout_pending:
510 /* Local Processing goes here... */
511 jmp host_target_message_loop;
514 mvi P_MESGIN|BSYO call change_phase;
515 test SEQ_FLAGS, DPHASE jz . + 2;
516 mvi MSG_SAVEDATAPOINTER call target_outb;
517 mvi MSG_DISCONNECT call target_outb;
520 /* Wait for preceding I/O session to complete. */
521 test SCSISIGI, ACKI jnz .;
523 and SIMODE1, ~ENBUSFREE;
524 if ((ahc->features & AHC_ULTRA2) != 0) {
528 mvi LASTPHASE, P_BUSFREE;
529 call complete_target_cmd;
534 * The target has dropped ATN (doesn't want to abort or BDR)
535 * and we believe this selection to be valid. If the ring
536 * buffer for new commands is full, return busy or queue full.
538 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
539 and A, HOST_TQINPOS, HS_MAILBOX;
541 mov A, KERNEL_TQINPOS;
543 cmp TQINPOS, A jne tqinfifo_has_space;
544 mvi P_STATUS|BSYO call change_phase;
545 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
546 mvi STATUS_QUEUE_FULL call target_outb;
547 jmp target_busfree_wait;
548 mvi STATUS_BUSY call target_outb;
549 jmp target_busfree_wait;
551 mvi P_COMMAND|BSYO call change_phase;
555 if ((ahc->features & AHC_CMD_CHAN) != 0) {
562 * Determine the number of bytes to read
563 * based on the command group code via table lookup.
564 * We reuse the first 8 bytes of the TARG_SCSIRATE
565 * BIOS array for this table. Count is one less than
566 * the total for the command since we've already fetched
569 shr A, CMD_GROUP_CODE_SHIFT;
570 add SINDEX, CMDSIZE_TABLE, A;
573 test A, 0xFF jz command_phase_done;
576 test SSTAT0, SPIORDY jz .;
578 and SXFRCTL0, ~SPIOEN; /* Last Byte */
579 if ((ahc->features & AHC_CMD_CHAN) != 0) {
580 mov CCSCBRAM, SCSIDATL;
585 test A, 0xFF jnz command_loop;
588 and SEQ_FLAGS, ~CMDPHASE_PENDING;
593 * Data phases on the bus are from the
594 * perspective of the initiator. The dma
595 * code looks at LASTPHASE to determine the
596 * data direction of the DMA. Toggle it for
599 xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
600 or SCB_TARGET_DATA_DIR, BSYO call change_phase;
604 mvi P_STATUS|BSYO call change_phase;
605 mvi LASTPHASE, P_STATUS;
606 mov SCB_SCSI_STATUS call target_outb;
607 /* XXX Watch for ATN or parity errors??? */
608 mvi SCSISIGO, P_MESGIN|BSYO;
609 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
610 mov ALLZEROS call target_outb;
611 jmp target_busfree_wait;
614 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
615 mov SCB_TAG jmp complete_post;
616 if ((ahc->features & AHC_CMD_CHAN) != 0) {
617 /* Set the valid byte */
619 mov CCSCBRAM, ALLONES;
621 or CCSCBCTL, CCSCBEN|CCSCBRESET;
622 test CCSCBCTL, CCSCBDONE jz .;
625 /* Set the valid byte */
626 or DFCNTRL, FIFORESET;
627 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
629 mvi 28 call set_hcnt;
630 or DFCNTRL, HDMAEN|FIFOFLUSH;
634 mvi INTSTAT,CMDCMPLT ret;
637 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
640 * As soon as we get a successful selection, the target
641 * should go into the message out phase since we have ATN
644 mvi MSG_OUT, MSG_IDENTIFYFLAG;
645 or SEQ_FLAGS, IDENTIFY_SEEN;
648 * Main loop for information transfer phases. Wait for the
649 * target to assert REQ before checking MSG, C/D and I/O for
658 test A, ~P_DATAIN jz p_data;
659 cmp A,P_COMMAND je p_command;
660 cmp A,P_MESGOUT je p_mesgout;
661 cmp A,P_STATUS je p_status;
662 cmp A,P_MESGIN je p_mesgin;
664 mvi BAD_PHASE call set_seqint;
665 jmp ITloop; /* Try reading the bus again. */
668 and SIMODE1, ~ENBUSFREE;
669 mov NONE, SCSIDATL; /* Ack the last byte */
670 if ((ahc->features & AHC_ULTRA2) != 0) {
671 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
673 and SXFRCTL0, ~SPIOEN;
674 test SSTAT1,REQINIT|BUSFREE jz .;
675 test SSTAT1, BUSFREE jnz poll_for_work;
676 mvi MISSED_BUSFREE call set_seqint;
681 * We assume that the kernel driver may reset us
682 * at any time, even in the middle of a DMA, so
686 or SXFRCTL0, CLRSTCNT|CLRCHN;
689 * We don't know the target we will connect to,
690 * so default to narrow transfers to avoid
693 if ((ahc->features & AHC_ULTRA2) != 0) {
694 bmov SCSIRATE, ALLZEROS, 2;
697 if ((ahc->features & AHC_ULTRA) != 0) {
698 and SXFRCTL0, ~(FAST20);
701 mvi LASTPHASE, P_BUSFREE;
702 /* clear target specific flags */
706 clr A; /* add sizeof(struct scatter) */
707 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
708 adc SCB_RESIDUAL_SGPTR[1],A;
709 adc SCB_RESIDUAL_SGPTR[2],A;
710 adc SCB_RESIDUAL_SGPTR[3],A ret;
712 if ((ahc->features & AHC_CMD_CHAN) != 0) {
714 test CCSGCTL, CCSGEN jz return;
715 test CCSGCTL, CCSGDONE jz .;
716 disable_ccsgen_fetch_done:
718 test CCSGCTL, CCSGEN jnz .;
722 * Do we need any more segments for this transfer?
724 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
726 /* Did we just finish fetching segs? */
727 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
729 /* Are we actively fetching segments? */
730 test CCSGCTL, CCSGEN jnz return;
733 * Do we have any prefetch left???
735 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
738 * Need to fetch segments, but we can only do that
739 * if the command channel is completely idle. Make
740 * sure we don't have an SCB prefetch going on.
742 test CCSCBCTL, CCSCBEN jnz return;
745 * We fetch a "cacheline aligned" and sized amount of data
746 * so we don't end up referencing a non-existant page.
747 * Cacheline aligned is in quotes because the kernel will
748 * set the prefetch amount to a reasonable level if the
749 * cacheline size is unknown.
751 mvi CCHCNT, SG_PREFETCH_CNT;
752 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
753 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
754 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
755 idle_sgfetch_complete:
756 call disable_ccsgen_fetch_done;
757 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
759 if ((ahc->features & AHC_ULTRA2) != 0) {
760 /* Does the hardware have space for another SG entry? */
761 test DFSTATUS, PRELOAD_AVAIL jz return;
762 bmov HADDR, CCSGRAM, 7;
763 test HCNT[0], 0x1 jz . + 2;
764 xor DATA_COUNT_ODD, 0x1;
765 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
766 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
767 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
770 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
771 test DATA_COUNT_ODD, 0x1 jz . + 2;
773 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
775 mov SG_CACHE_PRE, SINDEX;
776 /* Load the segment */
777 or DFCNTRL, PRELOADEN;
782 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
784 * Calculate the trailing portion of this S/G segment that cannot
785 * be transferred using memory write and invalidate PCI transactions.
786 * XXX Can we optimize this for PCI writes only???
790 * If the ending address is on a cacheline boundary,
791 * there is no need for an extra segment.
795 and A, CACHESIZE_MASK;
796 test A, 0xFF jz return;
799 * If the transfer is less than a cachline,
800 * there is no need for an extra segment.
802 test HCNT[1], 0xFF jnz calc_mwi_residual_final;
803 test HCNT[2], 0xFF jnz calc_mwi_residual_final;
804 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
807 calc_mwi_residual_final:
817 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_data_okay;
818 mvi NO_IDENT jmp set_seqint;
820 if ((ahc->features & AHC_ULTRA2) != 0) {
821 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
823 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
825 test LASTPHASE, IOI jnz . + 2;
826 or DMAPARAMS, DIRECTION;
827 if ((ahc->features & AHC_CMD_CHAN) != 0) {
828 /* We don't have any valid S/G elements */
829 mvi CCSGADDR, SG_PREFETCH_CNT;
831 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
834 * If we re-enter the data phase after going through another
835 * phase, our transfer location has almost certainly been
836 * corrupted by the interveining, non-data, transfers. Ask
837 * the host driver to fix us up based on the transfer residual.
839 mvi PDATA_REINIT call set_seqint;
842 data_phase_initialize:
843 /* We have seen a data phase for the first time */
844 or SEQ_FLAGS, DPHASE;
847 * Initialize the DMA address and counter from the SCB.
848 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
849 * flag in the highest byte of the data count. We cannot
850 * modify the saved values in the SCB until we see a save
851 * data pointers message.
853 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
854 /* The lowest address byte must be loaded last. */
855 mov SCB_DATACNT[3] call set_hhaddr;
857 if ((ahc->features & AHC_CMD_CHAN) != 0) {
858 bmov HADDR, SCB_DATAPTR, 7;
859 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
862 mvi SCB_DATAPTR call bcopy_7;
863 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
864 mvi SCB_DATACNT + 3 call bcopy_5;
866 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
867 call calc_mwi_residual;
869 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
870 and DATA_COUNT_ODD, 0x1, HCNT[0];
872 if ((ahc->features & AHC_ULTRA2) == 0) {
873 if ((ahc->features & AHC_CMD_CHAN) != 0) {
876 call set_stcnt_from_hcnt;
881 /* Guard against overruns */
882 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
885 * Turn on `Bit Bucket' mode, wait until the target takes
886 * us to another phase, and then notify the host.
888 and DMAPARAMS, DIRECTION;
889 mov DFCNTRL, DMAPARAMS;
890 or SXFRCTL1,BITBUCKET;
891 if ((ahc->features & AHC_DT) == 0) {
892 test SSTAT1,PHASEMIS jz .;
894 test SCSIPHASE, DATA_PHASE_MASK jnz .;
896 and SXFRCTL1, ~BITBUCKET;
897 mvi DATA_OVERRUN call set_seqint;
901 if ((ahc->features & AHC_ULTRA2) != 0) {
902 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
903 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
905 test DATA_COUNT_ODD, 0x1 jz . + 2;
907 mov SG_CACHE_PRE, SINDEX;
908 mov DFCNTRL, DMAPARAMS;
912 * The transfer is complete if either the last segment
913 * completes or the target changes phase.
915 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
916 if ((ahc->features & AHC_DT) == 0) {
917 if ((ahc->flags & AHC_TARGETROLE) != 0) {
919 * As a target, we control the phases,
920 * so ignore PHASEMIS.
922 test SSTAT0, TARGET jnz ultra2_dma_loop;
924 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
925 test SSTAT1,PHASEMIS jz ultra2_dma_loop;
928 test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
933 * The transfer has terminated either due to a phase
934 * change, and/or the completion of the last segment.
935 * We have two goals here. Do as much other work
936 * as possible while the data fifo drains on a read
937 * and respond as quickly as possible to the standard
938 * messages (save data pointers/disconnect and command
939 * complete) that usually follow a data phase.
941 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
943 * On chips with broken auto-flush, start
944 * the flushing process now. We'll poke
945 * the chip from time to time to keep the
946 * flush process going as we complete the
949 or DFCNTRL, FIFOFLUSH;
952 * We assume that, even though data may still be
953 * transferring to the host, that the SCSI side of
954 * the DMA engine is now in a static state. This
955 * allows us to update our notion of where we are
958 * If, by chance, we stopped before being able
959 * to fetch additional segments for this transfer,
960 * yet the last S/G was completely exhausted,
961 * call our idle loop until it is able to load
962 * another segment. This will allow us to immediately
963 * pickup on the next segment on the next data phase.
965 * If we happened to stop on the last segment, then
966 * our residual information is still correct from
967 * the idle loop and there is no need to perform
971 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
972 /* Record if we've consumed all S/G entries */
973 test SSTAT2, SHVALID jnz residuals_correct;
974 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
975 jmp residuals_correct;
978 test SSTAT2, SHVALID jnz sgptr_fixup;
980 jmp ultra2_ensure_sg;
984 * Fixup the residual next S/G pointer. The S/G preload
985 * feature of the chip allows us to load two elements
986 * in addition to the currently active element. We
987 * store the bottom byte of the next S/G pointer in
988 * the SG_CACEPTR register so we can restore the
989 * correct value when the DMA completes. If the next
990 * sg ptr value has advanced to the point where higher
991 * bytes in the address have been affected, fix them
994 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
995 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
996 add SCB_RESIDUAL_SGPTR[1], -1;
997 adc SCB_RESIDUAL_SGPTR[2], -1;
998 adc SCB_RESIDUAL_SGPTR[3], -1;
1000 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1002 test SG_CACHE_SHADOW, ODD_SEG jz . + 2;
1003 or DATA_COUNT_ODD, 0x1;
1004 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1007 * Go ahead and shut down the DMA engine now.
1008 * In the future, we'll want to handle end of
1009 * transfer messages prior to doing this, but this
1010 * requires similar restructuring for pre-ULTRA2
1013 test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
1015 if ((ahc->features & AHC_DT) == 0) {
1016 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1018 * On Rev A of the aic7890, the autoflush
1019 * feature doesn't function correctly.
1020 * Perform an explicit manual flush. During
1021 * a manual flush, the FIFOEMP bit becomes
1022 * true every time the PCI FIFO empties
1023 * regardless of the state of the SCSI FIFO.
1024 * It can take up to 4 clock cycles for the
1025 * SCSI FIFO to get data into the PCI FIFO
1026 * and for FIFOEMP to de-assert. Here we
1027 * guard against this condition by making
1028 * sure the FIFOEMP bit stays on for 5 full
1031 or DFCNTRL, FIFOFLUSH;
1032 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1033 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1034 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1035 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1037 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1040 * We enable the auto-ack feature on DT capable
1041 * controllers. This means that the controller may
1042 * have already transferred some overrun bytes into
1043 * the data FIFO and acked them on the bus. The only
1044 * way to detect this situation is to wait for
1045 * LAST_SEG_DONE to come true on a completed transfer
1046 * and then test to see if the data FIFO is non-empty.
1048 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 4;
1049 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1050 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1052 jmp data_phase_loop;
1053 test DFSTATUS, FIFOEMP jz .;
1056 /* Don't clobber an inprogress host data transfer */
1057 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1059 and DFCNTRL, ~(SCSIEN|HDMAEN);
1060 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1061 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1063 * Keep HHADDR cleared for future, 32bit addressed
1064 * only, DMA operations.
1066 * Due to bayonette style S/G handling, our residual
1067 * data must be "fixed up" once the transfer is halted.
1068 * Here we fixup the HSHADDR stored in the high byte
1069 * of the residual data cnt. By postponing the fixup,
1070 * we can batch the clearing of HADDR with the fixup.
1071 * If we halted on the last segment, the residual is
1072 * already correct. If we are not on the last
1073 * segment, copy the high address directly from HSHADDR.
1074 * We don't need to worry about maintaining the
1075 * SG_LAST_SEG flag as it will always be false in the
1076 * case where an update is required.
1078 or DSCOMMAND1, HADDLDSEL0;
1079 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1080 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1082 and DSCOMMAND1, ~HADDLDSEL0;
1085 /* If we are the last SG block, tell the hardware. */
1086 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1087 && ahc->pci_cachesize != 0) {
1088 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1090 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1091 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1092 test SSTAT0, TARGET jz dma_last_sg;
1093 if ((ahc->flags & AHC_TMODE_WIDEODD_BUG) != 0) {
1094 test DMAPARAMS, DIRECTION jz dma_mid_sg;
1098 and DMAPARAMS, ~WIDEODD;
1100 /* Start DMA data transfer. */
1101 mov DFCNTRL, DMAPARAMS;
1103 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1106 test SSTAT0,DMADONE jnz dma_dmadone;
1107 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1110 * We will be "done" DMAing when the transfer count goes to
1111 * zero, or the target changes the phase (in light of this,
1112 * it makes sense that the DMA circuitry doesn't ACK when
1113 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1114 * the data FIFO should be flushed auto-magically on STCNT=0
1115 * or a phase change, so just wait for FIFO empty status.
1118 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1120 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1122 /* Don't clobber an inprogress host data transfer */
1123 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1126 * Now shut off the DMA and make sure that the DMA
1127 * hardware has actually stopped. Touching the DMA
1128 * counters, etc. while a DMA is active will result
1129 * in an ILLSADDR exception.
1132 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1135 * Some revisions of the aic78XX have a problem where, if the
1136 * data fifo is full, but the PCI input latch is not empty,
1137 * HDMAEN cannot be cleared. The fix used here is to drain
1138 * the prefetched but unused data from the data fifo until
1139 * there is space for the input latch to drain.
1141 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1144 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1146 /* See if we have completed this last segment */
1147 test STCNT[0], 0xff jnz data_phase_finish;
1148 test STCNT[1], 0xff jnz data_phase_finish;
1149 test STCNT[2], 0xff jnz data_phase_finish;
1152 * Advance the scatter-gather pointers if needed
1154 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1155 && ahc->pci_cachesize != 0) {
1156 test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
1158 * Reload HADDR from SHADDR and setup the
1159 * count to be the size of our residual.
1161 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1162 bmov HADDR, SHADDR, 4;
1163 mov HCNT, MWI_RESIDUAL;
1164 bmov HCNT[1], ALLZEROS, 2;
1167 mvi SHADDR call bcopy_4;
1168 mov MWI_RESIDUAL call set_hcnt;
1174 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
1175 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
1176 jmp data_phase_finish;
1179 * Load the next SG element's data address and length
1180 * into the DMA engine. If we don't have hardware
1181 * to perform a prefetch, we'll have to fetch the
1182 * segment from host memory first.
1184 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1185 /* Wait for the idle loop to complete */
1186 test CCSGCTL, CCSGEN jz . + 3;
1188 test CCSGCTL, CCSGEN jnz . - 1;
1189 bmov HADDR, CCSGRAM, 7;
1191 * Workaround for flaky external SCB RAM
1192 * on certain aic7895 setups. It seems
1193 * unable to handle direct transfers from
1194 * S/G ram to certain SCB locations.
1196 mov SINDEX, CCSGRAM;
1197 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1199 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1200 mov ALLZEROS call set_hhaddr;
1203 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1205 mvi SG_SIZEOF call set_hcnt;
1207 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1213 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1216 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1217 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1220 * The lowest address byte must be loaded
1221 * last as it triggers the computation of
1222 * some items in the PCI block. The ULTRA2
1223 * chips do this on PRELOAD.
1227 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1228 && ahc->pci_cachesize != 0) {
1229 call calc_mwi_residual;
1232 /* Point to the new next sg in memory */
1236 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1237 bmov STCNT, HCNT, 3;
1239 call set_stcnt_from_hcnt;
1241 /* Track odd'ness */
1242 test HCNT[0], 0x1 jz . + 2;
1243 xor DATA_COUNT_ODD, 0x1;
1245 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1246 test SSTAT0, TARGET jnz data_phase_loop;
1251 * If the target has left us in data phase, loop through
1252 * the dma code again. In the case of ULTRA2 adapters,
1253 * we should only loop if there is a data overrun. For
1254 * all other adapters, we'll loop after each S/G element
1255 * is loaded as well as if there is an overrun.
1257 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1258 test SSTAT0, TARGET jnz data_phase_done;
1260 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1261 test SSTAT1, REQINIT jz .;
1262 if ((ahc->features & AHC_DT) == 0) {
1263 test SSTAT1,PHASEMIS jz data_phase_loop;
1265 test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
1271 * After a DMA finishes, save the SG and STCNT residuals back into
1272 * the SCB. We use STCNT instead of HCNT, since it's a reflection
1273 * of how many bytes were transferred on the SCSI (as opposed to the
1276 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1277 /* Kill off any pending prefetch */
1278 call disable_ccsgen;
1281 if ((ahc->features & AHC_ULTRA2) == 0) {
1283 * Clear the high address byte so that all other DMA
1284 * operations, which use 32bit addressing, can assume
1287 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1288 mov ALLZEROS call set_hhaddr;
1293 * Update our residual information before the information is
1294 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1295 * transferred all data, no update is needed.
1298 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1299 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1300 && ahc->pci_cachesize != 0) {
1301 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1302 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1304 mov A, MWI_RESIDUAL;
1305 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1307 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
1308 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
1310 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1313 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1315 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1316 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1318 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1319 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1320 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1322 residual_update_done:
1324 * Since we've been through a data phase, the SCB_RESID* fields
1325 * are now initialized. Clear the full residual flag.
1327 and SCB_SGPTR[0], ~SG_FULL_RESID;
1329 if ((ahc->features & AHC_ULTRA2) != 0) {
1330 /* Clear the channel in case we return to data phase later */
1331 or SXFRCTL0, CLRSTCNT|CLRCHN;
1332 or SXFRCTL0, CLRSTCNT|CLRCHN;
1335 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1336 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1337 and SEQ_FLAGS, ~DPHASE_PENDING;
1339 * For data-in phases, wait for any pending acks from the
1340 * initiator before changing phase. We only need to
1341 * send Ignore Wide Residue messages for data-in phases.
1343 test DFCNTRL, DIRECTION jz target_ITloop;
1344 test SSTAT1, REQINIT jnz .;
1345 test DATA_COUNT_ODD, 0x1 jz target_ITloop;
1346 test SCSIRATE, WIDEXFER jz target_ITloop;
1348 * Issue an Ignore Wide Residue Message.
1350 mvi P_MESGIN|BSYO call change_phase;
1351 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1352 mvi 1 call target_outb;
1358 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1360 * Command phase. Set up the DMA registers and let 'er rip.
1363 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_command_okay;
1364 mvi NO_IDENT jmp set_seqint;
1367 if ((ahc->features & AHC_ULTRA2) != 0) {
1368 bmov HCNT[0], SCB_CDB_LEN, 1;
1369 bmov HCNT[1], ALLZEROS, 2;
1370 mvi SG_CACHE_PRE, LAST_SEG;
1371 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1372 bmov STCNT[0], SCB_CDB_LEN, 1;
1373 bmov STCNT[1], ALLZEROS, 2;
1375 mov STCNT[0], SCB_CDB_LEN;
1379 add NONE, -13, SCB_CDB_LEN;
1380 mvi SCB_CDB_STORE jnc p_command_embedded;
1381 p_command_from_host:
1382 if ((ahc->features & AHC_ULTRA2) != 0) {
1383 bmov HADDR[0], SCB_CDB_PTR, 4;
1384 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
1386 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1387 bmov HADDR[0], SCB_CDB_PTR, 4;
1388 bmov HCNT, STCNT, 3;
1391 mvi SCB_CDB_PTR call bcopy_4;
1392 mov SCB_CDB_LEN call set_hcnt;
1394 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
1399 * The data fifo seems to require 4 byte aligned
1400 * transfers from the sequencer. Force this to
1401 * be the case by clearing HADDR[0] even though
1402 * we aren't going to touch host memory.
1405 if ((ahc->features & AHC_ULTRA2) != 0) {
1406 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
1407 bmov DFDAT, SCB_CDB_STORE, 12;
1408 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1409 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1411 * On the 7895 the data FIFO will
1412 * get corrupted if you try to dump
1413 * data from external SCB memory into
1414 * the FIFO while it is enabled. So,
1415 * fill the fifo and then enable SCSI
1418 mvi DFCNTRL, (DIRECTION|FIFORESET);
1420 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1422 bmov DFDAT, SCB_CDB_STORE, 12;
1423 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1424 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
1426 or DFCNTRL, FIFOFLUSH;
1429 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1430 call copy_to_fifo_6;
1431 call copy_to_fifo_6;
1432 or DFCNTRL, FIFOFLUSH;
1435 if ((ahc->features & AHC_DT) == 0) {
1436 test SSTAT0, SDONE jnz . + 2;
1437 test SSTAT1, PHASEMIS jz p_command_loop;
1439 * Wait for our ACK to go-away on it's own
1440 * instead of being killed by SCSIEN getting cleared.
1442 test SCSISIGI, ACKI jnz .;
1444 test DFCNTRL, SCSIEN jnz p_command_loop;
1446 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1447 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
1448 if ((ahc->features & AHC_ULTRA2) != 0) {
1449 /* Drop any residual from the S/G Preload queue */
1450 or SXFRCTL0, CLRSTCNT;
1455 * Status phase. Wait for the data byte to appear, then read it
1456 * and store it into the SCB.
1459 test SEQ_FLAGS,IDENTIFY_SEEN jnz p_status_okay;
1460 mvi NO_IDENT jmp set_seqint;
1462 mov SCB_SCSI_STATUS, SCSIDATL;
1466 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1467 * indentify message sequence and send it to the target. The host may
1468 * override this behavior by setting the MK_MESSAGE bit in the SCB
1469 * control byte. This will cause us to interrupt the host and allow
1470 * it to handle the message phase completely on its own. If the bit
1471 * associated with this target is set, we will also interrupt the host,
1472 * thereby allowing it to send a message on the next selection regardless
1473 * of the transaction being sent.
1475 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
1476 * This is done to allow the host to send messages outside of an identify
1477 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
1478 * on an SCB that might not be for the current nexus. (For example, a
1479 * BDR message in responce to a bad reselection would leave us pointed to
1480 * an SCB that doesn't have anything to do with the current target).
1482 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
1483 * bus device reset).
1485 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
1486 * in case the target decides to put us in this phase for some strange
1490 /* Turn on ATN for the retry */
1491 if ((ahc->features & AHC_DT) == 0) {
1492 or SCSISIGO, ATNO, LASTPHASE;
1497 mov SINDEX, MSG_OUT;
1498 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
1499 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
1501 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
1502 test SCB_CONTROL, DISCENB jnz . + 2;
1503 and SINDEX, ~DISCENB;
1505 * Send a tag message if TAG_ENB is set in the SCB control block.
1506 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
1509 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
1510 mov SCSIDATL, SINDEX; /* Send the identify message */
1512 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1513 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
1515 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1516 mov SCB_TAG jmp p_mesgout_onebyte;
1518 * Interrupt the driver, and allow it to handle this message
1519 * phase and any required retries.
1521 p_mesgout_from_host:
1522 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1523 jmp host_message_loop;
1526 mvi CLRSINT1, CLRATNO;
1527 mov SCSIDATL, SINDEX;
1530 * If the next bus phase after ATN drops is message out, it means
1531 * that the target is requesting that the last message(s) be resent.
1534 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1537 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1538 mov LAST_MSG, MSG_OUT;
1539 mvi MSG_OUT, MSG_NOOP; /* No message left */
1543 * Message in phase. Bytes are read using Automatic PIO mode.
1546 mvi ACCUM call inb_first; /* read the 1st message byte */
1548 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1549 cmp A,MSG_DISCONNECT je mesgin_disconnect;
1550 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1551 cmp ALLZEROS,A je mesgin_complete;
1552 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1553 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1554 cmp A,MSG_NOOP je mesgin_done;
1557 * Pushed message loop to allow the kernel to
1558 * run it's own message state engine. To avoid an
1559 * extra nop instruction after signaling the kernel,
1560 * we perform the phase_lock before checking to see
1561 * if we should exit the loop and skip the phase_lock
1562 * in the ITloop. Performing back to back phase_locks
1563 * shouldn't hurt, but why do it twice...
1566 mvi HOST_MSG_LOOP call set_seqint;
1568 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
1569 jmp host_message_loop;
1571 mesgin_ign_wide_residue:
1572 if ((ahc->features & AHC_WIDE) != 0) {
1573 test SCSIRATE, WIDEXFER jz mesgin_reject;
1574 /* Pull the residue byte */
1575 mvi ARG_1 call inb_next;
1576 cmp ARG_1, 0x01 jne mesgin_reject;
1577 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1578 test DATA_COUNT_ODD, 0x1 jz mesgin_done;
1579 mvi IGN_WIDE_RES call set_seqint;
1584 mvi MSG_MESSAGE_REJECT call mk_mesg;
1586 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1591 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
1592 * and trigger a completion interrupt. Before doing so, check to see if there
1593 * is a residual or the status byte is something other than STATUS_GOOD (0).
1594 * In either of these conditions, we upload the SCB back to the host so it can
1595 * process this information. In the case of a non zero status byte, we
1596 * additionally interrupt the kernel driver synchronously, allowing it to
1597 * decide if sense should be retrieved. If the kernel driver wishes to request
1598 * sense, it will fill the kernel SCB with a request sense command, requeue
1599 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1600 * RETURN_1 to SEND_SENSE.
1604 * If ATN is raised, we still want to give the target a message.
1605 * Perhaps there was a parity error on this last message byte.
1606 * Either way, the target should take us to message out phase
1607 * and then attempt to complete the command again. We should use a
1608 * critical section here to guard against a timeout triggering
1609 * for this command and setting ATN while we are still processing
1611 test SCSISIGI, ATNI jnz mesgin_done;
1615 * See if we attempted to deliver a message but the target ingnored us.
1617 test SCB_CONTROL, MK_MESSAGE jz . + 2;
1618 mvi MKMSG_FAILED call set_seqint;
1621 * Check for residuals
1623 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
1624 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1625 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1627 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */
1629 or SCB_SGPTR, SG_RESID_VALID;
1630 mvi DMAPARAMS, FIFORESET;
1631 mov SCB_TAG call dma_scb;
1632 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */
1633 mvi BAD_STATUS call set_seqint; /* let driver know */
1634 cmp RETURN_1, SEND_SENSE jne complete;
1635 call add_scb_to_free_list;
1638 mov SCB_TAG call complete_post;
1643 /* Post the SCBID in SINDEX and issue an interrupt */
1644 call add_scb_to_free_list;
1646 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1651 mvi QOUTFIFO_OFFSET call post_byte_setup;
1652 mov ARG_1 call post_byte;
1653 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1656 mvi INTSTAT,CMDCMPLT ret;
1658 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1660 * Is it a disconnect message? Set a flag in the SCB to remind us
1661 * and await the bus going free. If this is an untagged transaction
1662 * store the SCB id for it in our untagged target table for lookup on
1667 * If ATN is raised, we still want to give the target a message.
1668 * Perhaps there was a parity error on this last message byte
1669 * or we want to abort this command. Either way, the target
1670 * should take us to message out phase and then attempt to
1672 * XXX - Wait for more testing.
1673 test SCSISIGI, ATNI jnz mesgin_done;
1676 or SCB_CONTROL,DISCONNECTED;
1677 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1678 call add_scb_to_disc_list;
1680 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1682 mov SAVED_LUN, SCB_LUN;
1683 mov SCB_SCSIID call set_busy_target;
1687 * Save data pointers message:
1688 * Copying RAM values back to SCB, for Save Data Pointers message, but
1689 * only if we've actually been into a data phase to change them. This
1690 * protects against bogus data in scratch ram and the residual counts
1691 * since they are only initialized when we go into data_in or data_out.
1692 * Ack the message as soon as possible. For chips without S/G pipelining,
1693 * we can only ack the message after SHADDR has been saved. On these
1694 * chips, SHADDR increments with every bus transaction, even PIO.
1697 if ((ahc->features & AHC_ULTRA2) != 0) {
1698 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1699 test SEQ_FLAGS, DPHASE jz ITloop;
1701 test SEQ_FLAGS, DPHASE jz mesgin_done;
1705 * If we are asked to save our position at the end of the
1706 * transfer, just mark us at the end rather than perform a
1709 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1710 or SCB_SGPTR, SG_LIST_NULL;
1711 if ((ahc->features & AHC_ULTRA2) != 0) {
1720 * The SCB_SGPTR becomes the next one we'll download,
1721 * and the SCB_DATAPTR becomes the current SHADDR.
1722 * Use the residual number since STCNT is corrupted by
1723 * any message transfer.
1725 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1726 bmov SCB_DATAPTR, SHADDR, 4;
1727 if ((ahc->features & AHC_ULTRA2) == 0) {
1728 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1730 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
1732 mvi DINDEX, SCB_DATAPTR;
1733 mvi SHADDR call bcopy_4;
1734 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1735 mvi SCB_RESIDUAL_DATACNT call bcopy_8;
1740 * Restore pointers message? Data pointers are recopied from the
1741 * SCB anytime we enter a data phase for the first time, so all
1742 * we need to do is clear the DPHASE flag and let the data phase
1746 and SEQ_FLAGS, ~DPHASE; /*
1748 * the next time through
1754 * Index into our Busy Target table. SINDEX and DINDEX are modified
1755 * upon return. SCBPTR may be modified by this action.
1758 shr DINDEX, 4, SINDEX;
1759 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1760 mov SCBPTR, SAVED_LUN;
1761 add DINDEX, SCB_64_BTT;
1763 add DINDEX, BUSY_TARGETS;
1765 mov DINDIR, ARG_1 ret;
1768 * Identify message? For a reconnecting target, this tells us the lun
1769 * that the reconnection is for - find the correct SCB and switch to it,
1770 * clearing the "disconnected" bit so we don't "find" it by accident later.
1774 * Determine whether a target is using tagged or non-tagged
1775 * transactions by first looking at the transaction stored in
1776 * the busy target array. If there is no untagged transaction
1777 * for this target or the transaction is for a different lun, then
1778 * this must be an untagged transaction.
1780 shr SINDEX, 4, SAVED_SCSIID;
1781 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1782 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1783 add SINDEX, SCB_64_BTT;
1784 mov SCBPTR, SAVED_LUN;
1785 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1786 add NONE, -SCB_64_BTT, SINDEX;
1788 mvi INTSTAT, OUT_OF_RANGE;
1790 add NONE, -(SCB_64_BTT + 16), SINDEX;
1792 mvi INTSTAT, OUT_OF_RANGE;
1796 add SINDEX, BUSY_TARGETS;
1797 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1798 add NONE, -BUSY_TARGETS, SINDEX;
1800 mvi INTSTAT, OUT_OF_RANGE;
1802 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1804 mvi INTSTAT, OUT_OF_RANGE;
1809 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
1810 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1811 mov ARG_1 call findSCB;
1815 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1816 jmp setup_SCB_id_lun_okay;
1819 * We only allow one untagged command per-target
1820 * at a time. So, if the lun doesn't match, look
1821 * for a tag message.
1824 cmp SAVED_LUN, A je setup_SCB_id_lun_okay;
1825 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1827 * findSCB removes the SCB from the
1828 * disconnected list, so we must replace
1829 * it there should this SCB be for another
1837 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1838 * If we get one, we use the tag returned to find the proper
1839 * SCB. With SCB paging, we must search for non-tagged
1840 * transactions since the SCB may exist in any slot. If we're not
1841 * using SCB paging, we can use the tag as the direct index to the
1845 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1848 mov NONE,SCSIDATL; /* ACK Identify MSG */
1850 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1853 cmp LASTPHASE, P_MESGIN jne not_found;
1854 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1857 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
1859 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1860 mvi ARG_1 call inb_next; /* tag value */
1861 mov ARG_1 call findSCB;
1863 mvi ARG_1 call inb_next; /* tag value */
1868 * Ensure that the SCB the tag points to is for
1869 * an SCB transaction to the reconnecting target.
1872 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1876 cmp SAVED_SCSIID, A jne not_found_cleanup_scb;
1877 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1882 cmp SAVED_LUN, A jne not_found_cleanup_scb;
1883 setup_SCB_id_lun_okay:
1884 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1887 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
1888 and SCB_CONTROL,~DISCONNECTED;
1889 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged;
1890 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1893 mvi ARG_1, SCB_LIST_NULL;
1894 mov SAVED_SCSIID call set_busy_target;
1895 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1899 mvi SEQ_FLAGS,IDENTIFY_SEEN; /* make note of IDENTIFY */
1900 call set_transfer_settings;
1901 /* See if the host wants to send a message upon reconnection */
1902 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1903 mvi HOST_MSG call mk_mesg;
1906 not_found_cleanup_scb:
1907 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1911 mvi NO_MATCH call set_seqint;
1915 if ((ahc->features & AHC_DT) == 0) {
1916 or SCSISIGO, ATNO, LASTPHASE;
1920 mov MSG_OUT,SINDEX ret;
1923 * Functions to read data in Automatic PIO mode.
1925 * According to Adaptec's documentation, an ACK is not sent on input from
1926 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1927 * latched (the usual way), then read the data byte directly off the bus
1928 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1929 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1930 * spec guarantees that the target will hold the data byte on the bus until
1933 * The assumption here is that these are called in a particular sequence,
1934 * and that REQ is already set when inb_first is called. inb_{first,next}
1935 * use the same calling convention as inb.
1938 mvi PERR_DETECTED call set_seqint;
1941 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1944 * If there is a parity error, wait for the kernel to
1945 * see the interrupt and prepare our message response
1946 * before continuing.
1948 test SSTAT1, REQINIT jz inb_next_wait;
1949 test SSTAT1, SCSIPERR jnz inb_next_wait_perr;
1950 inb_next_check_phase:
1951 and LASTPHASE, PHASE_MASK, SCSISIGI;
1952 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1955 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1957 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1960 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1962 * Change to a new phase. If we are changing the state of the I/O signal,
1963 * from out to in, wait an additional data release delay before continuing.
1966 /* Wait for preceeding I/O session to complete. */
1967 test SCSISIGI, ACKI jnz .;
1969 /* Change the phase */
1970 and DINDEX, IOI, SCSISIGI;
1971 mov SCSISIGO, SINDEX;
1975 * If the data direction has changed, from
1976 * out (initiator driving) to in (target driving),
1977 * we must wait at least a data release delay plus
1978 * the normal bus settle delay. [SCSI III SPI 10.11.0]
1980 cmp DINDEX, A je change_phase_wait;
1981 test SINDEX, IOI jz change_phase_wait;
1982 call change_phase_wait;
1990 * Send a byte to an initiator in Automatic PIO mode.
1993 or SXFRCTL0, SPIOEN;
1994 test SSTAT0, SPIORDY jz .;
1995 mov SCSIDATL, SINDEX;
1996 test SSTAT0, SPIORDY jz .;
1997 and SXFRCTL0, ~SPIOEN ret;
2001 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
2002 * be set to the position of the SCB. If the SCB cannot be found locally,
2003 * it will be paged in from host memory. RETURN_2 stores the address of the
2004 * preceding SCB in the disconnected list which can be used to speed up
2005 * removal of the found SCB from the disconnected list.
2007 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2010 mov A, SINDEX; /* Tag passed in SINDEX */
2011 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
2012 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */
2013 mvi ARG_2, SCB_LIST_NULL; /* Head of list */
2016 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
2018 mov SCBPTR,SCB_NEXT;
2020 cmp SCB_TAG, A jne findSCB_next;
2021 rem_scb_from_disc_list:
2022 cmp ARG_2, SCB_LIST_NULL je rHead;
2023 mov DINDEX, SCB_NEXT;
2026 mov SCB_NEXT, DINDEX;
2027 mov SCBPTR, SINDEX ret;
2029 mov DISCONNECTED_SCBH,SCB_NEXT ret;
2033 * We didn't find it. Page in the SCB.
2035 mov ARG_1, A; /* Save tag */
2036 mov ALLZEROS call get_free_or_disc_scb;
2037 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
2038 mov ARG_1 jmp dma_scb;
2042 * Prepare the hardware to post a byte to host memory given an
2043 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
2047 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2048 mvi DINDEX, CCHADDR;
2049 mvi SHARED_DATA_ADDR call set_1byte_addr;
2051 mvi CCSCBCTL, CCSCBRESET ret;
2054 mvi SHARED_DATA_ADDR call set_1byte_addr;
2055 mvi 1 call set_hcnt;
2056 mvi DFCNTRL, FIFORESET ret;
2060 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2061 bmov CCSCBRAM, SINDEX, 1;
2062 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2063 test CCSCBCTL, CCSCBDONE jz .;
2067 or DFCNTRL, HDMAEN|FIFOFLUSH;
2072 mvi PERR_DETECTED call set_seqint;
2075 * If there is a parity error, wait for the kernel to
2076 * see the interrupt and prepare our message response
2077 * before continuing.
2079 test SSTAT1, REQINIT jz phase_lock;
2080 test SSTAT1, SCSIPERR jnz phase_lock_perr;
2081 phase_lock_latch_phase:
2082 if ((ahc->features & AHC_DT) == 0) {
2083 and SCSISIGO, PHASE_MASK, SCSISIGI;
2085 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
2087 if ((ahc->features & AHC_CMD_CHAN) == 0) {
2089 mov HCNT[0], SINDEX;
2094 set_stcnt_from_hcnt:
2095 mov STCNT[0], HCNT[0];
2096 mov STCNT[1], HCNT[1];
2097 mov STCNT[2], HCNT[2] ret;
2111 mov DINDIR, SINDIR ret;
2114 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2116 * Setup addr assuming that A is an index into
2117 * an array of 32byte objects, SINDEX contains
2118 * the base address of that array, and DINDEX
2119 * contains the base address of the location
2120 * to store the indexed address.
2129 * Setup addr assuming that A is an index into
2130 * an array of 64byte objects, SINDEX contains
2131 * the base address of that array, and DINDEX
2132 * contains the base address of the location
2133 * to store the indexed address.
2140 * Setup addr assuming that A + (ARG_2 * 256) is an
2141 * index into an array of 1byte objects, SINDEX contains
2142 * the base address of that array, and DINDEX contains
2143 * the base address of the location to store the computed
2147 add DINDIR, A, SINDIR;
2149 adc DINDIR, A, SINDIR;
2151 adc DINDIR, A, SINDIR;
2152 adc DINDIR, A, SINDIR ret;
2155 * Either post or fetch an SCB from host memory based on the
2156 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
2160 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2161 mvi DINDEX, CCHADDR;
2162 mvi HSCB_ADDR call set_64byte_addr;
2163 mov CCSCBPTR, SCBPTR;
2164 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
2165 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2166 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64;
2168 mvi CCHCNT, SCB_DOWNLOAD_SIZE;
2170 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
2171 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
2174 mvi CCHCNT, SCB_UPLOAD_SIZE;
2175 if ((ahc->features & AHC_ULTRA2) == 0) {
2176 mvi CCSCBCTL, CCSCBRESET;
2177 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
2178 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2179 test CCSCBCTL, CCSCBDONE jz .;
2180 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2181 mvi CCSCBCTL, CCARREN|CCSCBRESET;
2182 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
2183 mvi CCHCNT, SCB_UPLOAD_SIZE;
2184 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
2185 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
2187 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
2188 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
2192 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
2196 mvi HSCB_ADDR call set_64byte_addr;
2197 mvi SCB_DOWNLOAD_SIZE call set_hcnt;
2198 mov DFCNTRL, DMAPARAMS;
2199 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
2200 /* Fill it with the SCB data */
2202 mvi SINDEX, SCB_BASE;
2203 add A, SCB_DOWNLOAD_SIZE, SINDEX;
2204 copy_scb_tofifo_loop:
2205 call copy_to_fifo_8;
2206 cmp SINDEX, A jne copy_scb_tofifo_loop;
2207 or DFCNTRL, HDMAEN|FIFOFLUSH;
2210 mvi DINDEX, SCB_BASE;
2211 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2213 * The PCI module will only issue a PCI
2214 * retry if the data FIFO is empty. If the
2215 * host disconnects in the middle of a
2216 * transfer, we must empty the fifo of all
2217 * available data to force the chip to
2218 * continue the transfer. This does not
2219 * happen for SCSI transfers as the SCSI module
2220 * will drain the FIFO as data is made available.
2221 * When the hang occurs, we know that a multiple
2222 * of 8 bytes are in the FIFO because the PCI
2223 * module has an 8 byte input latch that only
2224 * dumps to the FIFO when HCNT == 0 or the
2228 /* Wait for at least 8 bytes of data to arrive. */
2230 test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
2232 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
2233 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2234 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2235 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2237 * The PCI module no longer intends to perform
2238 * a PCI transaction. Drain the fifo.
2240 dma_scb_hang_dma_drain_fifo:
2242 add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
2245 cmp DINDEX, A jne . - 1;
2246 cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
2247 je dma_finish_nowait;
2248 /* Restore A as the lines left to transfer. */
2249 add A, -SCB_BASE, DINDEX;
2251 jmp dma_scb_hang_fifo;
2252 dma_scb_hang_dma_done:
2253 and DFCNTRL, ~HDMAEN;
2254 test DFCNTRL, HDMAEN jnz .;
2259 /* If we were putting the SCB, we are done */
2273 mov DINDIR,DFDAT ret;
2287 mov DFDAT,SINDIR ret;
2290 * Wait for DMA from host memory to data FIFO to complete, then disable
2291 * DMA and wait for it to acknowledge that it's off.
2294 test DFSTATUS,HDONE jz dma_finish;
2297 and DFCNTRL, ~HDMAEN;
2298 test DFCNTRL, HDMAEN jnz .;
2302 * Restore an SCB that failed to match an incoming reselection
2303 * to the correct/safe state. If the SCB is for a disconnected
2304 * transaction, it must be returned to the disconnected list.
2305 * If it is not in the disconnected state, it must be free.
2308 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2309 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
2311 add_scb_to_free_list:
2312 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2314 mov SCB_NEXT, FREE_SCBH;
2315 mvi SCB_TAG, SCB_LIST_NULL;
2316 mov FREE_SCBH, SCBPTR ret;
2319 mvi SCB_TAG, SCB_LIST_NULL ret;
2322 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2324 or DSCOMMAND1, HADDLDSEL0;
2325 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2326 and DSCOMMAND1, ~HADDLDSEL0 ret;
2329 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2330 get_free_or_disc_scb:
2332 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2333 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2335 mvi NO_FREE_SCB call set_seqint;
2336 mvi SINDEX, SCB_LIST_NULL ret;
2338 mov SCBPTR, DISCONNECTED_SCBH;
2339 mov DISCONNECTED_SCBH, SCB_NEXT;
2341 mvi DMAPARAMS, FIFORESET;
2342 mov SCB_TAG jmp dma_scb;
2345 mov SCBPTR, FREE_SCBH;
2346 mov FREE_SCBH, SCB_NEXT ret;
2349 add_scb_to_disc_list:
2351 * Link this SCB into the DISCONNECTED list. This list holds the
2352 * candidates for paging out an SCB if one is needed for a new command.
2353 * Modifying the disconnected list is a critical(pause dissabled) section.
2356 mov SCB_NEXT, DISCONNECTED_SCBH;
2357 mov DISCONNECTED_SCBH, SCBPTR ret;
2361 mov INTSTAT, SINDEX;