2 * Inline routines shareable across OS platforms.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
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17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
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20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#33 $
45 #ifndef _AIC7XXX_INLINE_H_
46 #define _AIC7XXX_INLINE_H_
48 /************************* Sequencer Execution Control ************************/
49 static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
50 static __inline int ahc_is_paused(struct ahc_softc *ahc);
51 static __inline void ahc_pause(struct ahc_softc *ahc);
52 static __inline void ahc_unpause(struct ahc_softc *ahc);
55 * Work around any chip bugs related to halting sequencer execution.
56 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
57 * reading a register that will set this signal and deassert it.
58 * Without this workaround, if the chip is paused, by an interrupt or
59 * manual pause while accessing scb ram, accesses to certain registers
60 * will hang the system (infinite pci retries).
63 ahc_pause_bug_fix(struct ahc_softc *ahc)
65 if ((ahc->features & AHC_ULTRA2) != 0)
66 (void)ahc_inb(ahc, CCSCBCTL);
70 * Determine whether the sequencer has halted code execution.
71 * Returns non-zero status if the sequencer is stopped.
74 ahc_is_paused(struct ahc_softc *ahc)
76 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
80 * Request that the sequencer stop and wait, indefinitely, for it
81 * to stop. The sequencer will only acknowledge that it is paused
82 * once it has reached an instruction boundary and PAUSEDIS is
83 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
84 * for critical sections.
87 ahc_pause(struct ahc_softc *ahc)
89 ahc_outb(ahc, HCNTRL, ahc->pause);
92 * Since the sequencer can disable pausing in a critical section, we
93 * must loop until it actually stops.
95 while (ahc_is_paused(ahc) == 0)
98 ahc_pause_bug_fix(ahc);
102 * Allow the sequencer to continue program execution.
103 * We check here to ensure that no additional interrupt
104 * sources that would cause the sequencer to halt have been
105 * asserted. If, for example, a SCSI bus reset is detected
106 * while we are fielding a different, pausing, interrupt type,
107 * we don't want to release the sequencer before going back
108 * into our interrupt handler and dealing with this new
112 ahc_unpause(struct ahc_softc *ahc)
114 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
115 ahc_outb(ahc, HCNTRL, ahc->unpause);
118 /*********************** Untagged Transaction Routines ************************/
119 static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
120 static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
123 * Block our completion routine from starting the next untagged
124 * transaction for this target or target lun.
127 ahc_freeze_untagged_queues(struct ahc_softc *ahc)
129 if ((ahc->flags & AHC_SCB_BTT) == 0)
130 ahc->untagged_queue_lock++;
134 * Allow the next untagged transaction for this target or target lun
135 * to be executed. We use a counting semaphore to allow the lock
136 * to be acquired recursively. Once the count drops to zero, the
137 * transaction queues will be run.
140 ahc_release_untagged_queues(struct ahc_softc *ahc)
142 if ((ahc->flags & AHC_SCB_BTT) == 0) {
143 ahc->untagged_queue_lock--;
144 if (ahc->untagged_queue_lock == 0)
145 ahc_run_untagged_queues(ahc);
149 /************************** Memory mapping routines ***************************/
150 static __inline struct ahc_dma_seg *
151 ahc_sg_bus_to_virt(struct scb *scb,
152 uint32_t sg_busaddr);
153 static __inline uint32_t
154 ahc_sg_virt_to_bus(struct scb *scb,
155 struct ahc_dma_seg *sg);
156 static __inline uint32_t
157 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
158 static __inline void ahc_sync_scb(struct ahc_softc *ahc,
159 struct scb *scb, int op);
160 static __inline void ahc_sync_sglist(struct ahc_softc *ahc,
161 struct scb *scb, int op);
162 static __inline uint32_t
163 ahc_targetcmd_offset(struct ahc_softc *ahc,
166 static __inline struct ahc_dma_seg *
167 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
171 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
172 /* sg_list_phys points to entry 1, not 0 */
175 return (&scb->sg_list[sg_index]);
178 static __inline uint32_t
179 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
183 /* sg_list_phys points to entry 1, not 0 */
184 sg_index = sg - &scb->sg_list[1];
186 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
189 static __inline uint32_t
190 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
192 return (ahc->scb_data->hscb_busaddr
193 + (sizeof(struct hardware_scb) * index));
197 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
199 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
200 ahc->scb_data->hscb_dmamap,
201 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
202 /*len*/sizeof(*scb->hscb), op);
206 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
208 if (scb->sg_count == 0)
211 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
212 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
213 * sizeof(struct ahc_dma_seg),
214 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
217 static __inline uint32_t
218 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
220 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
223 /******************************** Debugging ***********************************/
224 static __inline char *ahc_name(struct ahc_softc *ahc);
226 static __inline char *
227 ahc_name(struct ahc_softc *ahc)
232 /*********************** Miscelaneous Support Functions ***********************/
234 static __inline void ahc_update_residual(struct ahc_softc *ahc,
236 static __inline struct ahc_initiator_tinfo *
237 ahc_fetch_transinfo(struct ahc_softc *ahc,
238 char channel, u_int our_id,
240 struct ahc_tmode_tstate **tstate);
241 static __inline struct scb*
242 ahc_get_scb(struct ahc_softc *ahc);
243 static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
244 static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc,
246 static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
247 static __inline struct scsi_sense_data *
248 ahc_get_sense_buf(struct ahc_softc *ahc,
250 static __inline uint32_t
251 ahc_get_sense_bufaddr(struct ahc_softc *ahc,
255 * Determine whether the sequencer reported a residual
256 * for this SCB/transaction.
259 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
263 sgptr = ahc_le32toh(scb->hscb->sgptr);
264 if ((sgptr & SG_RESID_VALID) != 0)
265 ahc_calc_residual(ahc, scb);
269 * Return pointers to the transfer negotiation information
270 * for the specified our_id/remote_id pair.
272 static __inline struct ahc_initiator_tinfo *
273 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
274 u_int remote_id, struct ahc_tmode_tstate **tstate)
277 * Transfer data structures are stored from the perspective
278 * of the target role. Since the parameters for a connection
279 * in the initiator role to a given target are the same as
280 * when the roles are reversed, we pretend we are the target.
284 *tstate = ahc->enabled_targets[our_id];
285 return (&(*tstate)->transinfo[remote_id]);
289 * Get a free scb. If there are none, see if we can allocate a new SCB.
291 static __inline struct scb *
292 ahc_get_scb(struct ahc_softc *ahc)
296 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
298 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
302 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
307 * Return an SCB resource to the free list.
310 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
312 struct hardware_scb *hscb;
315 /* Clean up for the next user */
316 ahc->scb_data->scbindex[hscb->tag] = NULL;
317 scb->flags = SCB_FREE;
320 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
322 /* Notify the OSM that a resource is now available. */
323 ahc_platform_scb_free(ahc, scb);
326 static __inline struct scb *
327 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
331 scb = ahc->scb_data->scbindex[tag];
333 ahc_sync_scb(ahc, scb,
334 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
339 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
341 struct hardware_scb *q_hscb;
345 * Our queuing method is a bit tricky. The card
346 * knows in advance which HSCB to download, and we
347 * can't disappoint it. To achieve this, the next
348 * SCB to download is saved off in ahc->next_queued_scb.
349 * When we are called to queue "an arbitrary scb",
350 * we copy the contents of the incoming HSCB to the one
351 * the sequencer knows about, swap HSCB pointers and
352 * finally assign the SCB to the tag indexed location
353 * in the scb_array. This makes sure that we can still
354 * locate the correct SCB by SCB_TAG.
356 q_hscb = ahc->next_queued_scb->hscb;
357 saved_tag = q_hscb->tag;
358 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
359 if ((scb->flags & SCB_CDB32_PTR) != 0) {
360 q_hscb->shared_data.cdb_ptr =
361 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
362 + offsetof(struct hardware_scb, cdb32));
364 q_hscb->tag = saved_tag;
365 q_hscb->next = scb->hscb->tag;
367 /* Now swap HSCB pointers. */
368 ahc->next_queued_scb->hscb = scb->hscb;
371 /* Now define the mapping from tag to SCB in the scbindex */
372 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
376 * Tell the sequencer about a new transaction to execute.
379 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
381 ahc_swap_with_next_hscb(ahc, scb);
383 if (scb->hscb->tag == SCB_LIST_NULL
384 || scb->hscb->next == SCB_LIST_NULL)
385 panic("Attempt to queue invalid SCB tag %x:%x\n",
386 scb->hscb->tag, scb->hscb->next);
389 * Keep a history of SCBs we've downloaded in the qinfifo.
391 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
394 * Make sure our data is consistant from the
395 * perspective of the adapter.
397 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
399 /* Tell the adapter about the newly queued SCB */
400 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
401 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
403 if ((ahc->features & AHC_AUTOPAUSE) == 0)
405 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
406 if ((ahc->features & AHC_AUTOPAUSE) == 0)
411 static __inline struct scsi_sense_data *
412 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
416 offset = scb - ahc->scb_data->scbarray;
417 return (&ahc->scb_data->sense[offset]);
420 static __inline uint32_t
421 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
425 offset = scb - ahc->scb_data->scbarray;
426 return (ahc->scb_data->sense_busaddr
427 + (offset * sizeof(struct scsi_sense_data)));
430 /************************** Interrupt Processing ******************************/
431 static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op);
432 static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
433 static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
434 static __inline void ahc_intr(struct ahc_softc *ahc);
437 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
439 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
440 /*offset*/0, /*len*/256, op);
444 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
446 #ifdef AHC_TARGET_MODE
447 if ((ahc->flags & AHC_TARGETROLE) != 0) {
448 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
449 ahc->shared_data_dmamap,
450 ahc_targetcmd_offset(ahc, 0),
451 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
458 * See if the firmware has posted any completed commands
459 * into our in-core command complete fifos.
461 #define AHC_RUN_QOUTFIFO 0x1
462 #define AHC_RUN_TQINFIFO 0x2
463 static __inline u_int
464 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
469 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
470 /*offset*/ahc->qoutfifonext, /*len*/1,
471 BUS_DMASYNC_POSTREAD);
472 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
473 retval |= AHC_RUN_QOUTFIFO;
474 #ifdef AHC_TARGET_MODE
475 if ((ahc->flags & AHC_TARGETROLE) != 0
476 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
477 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
478 ahc->shared_data_dmamap,
479 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
480 /*len*/sizeof(struct target_cmd),
481 BUS_DMASYNC_POSTREAD);
482 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
483 retval |= AHC_RUN_TQINFIFO;
490 * Catch an interrupt from the adapter
493 ahc_intr(struct ahc_softc *ahc)
498 * Instead of directly reading the interrupt status register,
499 * infer the cause of the interrupt by checking our in-core
500 * completion queues. This avoids a costly PCI bus read in
503 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
504 && (ahc_check_cmdcmpltqueues(ahc) != 0))
507 intstat = ahc_inb(ahc, INTSTAT);
510 if (intstat & CMDCMPLT) {
511 ahc_outb(ahc, CLRINT, CLRCMDINT);
514 * Ensure that the chip sees that we've cleared
515 * this interrupt before we walk the output fifo.
516 * Otherwise, we may, due to posted bus writes,
517 * clear the interrupt after we finish the scan,
518 * and after the sequencer has added new entries
519 * and asserted the interrupt again.
521 ahc_flush_device_writes(ahc);
522 ahc_run_qoutfifo(ahc);
523 #ifdef AHC_TARGET_MODE
524 if ((ahc->flags & AHC_TARGETROLE) != 0)
525 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
529 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
533 if ((intstat & INT_PEND) == 0) {
534 #if AHC_PCI_CONFIG > 0
535 if (ahc->unsolicited_ints > 500) {
536 ahc->unsolicited_ints = 0;
537 if ((ahc->chip & AHC_PCI) != 0
538 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
542 ahc->unsolicited_ints++;
545 ahc->unsolicited_ints = 0;
547 if (intstat & BRKADRINT) {
548 ahc_handle_brkadrint(ahc);
549 /* Fatal error, no more interrupts to handle. */
553 if ((intstat & (SEQINT|SCSIINT)) != 0)
554 ahc_pause_bug_fix(ahc);
556 if ((intstat & SEQINT) != 0)
557 ahc_handle_seqint(ahc, intstat);
559 if ((intstat & SCSIINT) != 0)
560 ahc_handle_scsiint(ahc, intstat);
563 #endif /* _AIC7XXX_INLINE_H_ */