2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * SPDX-License-Identifier: BSD-3-Clause
8 * Copyright (c) 1994-2001 Justin T. Gibbs.
9 * Copyright (c) 2000-2001 Adaptec Inc.
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGES.
44 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
48 #include "aic7xxx_osm.h"
49 #include "aic7xxx_inline.h"
50 #include "aic7xxx_93cx6.h"
52 #include <sys/cdefs.h>
53 __FBSDID("$FreeBSD$");
54 #include <dev/aic7xxx/aic7xxx_osm.h>
55 #include <dev/aic7xxx/aic7xxx_inline.h>
56 #include <dev/aic7xxx/aic7xxx_93cx6.h>
59 static __inline uint64_t
60 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
66 | ((uint64_t)vendor << 32)
67 | ((uint64_t)device << 48);
72 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
73 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
74 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
75 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
76 #define ID_9005_SISL_ID 0x0005900500000000ull
77 #define ID_AIC7850 0x5078900400000000ull
78 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
79 #define ID_AIC7855 0x5578900400000000ull
80 #define ID_AIC7859 0x3860900400000000ull
81 #define ID_AHA_2930CU 0x3860900438699004ull
82 #define ID_AIC7860 0x6078900400000000ull
83 #define ID_AIC7860C 0x6078900478609004ull
84 #define ID_AHA_1480A 0x6075900400000000ull
85 #define ID_AHA_2940AU_0 0x6178900400000000ull
86 #define ID_AHA_2940AU_1 0x6178900478619004ull
87 #define ID_AHA_2940AU_CN 0x2178900478219004ull
88 #define ID_AHA_2930C_VAR 0x6038900438689004ull
90 #define ID_AIC7870 0x7078900400000000ull
91 #define ID_AHA_2940 0x7178900400000000ull
92 #define ID_AHA_3940 0x7278900400000000ull
93 #define ID_AHA_398X 0x7378900400000000ull
94 #define ID_AHA_2944 0x7478900400000000ull
95 #define ID_AHA_3944 0x7578900400000000ull
96 #define ID_AHA_4944 0x7678900400000000ull
98 #define ID_AIC7880 0x8078900400000000ull
99 #define ID_AIC7880_B 0x8078900478809004ull
100 #define ID_AHA_2940U 0x8178900400000000ull
101 #define ID_AHA_3940U 0x8278900400000000ull
102 #define ID_AHA_2944U 0x8478900400000000ull
103 #define ID_AHA_3944U 0x8578900400000000ull
104 #define ID_AHA_398XU 0x8378900400000000ull
105 #define ID_AHA_4944U 0x8678900400000000ull
106 #define ID_AHA_2940UB 0x8178900478819004ull
107 #define ID_AHA_2930U 0x8878900478889004ull
108 #define ID_AHA_2940U_PRO 0x8778900478879004ull
109 #define ID_AHA_2940U_CN 0x0078900478009004ull
111 #define ID_AIC7895 0x7895900478959004ull
112 #define ID_AIC7895_ARO 0x7890900478939004ull
113 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
114 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
115 #define ID_AHA_3940AU 0x7895900478929004ull
116 #define ID_AHA_3944AU 0x7895900478949004ull
118 #define ID_AIC7890 0x001F9005000F9005ull
119 #define ID_AIC7890_ARO 0x00139005000F9005ull
120 #define ID_AAA_131U2 0x0013900500039005ull
121 #define ID_AHA_2930U2 0x0011900501819005ull
122 #define ID_AHA_2940U2B 0x00109005A1009005ull
123 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
124 #define ID_AHA_2940U2 0x00109005A1809005ull
125 #define ID_AHA_2950U2B 0x00109005E1009005ull
127 #define ID_AIC7892 0x008F9005FFFF9005ull
128 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
129 #define ID_AHA_29160 0x00809005E2A09005ull
130 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
131 #define ID_AHA_29160N 0x0080900562A09005ull
132 #define ID_AHA_29160C 0x0080900562209005ull
133 #define ID_AHA_29160B 0x00809005E2209005ull
134 #define ID_AHA_19160B 0x0081900562A19005ull
135 #define ID_AHA_2915_30LP 0x0082900502109005ull
137 #define ID_AIC7896 0x005F9005FFFF9005ull
138 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
144 #define ID_AIC7899 0x00CF9005FFFF9005ull
145 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
146 #define ID_AHA_3960D 0x00C09005F6209005ull
147 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
149 #define ID_AIC7810 0x1078900400000000ull
150 #define ID_AIC7815 0x7815900400000000ull
152 #define DEVID_9005_TYPE(id) ((id) & 0xF)
153 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
154 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
155 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
156 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
158 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
159 #define DEVID_9005_MAXRATE_U160 0x0
160 #define DEVID_9005_MAXRATE_ULTRA2 0x1
161 #define DEVID_9005_MAXRATE_ULTRA 0x2
162 #define DEVID_9005_MAXRATE_FAST 0x3
164 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
166 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
167 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
169 #define SUBID_9005_TYPE(id) ((id) & 0xF)
170 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
171 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
172 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
173 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
175 #define SUBID_9005_TYPE_KNOWN(id) \
176 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
179 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
181 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
182 #define SUBID_9005_MAXRATE_ULTRA2 0x0
183 #define SUBID_9005_MAXRATE_ULTRA 0x1
184 #define SUBID_9005_MAXRATE_U160 0x2
185 #define SUBID_9005_MAXRATE_RESERVED 0x3
187 #define SUBID_9005_SEEPTYPE(id) \
188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
189 ? ((id) & 0xC0) >> 6 \
190 : ((id) & 0x300) >> 8)
191 #define SUBID_9005_SEEPTYPE_NONE 0x0
192 #define SUBID_9005_SEEPTYPE_1K 0x1
193 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
194 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
195 #define SUBID_9005_AUTOTERM(id) \
196 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
197 ? (((id) & 0x400) >> 10) == 0 \
198 : (((id) & 0x40) >> 6) == 0)
200 #define SUBID_9005_NUMCHAN(id) \
201 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
202 ? ((id) & 0x300) >> 8 \
203 : ((id) & 0xC00) >> 10)
205 #define SUBID_9005_LEGACYCONN(id) \
206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
208 : ((id) & 0x80) >> 7)
210 #define SUBID_9005_MFUNCENB(id) \
211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
212 ? ((id) & 0x800) >> 11 \
213 : ((id) & 0x1000) >> 12)
215 * Informational only. Should use chip register to be
216 * certain, but may be use in identification strings.
218 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
219 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
220 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
222 static ahc_device_setup_t ahc_aic785X_setup;
223 static ahc_device_setup_t ahc_aic7860_setup;
224 static ahc_device_setup_t ahc_apa1480_setup;
225 static ahc_device_setup_t ahc_aic7870_setup;
226 static ahc_device_setup_t ahc_aha394X_setup;
227 static ahc_device_setup_t ahc_aha494X_setup;
228 static ahc_device_setup_t ahc_aha398X_setup;
229 static ahc_device_setup_t ahc_aic7880_setup;
230 static ahc_device_setup_t ahc_aha2940Pro_setup;
231 static ahc_device_setup_t ahc_aha394XU_setup;
232 static ahc_device_setup_t ahc_aha398XU_setup;
233 static ahc_device_setup_t ahc_aic7890_setup;
234 static ahc_device_setup_t ahc_aic7892_setup;
235 static ahc_device_setup_t ahc_aic7895_setup;
236 static ahc_device_setup_t ahc_aic7896_setup;
237 static ahc_device_setup_t ahc_aic7899_setup;
238 static ahc_device_setup_t ahc_aha29160C_setup;
239 static ahc_device_setup_t ahc_raid_setup;
240 static ahc_device_setup_t ahc_aha394XX_setup;
241 static ahc_device_setup_t ahc_aha494XX_setup;
242 static ahc_device_setup_t ahc_aha398XX_setup;
244 struct ahc_pci_identity ahc_pci_ident_table [] =
246 /* aic7850 based controllers */
248 ID_AHA_2902_04_10_15_20C_30C,
250 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
253 /* aic7860 based controllers */
257 "Adaptec 2930CU SCSI adapter",
261 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
263 "Adaptec 1480A Ultra SCSI adapter",
267 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
269 "Adaptec 2940A Ultra SCSI adapter",
273 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
275 "Adaptec 2940A/CN Ultra SCSI adapter",
279 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
281 "Adaptec 2930C Ultra SCSI adapter (VAR)",
284 /* aic7870 based controllers */
288 "Adaptec 2940 SCSI adapter",
294 "Adaptec 3940 SCSI adapter",
300 "Adaptec 398X SCSI RAID adapter",
306 "Adaptec 2944 SCSI adapter",
312 "Adaptec 3944 SCSI adapter",
318 "Adaptec 4944 SCSI adapter",
321 /* aic7880 based controllers */
323 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
325 "Adaptec 2940 Ultra SCSI adapter",
329 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
331 "Adaptec 3940 Ultra SCSI adapter",
335 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
337 "Adaptec 2944 Ultra SCSI adapter",
341 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
343 "Adaptec 3944 Ultra SCSI adapter",
347 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
349 "Adaptec 398X Ultra SCSI RAID adapter",
354 * XXX Don't know the slot numbers
355 * so we can't identify channels
357 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
359 "Adaptec 4944 Ultra SCSI adapter",
363 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
365 "Adaptec 2930 Ultra SCSI adapter",
369 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
371 "Adaptec 2940 Pro Ultra SCSI adapter",
375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
377 "Adaptec 2940/CN Ultra SCSI adapter",
380 /* Ignore all SISL (AAC on MB) based controllers. */
387 /* aic7890 based controllers */
391 "Adaptec 2930 Ultra2 SCSI adapter",
397 "Adaptec 2940B Ultra2 SCSI adapter",
403 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
409 "Adaptec 2940 Ultra2 SCSI adapter",
415 "Adaptec 2950 Ultra2 SCSI adapter",
421 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
427 "Adaptec AAA-131 Ultra2 RAID adapter",
430 /* aic7892 based controllers */
434 "Adaptec 29160 Ultra160 SCSI adapter",
440 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
446 "Adaptec 29160N Ultra160 SCSI adapter",
452 "Adaptec 29160C Ultra160 SCSI adapter",
458 "Adaptec 29160B Ultra160 SCSI adapter",
464 "Adaptec 19160B Ultra160 SCSI adapter",
470 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
476 "Adaptec 2915/30LP Ultra160 SCSI adapter",
479 /* aic7895 based controllers */
483 "Adaptec 2940/DUAL Ultra SCSI adapter",
489 "Adaptec 3940A Ultra SCSI adapter",
495 "Adaptec 3944A Ultra SCSI adapter",
501 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
504 /* aic7896/97 based controllers */
508 "Adaptec 3950B Ultra2 SCSI adapter",
514 "Adaptec 3950B Ultra2 SCSI adapter",
520 "Adaptec 3950D Ultra2 SCSI adapter",
526 "Adaptec 3950D Ultra2 SCSI adapter",
532 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
535 /* aic7899 based controllers */
539 "Adaptec 3960D Ultra160 SCSI adapter",
545 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
551 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
554 /* Generic chip probes for devices we don't know 'exactly' */
556 ID_AIC7850 & ID_DEV_VENDOR_MASK,
558 "Adaptec aic7850 SCSI adapter",
562 ID_AIC7855 & ID_DEV_VENDOR_MASK,
564 "Adaptec aic7855 SCSI adapter",
568 ID_AIC7859 & ID_DEV_VENDOR_MASK,
570 "Adaptec aic7859 SCSI adapter",
574 ID_AIC7860 & ID_DEV_VENDOR_MASK,
576 "Adaptec aic7860 Ultra SCSI adapter",
580 ID_AIC7870 & ID_DEV_VENDOR_MASK,
582 "Adaptec aic7870 SCSI adapter",
586 ID_AIC7880 & ID_DEV_VENDOR_MASK,
588 "Adaptec aic7880 Ultra SCSI adapter",
592 ID_AIC7890 & ID_9005_GENERIC_MASK,
593 ID_9005_GENERIC_MASK,
594 "Adaptec aic7890/91 Ultra2 SCSI adapter",
598 ID_AIC7892 & ID_9005_GENERIC_MASK,
599 ID_9005_GENERIC_MASK,
600 "Adaptec aic7892 Ultra160 SCSI adapter",
604 ID_AIC7895 & ID_DEV_VENDOR_MASK,
606 "Adaptec aic7895 Ultra SCSI adapter",
610 ID_AIC7896 & ID_9005_GENERIC_MASK,
611 ID_9005_GENERIC_MASK,
612 "Adaptec aic7896/97 Ultra2 SCSI adapter",
616 ID_AIC7899 & ID_9005_GENERIC_MASK,
617 ID_9005_GENERIC_MASK,
618 "Adaptec aic7899 Ultra160 SCSI adapter",
622 ID_AIC7810 & ID_DEV_VENDOR_MASK,
624 "Adaptec aic7810 RAID memory controller",
628 ID_AIC7815 & ID_DEV_VENDOR_MASK,
630 "Adaptec aic7815 RAID memory controller",
635 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
637 #define AHC_394X_SLOT_CHANNEL_A 4
638 #define AHC_394X_SLOT_CHANNEL_B 5
640 #define AHC_398X_SLOT_CHANNEL_A 4
641 #define AHC_398X_SLOT_CHANNEL_B 8
642 #define AHC_398X_SLOT_CHANNEL_C 12
644 #define AHC_494X_SLOT_CHANNEL_A 4
645 #define AHC_494X_SLOT_CHANNEL_B 5
646 #define AHC_494X_SLOT_CHANNEL_C 6
647 #define AHC_494X_SLOT_CHANNEL_D 7
649 #define DEVCONFIG 0x40
650 #define PCIERRGENDIS 0x80000000ul
651 #define SCBSIZE32 0x00010000ul /* aic789X only */
652 #define REXTVALID 0x00001000ul /* ultra cards only */
653 #define MPORTMODE 0x00000400ul /* aic7870+ only */
654 #define RAMPSM 0x00000200ul /* aic7870+ only */
655 #define VOLSENSE 0x00000100ul
656 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
657 #define SCBRAMSEL 0x00000080ul
658 #define MRDCEN 0x00000040ul
659 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
660 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
661 #define BERREN 0x00000008ul
662 #define DACEN 0x00000004ul
663 #define STPWLEVEL 0x00000002ul
664 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
666 #define CSIZE_LATTIME 0x0c
667 #define CACHESIZE 0x0000003ful /* only 5 bits */
668 #define LATTIME 0x0000ff00ul
670 /* PCI STATUS definitions */
678 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
679 uint16_t subdevice, uint16_t subvendor);
680 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
681 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
682 int pcheck, int fast, int large);
683 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
684 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
685 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
686 struct seeprom_config *sc);
687 static void configure_termination(struct ahc_softc *ahc,
688 struct seeprom_descriptor *sd,
689 u_int adapter_control,
692 static void ahc_new_term_detect(struct ahc_softc *ahc,
697 int *eeprom_present);
698 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
699 int *internal68_present,
700 int *externalcable_present,
701 int *eeprom_present);
702 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
703 int *externalcable_present,
704 int *eeprom_present);
705 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
706 static uint8_t read_brdctl(struct ahc_softc *ahc);
707 static void ahc_pci_intr(struct ahc_softc *ahc);
708 static int ahc_pci_chip_init(struct ahc_softc *ahc);
709 static int ahc_pci_suspend(struct ahc_softc *ahc);
710 static int ahc_pci_resume(struct ahc_softc *ahc);
713 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
714 uint16_t subdevice, uint16_t subvendor)
718 /* Default to invalid. */
721 && subvendor == 0x9005
722 && subdevice != device
723 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
724 switch (SUBID_9005_TYPE(subdevice)) {
725 case SUBID_9005_TYPE_MB:
727 case SUBID_9005_TYPE_CARD:
728 case SUBID_9005_TYPE_LCCARD:
730 * Currently only trust Adaptec cards to
731 * get the sub device info correct.
733 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
736 case SUBID_9005_TYPE_RAID:
745 struct ahc_pci_identity *
746 ahc_find_pci_device(aic_dev_softc_t pci)
753 struct ahc_pci_identity *entry;
756 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
757 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
758 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
759 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
760 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
763 * If the second function is not hooked up, ignore it.
764 * Unfortunately, not all MB vendors implement the
765 * subdevice ID as per the Adaptec spec, so do our best
766 * to sanity check it prior to accepting the subdevice
769 if (aic_get_pci_function(pci) > 0
770 && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
771 && SUBID_9005_MFUNCENB(subdevice) == 0)
774 for (i = 0; i < ahc_num_pci_devs; i++) {
775 entry = &ahc_pci_ident_table[i];
776 if (entry->full_id == (full_id & entry->id_mask)) {
777 /* Honor exclusion entries. */
778 if (entry->name == NULL)
787 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
799 error = entry->setup(ahc);
802 ahc->chip |= AHC_PCI;
803 ahc->description = entry->name;
805 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
807 error = ahc_pci_map_registers(ahc);
812 * Before we continue probing the card, ensure that
813 * its interrupts are *disabled*. We don't want
814 * a misstep to hang the machine in an interrupt
817 ahc_intr_enable(ahc, FALSE);
819 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
822 * If we need to support high memory, enable dual
823 * address cycles. This bit must be set to enable
824 * high address bit generation even if we are on a
825 * 64bit bus (PCI64BIT set in devconfig).
827 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
829 printf("%s: Enabling 39Bit Addressing\n",
834 /* Ensure that pci error generation, a test feature, is disabled. */
835 devconfig |= PCIERRGENDIS;
837 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
839 /* Ensure busmastering is enabled */
840 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
841 command |= PCIM_CMD_BUSMASTEREN;
843 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
845 /* On all PCI adapters, we allow SCB paging */
846 ahc->flags |= AHC_PAGESCBS;
848 error = ahc_softc_init(ahc);
853 * Disable PCI parity error checking. Users typically
854 * do this to work around broken PCI chipsets that get
855 * the parity timing wrong and thus generate lots of spurious
856 * errors. The chip only allows us to disable *all* parity
857 * error reporting when doing this, so CIO bus, scb ram, and
858 * scratch ram parity errors will be ignored too.
860 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
861 ahc->seqctl |= FAILDIS;
863 ahc->bus_intr = ahc_pci_intr;
864 ahc->bus_chip_init = ahc_pci_chip_init;
865 ahc->bus_suspend = ahc_pci_suspend;
866 ahc->bus_resume = ahc_pci_resume;
868 /* Remember how the card was setup in case there is no SEEPROM */
869 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
871 if ((ahc->features & AHC_ULTRA2) != 0)
872 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
874 our_id = ahc_inb(ahc, SCSIID) & OID;
875 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
876 scsiseq = ahc_inb(ahc, SCSISEQ);
883 error = ahc_reset(ahc, /*reinit*/FALSE);
887 if ((ahc->features & AHC_DT) != 0) {
890 /* Perform ALT-Mode Setup */
891 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
892 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
893 ahc_outb(ahc, OPTIONMODE,
894 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
895 ahc_outb(ahc, SFUNCT, sfunct);
897 /* Normal mode setup */
898 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
902 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
903 dscommand0 |= MPARCKEN|CACHETHEN;
904 if ((ahc->features & AHC_ULTRA2) != 0) {
906 * DPARCKEN doesn't work correctly on
907 * some MBs so don't use it.
909 dscommand0 &= ~DPARCKEN;
913 * Handle chips that must have cache line
914 * streaming (dis/en)abled.
916 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
917 dscommand0 |= CACHETHEN;
919 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
920 dscommand0 &= ~CACHETHEN;
922 ahc_outb(ahc, DSCOMMAND0, dscommand0);
925 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
926 /*bytes*/1) & CACHESIZE;
927 ahc->pci_cachesize *= 4;
929 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
930 && ahc->pci_cachesize == 4) {
931 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
933 ahc->pci_cachesize = 0;
937 * We cannot perform ULTRA speeds without the presence
938 * of the external precision resistor.
940 if ((ahc->features & AHC_ULTRA) != 0) {
943 devconfig = aic_pci_read_config(ahc->dev_softc,
944 DEVCONFIG, /*bytes*/4);
945 if ((devconfig & REXTVALID) == 0)
946 ahc->features &= ~AHC_ULTRA;
949 /* See if we have a SEEPROM and perform auto-term */
950 check_extport(ahc, &sxfrctl1);
953 * Take the LED out of diagnostic mode
955 sblkctl = ahc_inb(ahc, SBLKCTL);
956 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
958 if ((ahc->features & AHC_ULTRA2) != 0) {
959 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
961 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
964 if (ahc->flags & AHC_USEDEFAULTS) {
966 * PCI Adapter default setup
967 * Should only be used if the adapter does not have
970 /* See if someone else set us up already */
971 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
973 printf("%s: Using left over BIOS settings\n",
975 ahc->flags &= ~AHC_USEDEFAULTS;
976 ahc->flags |= AHC_BIOS_ENABLED;
979 * Assume only one connector and always turn
985 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
987 ahc->our_id = our_id;
991 * Take a look to see if we have external SRAM.
992 * We currently do not attempt to use SRAM that is
993 * shared among multiple controllers.
995 ahc_probe_ext_scbram(ahc);
998 * Record our termination setting for the
999 * generic initialization routine.
1001 if ((sxfrctl1 & STPWEN) != 0)
1002 ahc->flags |= AHC_TERM_ENB_A;
1005 * Save chip register configuration data for chip resets
1006 * that occur during runtime and resume events.
1008 ahc->bus_softc.pci_softc.devconfig =
1009 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1010 ahc->bus_softc.pci_softc.command =
1011 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1012 ahc->bus_softc.pci_softc.csize_lattime =
1013 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1014 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1015 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1016 if ((ahc->features & AHC_DT) != 0) {
1019 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1020 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1021 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1022 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1023 ahc_outb(ahc, SFUNCT, sfunct);
1024 ahc->bus_softc.pci_softc.crccontrol1 =
1025 ahc_inb(ahc, CRCCONTROL1);
1027 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1028 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1030 if ((ahc->features & AHC_ULTRA2) != 0)
1031 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1033 /* Core initialization */
1034 error = ahc_init(ahc);
1039 * Allow interrupts now that we are completely setup.
1041 error = ahc_pci_map_int(ahc);
1047 * Link this softc in with all other ahc instances.
1049 ahc_softc_insert(ahc);
1055 * Test for the presence of external sram in an
1056 * "unshared" configuration.
1059 ahc_ext_scbram_present(struct ahc_softc *ahc)
1066 chip = ahc->chip & AHC_CHIPID_MASK;
1067 devconfig = aic_pci_read_config(ahc->dev_softc,
1068 DEVCONFIG, /*bytes*/4);
1069 single_user = (devconfig & MPORTMODE) != 0;
1071 if ((ahc->features & AHC_ULTRA2) != 0)
1072 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1073 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1075 * External SCBRAM arbitration is flakey
1076 * on these chips. Unfortunately this means
1077 * we don't use the extra SCB ram space on the
1081 else if (chip >= AHC_AIC7870)
1082 ramps = (devconfig & RAMPSM) != 0;
1086 if (ramps && single_user)
1092 * Enable external scbram.
1095 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1096 int fast, int large)
1100 if (ahc->features & AHC_MULTI_FUNC) {
1102 * Set the SCB Base addr (highest address bit)
1103 * depending on which channel we are.
1105 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1108 ahc->flags &= ~AHC_LSCBS_ENABLED;
1110 ahc->flags |= AHC_LSCBS_ENABLED;
1111 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1112 if ((ahc->features & AHC_ULTRA2) != 0) {
1115 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1117 dscommand0 &= ~INTSCBRAMSEL;
1119 dscommand0 |= INTSCBRAMSEL;
1121 dscommand0 &= ~USCBSIZE32;
1123 dscommand0 |= USCBSIZE32;
1124 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1127 devconfig &= ~EXTSCBTIME;
1129 devconfig |= EXTSCBTIME;
1131 devconfig &= ~SCBRAMSEL;
1133 devconfig |= SCBRAMSEL;
1135 devconfig &= ~SCBSIZE32;
1137 devconfig |= SCBSIZE32;
1140 devconfig |= EXTSCBPEN;
1142 devconfig &= ~EXTSCBPEN;
1144 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1148 * Take a look to see if we have external SRAM.
1149 * We currently do not attempt to use SRAM that is
1150 * shared among multiple controllers.
1153 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1168 if (ahc_ext_scbram_present(ahc) == 0)
1172 * Probe for the best parameters to use.
1174 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1175 num_scbs = ahc_probe_scbs(ahc);
1176 if (num_scbs == 0) {
1177 /* The SRAM wasn't really present. */
1183 * Clear any outstanding parity error
1184 * and ensure that parity error reporting
1187 ahc_outb(ahc, SEQCTL, 0);
1188 ahc_outb(ahc, CLRINT, CLRPARERR);
1189 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1191 /* Now see if we can do parity */
1192 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1193 num_scbs = ahc_probe_scbs(ahc);
1194 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1195 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1198 /* Clear any resulting parity error */
1199 ahc_outb(ahc, CLRINT, CLRPARERR);
1200 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1202 /* Now see if we can do fast timing */
1203 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1204 test_num_scbs = ahc_probe_scbs(ahc);
1205 if (test_num_scbs == num_scbs
1206 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1207 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1211 * See if we can use large SCBs and still maintain
1212 * the same overall count of SCBs.
1214 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1215 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1216 test_num_scbs = ahc_probe_scbs(ahc);
1217 if (test_num_scbs >= num_scbs) {
1219 num_scbs = test_num_scbs;
1220 if (num_scbs >= 64) {
1222 * We have enough space to move the
1223 * "busy targets table" into SCB space
1224 * and make it qualify all the way to the
1227 ahc->flags |= AHC_SCB_BTT;
1233 * Disable parity error reporting until we
1234 * can load instruction ram.
1236 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1237 /* Clear any latched parity error */
1238 ahc_outb(ahc, CLRINT, CLRPARERR);
1239 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1240 if (bootverbose && enable) {
1241 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1242 ahc_name(ahc), fast ? "fast" : "slow",
1243 pcheck ? ", parity checking enabled" : "",
1246 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1250 * Perform some simple tests that should catch situations where
1251 * our registers are invalidly mapped.
1254 ahc_pci_test_register_access(struct ahc_softc *ahc)
1264 * Enable PCI error interrupt status, but suppress NMIs
1265 * generated by SERR raised due to target aborts.
1267 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1268 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1269 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1272 * First a simple test to see if any
1273 * registers can be read. Reading
1274 * HCNTRL has no side effects and has
1275 * at least one bit that is guaranteed to
1276 * be zero so it is a good register to
1277 * use for this test.
1279 hcntrl = ahc_inb(ahc, HCNTRL);
1284 if ((hcntrl & CHIPRST) != 0) {
1286 * The chip has not been initialized since
1287 * PCI/EISA/VLB bus reset. Don't trust
1288 * "left over BIOS data".
1290 ahc->flags |= AHC_NO_BIOS_INIT;
1294 * Next create a situation where write combining
1295 * or read prefetching could be initiated by the
1296 * CPU or host bridge. Our device does not support
1297 * either, so look for data corruption and/or flagged
1298 * PCI errors. First pause without causing another
1302 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1303 while (ahc_is_paused(ahc) == 0)
1306 /* Clear any PCI errors that occurred before our driver attached. */
1307 status1 = aic_pci_read_config(ahc->dev_softc,
1308 PCIR_STATUS + 1, /*bytes*/1);
1309 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1310 status1, /*bytes*/1);
1311 ahc_outb(ahc, CLRINT, CLRPARERR);
1313 ahc_outb(ahc, SEQCTL, PERRORDIS);
1314 ahc_outb(ahc, SCBPTR, 0);
1315 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1316 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1319 status1 = aic_pci_read_config(ahc->dev_softc,
1320 PCIR_STATUS + 1, /*bytes*/1);
1321 if ((status1 & STA) != 0)
1327 /* Silently clear any latched errors. */
1328 status1 = aic_pci_read_config(ahc->dev_softc,
1329 PCIR_STATUS + 1, /*bytes*/1);
1330 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1331 status1, /*bytes*/1);
1332 ahc_outb(ahc, CLRINT, CLRPARERR);
1333 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1334 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1339 * Check the external port logic for a serial eeprom
1340 * and termination/cable detection contrls.
1343 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1345 struct seeprom_descriptor sd;
1346 struct seeprom_config *sc;
1351 sd.sd_control_offset = SEECTL;
1352 sd.sd_status_offset = SEECTL;
1353 sd.sd_dataout_offset = SEECTL;
1354 sc = ahc->seep_config;
1357 * For some multi-channel devices, the c46 is simply too
1358 * small to work. For the other controller types, we can
1359 * get our information from either SEEPROM type. Set the
1360 * type to start our probe with accordingly.
1362 if (ahc->flags & AHC_LARGE_SEEPROM)
1363 sd.sd_chip = C56_66;
1374 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1377 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1382 start_addr = 32 * (ahc->channel - 'A');
1384 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1389 have_seeprom = ahc_verify_cksum(sc);
1391 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1393 if (have_seeprom == 0)
1394 printf ("checksum error\n");
1400 sd.sd_chip = C56_66;
1402 ahc_release_seeprom(&sd);
1404 /* Remember the SEEPROM type for later */
1405 if (sd.sd_chip == C56_66)
1406 ahc->flags |= AHC_LARGE_SEEPROM;
1409 if (!have_seeprom) {
1411 * Pull scratch ram settings and treat them as
1412 * if they are the contents of an seeprom if
1413 * the 'ADPT' signature is found in SCB2.
1414 * We manually compose the data as 16bit values
1415 * to avoid endian issues.
1417 ahc_outb(ahc, SCBPTR, 2);
1418 if (ahc_inb(ahc, SCB_BASE) == 'A'
1419 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1420 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1421 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1425 sc_data = (uint16_t *)sc;
1426 for (i = 0; i < 32; i++, sc_data++) {
1430 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1431 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1433 have_seeprom = ahc_verify_cksum(sc);
1435 ahc->flags |= AHC_SCB_CONFIG_USED;
1438 * Clear any SCB parity errors in case this data and
1439 * its associated parity was not initialized by the BIOS
1441 ahc_outb(ahc, CLRINT, CLRPARERR);
1442 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1445 if (!have_seeprom) {
1447 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1448 ahc->flags |= AHC_USEDEFAULTS;
1449 free(ahc->seep_config, M_DEVBUF);
1450 ahc->seep_config = NULL;
1453 ahc_parse_pci_eeprom(ahc, sc);
1457 * Cards that have the external logic necessary to talk to
1458 * a SEEPROM, are almost certain to have the remaining logic
1459 * necessary for auto-termination control. This assumption
1460 * hasn't failed yet...
1462 have_autoterm = have_seeprom;
1465 * Some low-cost chips have SEEPROM and auto-term control built
1466 * in, instead of using a GAL. They can tell us directly
1467 * if the termination logic is enabled.
1469 if ((ahc->features & AHC_SPIOCAP) != 0) {
1470 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1471 have_autoterm = FALSE;
1474 if (have_autoterm) {
1475 ahc->flags |= AHC_HAS_TERM_LOGIC;
1476 ahc_acquire_seeprom(ahc, &sd);
1477 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1478 ahc_release_seeprom(&sd);
1479 } else if (have_seeprom) {
1480 *sxfrctl1 &= ~STPWEN;
1481 if ((sc->adapter_control & CFSTERM) != 0)
1482 *sxfrctl1 |= STPWEN;
1484 printf("%s: Low byte termination %sabled\n",
1486 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1491 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1494 * Put the data we've collected down into SRAM
1495 * where ahc_init will find it.
1498 int max_targ = sc->max_targets & CFMAXTARG;
1500 uint16_t discenable;
1505 if ((sc->adapter_control & CFULTRAEN) != 0) {
1507 * Determine if this adapter has a "newstyle"
1510 for (i = 0; i < max_targ; i++) {
1511 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1512 ahc->flags |= AHC_NEWEEPROM_FMT;
1518 for (i = 0; i < max_targ; i++) {
1520 uint16_t target_mask;
1522 target_mask = 0x01 << i;
1523 if (sc->device_flags[i] & CFDISC)
1524 discenable |= target_mask;
1525 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1526 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1527 ultraenb |= target_mask;
1528 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1529 ultraenb |= target_mask;
1531 if ((sc->device_flags[i] & CFXFER) == 0x04
1532 && (ultraenb & target_mask) != 0) {
1533 /* Treat 10MHz as a non-ultra speed */
1534 sc->device_flags[i] &= ~CFXFER;
1535 ultraenb &= ~target_mask;
1537 if ((ahc->features & AHC_ULTRA2) != 0) {
1540 if (sc->device_flags[i] & CFSYNCH)
1541 offset = MAX_OFFSET_ULTRA2;
1544 ahc_outb(ahc, TARG_OFFSET + i, offset);
1547 * The ultra enable bits contain the
1548 * high bit of the ultra2 sync rate
1551 scsirate = (sc->device_flags[i] & CFXFER)
1552 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1553 if (sc->device_flags[i] & CFWIDEB)
1554 scsirate |= WIDEXFER;
1556 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1557 if (sc->device_flags[i] & CFSYNCH)
1559 if (sc->device_flags[i] & CFWIDEB)
1560 scsirate |= WIDEXFER;
1562 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1564 ahc->our_id = sc->brtime_id & CFSCSIID;
1566 scsi_conf = (ahc->our_id & 0x7);
1567 if (sc->adapter_control & CFSPARITY)
1568 scsi_conf |= ENSPCHK;
1569 if (sc->adapter_control & CFRESETB)
1570 scsi_conf |= RESET_SCSI;
1572 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1574 if (sc->bios_control & CFEXTEND)
1575 ahc->flags |= AHC_EXTENDED_TRANS_A;
1577 if (sc->bios_control & CFBIOSEN)
1578 ahc->flags |= AHC_BIOS_ENABLED;
1579 if (ahc->features & AHC_ULTRA
1580 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1581 /* Should we enable Ultra mode? */
1582 if (!(sc->adapter_control & CFULTRAEN))
1583 /* Treat us as a non-ultra card */
1587 if (sc->signature == CFSIGNATURE
1588 || sc->signature == CFSIGNATURE2) {
1591 /* Honor the STPWLEVEL settings */
1592 devconfig = aic_pci_read_config(ahc->dev_softc,
1593 DEVCONFIG, /*bytes*/4);
1594 devconfig &= ~STPWLEVEL;
1595 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1596 devconfig |= STPWLEVEL;
1597 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1598 devconfig, /*bytes*/4);
1600 /* Set SCSICONF info */
1601 ahc_outb(ahc, SCSICONF, scsi_conf);
1602 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1603 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1604 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1605 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1609 configure_termination(struct ahc_softc *ahc,
1610 struct seeprom_descriptor *sd,
1611 u_int adapter_control,
1619 * Update the settings in sxfrctl1 to match the
1620 * termination settings
1625 * SEECS must be on for the GALS to latch
1626 * the data properly. Be sure to leave MS
1627 * on or we will release the seeprom.
1629 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1630 if ((adapter_control & CFAUTOTERM) != 0
1631 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1632 int internal50_present;
1633 int internal68_present;
1634 int externalcable_present;
1646 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1647 ahc_new_term_detect(ahc, &enableSEC_low,
1652 if ((adapter_control & CFSEAUTOTERM) == 0) {
1654 printf("%s: Manual SE Termination\n",
1656 enableSEC_low = (adapter_control & CFSELOWTERM);
1658 (adapter_control & CFSEHIGHTERM);
1660 if ((adapter_control & CFAUTOTERM) == 0) {
1662 printf("%s: Manual LVD Termination\n",
1664 enablePRI_low = (adapter_control & CFSTERM);
1665 enablePRI_high = (adapter_control & CFWSTERM);
1667 /* Make the table calculations below happy */
1668 internal50_present = 0;
1669 internal68_present = 1;
1670 externalcable_present = 1;
1671 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1672 aic785X_cable_detect(ahc, &internal50_present,
1673 &externalcable_present,
1675 /* Can never support a wide connector. */
1676 internal68_present = 0;
1678 aic787X_cable_detect(ahc, &internal50_present,
1679 &internal68_present,
1680 &externalcable_present,
1684 if ((ahc->features & AHC_WIDE) == 0)
1685 internal68_present = 0;
1688 && (ahc->features & AHC_ULTRA2) == 0) {
1689 printf("%s: internal 50 cable %s present",
1691 internal50_present ? "is":"not");
1693 if ((ahc->features & AHC_WIDE) != 0)
1694 printf(", internal 68 cable %s present",
1695 internal68_present ? "is":"not");
1696 printf("\n%s: external cable %s present\n",
1698 externalcable_present ? "is":"not");
1701 printf("%s: BIOS eeprom %s present\n",
1702 ahc_name(ahc), eeprom_present ? "is" : "not");
1704 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1706 * The 50 pin connector is a separate bus,
1707 * so force it to always be terminated.
1708 * In the future, perform current sensing
1709 * to determine if we are in the middle of
1710 * a properly terminated bus.
1712 internal50_present = 0;
1716 * Now set the termination based on what
1718 * Flash Enable = BRDDAT7
1719 * Secondary High Term Enable = BRDDAT6
1720 * Secondary Low Term Enable = BRDDAT5 (7890)
1721 * Primary High Term Enable = BRDDAT4 (7890)
1723 if ((ahc->features & AHC_ULTRA2) == 0
1724 && (internal50_present != 0)
1725 && (internal68_present != 0)
1726 && (externalcable_present != 0)) {
1727 printf("%s: Illegal cable configuration!!. "
1728 "Only two connectors on the "
1729 "adapter may be used at a "
1730 "time!\n", ahc_name(ahc));
1733 * Pretend there are no cables in the hope
1734 * that having all of the termination on
1735 * gives us a more stable bus.
1737 internal50_present = 0;
1738 internal68_present = 0;
1739 externalcable_present = 0;
1742 if ((ahc->features & AHC_WIDE) != 0
1743 && ((externalcable_present == 0)
1744 || (internal68_present == 0)
1745 || (enableSEC_high != 0))) {
1748 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1749 printf("%s: 68 pin termination "
1750 "Enabled\n", ahc_name(ahc));
1752 printf("%s: %sHigh byte termination "
1753 "Enabled\n", ahc_name(ahc),
1754 enableSEC_high ? "Secondary "
1759 sum = internal50_present + internal68_present
1760 + externalcable_present;
1761 if (sum < 2 || (enableSEC_low != 0)) {
1762 if ((ahc->features & AHC_ULTRA2) != 0)
1765 *sxfrctl1 |= STPWEN;
1767 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1768 printf("%s: 50 pin termination "
1769 "Enabled\n", ahc_name(ahc));
1771 printf("%s: %sLow byte termination "
1772 "Enabled\n", ahc_name(ahc),
1773 enableSEC_low ? "Secondary "
1778 if (enablePRI_low != 0) {
1779 *sxfrctl1 |= STPWEN;
1781 printf("%s: Primary Low Byte termination "
1782 "Enabled\n", ahc_name(ahc));
1786 * Setup STPWEN before setting up the rest of
1787 * the termination per the tech note on the U160 cards.
1789 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1791 if (enablePRI_high != 0) {
1794 printf("%s: Primary High Byte "
1795 "termination Enabled\n",
1799 write_brdctl(ahc, brddat);
1802 if ((adapter_control & CFSTERM) != 0) {
1803 *sxfrctl1 |= STPWEN;
1806 printf("%s: %sLow byte termination Enabled\n",
1808 (ahc->features & AHC_ULTRA2) ? "Primary "
1812 if ((adapter_control & CFWSTERM) != 0
1813 && (ahc->features & AHC_WIDE) != 0) {
1816 printf("%s: %sHigh byte termination Enabled\n",
1818 (ahc->features & AHC_ULTRA2)
1819 ? "Secondary " : "");
1823 * Setup STPWEN before setting up the rest of
1824 * the termination per the tech note on the U160 cards.
1826 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1828 if ((ahc->features & AHC_WIDE) != 0)
1829 write_brdctl(ahc, brddat);
1831 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1835 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1836 int *enableSEC_high, int *enablePRI_low,
1837 int *enablePRI_high, int *eeprom_present)
1843 * BRDDAT6 = Enable Secondary High Byte termination
1844 * BRDDAT5 = Enable Secondary Low Byte termination
1845 * BRDDAT4 = Enable Primary high byte termination
1846 * BRDDAT3 = Enable Primary low byte termination
1848 brdctl = read_brdctl(ahc);
1849 *eeprom_present = brdctl & BRDDAT7;
1850 *enableSEC_high = (brdctl & BRDDAT6);
1851 *enableSEC_low = (brdctl & BRDDAT5);
1852 *enablePRI_high = (brdctl & BRDDAT4);
1853 *enablePRI_low = (brdctl & BRDDAT3);
1857 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1858 int *internal68_present, int *externalcable_present,
1859 int *eeprom_present)
1864 * First read the status of our cables.
1865 * Set the rom bank to 0 since the
1866 * bank setting serves as a multiplexor
1867 * for the cable detection logic.
1868 * BRDDAT5 controls the bank switch.
1870 write_brdctl(ahc, 0);
1873 * Now read the state of the internal
1874 * connectors. BRDDAT6 is INT50 and
1877 brdctl = read_brdctl(ahc);
1878 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1879 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1882 * Set the rom bank to 1 and determine
1883 * the other signals.
1885 write_brdctl(ahc, BRDDAT5);
1888 * Now read the state of the external
1889 * connectors. BRDDAT6 is EXT68 and
1890 * BRDDAT7 is EPROMPS.
1892 brdctl = read_brdctl(ahc);
1893 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1894 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1898 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1899 int *externalcable_present, int *eeprom_present)
1904 spiocap = ahc_inb(ahc, SPIOCAP);
1905 spiocap &= ~SOFTCMDEN;
1906 spiocap |= EXT_BRDCTL;
1907 ahc_outb(ahc, SPIOCAP, spiocap);
1908 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1909 ahc_flush_device_writes(ahc);
1911 ahc_outb(ahc, BRDCTL, 0);
1912 ahc_flush_device_writes(ahc);
1914 brdctl = ahc_inb(ahc, BRDCTL);
1915 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1916 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1917 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1921 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1925 if ((ahc->features & AHC_SPIOCAP) != 0
1926 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1930 * Request access of the memory port. When access is
1931 * granted, SEERDY will go high. We use a 1 second
1932 * timeout which should be near 1 second more than
1933 * is needed. Reason: after the chip reset, there
1934 * should be no contention.
1936 SEEPROM_OUTB(sd, sd->sd_MS);
1937 wait = 1000; /* 1 second timeout in msec */
1938 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1939 aic_delay(1000); /* delay 1 msec */
1941 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1942 SEEPROM_OUTB(sd, 0);
1949 ahc_release_seeprom(struct seeprom_descriptor *sd)
1951 /* Release access to the memory port and the serial EEPROM. */
1952 SEEPROM_OUTB(sd, 0);
1956 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1960 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1962 if (ahc->channel == 'B')
1964 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1967 brdctl = BRDSTB|BRDCS;
1969 ahc_outb(ahc, BRDCTL, brdctl);
1970 ahc_flush_device_writes(ahc);
1972 ahc_outb(ahc, BRDCTL, brdctl);
1973 ahc_flush_device_writes(ahc);
1974 if ((ahc->features & AHC_ULTRA2) != 0)
1975 brdctl |= BRDSTB_ULTRA2;
1978 ahc_outb(ahc, BRDCTL, brdctl);
1979 ahc_flush_device_writes(ahc);
1980 if ((ahc->features & AHC_ULTRA2) != 0)
1984 ahc_outb(ahc, BRDCTL, brdctl);
1988 read_brdctl(struct ahc_softc *ahc)
1993 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1995 if (ahc->channel == 'B')
1997 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1998 brdctl = BRDRW_ULTRA2;
2000 brdctl = BRDRW|BRDCS;
2002 ahc_outb(ahc, BRDCTL, brdctl);
2003 ahc_flush_device_writes(ahc);
2004 value = ahc_inb(ahc, BRDCTL);
2005 ahc_outb(ahc, BRDCTL, 0);
2010 ahc_pci_intr(struct ahc_softc *ahc)
2015 error = ahc_inb(ahc, ERROR);
2016 if ((error & PCIERRSTAT) == 0)
2019 status1 = aic_pci_read_config(ahc->dev_softc,
2020 PCIR_STATUS + 1, /*bytes*/1);
2022 if ((status1 & ~DPE) != 0
2023 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2024 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2026 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2030 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2031 ahc->pci_target_perr_count++;
2032 printf("%s: Data Parity Error Detected during address "
2033 "or write data phase\n", ahc_name(ahc));
2035 if (status1 & SSE) {
2036 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2038 if (status1 & RMA) {
2039 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2041 if (status1 & RTA) {
2042 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2044 if (status1 & STA) {
2045 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2047 if (status1 & DPR) {
2048 printf("%s: Data Parity Error has been reported via PERR#\n",
2052 /* Clear latched errors. */
2053 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2054 status1, /*bytes*/1);
2056 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2057 printf("%s: Latched PCIERR interrupt with "
2058 "no status bits set\n", ahc_name(ahc));
2060 ahc_outb(ahc, CLRINT, CLRPARERR);
2063 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2064 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2066 "%s: WARNING WARNING WARNING WARNING\n"
2067 "%s: Too many PCI parity errors observed as a target.\n"
2068 "%s: Some device on this PCI bus is generating bad parity.\n"
2069 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2070 "%s: PCI parity error checking has been disabled.\n"
2071 "%s: WARNING WARNING WARNING WARNING\n",
2072 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2073 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2075 ahc->seqctl |= FAILDIS;
2076 ahc->flags |= AHC_DISABLE_PCI_PERR;
2077 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2083 ahc_pci_chip_init(struct ahc_softc *ahc)
2085 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2086 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2087 if ((ahc->features & AHC_DT) != 0) {
2090 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2091 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2092 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2093 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2094 ahc_outb(ahc, SFUNCT, sfunct);
2095 ahc_outb(ahc, CRCCONTROL1,
2096 ahc->bus_softc.pci_softc.crccontrol1);
2098 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2099 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2101 if ((ahc->features & AHC_ULTRA2) != 0)
2102 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2104 return (ahc_chip_init(ahc));
2108 ahc_pci_suspend(struct ahc_softc *ahc)
2110 return (ahc_suspend(ahc));
2114 ahc_pci_resume(struct ahc_softc *ahc)
2117 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2120 * We assume that the OS has restored our register
2121 * mappings, etc. Just update the config space registers
2122 * that the OS doesn't know about and rely on our chip
2123 * reset handler to handle the rest.
2125 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2126 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2127 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2128 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2129 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2130 ahc->bus_softc.pci_softc.csize_lattime,
2132 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2133 struct seeprom_descriptor sd;
2137 sd.sd_control_offset = SEECTL;
2138 sd.sd_status_offset = SEECTL;
2139 sd.sd_dataout_offset = SEECTL;
2141 ahc_acquire_seeprom(ahc, &sd);
2142 configure_termination(ahc, &sd,
2143 ahc->seep_config->adapter_control,
2145 ahc_release_seeprom(&sd);
2147 return (ahc_resume(ahc));
2151 ahc_aic785X_setup(struct ahc_softc *ahc)
2153 aic_dev_softc_t pci;
2156 pci = ahc->dev_softc;
2158 ahc->chip = AHC_AIC7850;
2159 ahc->features = AHC_AIC7850_FE;
2160 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2161 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2163 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2164 ahc->instruction_ram_size = 512;
2169 ahc_aic7860_setup(struct ahc_softc *ahc)
2171 aic_dev_softc_t pci;
2174 pci = ahc->dev_softc;
2176 ahc->chip = AHC_AIC7860;
2177 ahc->features = AHC_AIC7860_FE;
2178 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2179 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2181 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2182 ahc->instruction_ram_size = 512;
2187 ahc_apa1480_setup(struct ahc_softc *ahc)
2191 error = ahc_aic7860_setup(ahc);
2194 ahc->features |= AHC_REMOVABLE;
2199 ahc_aic7870_setup(struct ahc_softc *ahc)
2203 ahc->chip = AHC_AIC7870;
2204 ahc->features = AHC_AIC7870_FE;
2205 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2206 ahc->instruction_ram_size = 512;
2211 ahc_aha394X_setup(struct ahc_softc *ahc)
2215 error = ahc_aic7870_setup(ahc);
2217 error = ahc_aha394XX_setup(ahc);
2222 ahc_aha398X_setup(struct ahc_softc *ahc)
2226 error = ahc_aic7870_setup(ahc);
2228 error = ahc_aha398XX_setup(ahc);
2233 ahc_aha494X_setup(struct ahc_softc *ahc)
2237 error = ahc_aic7870_setup(ahc);
2239 error = ahc_aha494XX_setup(ahc);
2244 ahc_aic7880_setup(struct ahc_softc *ahc)
2246 aic_dev_softc_t pci;
2249 pci = ahc->dev_softc;
2251 ahc->chip = AHC_AIC7880;
2252 ahc->features = AHC_AIC7880_FE;
2253 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2254 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2256 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2258 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2260 ahc->instruction_ram_size = 512;
2265 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2268 ahc->flags |= AHC_INT50_SPEEDFLEX;
2269 return (ahc_aic7880_setup(ahc));
2273 ahc_aha394XU_setup(struct ahc_softc *ahc)
2277 error = ahc_aic7880_setup(ahc);
2279 error = ahc_aha394XX_setup(ahc);
2284 ahc_aha398XU_setup(struct ahc_softc *ahc)
2288 error = ahc_aic7880_setup(ahc);
2290 error = ahc_aha398XX_setup(ahc);
2295 ahc_aic7890_setup(struct ahc_softc *ahc)
2297 aic_dev_softc_t pci;
2300 pci = ahc->dev_softc;
2302 ahc->chip = AHC_AIC7890;
2303 ahc->features = AHC_AIC7890_FE;
2304 ahc->flags |= AHC_NEWEEPROM_FMT;
2305 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2307 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2308 ahc->instruction_ram_size = 768;
2313 ahc_aic7892_setup(struct ahc_softc *ahc)
2317 ahc->chip = AHC_AIC7892;
2318 ahc->features = AHC_AIC7892_FE;
2319 ahc->flags |= AHC_NEWEEPROM_FMT;
2320 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2321 ahc->instruction_ram_size = 1024;
2326 ahc_aic7895_setup(struct ahc_softc *ahc)
2328 aic_dev_softc_t pci;
2331 pci = ahc->dev_softc;
2332 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2334 * The 'C' revision of the aic7895 has a few additional features.
2336 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2338 ahc->chip = AHC_AIC7895C;
2339 ahc->features = AHC_AIC7895C_FE;
2343 ahc->chip = AHC_AIC7895;
2344 ahc->features = AHC_AIC7895_FE;
2347 * The BIOS disables the use of MWI transactions
2348 * since it does not have the MWI bug work around
2349 * we have. Disabling MWI reduces performance, so
2352 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2353 command |= PCIM_CMD_MWRICEN;
2354 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2355 ahc->bugs |= AHC_PCI_MWI_BUG;
2358 * XXX Does CACHETHEN really not work??? What about PCI retry?
2359 * on C level chips. Need to test, but for now, play it safe.
2361 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2362 | AHC_CACHETHEN_BUG;
2368 * Cachesize must also be zero due to stray DAC
2369 * problem when sitting behind some bridges.
2371 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2372 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2373 devconfig |= MRDCEN;
2374 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2376 ahc->flags |= AHC_NEWEEPROM_FMT;
2377 ahc->instruction_ram_size = 512;
2382 ahc_aic7896_setup(struct ahc_softc *ahc)
2384 aic_dev_softc_t pci;
2386 pci = ahc->dev_softc;
2387 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2388 ahc->chip = AHC_AIC7896;
2389 ahc->features = AHC_AIC7896_FE;
2390 ahc->flags |= AHC_NEWEEPROM_FMT;
2391 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2392 ahc->instruction_ram_size = 768;
2397 ahc_aic7899_setup(struct ahc_softc *ahc)
2399 aic_dev_softc_t pci;
2401 pci = ahc->dev_softc;
2402 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2403 ahc->chip = AHC_AIC7899;
2404 ahc->features = AHC_AIC7899_FE;
2405 ahc->flags |= AHC_NEWEEPROM_FMT;
2406 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2407 ahc->instruction_ram_size = 1024;
2412 ahc_aha29160C_setup(struct ahc_softc *ahc)
2416 error = ahc_aic7899_setup(ahc);
2419 ahc->features |= AHC_REMOVABLE;
2424 ahc_raid_setup(struct ahc_softc *ahc)
2426 printf("RAID functionality unsupported\n");
2431 ahc_aha394XX_setup(struct ahc_softc *ahc)
2433 aic_dev_softc_t pci;
2435 pci = ahc->dev_softc;
2436 switch (aic_get_pci_slot(pci)) {
2437 case AHC_394X_SLOT_CHANNEL_A:
2440 case AHC_394X_SLOT_CHANNEL_B:
2444 printf("adapter at unexpected slot %d\n"
2445 "unable to map to a channel\n",
2446 aic_get_pci_slot(pci));
2453 ahc_aha398XX_setup(struct ahc_softc *ahc)
2455 aic_dev_softc_t pci;
2457 pci = ahc->dev_softc;
2458 switch (aic_get_pci_slot(pci)) {
2459 case AHC_398X_SLOT_CHANNEL_A:
2462 case AHC_398X_SLOT_CHANNEL_B:
2465 case AHC_398X_SLOT_CHANNEL_C:
2469 printf("adapter at unexpected slot %d\n"
2470 "unable to map to a channel\n",
2471 aic_get_pci_slot(pci));
2475 ahc->flags |= AHC_LARGE_SEEPROM;
2480 ahc_aha494XX_setup(struct ahc_softc *ahc)
2482 aic_dev_softc_t pci;
2484 pci = ahc->dev_softc;
2485 switch (aic_get_pci_slot(pci)) {
2486 case AHC_494X_SLOT_CHANNEL_A:
2489 case AHC_494X_SLOT_CHANNEL_B:
2492 case AHC_494X_SLOT_CHANNEL_C:
2495 case AHC_494X_SLOT_CHANNEL_D:
2499 printf("adapter at unexpected slot %d\n"
2500 "unable to map to a channel\n",
2501 aic_get_pci_slot(pci));
2504 ahc->flags |= AHC_LARGE_SEEPROM;