2 * DO NOT EDIT - This file is automatically generated
3 * from the following source files:
5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
10 typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
11 typedef struct ahc_reg_parse_entry {
15 } ahc_reg_parse_entry_t;
17 #if AIC_DEBUG_REGISTERS
18 ahc_reg_print_t ahc_scsiseq_print;
20 #define ahc_scsiseq_print(regvalue, cur_col, wrap) \
21 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
24 #if AIC_DEBUG_REGISTERS
25 ahc_reg_print_t ahc_sxfrctl0_print;
27 #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \
28 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
31 #if AIC_DEBUG_REGISTERS
32 ahc_reg_print_t ahc_sxfrctl1_print;
34 #define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \
35 ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
38 #if AIC_DEBUG_REGISTERS
39 ahc_reg_print_t ahc_scsisigi_print;
41 #define ahc_scsisigi_print(regvalue, cur_col, wrap) \
42 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
45 #if AIC_DEBUG_REGISTERS
46 ahc_reg_print_t ahc_scsisigo_print;
48 #define ahc_scsisigo_print(regvalue, cur_col, wrap) \
49 ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
52 #if AIC_DEBUG_REGISTERS
53 ahc_reg_print_t ahc_scsirate_print;
55 #define ahc_scsirate_print(regvalue, cur_col, wrap) \
56 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
59 #if AIC_DEBUG_REGISTERS
60 ahc_reg_print_t ahc_scsiid_print;
62 #define ahc_scsiid_print(regvalue, cur_col, wrap) \
63 ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap)
66 #if AIC_DEBUG_REGISTERS
67 ahc_reg_print_t ahc_scsidatl_print;
69 #define ahc_scsidatl_print(regvalue, cur_col, wrap) \
70 ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap)
73 #if AIC_DEBUG_REGISTERS
74 ahc_reg_print_t ahc_scsidath_print;
76 #define ahc_scsidath_print(regvalue, cur_col, wrap) \
77 ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap)
80 #if AIC_DEBUG_REGISTERS
81 ahc_reg_print_t ahc_optionmode_print;
83 #define ahc_optionmode_print(regvalue, cur_col, wrap) \
84 ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
87 #if AIC_DEBUG_REGISTERS
88 ahc_reg_print_t ahc_stcnt_print;
90 #define ahc_stcnt_print(regvalue, cur_col, wrap) \
91 ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
94 #if AIC_DEBUG_REGISTERS
95 ahc_reg_print_t ahc_targcrccnt_print;
97 #define ahc_targcrccnt_print(regvalue, cur_col, wrap) \
98 ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap)
101 #if AIC_DEBUG_REGISTERS
102 ahc_reg_print_t ahc_clrsint0_print;
104 #define ahc_clrsint0_print(regvalue, cur_col, wrap) \
105 ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap)
108 #if AIC_DEBUG_REGISTERS
109 ahc_reg_print_t ahc_sstat0_print;
111 #define ahc_sstat0_print(regvalue, cur_col, wrap) \
112 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
115 #if AIC_DEBUG_REGISTERS
116 ahc_reg_print_t ahc_clrsint1_print;
118 #define ahc_clrsint1_print(regvalue, cur_col, wrap) \
119 ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap)
122 #if AIC_DEBUG_REGISTERS
123 ahc_reg_print_t ahc_sstat1_print;
125 #define ahc_sstat1_print(regvalue, cur_col, wrap) \
126 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
129 #if AIC_DEBUG_REGISTERS
130 ahc_reg_print_t ahc_sstat2_print;
132 #define ahc_sstat2_print(regvalue, cur_col, wrap) \
133 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
136 #if AIC_DEBUG_REGISTERS
137 ahc_reg_print_t ahc_sstat3_print;
139 #define ahc_sstat3_print(regvalue, cur_col, wrap) \
140 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
143 #if AIC_DEBUG_REGISTERS
144 ahc_reg_print_t ahc_scsiid_ultra2_print;
146 #define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \
147 ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap)
150 #if AIC_DEBUG_REGISTERS
151 ahc_reg_print_t ahc_simode0_print;
153 #define ahc_simode0_print(regvalue, cur_col, wrap) \
154 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
157 #if AIC_DEBUG_REGISTERS
158 ahc_reg_print_t ahc_simode1_print;
160 #define ahc_simode1_print(regvalue, cur_col, wrap) \
161 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
164 #if AIC_DEBUG_REGISTERS
165 ahc_reg_print_t ahc_scsibusl_print;
167 #define ahc_scsibusl_print(regvalue, cur_col, wrap) \
168 ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
171 #if AIC_DEBUG_REGISTERS
172 ahc_reg_print_t ahc_sxfrctl2_print;
174 #define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \
175 ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap)
178 #if AIC_DEBUG_REGISTERS
179 ahc_reg_print_t ahc_scsibush_print;
181 #define ahc_scsibush_print(regvalue, cur_col, wrap) \
182 ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap)
185 #if AIC_DEBUG_REGISTERS
186 ahc_reg_print_t ahc_shaddr_print;
188 #define ahc_shaddr_print(regvalue, cur_col, wrap) \
189 ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
192 #if AIC_DEBUG_REGISTERS
193 ahc_reg_print_t ahc_seltimer_print;
195 #define ahc_seltimer_print(regvalue, cur_col, wrap) \
196 ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap)
199 #if AIC_DEBUG_REGISTERS
200 ahc_reg_print_t ahc_selid_print;
202 #define ahc_selid_print(regvalue, cur_col, wrap) \
203 ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap)
206 #if AIC_DEBUG_REGISTERS
207 ahc_reg_print_t ahc_scamctl_print;
209 #define ahc_scamctl_print(regvalue, cur_col, wrap) \
210 ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap)
213 #if AIC_DEBUG_REGISTERS
214 ahc_reg_print_t ahc_targid_print;
216 #define ahc_targid_print(regvalue, cur_col, wrap) \
217 ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap)
220 #if AIC_DEBUG_REGISTERS
221 ahc_reg_print_t ahc_spiocap_print;
223 #define ahc_spiocap_print(regvalue, cur_col, wrap) \
224 ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap)
227 #if AIC_DEBUG_REGISTERS
228 ahc_reg_print_t ahc_brdctl_print;
230 #define ahc_brdctl_print(regvalue, cur_col, wrap) \
231 ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap)
234 #if AIC_DEBUG_REGISTERS
235 ahc_reg_print_t ahc_seectl_print;
237 #define ahc_seectl_print(regvalue, cur_col, wrap) \
238 ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap)
241 #if AIC_DEBUG_REGISTERS
242 ahc_reg_print_t ahc_sblkctl_print;
244 #define ahc_sblkctl_print(regvalue, cur_col, wrap) \
245 ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
248 #if AIC_DEBUG_REGISTERS
249 ahc_reg_print_t ahc_busy_targets_print;
251 #define ahc_busy_targets_print(regvalue, cur_col, wrap) \
252 ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap)
255 #if AIC_DEBUG_REGISTERS
256 ahc_reg_print_t ahc_ultra_enb_print;
258 #define ahc_ultra_enb_print(regvalue, cur_col, wrap) \
259 ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap)
262 #if AIC_DEBUG_REGISTERS
263 ahc_reg_print_t ahc_disc_dsb_print;
265 #define ahc_disc_dsb_print(regvalue, cur_col, wrap) \
266 ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap)
269 #if AIC_DEBUG_REGISTERS
270 ahc_reg_print_t ahc_cmdsize_table_tail_print;
272 #define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \
273 ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap)
276 #if AIC_DEBUG_REGISTERS
277 ahc_reg_print_t ahc_mwi_residual_print;
279 #define ahc_mwi_residual_print(regvalue, cur_col, wrap) \
280 ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap)
283 #if AIC_DEBUG_REGISTERS
284 ahc_reg_print_t ahc_next_queued_scb_print;
286 #define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \
287 ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap)
290 #if AIC_DEBUG_REGISTERS
291 ahc_reg_print_t ahc_msg_out_print;
293 #define ahc_msg_out_print(regvalue, cur_col, wrap) \
294 ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap)
297 #if AIC_DEBUG_REGISTERS
298 ahc_reg_print_t ahc_dmaparams_print;
300 #define ahc_dmaparams_print(regvalue, cur_col, wrap) \
301 ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap)
304 #if AIC_DEBUG_REGISTERS
305 ahc_reg_print_t ahc_seq_flags_print;
307 #define ahc_seq_flags_print(regvalue, cur_col, wrap) \
308 ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
311 #if AIC_DEBUG_REGISTERS
312 ahc_reg_print_t ahc_saved_scsiid_print;
314 #define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \
315 ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap)
318 #if AIC_DEBUG_REGISTERS
319 ahc_reg_print_t ahc_saved_lun_print;
321 #define ahc_saved_lun_print(regvalue, cur_col, wrap) \
322 ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap)
325 #if AIC_DEBUG_REGISTERS
326 ahc_reg_print_t ahc_lastphase_print;
328 #define ahc_lastphase_print(regvalue, cur_col, wrap) \
329 ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
332 #if AIC_DEBUG_REGISTERS
333 ahc_reg_print_t ahc_waiting_scbh_print;
335 #define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \
336 ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap)
339 #if AIC_DEBUG_REGISTERS
340 ahc_reg_print_t ahc_disconnected_scbh_print;
342 #define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \
343 ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap)
346 #if AIC_DEBUG_REGISTERS
347 ahc_reg_print_t ahc_free_scbh_print;
349 #define ahc_free_scbh_print(regvalue, cur_col, wrap) \
350 ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap)
353 #if AIC_DEBUG_REGISTERS
354 ahc_reg_print_t ahc_complete_scbh_print;
356 #define ahc_complete_scbh_print(regvalue, cur_col, wrap) \
357 ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap)
360 #if AIC_DEBUG_REGISTERS
361 ahc_reg_print_t ahc_hscb_addr_print;
363 #define ahc_hscb_addr_print(regvalue, cur_col, wrap) \
364 ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap)
367 #if AIC_DEBUG_REGISTERS
368 ahc_reg_print_t ahc_shared_data_addr_print;
370 #define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \
371 ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap)
374 #if AIC_DEBUG_REGISTERS
375 ahc_reg_print_t ahc_kernel_qinpos_print;
377 #define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \
378 ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap)
381 #if AIC_DEBUG_REGISTERS
382 ahc_reg_print_t ahc_qinpos_print;
384 #define ahc_qinpos_print(regvalue, cur_col, wrap) \
385 ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap)
388 #if AIC_DEBUG_REGISTERS
389 ahc_reg_print_t ahc_qoutpos_print;
391 #define ahc_qoutpos_print(regvalue, cur_col, wrap) \
392 ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap)
395 #if AIC_DEBUG_REGISTERS
396 ahc_reg_print_t ahc_kernel_tqinpos_print;
398 #define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \
399 ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap)
402 #if AIC_DEBUG_REGISTERS
403 ahc_reg_print_t ahc_tqinpos_print;
405 #define ahc_tqinpos_print(regvalue, cur_col, wrap) \
406 ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap)
409 #if AIC_DEBUG_REGISTERS
410 ahc_reg_print_t ahc_arg_1_print;
412 #define ahc_arg_1_print(regvalue, cur_col, wrap) \
413 ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap)
416 #if AIC_DEBUG_REGISTERS
417 ahc_reg_print_t ahc_arg_2_print;
419 #define ahc_arg_2_print(regvalue, cur_col, wrap) \
420 ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap)
423 #if AIC_DEBUG_REGISTERS
424 ahc_reg_print_t ahc_last_msg_print;
426 #define ahc_last_msg_print(regvalue, cur_col, wrap) \
427 ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap)
430 #if AIC_DEBUG_REGISTERS
431 ahc_reg_print_t ahc_scsiseq_template_print;
433 #define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \
434 ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap)
437 #if AIC_DEBUG_REGISTERS
438 ahc_reg_print_t ahc_ha_274_biosglobal_print;
440 #define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \
441 ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap)
444 #if AIC_DEBUG_REGISTERS
445 ahc_reg_print_t ahc_seq_flags2_print;
447 #define ahc_seq_flags2_print(regvalue, cur_col, wrap) \
448 ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap)
451 #if AIC_DEBUG_REGISTERS
452 ahc_reg_print_t ahc_scsiconf_print;
454 #define ahc_scsiconf_print(regvalue, cur_col, wrap) \
455 ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap)
458 #if AIC_DEBUG_REGISTERS
459 ahc_reg_print_t ahc_intdef_print;
461 #define ahc_intdef_print(regvalue, cur_col, wrap) \
462 ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap)
465 #if AIC_DEBUG_REGISTERS
466 ahc_reg_print_t ahc_hostconf_print;
468 #define ahc_hostconf_print(regvalue, cur_col, wrap) \
469 ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap)
472 #if AIC_DEBUG_REGISTERS
473 ahc_reg_print_t ahc_ha_274_biosctrl_print;
475 #define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \
476 ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap)
479 #if AIC_DEBUG_REGISTERS
480 ahc_reg_print_t ahc_seqctl_print;
482 #define ahc_seqctl_print(regvalue, cur_col, wrap) \
483 ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
486 #if AIC_DEBUG_REGISTERS
487 ahc_reg_print_t ahc_seqram_print;
489 #define ahc_seqram_print(regvalue, cur_col, wrap) \
490 ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap)
493 #if AIC_DEBUG_REGISTERS
494 ahc_reg_print_t ahc_seqaddr0_print;
496 #define ahc_seqaddr0_print(regvalue, cur_col, wrap) \
497 ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap)
500 #if AIC_DEBUG_REGISTERS
501 ahc_reg_print_t ahc_seqaddr1_print;
503 #define ahc_seqaddr1_print(regvalue, cur_col, wrap) \
504 ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap)
507 #if AIC_DEBUG_REGISTERS
508 ahc_reg_print_t ahc_accum_print;
510 #define ahc_accum_print(regvalue, cur_col, wrap) \
511 ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap)
514 #if AIC_DEBUG_REGISTERS
515 ahc_reg_print_t ahc_sindex_print;
517 #define ahc_sindex_print(regvalue, cur_col, wrap) \
518 ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap)
521 #if AIC_DEBUG_REGISTERS
522 ahc_reg_print_t ahc_dindex_print;
524 #define ahc_dindex_print(regvalue, cur_col, wrap) \
525 ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap)
528 #if AIC_DEBUG_REGISTERS
529 ahc_reg_print_t ahc_allones_print;
531 #define ahc_allones_print(regvalue, cur_col, wrap) \
532 ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap)
535 #if AIC_DEBUG_REGISTERS
536 ahc_reg_print_t ahc_none_print;
538 #define ahc_none_print(regvalue, cur_col, wrap) \
539 ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap)
542 #if AIC_DEBUG_REGISTERS
543 ahc_reg_print_t ahc_allzeros_print;
545 #define ahc_allzeros_print(regvalue, cur_col, wrap) \
546 ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap)
549 #if AIC_DEBUG_REGISTERS
550 ahc_reg_print_t ahc_flags_print;
552 #define ahc_flags_print(regvalue, cur_col, wrap) \
553 ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap)
556 #if AIC_DEBUG_REGISTERS
557 ahc_reg_print_t ahc_sindir_print;
559 #define ahc_sindir_print(regvalue, cur_col, wrap) \
560 ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap)
563 #if AIC_DEBUG_REGISTERS
564 ahc_reg_print_t ahc_dindir_print;
566 #define ahc_dindir_print(regvalue, cur_col, wrap) \
567 ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap)
570 #if AIC_DEBUG_REGISTERS
571 ahc_reg_print_t ahc_function1_print;
573 #define ahc_function1_print(regvalue, cur_col, wrap) \
574 ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap)
577 #if AIC_DEBUG_REGISTERS
578 ahc_reg_print_t ahc_stack_print;
580 #define ahc_stack_print(regvalue, cur_col, wrap) \
581 ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap)
584 #if AIC_DEBUG_REGISTERS
585 ahc_reg_print_t ahc_targ_offset_print;
587 #define ahc_targ_offset_print(regvalue, cur_col, wrap) \
588 ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap)
591 #if AIC_DEBUG_REGISTERS
592 ahc_reg_print_t ahc_sram_base_print;
594 #define ahc_sram_base_print(regvalue, cur_col, wrap) \
595 ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
598 #if AIC_DEBUG_REGISTERS
599 ahc_reg_print_t ahc_dscommand0_print;
601 #define ahc_dscommand0_print(regvalue, cur_col, wrap) \
602 ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
605 #if AIC_DEBUG_REGISTERS
606 ahc_reg_print_t ahc_bctl_print;
608 #define ahc_bctl_print(regvalue, cur_col, wrap) \
609 ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
612 #if AIC_DEBUG_REGISTERS
613 ahc_reg_print_t ahc_bustime_print;
615 #define ahc_bustime_print(regvalue, cur_col, wrap) \
616 ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap)
619 #if AIC_DEBUG_REGISTERS
620 ahc_reg_print_t ahc_dscommand1_print;
622 #define ahc_dscommand1_print(regvalue, cur_col, wrap) \
623 ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap)
626 #if AIC_DEBUG_REGISTERS
627 ahc_reg_print_t ahc_busspd_print;
629 #define ahc_busspd_print(regvalue, cur_col, wrap) \
630 ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap)
633 #if AIC_DEBUG_REGISTERS
634 ahc_reg_print_t ahc_hs_mailbox_print;
636 #define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
637 ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
640 #if AIC_DEBUG_REGISTERS
641 ahc_reg_print_t ahc_dspcistatus_print;
643 #define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
644 ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
647 #if AIC_DEBUG_REGISTERS
648 ahc_reg_print_t ahc_hcntrl_print;
650 #define ahc_hcntrl_print(regvalue, cur_col, wrap) \
651 ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap)
654 #if AIC_DEBUG_REGISTERS
655 ahc_reg_print_t ahc_haddr_print;
657 #define ahc_haddr_print(regvalue, cur_col, wrap) \
658 ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap)
661 #if AIC_DEBUG_REGISTERS
662 ahc_reg_print_t ahc_hcnt_print;
664 #define ahc_hcnt_print(regvalue, cur_col, wrap) \
665 ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap)
668 #if AIC_DEBUG_REGISTERS
669 ahc_reg_print_t ahc_scbptr_print;
671 #define ahc_scbptr_print(regvalue, cur_col, wrap) \
672 ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap)
675 #if AIC_DEBUG_REGISTERS
676 ahc_reg_print_t ahc_intstat_print;
678 #define ahc_intstat_print(regvalue, cur_col, wrap) \
679 ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap)
682 #if AIC_DEBUG_REGISTERS
683 ahc_reg_print_t ahc_error_print;
685 #define ahc_error_print(regvalue, cur_col, wrap) \
686 ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap)
689 #if AIC_DEBUG_REGISTERS
690 ahc_reg_print_t ahc_clrint_print;
692 #define ahc_clrint_print(regvalue, cur_col, wrap) \
693 ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap)
696 #if AIC_DEBUG_REGISTERS
697 ahc_reg_print_t ahc_dfcntrl_print;
699 #define ahc_dfcntrl_print(regvalue, cur_col, wrap) \
700 ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap)
703 #if AIC_DEBUG_REGISTERS
704 ahc_reg_print_t ahc_dfstatus_print;
706 #define ahc_dfstatus_print(regvalue, cur_col, wrap) \
707 ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
710 #if AIC_DEBUG_REGISTERS
711 ahc_reg_print_t ahc_dfwaddr_print;
713 #define ahc_dfwaddr_print(regvalue, cur_col, wrap) \
714 ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap)
717 #if AIC_DEBUG_REGISTERS
718 ahc_reg_print_t ahc_dfraddr_print;
720 #define ahc_dfraddr_print(regvalue, cur_col, wrap) \
721 ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap)
724 #if AIC_DEBUG_REGISTERS
725 ahc_reg_print_t ahc_dfdat_print;
727 #define ahc_dfdat_print(regvalue, cur_col, wrap) \
728 ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap)
731 #if AIC_DEBUG_REGISTERS
732 ahc_reg_print_t ahc_scbcnt_print;
734 #define ahc_scbcnt_print(regvalue, cur_col, wrap) \
735 ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap)
738 #if AIC_DEBUG_REGISTERS
739 ahc_reg_print_t ahc_qinfifo_print;
741 #define ahc_qinfifo_print(regvalue, cur_col, wrap) \
742 ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap)
745 #if AIC_DEBUG_REGISTERS
746 ahc_reg_print_t ahc_qincnt_print;
748 #define ahc_qincnt_print(regvalue, cur_col, wrap) \
749 ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap)
752 #if AIC_DEBUG_REGISTERS
753 ahc_reg_print_t ahc_crccontrol1_print;
755 #define ahc_crccontrol1_print(regvalue, cur_col, wrap) \
756 ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap)
759 #if AIC_DEBUG_REGISTERS
760 ahc_reg_print_t ahc_qoutfifo_print;
762 #define ahc_qoutfifo_print(regvalue, cur_col, wrap) \
763 ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap)
766 #if AIC_DEBUG_REGISTERS
767 ahc_reg_print_t ahc_qoutcnt_print;
769 #define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
770 ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
773 #if AIC_DEBUG_REGISTERS
774 ahc_reg_print_t ahc_scsiphase_print;
776 #define ahc_scsiphase_print(regvalue, cur_col, wrap) \
777 ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
780 #if AIC_DEBUG_REGISTERS
781 ahc_reg_print_t ahc_sfunct_print;
783 #define ahc_sfunct_print(regvalue, cur_col, wrap) \
784 ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
787 #if AIC_DEBUG_REGISTERS
788 ahc_reg_print_t ahc_scb_base_print;
790 #define ahc_scb_base_print(regvalue, cur_col, wrap) \
791 ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
794 #if AIC_DEBUG_REGISTERS
795 ahc_reg_print_t ahc_scb_cdb_ptr_print;
797 #define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \
798 ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap)
801 #if AIC_DEBUG_REGISTERS
802 ahc_reg_print_t ahc_scb_residual_sgptr_print;
804 #define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
805 ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap)
808 #if AIC_DEBUG_REGISTERS
809 ahc_reg_print_t ahc_scb_scsi_status_print;
811 #define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \
812 ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap)
815 #if AIC_DEBUG_REGISTERS
816 ahc_reg_print_t ahc_scb_target_phases_print;
818 #define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \
819 ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap)
822 #if AIC_DEBUG_REGISTERS
823 ahc_reg_print_t ahc_scb_target_data_dir_print;
825 #define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \
826 ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap)
829 #if AIC_DEBUG_REGISTERS
830 ahc_reg_print_t ahc_scb_target_itag_print;
832 #define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \
833 ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap)
836 #if AIC_DEBUG_REGISTERS
837 ahc_reg_print_t ahc_scb_dataptr_print;
839 #define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \
840 ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap)
843 #if AIC_DEBUG_REGISTERS
844 ahc_reg_print_t ahc_scb_datacnt_print;
846 #define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \
847 ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap)
850 #if AIC_DEBUG_REGISTERS
851 ahc_reg_print_t ahc_scb_sgptr_print;
853 #define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \
854 ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap)
857 #if AIC_DEBUG_REGISTERS
858 ahc_reg_print_t ahc_scb_control_print;
860 #define ahc_scb_control_print(regvalue, cur_col, wrap) \
861 ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap)
864 #if AIC_DEBUG_REGISTERS
865 ahc_reg_print_t ahc_scb_scsiid_print;
867 #define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \
868 ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap)
871 #if AIC_DEBUG_REGISTERS
872 ahc_reg_print_t ahc_scb_lun_print;
874 #define ahc_scb_lun_print(regvalue, cur_col, wrap) \
875 ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap)
878 #if AIC_DEBUG_REGISTERS
879 ahc_reg_print_t ahc_scb_tag_print;
881 #define ahc_scb_tag_print(regvalue, cur_col, wrap) \
882 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
885 #if AIC_DEBUG_REGISTERS
886 ahc_reg_print_t ahc_scb_cdb_len_print;
888 #define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \
889 ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap)
892 #if AIC_DEBUG_REGISTERS
893 ahc_reg_print_t ahc_scb_scsirate_print;
895 #define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \
896 ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap)
899 #if AIC_DEBUG_REGISTERS
900 ahc_reg_print_t ahc_scb_scsioffset_print;
902 #define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
903 ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
906 #if AIC_DEBUG_REGISTERS
907 ahc_reg_print_t ahc_scb_next_print;
909 #define ahc_scb_next_print(regvalue, cur_col, wrap) \
910 ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
913 #if AIC_DEBUG_REGISTERS
914 ahc_reg_print_t ahc_scb_64_spare_print;
916 #define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
917 ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
920 #if AIC_DEBUG_REGISTERS
921 ahc_reg_print_t ahc_seectl_2840_print;
923 #define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
924 ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
927 #if AIC_DEBUG_REGISTERS
928 ahc_reg_print_t ahc_status_2840_print;
930 #define ahc_status_2840_print(regvalue, cur_col, wrap) \
931 ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
934 #if AIC_DEBUG_REGISTERS
935 ahc_reg_print_t ahc_scb_64_btt_print;
937 #define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
938 ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
941 #if AIC_DEBUG_REGISTERS
942 ahc_reg_print_t ahc_cchaddr_print;
944 #define ahc_cchaddr_print(regvalue, cur_col, wrap) \
945 ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
948 #if AIC_DEBUG_REGISTERS
949 ahc_reg_print_t ahc_cchcnt_print;
951 #define ahc_cchcnt_print(regvalue, cur_col, wrap) \
952 ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
955 #if AIC_DEBUG_REGISTERS
956 ahc_reg_print_t ahc_ccsgram_print;
958 #define ahc_ccsgram_print(regvalue, cur_col, wrap) \
959 ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
962 #if AIC_DEBUG_REGISTERS
963 ahc_reg_print_t ahc_ccsgaddr_print;
965 #define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
966 ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
969 #if AIC_DEBUG_REGISTERS
970 ahc_reg_print_t ahc_ccsgctl_print;
972 #define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
973 ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
976 #if AIC_DEBUG_REGISTERS
977 ahc_reg_print_t ahc_ccscbram_print;
979 #define ahc_ccscbram_print(regvalue, cur_col, wrap) \
980 ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
983 #if AIC_DEBUG_REGISTERS
984 ahc_reg_print_t ahc_ccscbaddr_print;
986 #define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
987 ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
990 #if AIC_DEBUG_REGISTERS
991 ahc_reg_print_t ahc_ccscbctl_print;
993 #define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
994 ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
997 #if AIC_DEBUG_REGISTERS
998 ahc_reg_print_t ahc_ccscbcnt_print;
1000 #define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
1001 ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
1004 #if AIC_DEBUG_REGISTERS
1005 ahc_reg_print_t ahc_scbbaddr_print;
1007 #define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
1008 ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
1011 #if AIC_DEBUG_REGISTERS
1012 ahc_reg_print_t ahc_ccscbptr_print;
1014 #define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
1015 ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
1018 #if AIC_DEBUG_REGISTERS
1019 ahc_reg_print_t ahc_hnscb_qoff_print;
1021 #define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
1022 ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
1025 #if AIC_DEBUG_REGISTERS
1026 ahc_reg_print_t ahc_snscb_qoff_print;
1028 #define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
1029 ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
1032 #if AIC_DEBUG_REGISTERS
1033 ahc_reg_print_t ahc_sdscb_qoff_print;
1035 #define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
1036 ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
1039 #if AIC_DEBUG_REGISTERS
1040 ahc_reg_print_t ahc_qoff_ctlsta_print;
1042 #define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
1043 ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
1046 #if AIC_DEBUG_REGISTERS
1047 ahc_reg_print_t ahc_dff_thrsh_print;
1049 #define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
1050 ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
1053 #if AIC_DEBUG_REGISTERS
1054 ahc_reg_print_t ahc_sg_cache_shadow_print;
1056 #define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
1057 ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
1060 #if AIC_DEBUG_REGISTERS
1061 ahc_reg_print_t ahc_sg_cache_pre_print;
1063 #define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
1064 ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
1068 #define SCSISEQ 0x00
1070 #define SCSIRSTO 0x01
1072 #define SXFRCTL0 0x01
1076 #define CLRSTCNT 0x10
1081 #define SXFRCTL1 0x02
1082 #define STIMESEL 0x18
1083 #define BITBUCKET 0x80
1084 #define SWRAPEN 0x40
1085 #define ENSTIMER 0x04
1086 #define ACTNEGEN 0x02
1089 #define SCSISIGI 0x03
1090 #define P_DATAIN_DT 0x60
1091 #define P_DATAOUT_DT 0x20
1098 #define SCSISIGO 0x03
1108 #define SCSIRATE 0x04
1110 #define SXFR_ULTRA2 0x0f
1112 #define WIDEXFER 0x80
1113 #define ENABLE_CRC 0x40
1114 #define SINGLE_EDGE 0x10
1117 #define SCSIOFFSET 0x05
1118 #define SOFS_ULTRA2 0x7f
1120 #define SCSIDATL 0x06
1122 #define SCSIDATH 0x07
1124 #define OPTIONMODE 0x08
1125 #define OPTIONMODE_DEFAULTS 0x03
1126 #define AUTORATEEN 0x80
1127 #define AUTOACKEN 0x40
1128 #define ATNMGMNTEN 0x20
1129 #define BUSFREEREV 0x10
1130 #define EXPPHASEDIS 0x08
1131 #define SCSIDATL_IMGEN 0x04
1132 #define AUTO_MSGOUT_DE 0x02
1133 #define DIS_MSGIN_DUALEDGE 0x01
1137 #define TARGCRCCNT 0x0a
1139 #define CLRSINT0 0x0b
1140 #define CLRSELDO 0x40
1141 #define CLRSELDI 0x20
1142 #define CLRSELINGO 0x10
1143 #define CLRIOERR 0x08
1144 #define CLRSWRAP 0x08
1145 #define CLRSPIORDY 0x02
1151 #define SELINGO 0x10
1155 #define SPIORDY 0x02
1156 #define DMADONE 0x01
1158 #define CLRSINT1 0x0c
1159 #define CLRSELTIMEO 0x80
1160 #define CLRATNO 0x40
1161 #define CLRSCSIRSTI 0x20
1162 #define CLRBUSFREE 0x08
1163 #define CLRSCSIPERR 0x04
1164 #define CLRPHASECHG 0x02
1165 #define CLRREQINIT 0x01
1169 #define ATNTARG 0x40
1170 #define SCSIRSTI 0x20
1171 #define PHASEMIS 0x10
1172 #define BUSFREE 0x08
1173 #define SCSIPERR 0x04
1174 #define PHASECHG 0x02
1175 #define REQINIT 0x01
1179 #define OVERRUN 0x80
1180 #define SHVALID 0x40
1181 #define EXP_ACTIVE 0x10
1182 #define CRCVALERR 0x08
1183 #define CRCENDERR 0x04
1184 #define CRCREQERR 0x02
1185 #define DUAL_EDGE_ERR 0x01
1188 #define SCSICNT 0xf0
1189 #define U2OFFCNT 0x7f
1192 #define SCSIID_ULTRA2 0x0f
1194 #define SIMODE0 0x10
1195 #define ENSELDO 0x40
1196 #define ENSELDI 0x20
1197 #define ENSELINGO 0x10
1198 #define ENIOERR 0x08
1199 #define ENSWRAP 0x08
1200 #define ENSDONE 0x04
1201 #define ENSPIORDY 0x02
1202 #define ENDMADONE 0x01
1204 #define SIMODE1 0x11
1205 #define ENSELTIMO 0x80
1206 #define ENATNTARG 0x40
1207 #define ENSCSIRST 0x20
1208 #define ENPHASEMIS 0x10
1209 #define ENBUSFREE 0x08
1210 #define ENSCSIPERR 0x04
1211 #define ENPHASECHG 0x02
1212 #define ENREQINIT 0x01
1214 #define SCSIBUSL 0x12
1216 #define SXFRCTL2 0x13
1217 #define ASYNC_SETUP 0x07
1218 #define AUTORSTDIS 0x10
1219 #define CMDDMAEN 0x08
1221 #define SCSIBUSH 0x13
1225 #define SELTIMER 0x18
1226 #define TARGIDIN 0x18
1235 #define SELID_MASK 0xf0
1238 #define SCAMCTL 0x1a
1239 #define SCAMLVL 0x03
1240 #define ENSCAMSELO 0x80
1241 #define CLRSCAMSELID 0x40
1242 #define ALTSTIM 0x20
1243 #define DFLTTID 0x10
1247 #define SPIOCAP 0x1b
1250 #define SOFTCMDEN 0x20
1251 #define EXT_BRDCTL 0x10
1252 #define SEEPROM 0x08
1255 #define SSPIOCPS 0x01
1258 #define BRDDAT7 0x80
1259 #define BRDDAT6 0x40
1260 #define BRDDAT5 0x20
1261 #define BRDDAT4 0x10
1263 #define BRDDAT3 0x08
1265 #define BRDDAT2 0x04
1267 #define BRDCTL1 0x02
1268 #define BRDRW_ULTRA2 0x02
1269 #define BRDCTL0 0x01
1270 #define BRDSTB_ULTRA2 0x01
1273 #define EXTARBACK 0x80
1274 #define EXTARBREQ 0x40
1282 #define SBLKCTL 0x1f
1283 #define DIAGLEDEN 0x80
1284 #define DIAGLEDON 0x40
1285 #define AUTOFLUSHDIS 0x20
1287 #define SELBUSB 0x08
1289 #define SELWIDE 0x02
1292 #define BUSY_TARGETS 0x20
1293 #define TARG_SCSIRATE 0x20
1295 #define ULTRA_ENB 0x30
1296 #define CMDSIZE_TABLE 0x30
1298 #define DISC_DSB 0x32
1300 #define CMDSIZE_TABLE_TAIL 0x34
1302 #define MWI_RESIDUAL 0x38
1304 #define NEXT_QUEUED_SCB 0x39
1306 #define MSG_OUT 0x3a
1308 #define DMAPARAMS 0x3b
1309 #define PRELOADEN 0x80
1310 #define WIDEODD 0x40
1312 #define SDMAENACK 0x10
1315 #define HDMAENACK 0x08
1316 #define DIRECTION 0x04
1317 #define FIFOFLUSH 0x02
1318 #define FIFORESET 0x01
1320 #define SEQ_FLAGS 0x3c
1321 #define NOT_IDENTIFIED 0x80
1322 #define NO_CDB_SENT 0x40
1323 #define TARGET_CMD_IS_TAGGED 0x40
1325 #define TARG_CMD_PENDING 0x10
1326 #define CMDPHASE_PENDING 0x08
1327 #define DPHASE_PENDING 0x04
1328 #define SPHASE_PENDING 0x02
1329 #define NO_DISCONNECT 0x01
1331 #define SAVED_SCSIID 0x3d
1333 #define SAVED_LUN 0x3e
1335 #define LASTPHASE 0x3f
1336 #define PHASE_MASK 0xe0
1337 #define P_MESGIN 0xe0
1338 #define P_STATUS 0xc0
1339 #define P_MESGOUT 0xa0
1340 #define P_COMMAND 0x80
1341 #define P_DATAIN 0x40
1342 #define P_BUSFREE 0x01
1343 #define P_DATAOUT 0x00
1348 #define WAITING_SCBH 0x40
1350 #define DISCONNECTED_SCBH 0x41
1352 #define FREE_SCBH 0x42
1354 #define COMPLETE_SCBH 0x43
1356 #define HSCB_ADDR 0x44
1358 #define SHARED_DATA_ADDR 0x48
1360 #define KERNEL_QINPOS 0x4c
1364 #define QOUTPOS 0x4e
1366 #define KERNEL_TQINPOS 0x4f
1368 #define TQINPOS 0x50
1371 #define RETURN_1 0x51
1372 #define SEND_MSG 0x80
1373 #define SEND_SENSE 0x40
1374 #define SEND_REJ 0x20
1375 #define MSGOUT_PHASEMIS 0x10
1376 #define EXIT_MSG_LOOP 0x08
1377 #define CONT_MSG_LOOP 0x04
1378 #define CONT_TARG_SESSION 0x02
1382 #define RETURN_2 0x52
1384 #define LAST_MSG 0x53
1385 #define TARG_IMMEDIATE_SCB 0x53
1387 #define SCSISEQ_TEMPLATE 0x54
1390 #define ENRSELI 0x10
1391 #define ENAUTOATNO 0x08
1392 #define ENAUTOATNI 0x04
1393 #define ENAUTOATNP 0x02
1395 #define HA_274_BIOSGLOBAL 0x56
1396 #define INITIATOR_TAG 0x56
1397 #define HA_274_EXTENDED_TRANS 0x01
1399 #define SEQ_FLAGS2 0x57
1400 #define TARGET_MSG_PENDING 0x02
1401 #define SCB_DMA 0x01
1403 #define SCSICONF 0x5a
1404 #define HWSCSIID 0x0f
1405 #define HSCSIID 0x07
1406 #define TERM_ENB 0x80
1407 #define RESET_SCSI 0x40
1408 #define ENSPCHK 0x20
1412 #define EDGE_TRIG 0x80
1414 #define HOSTCONF 0x5d
1416 #define HA_274_BIOSCTRL 0x5f
1417 #define BIOSDISABLED 0x30
1418 #define BIOSMODE 0x30
1419 #define CHANNEL_B_PRIMARY 0x08
1422 #define PERRORDIS 0x80
1423 #define PAUSEDIS 0x40
1424 #define FAILDIS 0x20
1425 #define FASTMODE 0x10
1426 #define BRKADRINTEN 0x08
1428 #define SEQRESET 0x02
1429 #define LOADRAM 0x01
1433 #define SEQADDR0 0x62
1435 #define SEQADDR1 0x63
1436 #define SEQADDR1_MASK 0x01
1444 #define ALLONES 0x69
1448 #define ALLZEROS 0x6a
1458 #define FUNCTION1 0x6e
1462 #define TARG_OFFSET 0x70
1464 #define SRAM_BASE 0x70
1466 #define DSCOMMAND0 0x84
1467 #define CACHETHEN 0x80
1468 #define DPARCKEN 0x40
1469 #define MPARCKEN 0x20
1470 #define EXTREQLCK 0x10
1471 #define INTSCBRAMSEL 0x08
1473 #define USCBSIZE32 0x02
1474 #define CIOPARCKEN 0x01
1480 #define BUSTIME 0x85
1484 #define DSCOMMAND1 0x85
1486 #define HADDLDSEL1 0x02
1487 #define HADDLDSEL0 0x01
1490 #define DFTHRSH 0xc0
1491 #define DFTHRSH_75 0x80
1495 #define HS_MAILBOX 0x86
1496 #define HOST_MAILBOX 0xf0
1497 #define HOST_TQINPOS 0x80
1498 #define SEQ_MAILBOX 0x0f
1500 #define DSPCISTATUS 0x86
1501 #define DFTHRSH_100 0xc0
1509 #define CHIPRST 0x01
1510 #define CHIPRSTACK 0x01
1518 #define INTSTAT 0x91
1519 #define SEQINT_MASK 0xf1
1520 #define OUT_OF_RANGE 0xe1
1521 #define NO_FREE_SCB 0xd1
1522 #define SCB_MISMATCH 0xc1
1523 #define MISSED_BUSFREE 0xb1
1524 #define MKMSG_FAILED 0xa1
1525 #define DATA_OVERRUN 0x91
1526 #define PERR_DETECTED 0x81
1527 #define BAD_STATUS 0x71
1528 #define HOST_MSG_LOOP 0x61
1529 #define PDATA_REINIT 0x51
1530 #define IGN_WIDE_RES 0x41
1531 #define NO_MATCH 0x31
1532 #define PROTO_VIOLATION 0x21
1533 #define SEND_REJECT 0x11
1534 #define INT_PEND 0x0f
1535 #define BAD_PHASE 0x01
1536 #define BRKADRINT 0x08
1537 #define SCSIINT 0x04
1538 #define CMDCMPLT 0x02
1542 #define CIOPARERR 0x80
1543 #define PCIERRSTAT 0x40
1544 #define MPARERR 0x20
1545 #define DPARERR 0x10
1546 #define SQPARERR 0x08
1547 #define ILLOPCODE 0x04
1548 #define ILLSADDR 0x02
1549 #define ILLHADDR 0x01
1552 #define CLRPARERR 0x10
1553 #define CLRBRKADRINT 0x08
1554 #define CLRSCSIINT 0x04
1555 #define CLRCMDINT 0x02
1556 #define CLRSEQINT 0x01
1558 #define DFCNTRL 0x93
1560 #define DFSTATUS 0x94
1561 #define PRELOAD_AVAIL 0x80
1562 #define DFCACHETH 0x40
1563 #define FIFOQWDEMP 0x20
1564 #define MREQPEND 0x10
1566 #define DFTHRESH 0x04
1567 #define FIFOFULL 0x02
1568 #define FIFOEMP 0x01
1570 #define DFWADDR 0x95
1572 #define DFRADDR 0x97
1577 #define SCBCNT_MASK 0x1f
1578 #define SCBAUTO 0x80
1580 #define QINFIFO 0x9b
1584 #define CRCCONTROL1 0x9d
1585 #define CRCONSEEN 0x80
1586 #define CRCVALCHKEN 0x40
1587 #define CRCENDCHKEN 0x20
1588 #define CRCREQCHKEN 0x10
1589 #define TARGCRCENDEN 0x08
1590 #define TARGCRCCNTEN 0x04
1592 #define QOUTFIFO 0x9d
1594 #define QOUTCNT 0x9e
1596 #define SCSIPHASE 0x9e
1597 #define DATA_PHASE_MASK 0x03
1598 #define STATUS_PHASE 0x20
1599 #define COMMAND_PHASE 0x10
1600 #define MSG_IN_PHASE 0x08
1601 #define MSG_OUT_PHASE 0x04
1602 #define DATA_IN_PHASE 0x02
1603 #define DATA_OUT_PHASE 0x01
1606 #define ALT_MODE 0x80
1608 #define SCB_BASE 0xa0
1610 #define SCB_CDB_PTR 0xa0
1611 #define SCB_RESIDUAL_DATACNT 0xa0
1612 #define SCB_CDB_STORE 0xa0
1614 #define SCB_RESIDUAL_SGPTR 0xa4
1616 #define SCB_SCSI_STATUS 0xa8
1618 #define SCB_TARGET_PHASES 0xa9
1620 #define SCB_TARGET_DATA_DIR 0xaa
1622 #define SCB_TARGET_ITAG 0xab
1624 #define SCB_DATAPTR 0xac
1626 #define SCB_DATACNT 0xb0
1627 #define SG_HIGH_ADDR_BITS 0x7f
1628 #define SG_LAST_SEG 0x80
1630 #define SCB_SGPTR 0xb4
1631 #define SG_RESID_VALID 0x04
1632 #define SG_FULL_RESID 0x02
1633 #define SG_LIST_NULL 0x01
1635 #define SCB_CONTROL 0xb8
1636 #define SCB_TAG_TYPE 0x03
1637 #define STATUS_RCVD 0x80
1638 #define TARGET_SCB 0x80
1639 #define DISCENB 0x40
1640 #define TAG_ENB 0x20
1641 #define MK_MESSAGE 0x10
1642 #define ULTRAENB 0x08
1643 #define DISCONNECTED 0x04
1645 #define SCB_SCSIID 0xb9
1647 #define TWIN_TID 0x70
1649 #define TWIN_CHNLB 0x80
1651 #define SCB_LUN 0xba
1653 #define SCB_XFERLEN_ODD 0x80
1655 #define SCB_TAG 0xbb
1657 #define SCB_CDB_LEN 0xbc
1659 #define SCB_SCSIRATE 0xbd
1661 #define SCB_SCSIOFFSET 0xbe
1663 #define SCB_NEXT 0xbf
1665 #define SCB_64_SPARE 0xc0
1667 #define SEECTL_2840 0xc0
1668 #define CS_2840 0x04
1669 #define CK_2840 0x02
1670 #define DO_2840 0x01
1672 #define STATUS_2840 0xc1
1673 #define BIOS_SEL 0x60
1675 #define EEPROM_TF 0x80
1676 #define DI_2840 0x01
1678 #define SCB_64_BTT 0xd0
1680 #define CCHADDR 0xe0
1684 #define CCSGRAM 0xe9
1686 #define CCSGADDR 0xea
1688 #define CCSGCTL 0xeb
1689 #define CCSGDONE 0x80
1691 #define SG_FETCH_NEEDED 0x02
1692 #define CCSGRESET 0x01
1694 #define CCSCBRAM 0xec
1696 #define CCSCBADDR 0xed
1698 #define CCSCBCTL 0xee
1699 #define CCSCBDONE 0x80
1700 #define ARRDONE 0x40
1701 #define CCARREN 0x10
1702 #define CCSCBEN 0x08
1703 #define CCSCBDIR 0x04
1704 #define CCSCBRESET 0x01
1706 #define CCSCBCNT 0xef
1708 #define SCBBADDR 0xf0
1710 #define CCSCBPTR 0xf1
1712 #define HNSCB_QOFF 0xf4
1714 #define SNSCB_QOFF 0xf6
1716 #define SDSCB_QOFF 0xf8
1718 #define QOFF_CTLSTA 0xfa
1719 #define SCB_QSIZE 0x07
1720 #define SCB_QSIZE_256 0x06
1721 #define SCB_AVAIL 0x40
1722 #define SNSCB_ROLLOVER 0x20
1723 #define SDSCB_ROLLOVER 0x10
1725 #define DFF_THRSH 0xfb
1726 #define WR_DFTHRSH 0x70
1727 #define WR_DFTHRSH_MAX 0x70
1728 #define WR_DFTHRSH_90 0x60
1729 #define WR_DFTHRSH_85 0x50
1730 #define WR_DFTHRSH_75 0x40
1731 #define WR_DFTHRSH_63 0x30
1732 #define WR_DFTHRSH_50 0x20
1733 #define WR_DFTHRSH_25 0x10
1734 #define RD_DFTHRSH_MAX 0x07
1735 #define RD_DFTHRSH 0x07
1736 #define RD_DFTHRSH_90 0x06
1737 #define RD_DFTHRSH_85 0x05
1738 #define RD_DFTHRSH_75 0x04
1739 #define RD_DFTHRSH_63 0x03
1740 #define RD_DFTHRSH_50 0x02
1741 #define RD_DFTHRSH_25 0x01
1742 #define RD_DFTHRSH_MIN 0x00
1743 #define WR_DFTHRSH_MIN 0x00
1745 #define SG_CACHE_SHADOW 0xfc
1746 #define SG_ADDR_MASK 0xf8
1747 #define LAST_SEG 0x02
1748 #define LAST_SEG_DONE 0x01
1750 #define SG_CACHE_PRE 0xfc
1753 #define MAX_OFFSET_ULTRA2 0x7f
1754 #define SCB_LIST_NULL 0xff
1755 #define HOST_MSG 0xff
1756 #define MAX_OFFSET 0x7f
1757 #define BUS_32_BIT 0x02
1758 #define CMD_GROUP_CODE_SHIFT 0x05
1759 #define BUS_8_BIT 0x00
1760 #define CCSGRAM_MAXSEGS 0x10
1761 #define TARGET_DATA_IN 0x01
1762 #define STATUS_QUEUE_FULL 0x28
1763 #define STATUS_BUSY 0x08
1764 #define MAX_OFFSET_8BIT 0x0f
1765 #define BUS_16_BIT 0x01
1766 #define TID_SHIFT 0x04
1767 #define SCB_DOWNLOAD_SIZE_64 0x30
1768 #define SCB_UPLOAD_SIZE 0x20
1769 #define HOST_MAILBOX_SHIFT 0x04
1770 #define MAX_OFFSET_16BIT 0x08
1771 #define TARGET_CMD_CMPLT 0xfe
1772 #define SG_SIZEOF 0x08
1773 #define SCB_DOWNLOAD_SIZE 0x20
1774 #define SEQ_MAILBOX_SHIFT 0x00
1775 #define CCSGADDR_MAX 0x80
1776 #define STACK_SIZE 0x04
1779 /* Downloaded Constant Definitions */
1780 #define SG_PREFETCH_ADDR_MASK 0x06
1781 #define SG_PREFETCH_ALIGN_MASK 0x05
1782 #define QOUTFIFO_OFFSET 0x00
1783 #define SG_PREFETCH_CNT 0x04
1784 #define INVERTED_CACHESIZE_MASK 0x03
1785 #define CACHESIZE_MASK 0x02
1786 #define QINFIFO_OFFSET 0x01
1787 #define DOWNLOAD_CONST_COUNT 0x07
1790 /* Exported Labels */