2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/queue.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
53 #include <net/debugnet.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_llc.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/miivar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
75 #include <machine/bus.h>
76 #include <machine/in_cksum.h>
78 #include <dev/alc/if_alcreg.h>
79 #include <dev/alc/if_alcvar.h>
81 /* "device miibus" required. See GENERIC if you get errors here. */
82 #include "miibus_if.h"
83 #undef ALC_USE_CUSTOM_CSUM
85 #ifdef ALC_USE_CUSTOM_CSUM
86 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
88 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
91 MODULE_DEPEND(alc, pci, 1, 1, 1);
92 MODULE_DEPEND(alc, ether, 1, 1, 1);
93 MODULE_DEPEND(alc, miibus, 1, 1, 1);
96 static int msi_disable = 0;
97 static int msix_disable = 0;
98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
102 * Devices supported by this driver.
104 static struct alc_ident alc_ident_table[] = {
105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024,
106 "Atheros AR8131 PCIe Gigabit Ethernet" },
107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024,
108 "Atheros AR8132 PCIe Fast Ethernet" },
109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024,
110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024,
112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024,
114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024,
118 "Atheros AR8161 PCIe Gigabit Ethernet" },
119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024,
120 "Atheros AR8162 PCIe Fast Ethernet" },
121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024,
122 "Atheros AR8171 PCIe Gigabit Ethernet" },
123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024,
124 "Atheros AR8172 PCIe Fast Ethernet" },
125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024,
126 "Killer E2200 Gigabit Ethernet" },
127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024,
128 "Killer E2400 Gigabit Ethernet" },
129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024,
130 "Killer E2500 Gigabit Ethernet" },
134 static void alc_aspm(struct alc_softc *, int, int);
135 static void alc_aspm_813x(struct alc_softc *, int);
136 static void alc_aspm_816x(struct alc_softc *, int);
137 static int alc_attach(device_t);
138 static int alc_check_boundary(struct alc_softc *);
139 static void alc_config_msi(struct alc_softc *);
140 static int alc_detach(device_t);
141 static void alc_disable_l0s_l1(struct alc_softc *);
142 static int alc_dma_alloc(struct alc_softc *);
143 static void alc_dma_free(struct alc_softc *);
144 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
145 static void alc_dsp_fixup(struct alc_softc *, int);
146 static int alc_encap(struct alc_softc *, struct mbuf **);
147 static struct alc_ident *
148 alc_find_ident(device_t);
149 #ifndef __NO_STRICT_ALIGNMENT
151 alc_fixup_rx(struct ifnet *, struct mbuf *);
153 static void alc_get_macaddr(struct alc_softc *);
154 static void alc_get_macaddr_813x(struct alc_softc *);
155 static void alc_get_macaddr_816x(struct alc_softc *);
156 static void alc_get_macaddr_par(struct alc_softc *);
157 static void alc_init(void *);
158 static void alc_init_cmb(struct alc_softc *);
159 static void alc_init_locked(struct alc_softc *);
160 static void alc_init_rr_ring(struct alc_softc *);
161 static int alc_init_rx_ring(struct alc_softc *);
162 static void alc_init_smb(struct alc_softc *);
163 static void alc_init_tx_ring(struct alc_softc *);
164 static void alc_int_task(void *, int);
165 static int alc_intr(void *);
166 static int alc_ioctl(struct ifnet *, u_long, caddr_t);
167 static void alc_mac_config(struct alc_softc *);
168 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int);
169 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int);
170 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int);
171 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int);
172 static int alc_miibus_readreg(device_t, int, int);
173 static void alc_miibus_statchg(device_t);
174 static int alc_miibus_writereg(device_t, int, int, int);
175 static uint32_t alc_miidbg_readreg(struct alc_softc *, int);
176 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int);
177 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int);
178 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int);
179 static int alc_mediachange(struct ifnet *);
180 static int alc_mediachange_locked(struct alc_softc *);
181 static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
182 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
183 static void alc_osc_reset(struct alc_softc *);
184 static void alc_phy_down(struct alc_softc *);
185 static void alc_phy_reset(struct alc_softc *);
186 static void alc_phy_reset_813x(struct alc_softc *);
187 static void alc_phy_reset_816x(struct alc_softc *);
188 static int alc_probe(device_t);
189 static void alc_reset(struct alc_softc *);
190 static int alc_resume(device_t);
191 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
192 static int alc_rxintr(struct alc_softc *, int);
193 static void alc_rxfilter(struct alc_softc *);
194 static void alc_rxvlan(struct alc_softc *);
195 static void alc_setlinkspeed(struct alc_softc *);
196 static void alc_setwol(struct alc_softc *);
197 static void alc_setwol_813x(struct alc_softc *);
198 static void alc_setwol_816x(struct alc_softc *);
199 static int alc_shutdown(device_t);
200 static void alc_start(struct ifnet *);
201 static void alc_start_locked(struct ifnet *);
202 static void alc_start_queue(struct alc_softc *);
203 static void alc_start_tx(struct alc_softc *);
204 static void alc_stats_clear(struct alc_softc *);
205 static void alc_stats_update(struct alc_softc *);
206 static void alc_stop(struct alc_softc *);
207 static void alc_stop_mac(struct alc_softc *);
208 static void alc_stop_queue(struct alc_softc *);
209 static int alc_suspend(device_t);
210 static void alc_sysctl_node(struct alc_softc *);
211 static void alc_tick(void *);
212 static void alc_txeof(struct alc_softc *);
213 static void alc_watchdog(struct alc_softc *);
214 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
215 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
216 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
218 DEBUGNET_DEFINE(alc);
220 static device_method_t alc_methods[] = {
221 /* Device interface. */
222 DEVMETHOD(device_probe, alc_probe),
223 DEVMETHOD(device_attach, alc_attach),
224 DEVMETHOD(device_detach, alc_detach),
225 DEVMETHOD(device_shutdown, alc_shutdown),
226 DEVMETHOD(device_suspend, alc_suspend),
227 DEVMETHOD(device_resume, alc_resume),
230 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
231 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
232 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
237 static driver_t alc_driver = {
240 sizeof(struct alc_softc)
243 static devclass_t alc_devclass;
245 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0);
246 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table,
247 nitems(alc_ident_table) - 1);
248 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0);
250 static struct resource_spec alc_res_spec_mem[] = {
251 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
255 static struct resource_spec alc_irq_spec_legacy[] = {
256 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
260 static struct resource_spec alc_irq_spec_msi[] = {
261 { SYS_RES_IRQ, 1, RF_ACTIVE },
265 static struct resource_spec alc_irq_spec_msix[] = {
266 { SYS_RES_IRQ, 1, RF_ACTIVE },
270 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
273 alc_miibus_readreg(device_t dev, int phy, int reg)
275 struct alc_softc *sc;
278 sc = device_get_softc(dev);
279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
280 v = alc_mii_readreg_816x(sc, phy, reg);
282 v = alc_mii_readreg_813x(sc, phy, reg);
287 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)
293 * For AR8132 fast ethernet controller, do not report 1000baseT
294 * capability to mii(4). Even though AR8132 uses the same
295 * model/revision number of F1 gigabit PHY, the PHY has no
296 * ability to establish 1000baseT link.
298 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
302 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
303 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
304 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
306 v = CSR_READ_4(sc, ALC_MDIO);
307 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
312 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
316 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
320 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)
325 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
326 clk = MDIO_CLK_25_128;
329 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
330 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
331 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
333 v = CSR_READ_4(sc, ALC_MDIO);
334 if ((v & MDIO_OP_BUSY) == 0)
339 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
343 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
347 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
349 struct alc_softc *sc;
352 sc = device_get_softc(dev);
353 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
354 v = alc_mii_writereg_816x(sc, phy, reg, val);
356 v = alc_mii_writereg_813x(sc, phy, reg, val);
361 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)
366 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
367 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
368 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
369 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
371 v = CSR_READ_4(sc, ALC_MDIO);
372 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
377 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
383 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)
388 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
389 clk = MDIO_CLK_25_128;
392 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
393 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
394 MDIO_SUP_PREAMBLE | clk);
395 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
397 v = CSR_READ_4(sc, ALC_MDIO);
398 if ((v & MDIO_OP_BUSY) == 0)
403 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
409 alc_miibus_statchg(device_t dev)
411 struct alc_softc *sc;
412 struct mii_data *mii;
416 sc = device_get_softc(dev);
418 mii = device_get_softc(sc->alc_miibus);
420 if (mii == NULL || ifp == NULL ||
421 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
424 sc->alc_flags &= ~ALC_FLAG_LINK;
425 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
426 (IFM_ACTIVE | IFM_AVALID)) {
427 switch (IFM_SUBTYPE(mii->mii_media_active)) {
430 sc->alc_flags |= ALC_FLAG_LINK;
433 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
434 sc->alc_flags |= ALC_FLAG_LINK;
440 /* Stop Rx/Tx MACs. */
443 /* Program MACs with resolved speed/duplex/flow-control. */
444 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
447 /* Re-enable Tx/Rx MACs. */
448 reg = CSR_READ_4(sc, ALC_MAC_CFG);
449 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
450 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
452 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
453 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
457 alc_miidbg_readreg(struct alc_softc *sc, int reg)
460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
462 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
467 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
470 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
472 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
473 ALC_MII_DBG_DATA, val));
477 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
482 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
483 EXT_MDIO_DEVADDR(devaddr));
484 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
485 clk = MDIO_CLK_25_128;
488 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
489 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
490 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
492 v = CSR_READ_4(sc, ALC_MDIO);
493 if ((v & MDIO_OP_BUSY) == 0)
498 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n",
503 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
507 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
512 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
513 EXT_MDIO_DEVADDR(devaddr));
514 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
515 clk = MDIO_CLK_25_128;
518 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
519 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
520 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
521 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
523 v = CSR_READ_4(sc, ALC_MDIO);
524 if ((v & MDIO_OP_BUSY) == 0)
529 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n",
536 alc_dsp_fixup(struct alc_softc *sc, int media)
538 uint16_t agc, len, val;
540 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
542 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
547 * 1000BT/AZ, wrong cable length
549 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
550 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
551 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) &
552 EXT_CLDCTL6_CAB_LEN_MASK;
553 agc = alc_miidbg_readreg(sc, MII_DBG_AGC);
554 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK;
555 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G &&
556 agc > DBG_AGC_LONG1G_LIMT) ||
557 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT &&
558 agc > DBG_AGC_LONG1G_LIMT)) {
559 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
560 DBG_AZ_ANADECT_LONG);
561 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
563 val |= ANEG_AFEE_10BT_100M_TH;
564 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
567 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
568 DBG_AZ_ANADECT_DEFAULT);
569 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
571 val &= ~ANEG_AFEE_10BT_100M_TH;
572 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
575 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
576 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
577 if (media == IFM_1000_T) {
579 * Giga link threshold, raise the tolerance of
582 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
583 val &= ~DBG_MSE20DB_TH_MASK;
584 val |= (DBG_MSE20DB_TH_HI <<
585 DBG_MSE20DB_TH_SHIFT);
586 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
587 } else if (media == IFM_100_TX)
588 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
592 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
593 val &= ~ANEG_AFEE_10BT_100M_TH;
594 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
595 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
596 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
597 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
599 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
600 val &= ~DBG_MSE20DB_TH_MASK;
601 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
602 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
608 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
610 struct alc_softc *sc;
611 struct mii_data *mii;
615 if ((ifp->if_flags & IFF_UP) == 0) {
619 mii = device_get_softc(sc->alc_miibus);
622 ifmr->ifm_status = mii->mii_media_status;
623 ifmr->ifm_active = mii->mii_media_active;
628 alc_mediachange(struct ifnet *ifp)
630 struct alc_softc *sc;
635 error = alc_mediachange_locked(sc);
642 alc_mediachange_locked(struct alc_softc *sc)
644 struct mii_data *mii;
645 struct mii_softc *miisc;
650 mii = device_get_softc(sc->alc_miibus);
651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
653 error = mii_mediachg(mii);
658 static struct alc_ident *
659 alc_find_ident(device_t dev)
661 struct alc_ident *ident;
662 uint16_t vendor, devid;
664 vendor = pci_get_vendor(dev);
665 devid = pci_get_device(dev);
666 for (ident = alc_ident_table; ident->name != NULL; ident++) {
667 if (vendor == ident->vendorid && devid == ident->deviceid)
675 alc_probe(device_t dev)
677 struct alc_ident *ident;
679 ident = alc_find_ident(dev);
681 device_set_desc(dev, ident->name);
682 return (BUS_PROBE_DEFAULT);
689 alc_get_macaddr(struct alc_softc *sc)
692 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
693 alc_get_macaddr_816x(sc);
695 alc_get_macaddr_813x(sc);
699 alc_get_macaddr_813x(struct alc_softc *sc)
706 opt = CSR_READ_4(sc, ALC_OPT_CFG);
707 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
708 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
710 * EEPROM found, let TWSI reload EEPROM configuration.
711 * This will set ethernet address of controller.
714 switch (sc->alc_ident->deviceid) {
715 case DEVICEID_ATHEROS_AR8131:
716 case DEVICEID_ATHEROS_AR8132:
717 if ((opt & OPT_CFG_CLK_ENB) == 0) {
718 opt |= OPT_CFG_CLK_ENB;
719 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
720 CSR_READ_4(sc, ALC_OPT_CFG);
724 case DEVICEID_ATHEROS_AR8151:
725 case DEVICEID_ATHEROS_AR8151_V2:
726 case DEVICEID_ATHEROS_AR8152_B:
727 case DEVICEID_ATHEROS_AR8152_B2:
728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
729 ALC_MII_DBG_ADDR, 0x00);
730 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
733 ALC_MII_DBG_DATA, val & 0xFF7F);
734 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
735 ALC_MII_DBG_ADDR, 0x3B);
736 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
738 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
739 ALC_MII_DBG_DATA, val | 0x0008);
744 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
745 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
746 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
747 CSR_READ_4(sc, ALC_WOL_CFG);
749 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
750 TWSI_CFG_SW_LD_START);
751 for (i = 100; i > 0; i--) {
753 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
754 TWSI_CFG_SW_LD_START) == 0)
758 device_printf(sc->alc_dev,
759 "reloading EEPROM timeout!\n");
762 device_printf(sc->alc_dev, "EEPROM not found!\n");
765 switch (sc->alc_ident->deviceid) {
766 case DEVICEID_ATHEROS_AR8131:
767 case DEVICEID_ATHEROS_AR8132:
768 if ((opt & OPT_CFG_CLK_ENB) != 0) {
769 opt &= ~OPT_CFG_CLK_ENB;
770 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
771 CSR_READ_4(sc, ALC_OPT_CFG);
775 case DEVICEID_ATHEROS_AR8151:
776 case DEVICEID_ATHEROS_AR8151_V2:
777 case DEVICEID_ATHEROS_AR8152_B:
778 case DEVICEID_ATHEROS_AR8152_B2:
779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
780 ALC_MII_DBG_ADDR, 0x00);
781 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
784 ALC_MII_DBG_DATA, val | 0x0080);
785 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
786 ALC_MII_DBG_ADDR, 0x3B);
787 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
789 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
790 ALC_MII_DBG_DATA, val & 0xFFF7);
796 alc_get_macaddr_par(sc);
800 alc_get_macaddr_816x(struct alc_softc *sc)
806 /* Try to reload station address via TWSI. */
807 for (i = 100; i > 0; i--) {
808 reg = CSR_READ_4(sc, ALC_SLD);
809 if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
814 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
815 for (i = 100; i > 0; i--) {
817 reg = CSR_READ_4(sc, ALC_SLD);
818 if ((reg & SLD_START) == 0)
823 else if (bootverbose)
824 device_printf(sc->alc_dev,
825 "reloading station address via TWSI timed out!\n");
828 /* Try to reload station address from EEPROM or FLASH. */
830 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
831 if ((reg & (EEPROM_LD_EEPROM_EXIST |
832 EEPROM_LD_FLASH_EXIST)) != 0) {
833 for (i = 100; i > 0; i--) {
834 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
835 if ((reg & (EEPROM_LD_PROGRESS |
836 EEPROM_LD_START)) == 0)
841 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
843 for (i = 100; i > 0; i--) {
845 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
846 if ((reg & EEPROM_LD_START) == 0)
849 } else if (bootverbose)
850 device_printf(sc->alc_dev,
851 "reloading EEPROM/FLASH timed out!\n");
855 alc_get_macaddr_par(sc);
859 alc_get_macaddr_par(struct alc_softc *sc)
863 ea[0] = CSR_READ_4(sc, ALC_PAR0);
864 ea[1] = CSR_READ_4(sc, ALC_PAR1);
865 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
866 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
867 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
868 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
869 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
870 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
874 alc_disable_l0s_l1(struct alc_softc *sc)
878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
879 /* Another magic from vendor. */
880 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
881 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
882 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
883 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1);
884 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
885 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB;
886 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
891 alc_phy_reset(struct alc_softc *sc)
894 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
895 alc_phy_reset_816x(sc);
897 alc_phy_reset_813x(sc);
901 alc_phy_reset_813x(struct alc_softc *sc)
905 /* Reset magic from Linux. */
906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
907 CSR_READ_2(sc, ALC_GPHY_CFG);
910 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
911 GPHY_CFG_SEL_ANA_RESET);
912 CSR_READ_2(sc, ALC_GPHY_CFG);
915 /* DSP fixup, Vendor magic. */
916 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
917 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
918 ALC_MII_DBG_ADDR, 0x000A);
919 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
921 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
922 ALC_MII_DBG_DATA, data & 0xDFFF);
924 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
929 ALC_MII_DBG_ADDR, 0x003B);
930 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
932 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
933 ALC_MII_DBG_DATA, data & 0xFFF7);
936 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) {
937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
938 ALC_MII_DBG_ADDR, 0x0029);
939 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
940 ALC_MII_DBG_DATA, 0x929D);
942 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
947 ALC_MII_DBG_ADDR, 0x0029);
948 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
949 ALC_MII_DBG_DATA, 0xB6DD);
952 /* Load DSP codes, vendor magic. */
953 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
954 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
956 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
958 ALC_MII_DBG_DATA, data);
960 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
961 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
964 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
966 ALC_MII_DBG_DATA, data);
968 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
969 ANA_LONG_CABLE_TH_100_MASK) |
970 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
971 ANA_SHORT_CABLE_TH_100_SHIFT) |
972 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
974 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
975 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
976 ALC_MII_DBG_DATA, data);
978 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
979 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
980 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
981 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
983 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
985 ALC_MII_DBG_DATA, data);
987 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
988 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
991 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
993 ALC_MII_DBG_DATA, data);
996 /* Disable hibernation. */
997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
999 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1002 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1005 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
1007 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1010 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1015 alc_phy_reset_816x(struct alc_softc *sc)
1019 val = CSR_READ_4(sc, ALC_GPHY_CFG);
1020 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1021 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON |
1022 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB);
1023 val |= GPHY_CFG_SEL_ANA_RESET;
1025 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET;
1027 /* Disable PHY hibernation. */
1028 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
1032 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
1035 /* Vendor PHY magic. */
1037 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT);
1038 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT);
1039 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS,
1040 EXT_VDRVBIAS_DEFAULT);
1042 /* Disable PHY hibernation. */
1043 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
1044 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB);
1045 alc_miidbg_writereg(sc, MII_DBG_HIBNEG,
1046 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE));
1047 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
1050 /* XXX Disable EEE. */
1051 val = CSR_READ_4(sc, ALC_LPI_CTL);
1052 val &= ~LPI_CTL_ENB;
1053 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
1054 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
1056 /* PHY power saving. */
1057 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
1058 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
1059 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
1060 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
1061 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1062 val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
1063 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1065 /* RTL8139C, 120m issue. */
1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
1067 ANEG_NLP78_120M_DEFAULT);
1068 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
1069 ANEG_S3DIG10_DEFAULT);
1071 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
1072 /* Turn off half amplitude. */
1073 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
1074 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
1075 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
1076 /* Turn off Green feature. */
1077 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1078 val |= DBG_GREENCFG2_BP_GREEN;
1079 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1080 /* Turn off half bias. */
1081 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
1082 val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
1083 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
1088 alc_phy_down(struct alc_softc *sc)
1092 switch (sc->alc_ident->deviceid) {
1093 case DEVICEID_ATHEROS_AR8161:
1094 case DEVICEID_ATHEROS_E2200:
1095 case DEVICEID_ATHEROS_E2400:
1096 case DEVICEID_ATHEROS_E2500:
1097 case DEVICEID_ATHEROS_AR8162:
1098 case DEVICEID_ATHEROS_AR8171:
1099 case DEVICEID_ATHEROS_AR8172:
1100 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
1101 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1102 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON);
1103 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
1104 GPHY_CFG_SEL_ANA_RESET;
1105 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
1106 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
1108 case DEVICEID_ATHEROS_AR8151:
1109 case DEVICEID_ATHEROS_AR8151_V2:
1110 case DEVICEID_ATHEROS_AR8152_B:
1111 case DEVICEID_ATHEROS_AR8152_B2:
1113 * GPHY power down caused more problems on AR8151 v2.0.
1114 * When driver is reloaded after GPHY power down,
1115 * accesses to PHY/MAC registers hung the system. Only
1116 * cold boot recovered from it. I'm not sure whether
1117 * AR8151 v1.0 also requires this one though. I don't
1118 * have AR8151 v1.0 controller in hand.
1119 * The only option left is to isolate the PHY and
1120 * initiates power down the PHY which in turn saves
1121 * more power when driver is unloaded.
1123 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1124 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
1127 /* Force PHY down. */
1128 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1129 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
1130 GPHY_CFG_PWDOWN_HW);
1137 alc_aspm(struct alc_softc *sc, int init, int media)
1140 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1141 alc_aspm_816x(sc, init);
1143 alc_aspm_813x(sc, media);
1147 alc_aspm_813x(struct alc_softc *sc, int media)
1152 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1155 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1156 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
1157 (ALC_FLAG_APS | ALC_FLAG_PCIE))
1158 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
1162 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
1163 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
1164 pmcfg |= PM_CFG_MAC_ASPM_CHK;
1165 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
1166 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1168 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1169 /* Disable extended sync except AR8152 B v1.0 */
1170 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
1171 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1172 sc->alc_rev == ATHEROS_AR8152_B_V10)
1173 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
1174 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
1176 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
1178 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
1179 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1180 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1181 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
1182 PM_CFG_PM_REQ_TIMER_SHIFT);
1183 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
1186 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1187 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1188 pmcfg |= PM_CFG_ASPM_L0S_ENB;
1189 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1190 pmcfg |= PM_CFG_ASPM_L1_ENB;
1191 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1192 if (sc->alc_ident->deviceid ==
1193 DEVICEID_ATHEROS_AR8152_B)
1194 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
1195 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
1196 PM_CFG_SERDES_PLL_L1_ENB |
1197 PM_CFG_SERDES_BUDS_RX_L1_ENB);
1198 pmcfg |= PM_CFG_CLK_SWH_L1;
1199 if (media == IFM_100_TX || media == IFM_1000_T) {
1200 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
1201 switch (sc->alc_ident->deviceid) {
1202 case DEVICEID_ATHEROS_AR8152_B:
1204 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1206 case DEVICEID_ATHEROS_AR8152_B2:
1207 case DEVICEID_ATHEROS_AR8151_V2:
1209 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1213 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1218 pmcfg |= PM_CFG_SERDES_L1_ENB |
1219 PM_CFG_SERDES_PLL_L1_ENB |
1220 PM_CFG_SERDES_BUDS_RX_L1_ENB;
1221 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
1222 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1225 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
1226 PM_CFG_SERDES_PLL_L1_ENB);
1227 pmcfg |= PM_CFG_CLK_SWH_L1;
1228 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1229 pmcfg |= PM_CFG_ASPM_L1_ENB;
1231 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1235 alc_aspm_816x(struct alc_softc *sc, int init)
1239 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1240 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
1241 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
1242 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1243 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
1244 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
1245 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
1246 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
1247 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
1248 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB |
1249 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
1250 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB |
1251 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST);
1252 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1253 (sc->alc_rev & 0x01) != 0)
1254 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
1255 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1256 /* Link up, enable both L0s, L1s. */
1257 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1258 PM_CFG_MAC_ASPM_CHK;
1261 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1262 PM_CFG_MAC_ASPM_CHK;
1263 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1264 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
1266 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1270 alc_init_pcie(struct alc_softc *sc)
1272 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
1273 uint32_t cap, ctl, val;
1276 /* Clear data link and flow-control protocol error. */
1277 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1278 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
1279 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1281 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1282 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1283 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1284 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1285 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1286 PCIE_PHYMISC_FORCE_RCV_DET);
1287 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1288 sc->alc_rev == ATHEROS_AR8152_B_V10) {
1289 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1290 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
1291 PCIE_PHYMISC2_SERDES_TH_MASK);
1292 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
1293 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
1294 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1296 /* Disable ASPM L0S and L1. */
1297 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
1298 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1299 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
1300 if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
1301 sc->alc_rcb = DMA_CFG_RCB_128;
1303 device_printf(sc->alc_dev, "RCB %u bytes\n",
1304 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
1305 state = ctl & PCIEM_LINK_CTL_ASPMC;
1306 if (state & PCIEM_LINK_CTL_ASPMC_L0S)
1307 sc->alc_flags |= ALC_FLAG_L0S;
1308 if (state & PCIEM_LINK_CTL_ASPMC_L1)
1309 sc->alc_flags |= ALC_FLAG_L1S;
1311 device_printf(sc->alc_dev, "ASPM %s %s\n",
1313 state == 0 ? "disabled" : "enabled");
1314 alc_disable_l0s_l1(sc);
1317 device_printf(sc->alc_dev,
1318 "no ASPM support\n");
1321 val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1322 val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
1323 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1324 val = CSR_READ_4(sc, ALC_MASTER_CFG);
1325 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1326 (sc->alc_rev & 0x01) != 0) {
1327 if ((val & MASTER_WAKEN_25M) == 0 ||
1328 (val & MASTER_CLK_SEL_DIS) == 0) {
1329 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
1330 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1333 if ((val & MASTER_WAKEN_25M) == 0 ||
1334 (val & MASTER_CLK_SEL_DIS) != 0) {
1335 val |= MASTER_WAKEN_25M;
1336 val &= ~MASTER_CLK_SEL_DIS;
1337 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1341 alc_aspm(sc, 1, IFM_UNKNOWN);
1345 alc_config_msi(struct alc_softc *sc)
1349 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
1351 * It seems interrupt moderation is controlled by
1352 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active.
1353 * Driver uses RX interrupt moderation parameter to
1354 * program ALC_MSI_RETRANS_TIMER register.
1356 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
1357 ctl &= ~MSI_RETRANS_TIMER_MASK;
1358 ctl &= ~MSI_RETRANS_MASK_SEL_LINE;
1359 mod = ALC_USECS(sc->alc_int_rx_mod);
1363 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1364 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1365 MSI_RETRANS_MASK_SEL_STD);
1366 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1367 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1368 MSI_RETRANS_MASK_SEL_LINE);
1370 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
1375 alc_attach(device_t dev)
1377 struct alc_softc *sc;
1379 int base, error, i, msic, msixc;
1383 sc = device_get_softc(dev);
1385 sc->alc_rev = pci_get_revid(dev);
1387 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1389 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
1390 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
1391 sc->alc_ident = alc_find_ident(dev);
1393 /* Map the device. */
1394 pci_enable_busmaster(dev);
1395 sc->alc_res_spec = alc_res_spec_mem;
1396 sc->alc_irq_spec = alc_irq_spec_legacy;
1397 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
1399 device_printf(dev, "cannot allocate memory resources.\n");
1403 /* Set PHY address. */
1404 sc->alc_phyaddr = ALC_PHY_ADDR;
1407 * One odd thing is AR8132 uses the same PHY hardware(F1
1408 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
1409 * the PHY supports 1000Mbps but that's not true. The PHY
1410 * used in AR8132 can't establish gigabit link even if it
1411 * shows the same PHY model/revision number of AR8131.
1413 switch (sc->alc_ident->deviceid) {
1414 case DEVICEID_ATHEROS_E2200:
1415 case DEVICEID_ATHEROS_E2400:
1416 case DEVICEID_ATHEROS_E2500:
1417 sc->alc_flags |= ALC_FLAG_E2X00;
1419 case DEVICEID_ATHEROS_AR8161:
1420 if (pci_get_subvendor(dev) == VENDORID_ATHEROS &&
1421 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0)
1422 sc->alc_flags |= ALC_FLAG_LINK_WAR;
1424 case DEVICEID_ATHEROS_AR8171:
1425 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
1427 case DEVICEID_ATHEROS_AR8162:
1428 case DEVICEID_ATHEROS_AR8172:
1429 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
1431 case DEVICEID_ATHEROS_AR8152_B:
1432 case DEVICEID_ATHEROS_AR8152_B2:
1433 sc->alc_flags |= ALC_FLAG_APS;
1435 case DEVICEID_ATHEROS_AR8132:
1436 sc->alc_flags |= ALC_FLAG_FASTETHER;
1438 case DEVICEID_ATHEROS_AR8151:
1439 case DEVICEID_ATHEROS_AR8151_V2:
1440 sc->alc_flags |= ALC_FLAG_APS;
1441 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC)
1442 sc->alc_flags |= ALC_FLAG_MT;
1447 sc->alc_flags |= ALC_FLAG_JUMBO;
1450 * It seems that AR813x/AR815x has silicon bug for SMB. In
1451 * addition, Atheros said that enabling SMB wouldn't improve
1452 * performance. However I think it's bad to access lots of
1453 * registers to extract MAC statistics.
1455 sc->alc_flags |= ALC_FLAG_SMB_BUG;
1457 * Don't use Tx CMB. It is known to have silicon bug.
1459 sc->alc_flags |= ALC_FLAG_CMB_BUG;
1460 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1461 MASTER_CHIP_REV_SHIFT;
1463 device_printf(dev, "PCI device revision : 0x%04x\n",
1465 device_printf(dev, "Chip id/revision : 0x%04x\n",
1467 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1468 device_printf(dev, "AR816x revision : 0x%x\n",
1469 AR816X_REV(sc->alc_rev));
1471 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
1472 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1473 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
1475 /* Initialize DMA parameters. */
1476 sc->alc_dma_rd_burst = 0;
1477 sc->alc_dma_wr_burst = 0;
1478 sc->alc_rcb = DMA_CFG_RCB_64;
1479 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
1480 sc->alc_flags |= ALC_FLAG_PCIE;
1481 sc->alc_expcap = base;
1482 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
1483 sc->alc_dma_rd_burst =
1484 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
1485 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5;
1487 device_printf(dev, "Read request size : %u bytes.\n",
1488 alc_dma_burst[sc->alc_dma_rd_burst]);
1489 device_printf(dev, "TLP payload size : %u bytes.\n",
1490 alc_dma_burst[sc->alc_dma_wr_burst]);
1492 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
1493 sc->alc_dma_rd_burst = 3;
1494 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
1495 sc->alc_dma_wr_burst = 3;
1497 * Force maximum payload size to 128 bytes for
1498 * E2200/E2400/E2500.
1499 * Otherwise it triggers DMA write error.
1501 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0)
1502 sc->alc_dma_wr_burst = 0;
1509 /* Reset the ethernet controller. */
1513 /* Allocate IRQ resources. */
1514 msixc = pci_msix_count(dev);
1515 msic = pci_msi_count(dev);
1517 device_printf(dev, "MSIX count : %d\n", msixc);
1518 device_printf(dev, "MSI count : %d\n", msic);
1525 * Prefer MSIX over MSI.
1526 * AR816x controller has a silicon bug that MSI interrupt
1527 * does not assert if PCIM_CMD_INTxDIS bit of command
1528 * register is set. pci(4) was taught to handle that case.
1530 if (msix_disable == 0 || msi_disable == 0) {
1531 if (msix_disable == 0 && msixc > 0 &&
1532 pci_alloc_msix(dev, &msixc) == 0) {
1535 "Using %d MSIX message(s).\n", msixc);
1536 sc->alc_flags |= ALC_FLAG_MSIX;
1537 sc->alc_irq_spec = alc_irq_spec_msix;
1539 pci_release_msi(dev);
1541 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
1542 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
1545 "Using %d MSI message(s).\n", msic);
1546 sc->alc_flags |= ALC_FLAG_MSI;
1547 sc->alc_irq_spec = alc_irq_spec_msi;
1549 pci_release_msi(dev);
1553 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1555 device_printf(dev, "cannot allocate IRQ resources.\n");
1559 /* Create device sysctl node. */
1560 alc_sysctl_node(sc);
1562 if ((error = alc_dma_alloc(sc)) != 0)
1565 /* Load station address. */
1566 alc_get_macaddr(sc);
1568 ifp = sc->alc_ifp = if_alloc(IFT_ETHER);
1570 device_printf(dev, "cannot allocate ifnet structure.\n");
1576 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1577 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1578 ifp->if_ioctl = alc_ioctl;
1579 ifp->if_start = alc_start;
1580 ifp->if_init = alc_init;
1581 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1;
1582 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1583 IFQ_SET_READY(&ifp->if_snd);
1584 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1585 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
1586 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) {
1587 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
1588 sc->alc_flags |= ALC_FLAG_PM;
1589 sc->alc_pmcap = base;
1591 ifp->if_capenable = ifp->if_capabilities;
1593 /* Set up MII bus. */
1594 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange,
1595 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY,
1598 device_printf(dev, "attaching PHYs failed\n");
1602 ether_ifattach(ifp, sc->alc_eaddr);
1604 /* VLAN capability setup. */
1605 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
1606 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
1607 ifp->if_capenable = ifp->if_capabilities;
1610 * It seems enabling Tx checksum offloading makes more trouble.
1611 * Sometimes the controller does not receive any frames when
1612 * Tx checksum offloading is enabled. I'm not sure whether this
1613 * is a bug in Tx checksum offloading logic or I got broken
1614 * sample boards. To safety, don't enable Tx checksum offloading
1615 * by default but give chance to users to toggle it if they know
1616 * their controllers work without problems.
1617 * Fortunately, Tx checksum offloading for AR816x family
1620 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1621 ifp->if_capenable &= ~IFCAP_TXCSUM;
1622 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
1625 /* Tell the upper layer(s) we support long frames. */
1626 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1628 /* Create local taskq. */
1629 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK,
1630 taskqueue_thread_enqueue, &sc->alc_tq);
1631 if (sc->alc_tq == NULL) {
1632 device_printf(dev, "could not create taskqueue.\n");
1633 ether_ifdetach(ifp);
1637 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq",
1638 device_get_nameunit(sc->alc_dev));
1641 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1642 msic = ALC_MSIX_MESSAGES;
1643 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1644 msic = ALC_MSI_MESSAGES;
1647 for (i = 0; i < msic; i++) {
1648 error = bus_setup_intr(dev, sc->alc_irq[i],
1649 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc,
1650 &sc->alc_intrhand[i]);
1655 device_printf(dev, "could not set up interrupt handler.\n");
1656 taskqueue_free(sc->alc_tq);
1658 ether_ifdetach(ifp);
1662 /* Attach driver debugnet methods. */
1663 DEBUGNET_SET(ifp, alc);
1673 alc_detach(device_t dev)
1675 struct alc_softc *sc;
1679 sc = device_get_softc(dev);
1682 if (device_is_attached(dev)) {
1683 ether_ifdetach(ifp);
1687 callout_drain(&sc->alc_tick_ch);
1688 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1691 if (sc->alc_tq != NULL) {
1692 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1693 taskqueue_free(sc->alc_tq);
1697 if (sc->alc_miibus != NULL) {
1698 device_delete_child(dev, sc->alc_miibus);
1699 sc->alc_miibus = NULL;
1701 bus_generic_detach(dev);
1709 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1710 msic = ALC_MSIX_MESSAGES;
1711 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1712 msic = ALC_MSI_MESSAGES;
1715 for (i = 0; i < msic; i++) {
1716 if (sc->alc_intrhand[i] != NULL) {
1717 bus_teardown_intr(dev, sc->alc_irq[i],
1718 sc->alc_intrhand[i]);
1719 sc->alc_intrhand[i] = NULL;
1722 if (sc->alc_res[0] != NULL)
1724 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1725 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
1726 pci_release_msi(dev);
1727 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
1728 mtx_destroy(&sc->alc_mtx);
1733 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
1734 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1735 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
1736 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
1739 alc_sysctl_node(struct alc_softc *sc)
1741 struct sysctl_ctx_list *ctx;
1742 struct sysctl_oid_list *child, *parent;
1743 struct sysctl_oid *tree;
1744 struct alc_hw_stats *stats;
1747 stats = &sc->alc_stats;
1748 ctx = device_get_sysctl_ctx(sc->alc_dev);
1749 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev));
1751 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
1752 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod,
1753 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1754 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
1755 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod,
1756 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1757 /* Pull in device tunables. */
1758 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1759 error = resource_int_value(device_get_name(sc->alc_dev),
1760 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
1762 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
1763 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
1764 device_printf(sc->alc_dev, "int_rx_mod value out of "
1765 "range; using default: %d\n",
1766 ALC_IM_RX_TIMER_DEFAULT);
1767 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1770 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1771 error = resource_int_value(device_get_name(sc->alc_dev),
1772 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
1774 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
1775 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
1776 device_printf(sc->alc_dev, "int_tx_mod value out of "
1777 "range; using default: %d\n",
1778 ALC_IM_TX_TIMER_DEFAULT);
1779 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1782 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1783 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
1784 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I",
1785 "max number of Rx events to process");
1786 /* Pull in device tunables. */
1787 sc->alc_process_limit = ALC_PROC_DEFAULT;
1788 error = resource_int_value(device_get_name(sc->alc_dev),
1789 device_get_unit(sc->alc_dev), "process_limit",
1790 &sc->alc_process_limit);
1792 if (sc->alc_process_limit < ALC_PROC_MIN ||
1793 sc->alc_process_limit > ALC_PROC_MAX) {
1794 device_printf(sc->alc_dev,
1795 "process_limit value out of range; "
1796 "using default: %d\n", ALC_PROC_DEFAULT);
1797 sc->alc_process_limit = ALC_PROC_DEFAULT;
1801 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
1802 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics");
1803 parent = SYSCTL_CHILDREN(tree);
1805 /* Rx statistics. */
1806 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
1807 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
1808 child = SYSCTL_CHILDREN(tree);
1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1810 &stats->rx_frames, "Good frames");
1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1812 &stats->rx_bcast_frames, "Good broadcast frames");
1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1814 &stats->rx_mcast_frames, "Good multicast frames");
1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1816 &stats->rx_pause_frames, "Pause control frames");
1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1818 &stats->rx_control_frames, "Control frames");
1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1820 &stats->rx_crcerrs, "CRC errors");
1821 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1822 &stats->rx_lenerrs, "Frames with length mismatched");
1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1824 &stats->rx_bytes, "Good octets");
1825 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1826 &stats->rx_bcast_bytes, "Good broadcast octets");
1827 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1828 &stats->rx_mcast_bytes, "Good multicast octets");
1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
1830 &stats->rx_runts, "Too short frames");
1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
1832 &stats->rx_fragments, "Fragmented frames");
1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1834 &stats->rx_pkts_64, "64 bytes frames");
1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1836 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1838 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1840 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1842 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1844 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1846 &stats->rx_pkts_1519_max, "1519 to max frames");
1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1848 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1850 &stats->rx_fifo_oflows, "FIFO overflows");
1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1852 &stats->rx_rrs_errs, "Return status write-back errors");
1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1854 &stats->rx_alignerrs, "Alignment errors");
1855 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1856 &stats->rx_pkts_filtered,
1857 "Frames dropped due to address filtering");
1859 /* Tx statistics. */
1860 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
1861 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
1862 child = SYSCTL_CHILDREN(tree);
1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1864 &stats->tx_frames, "Good frames");
1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1866 &stats->tx_bcast_frames, "Good broadcast frames");
1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1868 &stats->tx_mcast_frames, "Good multicast frames");
1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1870 &stats->tx_pause_frames, "Pause control frames");
1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1872 &stats->tx_control_frames, "Control frames");
1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1874 &stats->tx_excess_defer, "Frames with excessive derferrals");
1875 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1876 &stats->tx_excess_defer, "Frames with derferrals");
1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1878 &stats->tx_bytes, "Good octets");
1879 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1880 &stats->tx_bcast_bytes, "Good broadcast octets");
1881 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1882 &stats->tx_mcast_bytes, "Good multicast octets");
1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1884 &stats->tx_pkts_64, "64 bytes frames");
1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1886 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1888 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1890 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1892 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1894 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1896 &stats->tx_pkts_1519_max, "1519 to max frames");
1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1898 &stats->tx_single_colls, "Single collisions");
1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1900 &stats->tx_multi_colls, "Multiple collisions");
1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1902 &stats->tx_late_colls, "Late collisions");
1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1904 &stats->tx_excess_colls, "Excessive collisions");
1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1906 &stats->tx_underrun, "FIFO underruns");
1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1908 &stats->tx_desc_underrun, "Descriptor write-back errors");
1909 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1910 &stats->tx_lenerrs, "Frames with length mismatched");
1911 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1912 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1915 #undef ALC_SYSCTL_STAT_ADD32
1916 #undef ALC_SYSCTL_STAT_ADD64
1918 struct alc_dmamap_arg {
1919 bus_addr_t alc_busaddr;
1923 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1925 struct alc_dmamap_arg *ctx;
1930 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1932 ctx = (struct alc_dmamap_arg *)arg;
1933 ctx->alc_busaddr = segs[0].ds_addr;
1937 * Normal and high Tx descriptors shares single Tx high address.
1938 * Four Rx descriptor/return rings and CMB shares the same Rx
1942 alc_check_boundary(struct alc_softc *sc)
1944 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1946 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1947 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1948 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1949 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1951 /* 4GB boundary crossing is not allowed. */
1952 if ((ALC_ADDR_HI(rx_ring_end) !=
1953 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1954 (ALC_ADDR_HI(rr_ring_end) !=
1955 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1956 (ALC_ADDR_HI(cmb_end) !=
1957 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1958 (ALC_ADDR_HI(tx_ring_end) !=
1959 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1962 * Make sure Rx return descriptor/Rx descriptor/CMB use
1963 * the same high address.
1965 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1966 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1973 alc_dma_alloc(struct alc_softc *sc)
1975 struct alc_txdesc *txd;
1976 struct alc_rxdesc *rxd;
1978 struct alc_dmamap_arg ctx;
1981 lowaddr = BUS_SPACE_MAXADDR;
1982 if (sc->alc_flags & ALC_FLAG_MT)
1983 lowaddr = BUS_SPACE_MAXSIZE_32BIT;
1985 /* Create parent DMA tag. */
1986 error = bus_dma_tag_create(
1987 bus_get_dma_tag(sc->alc_dev), /* parent */
1988 1, 0, /* alignment, boundary */
1989 lowaddr, /* lowaddr */
1990 BUS_SPACE_MAXADDR, /* highaddr */
1991 NULL, NULL, /* filter, filterarg */
1992 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1994 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1996 NULL, NULL, /* lockfunc, lockarg */
1997 &sc->alc_cdata.alc_parent_tag);
1999 device_printf(sc->alc_dev,
2000 "could not create parent DMA tag.\n");
2004 /* Create DMA tag for Tx descriptor ring. */
2005 error = bus_dma_tag_create(
2006 sc->alc_cdata.alc_parent_tag, /* parent */
2007 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
2008 BUS_SPACE_MAXADDR, /* lowaddr */
2009 BUS_SPACE_MAXADDR, /* highaddr */
2010 NULL, NULL, /* filter, filterarg */
2011 ALC_TX_RING_SZ, /* maxsize */
2013 ALC_TX_RING_SZ, /* maxsegsize */
2015 NULL, NULL, /* lockfunc, lockarg */
2016 &sc->alc_cdata.alc_tx_ring_tag);
2018 device_printf(sc->alc_dev,
2019 "could not create Tx ring DMA tag.\n");
2023 /* Create DMA tag for Rx free descriptor ring. */
2024 error = bus_dma_tag_create(
2025 sc->alc_cdata.alc_parent_tag, /* parent */
2026 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
2027 BUS_SPACE_MAXADDR, /* lowaddr */
2028 BUS_SPACE_MAXADDR, /* highaddr */
2029 NULL, NULL, /* filter, filterarg */
2030 ALC_RX_RING_SZ, /* maxsize */
2032 ALC_RX_RING_SZ, /* maxsegsize */
2034 NULL, NULL, /* lockfunc, lockarg */
2035 &sc->alc_cdata.alc_rx_ring_tag);
2037 device_printf(sc->alc_dev,
2038 "could not create Rx ring DMA tag.\n");
2041 /* Create DMA tag for Rx return descriptor ring. */
2042 error = bus_dma_tag_create(
2043 sc->alc_cdata.alc_parent_tag, /* parent */
2044 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
2045 BUS_SPACE_MAXADDR, /* lowaddr */
2046 BUS_SPACE_MAXADDR, /* highaddr */
2047 NULL, NULL, /* filter, filterarg */
2048 ALC_RR_RING_SZ, /* maxsize */
2050 ALC_RR_RING_SZ, /* maxsegsize */
2052 NULL, NULL, /* lockfunc, lockarg */
2053 &sc->alc_cdata.alc_rr_ring_tag);
2055 device_printf(sc->alc_dev,
2056 "could not create Rx return ring DMA tag.\n");
2060 /* Create DMA tag for coalescing message block. */
2061 error = bus_dma_tag_create(
2062 sc->alc_cdata.alc_parent_tag, /* parent */
2063 ALC_CMB_ALIGN, 0, /* alignment, boundary */
2064 BUS_SPACE_MAXADDR, /* lowaddr */
2065 BUS_SPACE_MAXADDR, /* highaddr */
2066 NULL, NULL, /* filter, filterarg */
2067 ALC_CMB_SZ, /* maxsize */
2069 ALC_CMB_SZ, /* maxsegsize */
2071 NULL, NULL, /* lockfunc, lockarg */
2072 &sc->alc_cdata.alc_cmb_tag);
2074 device_printf(sc->alc_dev,
2075 "could not create CMB DMA tag.\n");
2078 /* Create DMA tag for status message block. */
2079 error = bus_dma_tag_create(
2080 sc->alc_cdata.alc_parent_tag, /* parent */
2081 ALC_SMB_ALIGN, 0, /* alignment, boundary */
2082 BUS_SPACE_MAXADDR, /* lowaddr */
2083 BUS_SPACE_MAXADDR, /* highaddr */
2084 NULL, NULL, /* filter, filterarg */
2085 ALC_SMB_SZ, /* maxsize */
2087 ALC_SMB_SZ, /* maxsegsize */
2089 NULL, NULL, /* lockfunc, lockarg */
2090 &sc->alc_cdata.alc_smb_tag);
2092 device_printf(sc->alc_dev,
2093 "could not create SMB DMA tag.\n");
2097 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2098 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
2099 (void **)&sc->alc_rdata.alc_tx_ring,
2100 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2101 &sc->alc_cdata.alc_tx_ring_map);
2103 device_printf(sc->alc_dev,
2104 "could not allocate DMA'able memory for Tx ring.\n");
2107 ctx.alc_busaddr = 0;
2108 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
2109 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
2110 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2111 if (error != 0 || ctx.alc_busaddr == 0) {
2112 device_printf(sc->alc_dev,
2113 "could not load DMA'able memory for Tx ring.\n");
2116 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
2118 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2119 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
2120 (void **)&sc->alc_rdata.alc_rx_ring,
2121 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2122 &sc->alc_cdata.alc_rx_ring_map);
2124 device_printf(sc->alc_dev,
2125 "could not allocate DMA'able memory for Rx ring.\n");
2128 ctx.alc_busaddr = 0;
2129 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
2130 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
2131 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2132 if (error != 0 || ctx.alc_busaddr == 0) {
2133 device_printf(sc->alc_dev,
2134 "could not load DMA'able memory for Rx ring.\n");
2137 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
2139 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
2140 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
2141 (void **)&sc->alc_rdata.alc_rr_ring,
2142 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2143 &sc->alc_cdata.alc_rr_ring_map);
2145 device_printf(sc->alc_dev,
2146 "could not allocate DMA'able memory for Rx return ring.\n");
2149 ctx.alc_busaddr = 0;
2150 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
2151 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
2152 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
2153 if (error != 0 || ctx.alc_busaddr == 0) {
2154 device_printf(sc->alc_dev,
2155 "could not load DMA'able memory for Tx ring.\n");
2158 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
2160 /* Allocate DMA'able memory and load the DMA map for CMB. */
2161 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
2162 (void **)&sc->alc_rdata.alc_cmb,
2163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2164 &sc->alc_cdata.alc_cmb_map);
2166 device_printf(sc->alc_dev,
2167 "could not allocate DMA'able memory for CMB.\n");
2170 ctx.alc_busaddr = 0;
2171 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
2172 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
2173 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
2174 if (error != 0 || ctx.alc_busaddr == 0) {
2175 device_printf(sc->alc_dev,
2176 "could not load DMA'able memory for CMB.\n");
2179 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
2181 /* Allocate DMA'able memory and load the DMA map for SMB. */
2182 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
2183 (void **)&sc->alc_rdata.alc_smb,
2184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2185 &sc->alc_cdata.alc_smb_map);
2187 device_printf(sc->alc_dev,
2188 "could not allocate DMA'able memory for SMB.\n");
2191 ctx.alc_busaddr = 0;
2192 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
2193 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
2194 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
2195 if (error != 0 || ctx.alc_busaddr == 0) {
2196 device_printf(sc->alc_dev,
2197 "could not load DMA'able memory for CMB.\n");
2200 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
2202 /* Make sure we've not crossed 4GB boundary. */
2203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
2204 (error = alc_check_boundary(sc)) != 0) {
2205 device_printf(sc->alc_dev, "4GB boundary crossed, "
2206 "switching to 32bit DMA addressing mode.\n");
2209 * Limit max allowable DMA address space to 32bit
2212 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2217 * Create Tx buffer parent tag.
2218 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers
2219 * so it needs separate parent DMA tag as parent DMA address
2220 * space could be restricted to be within 32bit address space
2221 * by 4GB boundary crossing.
2223 error = bus_dma_tag_create(
2224 bus_get_dma_tag(sc->alc_dev), /* parent */
2225 1, 0, /* alignment, boundary */
2226 lowaddr, /* lowaddr */
2227 BUS_SPACE_MAXADDR, /* highaddr */
2228 NULL, NULL, /* filter, filterarg */
2229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2233 NULL, NULL, /* lockfunc, lockarg */
2234 &sc->alc_cdata.alc_buffer_tag);
2236 device_printf(sc->alc_dev,
2237 "could not create parent buffer DMA tag.\n");
2241 /* Create DMA tag for Tx buffers. */
2242 error = bus_dma_tag_create(
2243 sc->alc_cdata.alc_buffer_tag, /* parent */
2244 1, 0, /* alignment, boundary */
2245 BUS_SPACE_MAXADDR, /* lowaddr */
2246 BUS_SPACE_MAXADDR, /* highaddr */
2247 NULL, NULL, /* filter, filterarg */
2248 ALC_TSO_MAXSIZE, /* maxsize */
2249 ALC_MAXTXSEGS, /* nsegments */
2250 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
2252 NULL, NULL, /* lockfunc, lockarg */
2253 &sc->alc_cdata.alc_tx_tag);
2255 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
2259 /* Create DMA tag for Rx buffers. */
2260 error = bus_dma_tag_create(
2261 sc->alc_cdata.alc_buffer_tag, /* parent */
2262 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
2263 BUS_SPACE_MAXADDR, /* lowaddr */
2264 BUS_SPACE_MAXADDR, /* highaddr */
2265 NULL, NULL, /* filter, filterarg */
2266 MCLBYTES, /* maxsize */
2268 MCLBYTES, /* maxsegsize */
2270 NULL, NULL, /* lockfunc, lockarg */
2271 &sc->alc_cdata.alc_rx_tag);
2273 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
2276 /* Create DMA maps for Tx buffers. */
2277 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2278 txd = &sc->alc_cdata.alc_txdesc[i];
2280 txd->tx_dmamap = NULL;
2281 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
2284 device_printf(sc->alc_dev,
2285 "could not create Tx dmamap.\n");
2289 /* Create DMA maps for Rx buffers. */
2290 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2291 &sc->alc_cdata.alc_rx_sparemap)) != 0) {
2292 device_printf(sc->alc_dev,
2293 "could not create spare Rx dmamap.\n");
2296 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2297 rxd = &sc->alc_cdata.alc_rxdesc[i];
2299 rxd->rx_dmamap = NULL;
2300 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2303 device_printf(sc->alc_dev,
2304 "could not create Rx dmamap.\n");
2314 alc_dma_free(struct alc_softc *sc)
2316 struct alc_txdesc *txd;
2317 struct alc_rxdesc *rxd;
2321 if (sc->alc_cdata.alc_tx_tag != NULL) {
2322 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2323 txd = &sc->alc_cdata.alc_txdesc[i];
2324 if (txd->tx_dmamap != NULL) {
2325 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
2327 txd->tx_dmamap = NULL;
2330 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
2331 sc->alc_cdata.alc_tx_tag = NULL;
2334 if (sc->alc_cdata.alc_rx_tag != NULL) {
2335 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2336 rxd = &sc->alc_cdata.alc_rxdesc[i];
2337 if (rxd->rx_dmamap != NULL) {
2338 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2340 rxd->rx_dmamap = NULL;
2343 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
2344 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2345 sc->alc_cdata.alc_rx_sparemap);
2346 sc->alc_cdata.alc_rx_sparemap = NULL;
2348 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
2349 sc->alc_cdata.alc_rx_tag = NULL;
2351 /* Tx descriptor ring. */
2352 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
2353 if (sc->alc_rdata.alc_tx_ring_paddr != 0)
2354 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
2355 sc->alc_cdata.alc_tx_ring_map);
2356 if (sc->alc_rdata.alc_tx_ring != NULL)
2357 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
2358 sc->alc_rdata.alc_tx_ring,
2359 sc->alc_cdata.alc_tx_ring_map);
2360 sc->alc_rdata.alc_tx_ring_paddr = 0;
2361 sc->alc_rdata.alc_tx_ring = NULL;
2362 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
2363 sc->alc_cdata.alc_tx_ring_tag = NULL;
2366 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
2367 if (sc->alc_rdata.alc_rx_ring_paddr != 0)
2368 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
2369 sc->alc_cdata.alc_rx_ring_map);
2370 if (sc->alc_rdata.alc_rx_ring != NULL)
2371 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
2372 sc->alc_rdata.alc_rx_ring,
2373 sc->alc_cdata.alc_rx_ring_map);
2374 sc->alc_rdata.alc_rx_ring_paddr = 0;
2375 sc->alc_rdata.alc_rx_ring = NULL;
2376 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
2377 sc->alc_cdata.alc_rx_ring_tag = NULL;
2379 /* Rx return ring. */
2380 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
2381 if (sc->alc_rdata.alc_rr_ring_paddr != 0)
2382 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
2383 sc->alc_cdata.alc_rr_ring_map);
2384 if (sc->alc_rdata.alc_rr_ring != NULL)
2385 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
2386 sc->alc_rdata.alc_rr_ring,
2387 sc->alc_cdata.alc_rr_ring_map);
2388 sc->alc_rdata.alc_rr_ring_paddr = 0;
2389 sc->alc_rdata.alc_rr_ring = NULL;
2390 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
2391 sc->alc_cdata.alc_rr_ring_tag = NULL;
2394 if (sc->alc_cdata.alc_cmb_tag != NULL) {
2395 if (sc->alc_rdata.alc_cmb_paddr != 0)
2396 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
2397 sc->alc_cdata.alc_cmb_map);
2398 if (sc->alc_rdata.alc_cmb != NULL)
2399 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
2400 sc->alc_rdata.alc_cmb,
2401 sc->alc_cdata.alc_cmb_map);
2402 sc->alc_rdata.alc_cmb_paddr = 0;
2403 sc->alc_rdata.alc_cmb = NULL;
2404 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
2405 sc->alc_cdata.alc_cmb_tag = NULL;
2408 if (sc->alc_cdata.alc_smb_tag != NULL) {
2409 if (sc->alc_rdata.alc_smb_paddr != 0)
2410 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
2411 sc->alc_cdata.alc_smb_map);
2412 if (sc->alc_rdata.alc_smb != NULL)
2413 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
2414 sc->alc_rdata.alc_smb,
2415 sc->alc_cdata.alc_smb_map);
2416 sc->alc_rdata.alc_smb_paddr = 0;
2417 sc->alc_rdata.alc_smb = NULL;
2418 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
2419 sc->alc_cdata.alc_smb_tag = NULL;
2421 if (sc->alc_cdata.alc_buffer_tag != NULL) {
2422 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
2423 sc->alc_cdata.alc_buffer_tag = NULL;
2425 if (sc->alc_cdata.alc_parent_tag != NULL) {
2426 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
2427 sc->alc_cdata.alc_parent_tag = NULL;
2432 alc_shutdown(device_t dev)
2435 return (alc_suspend(dev));
2439 * Note, this driver resets the link speed to 10/100Mbps by
2440 * restarting auto-negotiation in suspend/shutdown phase but we
2441 * don't know whether that auto-negotiation would succeed or not
2442 * as driver has no control after powering off/suspend operation.
2443 * If the renegotiation fail WOL may not work. Running at 1Gbps
2444 * will draw more power than 375mA at 3.3V which is specified in
2445 * PCI specification and that would result in complete
2446 * shutdowning power to ethernet controller.
2449 * Save current negotiated media speed/duplex/flow-control to
2450 * softc and restore the same link again after resuming. PHY
2451 * handling such as power down/resetting to 100Mbps may be better
2452 * handled in suspend method in phy driver.
2455 alc_setlinkspeed(struct alc_softc *sc)
2457 struct mii_data *mii;
2460 mii = device_get_softc(sc->alc_miibus);
2463 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2464 (IFM_ACTIVE | IFM_AVALID)) {
2465 switch IFM_SUBTYPE(mii->mii_media_active) {
2476 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2478 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
2479 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2480 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
2484 * Poll link state until alc(4) get a 10/100Mbps link.
2486 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
2488 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
2489 == (IFM_ACTIVE | IFM_AVALID)) {
2490 switch (IFM_SUBTYPE(
2491 mii->mii_media_active)) {
2501 pause("alclnk", hz);
2504 if (i == MII_ANEGTICKS_GIGE)
2505 device_printf(sc->alc_dev,
2506 "establishing a link failed, WOL may not work!");
2509 * No link, force MAC to have 100Mbps, full-duplex link.
2510 * This is the last resort and may/may not work.
2512 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
2513 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
2518 alc_setwol(struct alc_softc *sc)
2521 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2522 alc_setwol_816x(sc);
2524 alc_setwol_813x(sc);
2528 alc_setwol_813x(struct alc_softc *sc)
2534 ALC_LOCK_ASSERT(sc);
2536 alc_disable_l0s_l1(sc);
2538 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2540 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2541 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2542 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2543 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2544 /* Force PHY power down. */
2546 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2547 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2551 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2552 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2553 alc_setlinkspeed(sc);
2554 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2555 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
2559 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2560 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2561 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2562 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2563 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2565 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2566 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2567 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2568 reg |= MAC_CFG_RX_ENB;
2569 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2571 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2572 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2573 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2574 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
2575 /* WOL disabled, PHY power down. */
2577 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2578 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2581 pmstat = pci_read_config(sc->alc_dev,
2582 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2583 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2584 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2585 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2586 pci_write_config(sc->alc_dev,
2587 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2591 alc_setwol_816x(struct alc_softc *sc)
2594 uint32_t gphy, mac, master, pmcs, reg;
2597 ALC_LOCK_ASSERT(sc);
2600 master = CSR_READ_4(sc, ALC_MASTER_CFG);
2601 master &= ~MASTER_CLK_SEL_DIS;
2602 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
2603 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB |
2604 GPHY_CFG_PHY_PLL_ON);
2605 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET;
2606 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2607 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2608 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
2609 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2611 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2612 gphy |= GPHY_CFG_EXT_RESET;
2613 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2614 alc_setlinkspeed(sc);
2617 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2618 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2619 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2620 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2621 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2623 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2624 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2625 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2626 mac |= MAC_CFG_RX_ENB;
2627 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
2632 reg = CSR_READ_4(sc, ALC_MISC);
2633 reg &= ~MISC_INTNLOSC_OPEN;
2634 CSR_WRITE_4(sc, ALC_MISC, reg);
2635 reg |= MISC_INTNLOSC_OPEN;
2636 CSR_WRITE_4(sc, ALC_MISC, reg);
2637 CSR_WRITE_4(sc, ALC_MASTER_CFG, master);
2638 CSR_WRITE_4(sc, ALC_MAC_CFG, mac);
2639 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
2640 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);
2641 reg |= PDLL_TRNS1_D3PLLOFF_ENB;
2642 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg);
2644 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2646 pmstat = pci_read_config(sc->alc_dev,
2647 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2648 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2649 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2650 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2651 pci_write_config(sc->alc_dev,
2652 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2657 alc_suspend(device_t dev)
2659 struct alc_softc *sc;
2661 sc = device_get_softc(dev);
2672 alc_resume(device_t dev)
2674 struct alc_softc *sc;
2678 sc = device_get_softc(dev);
2681 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2682 /* Disable PME and clear PME status. */
2683 pmstat = pci_read_config(sc->alc_dev,
2684 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2685 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2686 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2687 pci_write_config(sc->alc_dev,
2688 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2694 if ((ifp->if_flags & IFF_UP) != 0) {
2695 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2696 alc_init_locked(sc);
2704 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
2706 struct alc_txdesc *txd, *txd_last;
2707 struct tx_desc *desc;
2711 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
2713 uint32_t cflags, hdrlen, ip_off, poff, vtag;
2714 int error, idx, nsegs, prod;
2716 ALC_LOCK_ASSERT(sc);
2718 M_ASSERTPKTHDR((*m_head));
2724 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
2726 * AR81[3567]x requires offset of TCP/UDP header in its
2727 * Tx descriptor to perform Tx checksum offloading. TSO
2728 * also requires TCP header offset and modification of
2729 * IP/TCP header. This kind of operation takes many CPU
2730 * cycles on FreeBSD so fast host CPU is required to get
2731 * smooth TSO performance.
2733 struct ether_header *eh;
2735 if (M_WRITABLE(m) == 0) {
2736 /* Get a writable copy. */
2737 m = m_dup(*m_head, M_NOWAIT);
2738 /* Release original mbufs. */
2747 ip_off = sizeof(struct ether_header);
2748 m = m_pullup(m, ip_off);
2753 eh = mtod(m, struct ether_header *);
2755 * Check if hardware VLAN insertion is off.
2756 * Additional check for LLC/SNAP frame?
2758 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2759 ip_off = sizeof(struct ether_vlan_header);
2760 m = m_pullup(m, ip_off);
2766 m = m_pullup(m, ip_off + sizeof(struct ip));
2771 ip = (struct ip *)(mtod(m, char *) + ip_off);
2772 poff = ip_off + (ip->ip_hl << 2);
2773 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2774 m = m_pullup(m, poff + sizeof(struct tcphdr));
2779 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2780 m = m_pullup(m, poff + (tcp->th_off << 2));
2786 * Due to strict adherence of Microsoft NDIS
2787 * Large Send specification, hardware expects
2788 * a pseudo TCP checksum inserted by upper
2789 * stack. Unfortunately the pseudo TCP
2790 * checksum that NDIS refers to does not include
2791 * TCP payload length so driver should recompute
2792 * the pseudo checksum here. Hopefully this
2793 * wouldn't be much burden on modern CPUs.
2795 * Reset IP checksum and recompute TCP pseudo
2796 * checksum as NDIS specification said.
2798 ip = (struct ip *)(mtod(m, char *) + ip_off);
2799 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2801 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
2802 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2807 prod = sc->alc_cdata.alc_tx_prod;
2808 txd = &sc->alc_cdata.alc_txdesc[prod];
2810 map = txd->tx_dmamap;
2812 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2813 *m_head, txsegs, &nsegs, 0);
2814 if (error == EFBIG) {
2815 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS);
2822 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2823 *m_head, txsegs, &nsegs, 0);
2829 } else if (error != 0)
2837 /* Check descriptor overrun. */
2838 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
2839 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
2842 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
2845 cflags = TD_ETHERNET;
2849 /* Configure VLAN hardware tag insertion. */
2850 if ((m->m_flags & M_VLANTAG) != 0) {
2851 vtag = htons(m->m_pkthdr.ether_vtag);
2852 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
2853 cflags |= TD_INS_VLAN_TAG;
2855 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2856 /* Request TSO and set MSS. */
2857 cflags |= TD_TSO | TD_TSO_DESCV1;
2858 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
2860 /* Set TCP header offset. */
2861 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
2862 TD_TCPHDR_OFFSET_MASK;
2864 * AR81[3567]x requires the first buffer should
2865 * only hold IP/TCP header data. Payload should
2866 * be handled in other descriptors.
2868 hdrlen = poff + (tcp->th_off << 2);
2869 desc = &sc->alc_rdata.alc_tx_ring[prod];
2870 desc->len = htole32(TX_BYTES(hdrlen | vtag));
2871 desc->flags = htole32(cflags);
2872 desc->addr = htole64(txsegs[0].ds_addr);
2873 sc->alc_cdata.alc_tx_cnt++;
2874 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2875 if (m->m_len - hdrlen > 0) {
2876 /* Handle remaining payload of the first fragment. */
2877 desc = &sc->alc_rdata.alc_tx_ring[prod];
2878 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2880 desc->flags = htole32(cflags);
2881 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2882 sc->alc_cdata.alc_tx_cnt++;
2883 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2885 /* Handle remaining fragments. */
2887 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2888 /* Configure Tx checksum offload. */
2889 #ifdef ALC_USE_CUSTOM_CSUM
2890 cflags |= TD_CUSTOM_CSUM;
2891 /* Set checksum start offset. */
2892 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
2893 TD_PLOAD_OFFSET_MASK;
2894 /* Set checksum insertion position of TCP/UDP. */
2895 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
2896 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
2898 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2899 cflags |= TD_IPCSUM;
2900 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2901 cflags |= TD_TCPCSUM;
2902 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2903 cflags |= TD_UDPCSUM;
2904 /* Set TCP/UDP header offset. */
2905 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
2906 TD_L4HDR_OFFSET_MASK;
2909 for (; idx < nsegs; idx++) {
2910 desc = &sc->alc_rdata.alc_tx_ring[prod];
2911 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2912 desc->flags = htole32(cflags);
2913 desc->addr = htole64(txsegs[idx].ds_addr);
2914 sc->alc_cdata.alc_tx_cnt++;
2915 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2917 /* Update producer index. */
2918 sc->alc_cdata.alc_tx_prod = prod;
2920 /* Finally set EOP on the last descriptor. */
2921 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2922 desc = &sc->alc_rdata.alc_tx_ring[prod];
2923 desc->flags |= htole32(TD_EOP);
2925 /* Swap dmamap of the first and the last. */
2926 txd = &sc->alc_cdata.alc_txdesc[prod];
2927 map = txd_last->tx_dmamap;
2928 txd_last->tx_dmamap = txd->tx_dmamap;
2929 txd->tx_dmamap = map;
2936 alc_start(struct ifnet *ifp)
2938 struct alc_softc *sc;
2942 alc_start_locked(ifp);
2947 alc_start_locked(struct ifnet *ifp)
2949 struct alc_softc *sc;
2950 struct mbuf *m_head;
2955 ALC_LOCK_ASSERT(sc);
2957 /* Reclaim transmitted frames. */
2958 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2961 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2962 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0)
2965 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
2966 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2970 * Pack the data into the transmit ring. If we
2971 * don't have room, set the OACTIVE flag and wait
2972 * for the NIC to drain the ring.
2974 if (alc_encap(sc, &m_head)) {
2977 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2978 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2984 * If there's a BPF listener, bounce a copy of this frame
2987 ETHER_BPF_MTAP(ifp, m_head);
2995 alc_start_tx(struct alc_softc *sc)
2998 /* Sync descriptors. */
2999 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3000 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
3001 /* Kick. Assume we're using normal Tx priority queue. */
3002 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3003 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
3004 (uint16_t)sc->alc_cdata.alc_tx_prod);
3006 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
3007 (sc->alc_cdata.alc_tx_prod <<
3008 MBOX_TD_PROD_LO_IDX_SHIFT) &
3009 MBOX_TD_PROD_LO_IDX_MASK);
3010 /* Set a timeout in case the chip goes out to lunch. */
3011 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
3015 alc_watchdog(struct alc_softc *sc)
3019 ALC_LOCK_ASSERT(sc);
3021 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
3025 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
3026 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
3027 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3028 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3029 alc_init_locked(sc);
3032 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
3033 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3034 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3035 alc_init_locked(sc);
3036 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3037 alc_start_locked(ifp);
3041 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3043 struct alc_softc *sc;
3045 struct mii_data *mii;
3049 ifr = (struct ifreq *)data;
3053 if (ifr->ifr_mtu < ETHERMIN ||
3054 ifr->ifr_mtu > (sc->alc_ident->max_framelen -
3055 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) ||
3056 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
3057 ifr->ifr_mtu > ETHERMTU))
3059 else if (ifp->if_mtu != ifr->ifr_mtu) {
3061 ifp->if_mtu = ifr->ifr_mtu;
3062 /* AR81[3567]x has 13 bits MSS field. */
3063 if (ifp->if_mtu > ALC_TSO_MTU &&
3064 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3065 ifp->if_capenable &= ~IFCAP_TSO4;
3066 ifp->if_hwassist &= ~CSUM_TSO;
3067 VLAN_CAPABILITIES(ifp);
3074 if ((ifp->if_flags & IFF_UP) != 0) {
3075 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3076 ((ifp->if_flags ^ sc->alc_if_flags) &
3077 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3080 alc_init_locked(sc);
3081 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3083 sc->alc_if_flags = ifp->if_flags;
3089 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3095 mii = device_get_softc(sc->alc_miibus);
3096 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
3100 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3101 if ((mask & IFCAP_TXCSUM) != 0 &&
3102 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3103 ifp->if_capenable ^= IFCAP_TXCSUM;
3104 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3105 ifp->if_hwassist |= ALC_CSUM_FEATURES;
3107 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
3109 if ((mask & IFCAP_TSO4) != 0 &&
3110 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3111 ifp->if_capenable ^= IFCAP_TSO4;
3112 if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
3113 /* AR81[3567]x has 13 bits MSS field. */
3114 if (ifp->if_mtu > ALC_TSO_MTU) {
3115 ifp->if_capenable &= ~IFCAP_TSO4;
3116 ifp->if_hwassist &= ~CSUM_TSO;
3118 ifp->if_hwassist |= CSUM_TSO;
3120 ifp->if_hwassist &= ~CSUM_TSO;
3122 if ((mask & IFCAP_WOL_MCAST) != 0 &&
3123 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
3124 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3125 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3126 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3127 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3128 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3129 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3130 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3133 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3134 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3135 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3136 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3137 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3138 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3139 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3140 ifp->if_capenable &=
3141 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
3143 VLAN_CAPABILITIES(ifp);
3146 error = ether_ioctl(ifp, cmd, data);
3154 alc_mac_config(struct alc_softc *sc)
3156 struct mii_data *mii;
3159 ALC_LOCK_ASSERT(sc);
3161 mii = device_get_softc(sc->alc_miibus);
3162 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3163 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
3164 MAC_CFG_SPEED_MASK);
3165 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3166 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
3167 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
3168 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
3169 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3170 /* Reprogram MAC with resolved speed/duplex. */
3171 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3174 reg |= MAC_CFG_SPEED_10_100;
3177 reg |= MAC_CFG_SPEED_1000;
3180 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
3181 reg |= MAC_CFG_FULL_DUPLEX;
3182 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
3183 reg |= MAC_CFG_TX_FC;
3184 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
3185 reg |= MAC_CFG_RX_FC;
3187 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3191 alc_stats_clear(struct alc_softc *sc)
3193 struct smb sb, *smb;
3197 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3198 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3199 sc->alc_cdata.alc_smb_map,
3200 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3201 smb = sc->alc_rdata.alc_smb;
3202 /* Update done, clear. */
3204 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3205 sc->alc_cdata.alc_smb_map,
3206 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3208 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3210 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3211 i += sizeof(uint32_t);
3213 /* Read Tx statistics. */
3214 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3216 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3217 i += sizeof(uint32_t);
3223 alc_stats_update(struct alc_softc *sc)
3225 struct alc_hw_stats *stat;
3226 struct smb sb, *smb;
3231 ALC_LOCK_ASSERT(sc);
3234 stat = &sc->alc_stats;
3235 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3236 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3237 sc->alc_cdata.alc_smb_map,
3238 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3239 smb = sc->alc_rdata.alc_smb;
3240 if (smb->updated == 0)
3244 /* Read Rx statistics. */
3245 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3247 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3248 i += sizeof(uint32_t);
3250 /* Read Tx statistics. */
3251 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3253 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3254 i += sizeof(uint32_t);
3259 stat->rx_frames += smb->rx_frames;
3260 stat->rx_bcast_frames += smb->rx_bcast_frames;
3261 stat->rx_mcast_frames += smb->rx_mcast_frames;
3262 stat->rx_pause_frames += smb->rx_pause_frames;
3263 stat->rx_control_frames += smb->rx_control_frames;
3264 stat->rx_crcerrs += smb->rx_crcerrs;
3265 stat->rx_lenerrs += smb->rx_lenerrs;
3266 stat->rx_bytes += smb->rx_bytes;
3267 stat->rx_runts += smb->rx_runts;
3268 stat->rx_fragments += smb->rx_fragments;
3269 stat->rx_pkts_64 += smb->rx_pkts_64;
3270 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
3271 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
3272 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
3273 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
3274 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
3275 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
3276 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
3277 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
3278 stat->rx_rrs_errs += smb->rx_rrs_errs;
3279 stat->rx_alignerrs += smb->rx_alignerrs;
3280 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
3281 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
3282 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
3285 stat->tx_frames += smb->tx_frames;
3286 stat->tx_bcast_frames += smb->tx_bcast_frames;
3287 stat->tx_mcast_frames += smb->tx_mcast_frames;
3288 stat->tx_pause_frames += smb->tx_pause_frames;
3289 stat->tx_excess_defer += smb->tx_excess_defer;
3290 stat->tx_control_frames += smb->tx_control_frames;
3291 stat->tx_deferred += smb->tx_deferred;
3292 stat->tx_bytes += smb->tx_bytes;
3293 stat->tx_pkts_64 += smb->tx_pkts_64;
3294 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
3295 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
3296 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
3297 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
3298 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
3299 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
3300 stat->tx_single_colls += smb->tx_single_colls;
3301 stat->tx_multi_colls += smb->tx_multi_colls;
3302 stat->tx_late_colls += smb->tx_late_colls;
3303 stat->tx_excess_colls += smb->tx_excess_colls;
3304 stat->tx_underrun += smb->tx_underrun;
3305 stat->tx_desc_underrun += smb->tx_desc_underrun;
3306 stat->tx_lenerrs += smb->tx_lenerrs;
3307 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
3308 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
3309 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
3311 /* Update counters in ifnet. */
3312 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
3314 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
3315 smb->tx_multi_colls * 2 + smb->tx_late_colls +
3316 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
3318 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
3319 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
3321 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
3323 if_inc_counter(ifp, IFCOUNTER_IERRORS,
3324 smb->rx_crcerrs + smb->rx_lenerrs +
3325 smb->rx_runts + smb->rx_pkts_truncated +
3326 smb->rx_fifo_oflows + smb->rx_rrs_errs +
3329 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3330 /* Update done, clear. */
3332 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3333 sc->alc_cdata.alc_smb_map,
3334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3341 struct alc_softc *sc;
3344 sc = (struct alc_softc *)arg;
3346 if (sc->alc_flags & ALC_FLAG_MT) {
3347 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3348 return (FILTER_HANDLED);
3351 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3352 if ((status & ALC_INTRS) == 0)
3353 return (FILTER_STRAY);
3354 /* Disable interrupts. */
3355 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
3356 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3358 return (FILTER_HANDLED);
3362 alc_int_task(void *arg, int pending)
3364 struct alc_softc *sc;
3369 sc = (struct alc_softc *)arg;
3372 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3374 if (sc->alc_morework != 0) {
3375 sc->alc_morework = 0;
3376 status |= INTR_RX_PKT;
3378 if ((status & ALC_INTRS) == 0)
3381 /* Acknowledge interrupts but still disable interrupts. */
3382 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
3385 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3386 if ((status & INTR_RX_PKT) != 0) {
3387 more = alc_rxintr(sc, sc->alc_process_limit);
3389 sc->alc_morework = 1;
3390 else if (more == EIO) {
3391 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3392 alc_init_locked(sc);
3397 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
3398 INTR_TXQ_TO_RST)) != 0) {
3399 if ((status & INTR_DMA_RD_TO_RST) != 0)
3400 device_printf(sc->alc_dev,
3401 "DMA read error! -- resetting\n");
3402 if ((status & INTR_DMA_WR_TO_RST) != 0)
3403 device_printf(sc->alc_dev,
3404 "DMA write error! -- resetting\n");
3405 if ((status & INTR_TXQ_TO_RST) != 0)
3406 device_printf(sc->alc_dev,
3407 "TxQ reset! -- resetting\n");
3408 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3409 alc_init_locked(sc);
3413 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3414 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3415 alc_start_locked(ifp);
3418 if (more == EAGAIN ||
3419 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
3421 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3426 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3427 /* Re-enable interrupts if we're running. */
3428 if (sc->alc_flags & ALC_FLAG_MT)
3429 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3431 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
3437 alc_txeof(struct alc_softc *sc)
3440 struct alc_txdesc *txd;
3441 uint32_t cons, prod;
3444 ALC_LOCK_ASSERT(sc);
3448 if (sc->alc_cdata.alc_tx_cnt == 0)
3450 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3451 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3452 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3453 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3454 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
3455 prod = sc->alc_rdata.alc_cmb->cons;
3457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3458 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
3460 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
3461 /* Assume we're using normal Tx priority queue. */
3462 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
3463 MBOX_TD_CONS_LO_IDX_SHIFT;
3466 cons = sc->alc_cdata.alc_tx_cons;
3468 * Go through our Tx list and free mbufs for those
3469 * frames which have been transmitted.
3471 for (prog = 0; cons != prod; prog++,
3472 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
3473 if (sc->alc_cdata.alc_tx_cnt <= 0)
3476 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3477 sc->alc_cdata.alc_tx_cnt--;
3478 txd = &sc->alc_cdata.alc_txdesc[cons];
3479 if (txd->tx_m != NULL) {
3480 /* Reclaim transmitted mbufs. */
3481 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3482 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3483 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3490 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3491 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3492 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
3493 sc->alc_cdata.alc_tx_cons = cons;
3495 * Unarm watchdog timer only when there is no pending
3496 * frames in Tx queue.
3498 if (sc->alc_cdata.alc_tx_cnt == 0)
3499 sc->alc_watchdog_timer = 0;
3503 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
3506 bus_dma_segment_t segs[1];
3510 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3513 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
3514 #ifndef __NO_STRICT_ALIGNMENT
3515 m_adj(m, sizeof(uint64_t));
3518 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag,
3519 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3523 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3525 if (rxd->rx_m != NULL) {
3526 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3527 BUS_DMASYNC_POSTREAD);
3528 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
3530 map = rxd->rx_dmamap;
3531 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
3532 sc->alc_cdata.alc_rx_sparemap = map;
3533 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3534 BUS_DMASYNC_PREREAD);
3536 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
3541 alc_rxintr(struct alc_softc *sc, int count)
3544 struct rx_rdesc *rrd;
3545 uint32_t nsegs, status;
3548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3549 sc->alc_cdata.alc_rr_ring_map,
3550 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3551 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3552 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
3553 rr_cons = sc->alc_cdata.alc_rr_cons;
3555 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) {
3558 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
3559 status = le32toh(rrd->status);
3560 if ((status & RRD_VALID) == 0)
3562 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
3564 /* This should not happen! */
3565 device_printf(sc->alc_dev,
3566 "unexpected segment count -- resetting\n");
3570 /* Clear Rx return status. */
3572 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
3573 sc->alc_cdata.alc_rx_cons += nsegs;
3574 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
3579 /* Update the consumer index. */
3580 sc->alc_cdata.alc_rr_cons = rr_cons;
3581 /* Sync Rx return descriptors. */
3582 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3583 sc->alc_cdata.alc_rr_ring_map,
3584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3586 * Sync updated Rx descriptors such that controller see
3587 * modified buffer addresses.
3589 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3590 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3592 * Let controller know availability of new Rx buffers.
3593 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
3594 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
3595 * only when Rx buffer pre-fetching is required. In
3596 * addition we already set ALC_RX_RD_FREE_THRESH to
3597 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
3598 * it still seems that pre-fetching needs more
3601 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3602 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
3603 (uint16_t)sc->alc_cdata.alc_rx_cons);
3605 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
3606 sc->alc_cdata.alc_rx_cons);
3609 return (count > 0 ? 0 : EAGAIN);
3612 #ifndef __NO_STRICT_ALIGNMENT
3613 static struct mbuf *
3614 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m)
3618 uint16_t *src, *dst;
3620 src = mtod(m, uint16_t *);
3623 if (m->m_next == NULL) {
3624 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3630 * Append a new mbuf to received mbuf chain and copy ethernet
3631 * header from the mbuf chain. This can save lots of CPU
3632 * cycles for jumbo frame.
3634 MGETHDR(n, M_NOWAIT, MT_DATA);
3636 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3640 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
3641 m->m_data += ETHER_HDR_LEN;
3642 m->m_len -= ETHER_HDR_LEN;
3643 n->m_len = ETHER_HDR_LEN;
3644 M_MOVE_PKTHDR(n, m);
3650 /* Receive a frame. */
3652 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
3654 struct alc_rxdesc *rxd;
3656 struct mbuf *mp, *m;
3657 uint32_t rdinfo, status, vtag;
3658 int count, nsegs, rx_cons;
3661 status = le32toh(rrd->status);
3662 rdinfo = le32toh(rrd->rdinfo);
3663 rx_cons = RRD_RD_IDX(rdinfo);
3664 nsegs = RRD_RD_CNT(rdinfo);
3666 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
3667 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
3669 * We want to pass the following frames to upper
3670 * layer regardless of error status of Rx return
3673 * o IP/TCP/UDP checksum is bad.
3674 * o frame length and protocol specific length
3677 * Force network stack compute checksum for
3680 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
3681 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
3682 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
3686 for (count = 0; count < nsegs; count++,
3687 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
3688 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
3690 /* Add a new receive buffer to the ring. */
3691 if (alc_newbuf(sc, rxd) != 0) {
3692 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3693 /* Reuse Rx buffers. */
3694 if (sc->alc_cdata.alc_rxhead != NULL)
3695 m_freem(sc->alc_cdata.alc_rxhead);
3700 * Assume we've received a full sized frame.
3701 * Actual size is fixed when we encounter the end of
3702 * multi-segmented frame.
3704 mp->m_len = sc->alc_buf_size;
3706 /* Chain received mbufs. */
3707 if (sc->alc_cdata.alc_rxhead == NULL) {
3708 sc->alc_cdata.alc_rxhead = mp;
3709 sc->alc_cdata.alc_rxtail = mp;
3711 mp->m_flags &= ~M_PKTHDR;
3712 sc->alc_cdata.alc_rxprev_tail =
3713 sc->alc_cdata.alc_rxtail;
3714 sc->alc_cdata.alc_rxtail->m_next = mp;
3715 sc->alc_cdata.alc_rxtail = mp;
3718 if (count == nsegs - 1) {
3719 /* Last desc. for this frame. */
3720 m = sc->alc_cdata.alc_rxhead;
3721 m->m_flags |= M_PKTHDR;
3723 * It seems that L1C/L2C controller has no way
3724 * to tell hardware to strip CRC bytes.
3727 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
3729 /* Set last mbuf size. */
3730 mp->m_len = sc->alc_cdata.alc_rxlen -
3731 (nsegs - 1) * sc->alc_buf_size;
3732 /* Remove the CRC bytes in chained mbufs. */
3733 if (mp->m_len <= ETHER_CRC_LEN) {
3734 sc->alc_cdata.alc_rxtail =
3735 sc->alc_cdata.alc_rxprev_tail;
3736 sc->alc_cdata.alc_rxtail->m_len -=
3737 (ETHER_CRC_LEN - mp->m_len);
3738 sc->alc_cdata.alc_rxtail->m_next = NULL;
3741 mp->m_len -= ETHER_CRC_LEN;
3744 m->m_len = m->m_pkthdr.len;
3745 m->m_pkthdr.rcvif = ifp;
3747 * Due to hardware bugs, Rx checksum offloading
3748 * was intentionally disabled.
3750 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
3751 (status & RRD_VLAN_TAG) != 0) {
3752 vtag = RRD_VLAN(le32toh(rrd->vtag));
3753 m->m_pkthdr.ether_vtag = ntohs(vtag);
3754 m->m_flags |= M_VLANTAG;
3756 #ifndef __NO_STRICT_ALIGNMENT
3757 m = alc_fixup_rx(ifp, m);
3763 (*ifp->if_input)(ifp, m);
3768 /* Reset mbuf chains. */
3769 ALC_RXCHAIN_RESET(sc);
3775 struct alc_softc *sc;
3776 struct mii_data *mii;
3778 sc = (struct alc_softc *)arg;
3780 ALC_LOCK_ASSERT(sc);
3782 mii = device_get_softc(sc->alc_miibus);
3784 alc_stats_update(sc);
3786 * alc(4) does not rely on Tx completion interrupts to reclaim
3787 * transferred buffers. Instead Tx completion interrupts are
3788 * used to hint for scheduling Tx task. So it's necessary to
3789 * release transmitted buffers by kicking Tx completion
3790 * handler. This limits the maximum reclamation delay to a hz.
3794 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3798 alc_osc_reset(struct alc_softc *sc)
3802 reg = CSR_READ_4(sc, ALC_MISC3);
3803 reg &= ~MISC3_25M_BY_SW;
3804 reg |= MISC3_25M_NOTO_INTNL;
3805 CSR_WRITE_4(sc, ALC_MISC3, reg);
3807 reg = CSR_READ_4(sc, ALC_MISC);
3808 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
3810 * Restore over-current protection default value.
3811 * This value could be reset by MAC reset.
3813 reg &= ~MISC_PSW_OCP_MASK;
3814 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
3815 reg &= ~MISC_INTNLOSC_OPEN;
3816 CSR_WRITE_4(sc, ALC_MISC, reg);
3817 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3818 reg = CSR_READ_4(sc, ALC_MISC2);
3819 reg &= ~MISC2_CALB_START;
3820 CSR_WRITE_4(sc, ALC_MISC2, reg);
3821 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
3824 reg &= ~MISC_INTNLOSC_OPEN;
3825 /* Disable isolate for revision A devices. */
3826 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3827 reg &= ~MISC_ISO_ENB;
3828 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3829 CSR_WRITE_4(sc, ALC_MISC, reg);
3836 alc_reset(struct alc_softc *sc)
3838 uint32_t pmcfg, reg;
3842 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3843 /* Reset workaround. */
3844 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
3845 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3846 (sc->alc_rev & 0x01) != 0) {
3847 /* Disable L0s/L1s before reset. */
3848 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
3849 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3851 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
3852 PM_CFG_ASPM_L1_ENB);
3853 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3857 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3858 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
3859 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3861 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3862 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3864 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
3868 device_printf(sc->alc_dev, "MAC reset timeout!\n");
3870 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3872 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
3876 device_printf(sc->alc_dev, "master reset timeout!\n");
3878 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3879 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3880 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
3881 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3886 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
3888 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3889 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3890 (sc->alc_rev & 0x01) != 0) {
3891 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3892 reg |= MASTER_CLK_SEL_DIS;
3893 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3894 /* Restore L0s/L1s config. */
3895 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3897 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3901 reg = CSR_READ_4(sc, ALC_MISC3);
3902 reg &= ~MISC3_25M_BY_SW;
3903 reg |= MISC3_25M_NOTO_INTNL;
3904 CSR_WRITE_4(sc, ALC_MISC3, reg);
3905 reg = CSR_READ_4(sc, ALC_MISC);
3906 reg &= ~MISC_INTNLOSC_OPEN;
3907 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3908 reg &= ~MISC_ISO_ENB;
3909 CSR_WRITE_4(sc, ALC_MISC, reg);
3912 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3913 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3914 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
3915 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
3916 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
3917 SERDES_PHY_CLK_SLOWDOWN);
3923 struct alc_softc *sc;
3925 sc = (struct alc_softc *)xsc;
3927 alc_init_locked(sc);
3932 alc_init_locked(struct alc_softc *sc)
3935 struct mii_data *mii;
3936 uint8_t eaddr[ETHER_ADDR_LEN];
3938 uint32_t reg, rxf_hi, rxf_lo;
3940 ALC_LOCK_ASSERT(sc);
3943 mii = device_get_softc(sc->alc_miibus);
3945 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3948 * Cancel any pending I/O.
3952 * Reset the chip to a known state.
3956 /* Initialize Rx descriptors. */
3957 if (alc_init_rx_ring(sc) != 0) {
3958 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
3962 alc_init_rr_ring(sc);
3963 alc_init_tx_ring(sc);
3967 /* Enable all clocks. */
3968 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3969 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
3970 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
3971 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
3972 CLK_GATING_RXMAC_ENB);
3973 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
3974 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
3975 IDLE_DECISN_TIMER_DEFAULT_1MS);
3977 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
3979 /* Reprogram the station address. */
3980 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3981 CSR_WRITE_4(sc, ALC_PAR0,
3982 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
3983 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
3985 * Clear WOL status and disable all WOL feature as WOL
3986 * would interfere Rx operation under normal environments.
3988 CSR_READ_4(sc, ALC_WOL_CFG);
3989 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
3990 /* Set Tx descriptor base addresses. */
3991 paddr = sc->alc_rdata.alc_tx_ring_paddr;
3992 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3993 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3994 /* We don't use high priority ring. */
3995 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
3996 /* Set Tx descriptor counter. */
3997 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
3998 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
3999 /* Set Rx descriptor base addresses. */
4000 paddr = sc->alc_rdata.alc_rx_ring_paddr;
4001 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
4002 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
4003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4004 /* We use one Rx ring. */
4005 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
4006 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
4007 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
4009 /* Set Rx descriptor counter. */
4010 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
4011 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
4014 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
4015 * if it do not fit the buffer size. Rx return descriptor holds
4016 * a counter that indicates how many fragments were made by the
4017 * hardware. The buffer size should be multiple of 8 bytes.
4018 * Since hardware has limit on the size of buffer size, always
4019 * use the maximum value.
4020 * For strict-alignment architectures make sure to reduce buffer
4021 * size by 8 bytes to make room for alignment fixup.
4023 #ifndef __NO_STRICT_ALIGNMENT
4024 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
4026 sc->alc_buf_size = RX_BUF_SIZE_MAX;
4028 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
4030 paddr = sc->alc_rdata.alc_rr_ring_paddr;
4031 /* Set Rx return descriptor base addresses. */
4032 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
4033 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4034 /* We use one Rx return ring. */
4035 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
4036 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
4037 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
4039 /* Set Rx return descriptor counter. */
4040 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
4041 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
4042 paddr = sc->alc_rdata.alc_cmb_paddr;
4043 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4044 paddr = sc->alc_rdata.alc_smb_paddr;
4045 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
4046 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4048 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
4049 /* Reconfigure SRAM - Vendor magic. */
4050 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
4051 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
4052 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
4053 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
4054 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
4055 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
4056 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
4057 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
4060 /* Tell hardware that we're ready to load DMA blocks. */
4061 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
4063 /* Configure interrupt moderation timer. */
4064 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
4065 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
4066 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
4067 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
4069 * We don't want to automatic interrupt clear as task queue
4070 * for the interrupt should know interrupt status.
4072 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
4073 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
4074 reg |= MASTER_SA_TIMER_ENB;
4075 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
4076 reg |= MASTER_IM_RX_TIMER_ENB;
4077 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
4078 ALC_USECS(sc->alc_int_tx_mod) != 0)
4079 reg |= MASTER_IM_TX_TIMER_ENB;
4080 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
4082 * Disable interrupt re-trigger timer. We don't want automatic
4083 * re-triggering of un-ACKed interrupts.
4085 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
4086 /* Configure CMB. */
4087 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4088 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
4089 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
4090 ALC_USECS(sc->alc_int_tx_mod));
4092 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
4093 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
4094 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
4096 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
4099 * Hardware can be configured to issue SMB interrupt based
4100 * on programmed interval. Since there is a callout that is
4101 * invoked for every hz in driver we use that instead of
4102 * relying on periodic SMB interrupt.
4104 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
4105 /* Clear MAC statistics. */
4106 alc_stats_clear(sc);
4109 * Always use maximum frame size that controller can support.
4110 * Otherwise received frames that has larger frame length
4111 * than alc(4) MTU would be silently dropped in hardware. This
4112 * would make path-MTU discovery hard as sender wouldn't get
4113 * any responses from receiver. alc(4) supports
4114 * multi-fragmented frames on Rx path so it has no issue on
4115 * assembling fragmented frames. Using maximum frame size also
4116 * removes the need to reinitialize hardware when interface
4117 * MTU configuration was changed.
4119 * Be conservative in what you do, be liberal in what you
4120 * accept from others - RFC 793.
4122 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
4124 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4125 /* Disable header split(?) */
4126 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
4128 /* Configure IPG/IFG parameters. */
4129 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
4130 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) &
4131 IPG_IFG_IPGT_MASK) |
4132 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) &
4133 IPG_IFG_MIFG_MASK) |
4134 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) &
4135 IPG_IFG_IPG1_MASK) |
4136 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) &
4137 IPG_IFG_IPG2_MASK));
4138 /* Set parameters for half-duplex media. */
4139 CSR_WRITE_4(sc, ALC_HDPX_CFG,
4140 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
4141 HDPX_CFG_LCOL_MASK) |
4142 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
4143 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
4144 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
4145 HDPX_CFG_ABEBT_MASK) |
4146 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
4147 HDPX_CFG_JAMIPG_MASK));
4151 * Set TSO/checksum offload threshold. For frames that is
4152 * larger than this threshold, hardware wouldn't do
4153 * TSO/checksum offloading.
4155 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
4156 TSO_OFFLOAD_THRESH_MASK;
4157 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
4158 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
4159 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
4160 /* Configure TxQ. */
4161 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
4162 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
4163 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
4164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4166 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
4167 TXQ_CFG_TD_BURST_MASK;
4168 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
4169 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
4170 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4171 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
4172 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT |
4173 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT |
4174 HQTD_CFG_BURST_ENB);
4175 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
4176 reg = WRR_PRI_RESTRICT_NONE;
4177 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
4178 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT |
4179 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT |
4180 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT);
4181 CSR_WRITE_4(sc, ALC_WRR, reg);
4183 /* Configure Rx free descriptor pre-fetching. */
4184 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
4185 ((RX_RD_FREE_THRESH_HI_DEFAULT <<
4186 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) |
4187 ((RX_RD_FREE_THRESH_LO_DEFAULT <<
4188 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK));
4192 * Configure flow control parameters.
4193 * XON : 80% of Rx FIFO
4194 * XOFF : 30% of Rx FIFO
4196 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4197 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4198 reg &= SRAM_RX_FIFO_LEN_MASK;
4201 reg -= RX_FIFO_PAUSE_816X_RSVD;
4203 reg -= RX_BUF_SIZE_MAX;
4205 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4206 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4207 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4208 (((RX_FIFO_PAUSE_816X_RSVD / 8) <<
4209 RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4210 RX_FIFO_PAUSE_THRESH_HI_MASK));
4211 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
4212 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
4213 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4214 rxf_hi = (reg * 8) / 10;
4215 rxf_lo = (reg * 3) / 10;
4216 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4217 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4218 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4219 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4220 RX_FIFO_PAUSE_THRESH_HI_MASK));
4223 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4224 /* Disable RSS until I understand L1C/L2C's RSS logic. */
4225 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
4226 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
4229 /* Configure RxQ. */
4230 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
4231 RXQ_CFG_RD_BURST_MASK;
4232 reg |= RXQ_CFG_RSS_MODE_DIS;
4233 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4234 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
4235 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
4236 RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
4237 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
4238 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4240 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
4241 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
4242 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4244 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4246 /* Configure DMA parameters. */
4247 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
4249 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
4250 reg |= DMA_CFG_CMB_ENB;
4251 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
4252 reg |= DMA_CFG_SMB_ENB;
4254 reg |= DMA_CFG_SMB_DIS;
4255 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
4256 DMA_CFG_RD_BURST_SHIFT;
4257 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
4258 DMA_CFG_WR_BURST_SHIFT;
4259 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
4260 DMA_CFG_RD_DELAY_CNT_MASK;
4261 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
4262 DMA_CFG_WR_DELAY_CNT_MASK;
4263 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4264 switch (AR816X_REV(sc->alc_rev)) {
4267 reg |= DMA_CFG_RD_CHNL_SEL_2;
4272 reg |= DMA_CFG_RD_CHNL_SEL_4;
4276 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4279 * Configure Tx/Rx MACs.
4280 * - Auto-padding for short frames.
4281 * - Enable CRC generation.
4282 * Actual reconfiguration of MAC for resolved speed/duplex
4283 * is followed after detection of link establishment.
4284 * AR813x/AR815x always does checksum computation regardless
4285 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
4286 * have bug in protocol field in Rx return structure so
4287 * these controllers can't handle fragmented frames. Disable
4288 * Rx checksum offloading until there is a newer controller
4289 * that has sane implementation.
4291 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
4292 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
4293 MAC_CFG_PREAMBLE_MASK);
4294 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
4295 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
4296 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
4297 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4298 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
4299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
4300 reg |= MAC_CFG_SPEED_10_100;
4302 reg |= MAC_CFG_SPEED_1000;
4303 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4305 /* Set up the receive filter. */
4309 /* Acknowledge all pending interrupts and clear it. */
4310 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
4311 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4312 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
4314 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4315 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4317 sc->alc_flags &= ~ALC_FLAG_LINK;
4318 /* Switch to the current media. */
4319 alc_mediachange_locked(sc);
4321 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
4325 alc_stop(struct alc_softc *sc)
4328 struct alc_txdesc *txd;
4329 struct alc_rxdesc *rxd;
4333 ALC_LOCK_ASSERT(sc);
4335 * Mark the interface down and cancel the watchdog timer.
4338 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4339 sc->alc_flags &= ~ALC_FLAG_LINK;
4340 callout_stop(&sc->alc_tick_ch);
4341 sc->alc_watchdog_timer = 0;
4342 alc_stats_update(sc);
4343 /* Disable interrupts. */
4344 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
4345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4347 reg = CSR_READ_4(sc, ALC_DMA_CFG);
4348 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
4349 reg |= DMA_CFG_SMB_DIS;
4350 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4352 /* Stop Rx/Tx MACs. */
4354 /* Disable interrupts which might be touched in taskq handler. */
4355 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4356 /* Disable L0s/L1s */
4357 alc_aspm(sc, 0, IFM_UNKNOWN);
4358 /* Reclaim Rx buffers that have been processed. */
4359 if (sc->alc_cdata.alc_rxhead != NULL)
4360 m_freem(sc->alc_cdata.alc_rxhead);
4361 ALC_RXCHAIN_RESET(sc);
4363 * Free Tx/Rx mbufs still in the queues.
4365 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4366 rxd = &sc->alc_cdata.alc_rxdesc[i];
4367 if (rxd->rx_m != NULL) {
4368 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
4369 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4370 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
4376 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4377 txd = &sc->alc_cdata.alc_txdesc[i];
4378 if (txd->tx_m != NULL) {
4379 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
4380 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4381 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
4390 alc_stop_mac(struct alc_softc *sc)
4396 /* Disable Rx/Tx MAC. */
4397 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4398 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
4399 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
4400 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4402 for (i = ALC_TIMEOUT; i > 0; i--) {
4403 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4404 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
4409 device_printf(sc->alc_dev,
4410 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
4414 alc_start_queue(struct alc_softc *sc)
4419 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
4420 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
4425 ALC_LOCK_ASSERT(sc);
4428 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
4429 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4430 cfg &= ~RXQ_CFG_ENB;
4433 cfg |= RXQ_CFG_QUEUE0_ENB;
4434 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
4436 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
4438 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
4442 alc_stop_queue(struct alc_softc *sc)
4448 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
4449 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4450 if ((reg & RXQ_CFG_ENB) != 0) {
4451 reg &= ~RXQ_CFG_ENB;
4452 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4455 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
4456 reg &= ~RXQ_CFG_QUEUE0_ENB;
4457 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4461 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
4462 if ((reg & TXQ_CFG_ENB) != 0) {
4463 reg &= ~TXQ_CFG_ENB;
4464 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
4467 for (i = ALC_TIMEOUT; i > 0; i--) {
4468 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4469 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
4474 device_printf(sc->alc_dev,
4475 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
4479 alc_init_tx_ring(struct alc_softc *sc)
4481 struct alc_ring_data *rd;
4482 struct alc_txdesc *txd;
4485 ALC_LOCK_ASSERT(sc);
4487 sc->alc_cdata.alc_tx_prod = 0;
4488 sc->alc_cdata.alc_tx_cons = 0;
4489 sc->alc_cdata.alc_tx_cnt = 0;
4491 rd = &sc->alc_rdata;
4492 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
4493 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4494 txd = &sc->alc_cdata.alc_txdesc[i];
4498 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
4499 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
4503 alc_init_rx_ring(struct alc_softc *sc)
4505 struct alc_ring_data *rd;
4506 struct alc_rxdesc *rxd;
4509 ALC_LOCK_ASSERT(sc);
4511 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
4512 sc->alc_morework = 0;
4513 rd = &sc->alc_rdata;
4514 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
4515 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4516 rxd = &sc->alc_cdata.alc_rxdesc[i];
4518 rxd->rx_desc = &rd->alc_rx_ring[i];
4519 if (alc_newbuf(sc, rxd) != 0)
4524 * Since controller does not update Rx descriptors, driver
4525 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
4526 * is enough to ensure coherence.
4528 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
4529 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
4530 /* Let controller know availability of new Rx buffers. */
4531 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
4537 alc_init_rr_ring(struct alc_softc *sc)
4539 struct alc_ring_data *rd;
4541 ALC_LOCK_ASSERT(sc);
4543 sc->alc_cdata.alc_rr_cons = 0;
4544 ALC_RXCHAIN_RESET(sc);
4546 rd = &sc->alc_rdata;
4547 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
4548 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
4549 sc->alc_cdata.alc_rr_ring_map,
4550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4554 alc_init_cmb(struct alc_softc *sc)
4556 struct alc_ring_data *rd;
4558 ALC_LOCK_ASSERT(sc);
4560 rd = &sc->alc_rdata;
4561 bzero(rd->alc_cmb, ALC_CMB_SZ);
4562 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
4563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4567 alc_init_smb(struct alc_softc *sc)
4569 struct alc_ring_data *rd;
4571 ALC_LOCK_ASSERT(sc);
4573 rd = &sc->alc_rdata;
4574 bzero(rd->alc_smb, ALC_SMB_SZ);
4575 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
4576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4580 alc_rxvlan(struct alc_softc *sc)
4585 ALC_LOCK_ASSERT(sc);
4588 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4589 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
4590 reg |= MAC_CFG_VLAN_TAG_STRIP;
4592 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
4593 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4597 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
4599 uint32_t *mchash = arg;
4602 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
4603 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
4609 alc_rxfilter(struct alc_softc *sc)
4615 ALC_LOCK_ASSERT(sc);
4619 bzero(mchash, sizeof(mchash));
4620 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
4621 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
4622 if ((ifp->if_flags & IFF_BROADCAST) != 0)
4623 rxcfg |= MAC_CFG_BCAST;
4624 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
4625 if ((ifp->if_flags & IFF_PROMISC) != 0)
4626 rxcfg |= MAC_CFG_PROMISC;
4627 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
4628 rxcfg |= MAC_CFG_ALLMULTI;
4629 mchash[0] = 0xFFFFFFFF;
4630 mchash[1] = 0xFFFFFFFF;
4634 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash);
4637 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
4638 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
4639 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
4643 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4649 value = *(int *)arg1;
4650 error = sysctl_handle_int(oidp, &value, 0, req);
4651 if (error || req->newptr == NULL)
4653 if (value < low || value > high)
4655 *(int *)arg1 = value;
4661 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
4663 return (sysctl_int_range(oidp, arg1, arg2, req,
4664 ALC_PROC_MIN, ALC_PROC_MAX));
4668 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
4671 return (sysctl_int_range(oidp, arg1, arg2, req,
4672 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
4677 alc_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
4679 struct alc_softc *sc;
4681 sc = if_getsoftc(ifp);
4682 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size"));
4684 *nrxr = ALC_RX_RING_CNT;
4685 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4690 alc_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused)
4695 alc_debugnet_transmit(struct ifnet *ifp, struct mbuf *m)
4697 struct alc_softc *sc;
4700 sc = if_getsoftc(ifp);
4701 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4705 error = alc_encap(sc, &m);
4712 alc_debugnet_poll(struct ifnet *ifp, int count)
4714 struct alc_softc *sc;
4716 sc = if_getsoftc(ifp);
4717 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4722 return (alc_rxintr(sc, count));
4724 #endif /* DEBUGNET */