2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/queue.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
53 #include <net/debugnet.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_llc.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/miivar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
75 #include <machine/bus.h>
76 #include <machine/in_cksum.h>
78 #include <dev/alc/if_alcreg.h>
79 #include <dev/alc/if_alcvar.h>
81 /* "device miibus" required. See GENERIC if you get errors here. */
82 #include "miibus_if.h"
83 #undef ALC_USE_CUSTOM_CSUM
85 #ifdef ALC_USE_CUSTOM_CSUM
86 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
88 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
91 MODULE_DEPEND(alc, pci, 1, 1, 1);
92 MODULE_DEPEND(alc, ether, 1, 1, 1);
93 MODULE_DEPEND(alc, miibus, 1, 1, 1);
96 static int msi_disable = 0;
97 static int msix_disable = 0;
98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable);
99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable);
102 * Devices supported by this driver.
104 static struct alc_ident alc_ident_table[] = {
105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024,
106 "Atheros AR8131 PCIe Gigabit Ethernet" },
107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024,
108 "Atheros AR8132 PCIe Fast Ethernet" },
109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024,
110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024,
112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024,
114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" },
115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024,
116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024,
118 "Atheros AR8161 PCIe Gigabit Ethernet" },
119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024,
120 "Atheros AR8162 PCIe Fast Ethernet" },
121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024,
122 "Atheros AR8171 PCIe Gigabit Ethernet" },
123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024,
124 "Atheros AR8172 PCIe Fast Ethernet" },
125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024,
126 "Killer E2200 Gigabit Ethernet" },
127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024,
128 "Killer E2400 Gigabit Ethernet" },
129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024,
130 "Killer E2500 Gigabit Ethernet" },
134 static void alc_aspm(struct alc_softc *, int, int);
135 static void alc_aspm_813x(struct alc_softc *, int);
136 static void alc_aspm_816x(struct alc_softc *, int);
137 static int alc_attach(device_t);
138 static int alc_check_boundary(struct alc_softc *);
139 static void alc_config_msi(struct alc_softc *);
140 static int alc_detach(device_t);
141 static void alc_disable_l0s_l1(struct alc_softc *);
142 static int alc_dma_alloc(struct alc_softc *);
143 static void alc_dma_free(struct alc_softc *);
144 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
145 static void alc_dsp_fixup(struct alc_softc *, int);
146 static int alc_encap(struct alc_softc *, struct mbuf **);
147 static struct alc_ident *
148 alc_find_ident(device_t);
149 #ifndef __NO_STRICT_ALIGNMENT
151 alc_fixup_rx(struct ifnet *, struct mbuf *);
153 static void alc_get_macaddr(struct alc_softc *);
154 static void alc_get_macaddr_813x(struct alc_softc *);
155 static void alc_get_macaddr_816x(struct alc_softc *);
156 static void alc_get_macaddr_par(struct alc_softc *);
157 static void alc_init(void *);
158 static void alc_init_cmb(struct alc_softc *);
159 static void alc_init_locked(struct alc_softc *);
160 static void alc_init_rr_ring(struct alc_softc *);
161 static int alc_init_rx_ring(struct alc_softc *);
162 static void alc_init_smb(struct alc_softc *);
163 static void alc_init_tx_ring(struct alc_softc *);
164 static void alc_int_task(void *, int);
165 static int alc_intr(void *);
166 static int alc_ioctl(struct ifnet *, u_long, caddr_t);
167 static void alc_mac_config(struct alc_softc *);
168 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int);
169 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int);
170 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int);
171 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int);
172 static int alc_miibus_readreg(device_t, int, int);
173 static void alc_miibus_statchg(device_t);
174 static int alc_miibus_writereg(device_t, int, int, int);
175 static uint32_t alc_miidbg_readreg(struct alc_softc *, int);
176 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int);
177 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int);
178 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int);
179 static int alc_mediachange(struct ifnet *);
180 static int alc_mediachange_locked(struct alc_softc *);
181 static void alc_mediastatus(struct ifnet *, struct ifmediareq *);
182 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *);
183 static void alc_osc_reset(struct alc_softc *);
184 static void alc_phy_down(struct alc_softc *);
185 static void alc_phy_reset(struct alc_softc *);
186 static void alc_phy_reset_813x(struct alc_softc *);
187 static void alc_phy_reset_816x(struct alc_softc *);
188 static int alc_probe(device_t);
189 static void alc_reset(struct alc_softc *);
190 static int alc_resume(device_t);
191 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *);
192 static int alc_rxintr(struct alc_softc *, int);
193 static void alc_rxfilter(struct alc_softc *);
194 static void alc_rxvlan(struct alc_softc *);
195 static void alc_setlinkspeed(struct alc_softc *);
196 static void alc_setwol(struct alc_softc *);
197 static void alc_setwol_813x(struct alc_softc *);
198 static void alc_setwol_816x(struct alc_softc *);
199 static int alc_shutdown(device_t);
200 static void alc_start(struct ifnet *);
201 static void alc_start_locked(struct ifnet *);
202 static void alc_start_queue(struct alc_softc *);
203 static void alc_start_tx(struct alc_softc *);
204 static void alc_stats_clear(struct alc_softc *);
205 static void alc_stats_update(struct alc_softc *);
206 static void alc_stop(struct alc_softc *);
207 static void alc_stop_mac(struct alc_softc *);
208 static void alc_stop_queue(struct alc_softc *);
209 static int alc_suspend(device_t);
210 static void alc_sysctl_node(struct alc_softc *);
211 static void alc_tick(void *);
212 static void alc_txeof(struct alc_softc *);
213 static void alc_watchdog(struct alc_softc *);
214 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
215 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS);
216 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS);
218 DEBUGNET_DEFINE(alc);
220 static device_method_t alc_methods[] = {
221 /* Device interface. */
222 DEVMETHOD(device_probe, alc_probe),
223 DEVMETHOD(device_attach, alc_attach),
224 DEVMETHOD(device_detach, alc_detach),
225 DEVMETHOD(device_shutdown, alc_shutdown),
226 DEVMETHOD(device_suspend, alc_suspend),
227 DEVMETHOD(device_resume, alc_resume),
230 DEVMETHOD(miibus_readreg, alc_miibus_readreg),
231 DEVMETHOD(miibus_writereg, alc_miibus_writereg),
232 DEVMETHOD(miibus_statchg, alc_miibus_statchg),
237 static driver_t alc_driver = {
240 sizeof(struct alc_softc)
243 static devclass_t alc_devclass;
245 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0);
246 MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table,
247 nitems(alc_ident_table) - 1);
248 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0);
250 static struct resource_spec alc_res_spec_mem[] = {
251 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
255 static struct resource_spec alc_irq_spec_legacy[] = {
256 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
260 static struct resource_spec alc_irq_spec_msi[] = {
261 { SYS_RES_IRQ, 1, RF_ACTIVE },
265 static struct resource_spec alc_irq_spec_msix[] = {
266 { SYS_RES_IRQ, 1, RF_ACTIVE },
270 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
273 alc_miibus_readreg(device_t dev, int phy, int reg)
275 struct alc_softc *sc;
278 sc = device_get_softc(dev);
279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
280 v = alc_mii_readreg_816x(sc, phy, reg);
282 v = alc_mii_readreg_813x(sc, phy, reg);
287 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg)
293 * For AR8132 fast ethernet controller, do not report 1000baseT
294 * capability to mii(4). Even though AR8132 uses the same
295 * model/revision number of F1 gigabit PHY, the PHY has no
296 * ability to establish 1000baseT link.
298 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
302 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
303 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
304 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
306 v = CSR_READ_4(sc, ALC_MDIO);
307 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
312 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
316 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
320 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg)
325 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
326 clk = MDIO_CLK_25_128;
329 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
330 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));
331 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
333 v = CSR_READ_4(sc, ALC_MDIO);
334 if ((v & MDIO_OP_BUSY) == 0)
339 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg);
343 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
347 alc_miibus_writereg(device_t dev, int phy, int reg, int val)
349 struct alc_softc *sc;
352 sc = device_get_softc(dev);
353 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
354 v = alc_mii_writereg_816x(sc, phy, reg, val);
356 v = alc_mii_writereg_813x(sc, phy, reg, val);
361 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val)
366 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
367 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
368 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
369 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
371 v = CSR_READ_4(sc, ALC_MDIO);
372 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
377 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
383 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val)
388 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
389 clk = MDIO_CLK_25_128;
392 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
393 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |
394 MDIO_SUP_PREAMBLE | clk);
395 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
397 v = CSR_READ_4(sc, ALC_MDIO);
398 if ((v & MDIO_OP_BUSY) == 0)
403 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg);
409 alc_miibus_statchg(device_t dev)
411 struct alc_softc *sc;
412 struct mii_data *mii;
416 sc = device_get_softc(dev);
418 mii = device_get_softc(sc->alc_miibus);
420 if (mii == NULL || ifp == NULL ||
421 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
424 sc->alc_flags &= ~ALC_FLAG_LINK;
425 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
426 (IFM_ACTIVE | IFM_AVALID)) {
427 switch (IFM_SUBTYPE(mii->mii_media_active)) {
430 sc->alc_flags |= ALC_FLAG_LINK;
433 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
434 sc->alc_flags |= ALC_FLAG_LINK;
440 /* Stop Rx/Tx MACs. */
443 /* Program MACs with resolved speed/duplex/flow-control. */
444 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
447 /* Re-enable Tx/Rx MACs. */
448 reg = CSR_READ_4(sc, ALC_MAC_CFG);
449 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
450 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
452 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
453 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
457 alc_miidbg_readreg(struct alc_softc *sc, int reg)
460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
462 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
467 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
470 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
472 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
473 ALC_MII_DBG_DATA, val));
477 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
482 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
483 EXT_MDIO_DEVADDR(devaddr));
484 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
485 clk = MDIO_CLK_25_128;
488 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
489 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
490 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
492 v = CSR_READ_4(sc, ALC_MDIO);
493 if ((v & MDIO_OP_BUSY) == 0)
498 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n",
503 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
507 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
512 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
513 EXT_MDIO_DEVADDR(devaddr));
514 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
515 clk = MDIO_CLK_25_128;
518 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
519 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) |
520 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT);
521 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
523 v = CSR_READ_4(sc, ALC_MDIO);
524 if ((v & MDIO_OP_BUSY) == 0)
529 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n",
536 alc_dsp_fixup(struct alc_softc *sc, int media)
538 uint16_t agc, len, val;
540 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
542 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
547 * 1000BT/AZ, wrong cable length
549 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
550 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
551 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) &
552 EXT_CLDCTL6_CAB_LEN_MASK;
553 agc = alc_miidbg_readreg(sc, MII_DBG_AGC);
554 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK;
555 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G &&
556 agc > DBG_AGC_LONG1G_LIMT) ||
557 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT &&
558 agc > DBG_AGC_LONG1G_LIMT)) {
559 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
560 DBG_AZ_ANADECT_LONG);
561 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
563 val |= ANEG_AFEE_10BT_100M_TH;
564 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
567 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
568 DBG_AZ_ANADECT_DEFAULT);
569 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
571 val &= ~ANEG_AFEE_10BT_100M_TH;
572 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
575 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
576 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
577 if (media == IFM_1000_T) {
579 * Giga link threshold, raise the tolerance of
582 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
583 val &= ~DBG_MSE20DB_TH_MASK;
584 val |= (DBG_MSE20DB_TH_HI <<
585 DBG_MSE20DB_TH_SHIFT);
586 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
587 } else if (media == IFM_100_TX)
588 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
592 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
593 val &= ~ANEG_AFEE_10BT_100M_TH;
594 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
595 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
596 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
597 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
599 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
600 val &= ~DBG_MSE20DB_TH_MASK;
601 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT);
602 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
608 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
610 struct alc_softc *sc;
611 struct mii_data *mii;
615 if ((ifp->if_flags & IFF_UP) == 0) {
619 mii = device_get_softc(sc->alc_miibus);
622 ifmr->ifm_status = mii->mii_media_status;
623 ifmr->ifm_active = mii->mii_media_active;
628 alc_mediachange(struct ifnet *ifp)
630 struct alc_softc *sc;
635 error = alc_mediachange_locked(sc);
642 alc_mediachange_locked(struct alc_softc *sc)
644 struct mii_data *mii;
645 struct mii_softc *miisc;
650 mii = device_get_softc(sc->alc_miibus);
651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
653 error = mii_mediachg(mii);
658 static struct alc_ident *
659 alc_find_ident(device_t dev)
661 struct alc_ident *ident;
662 uint16_t vendor, devid;
664 vendor = pci_get_vendor(dev);
665 devid = pci_get_device(dev);
666 for (ident = alc_ident_table; ident->name != NULL; ident++) {
667 if (vendor == ident->vendorid && devid == ident->deviceid)
675 alc_probe(device_t dev)
677 struct alc_ident *ident;
679 ident = alc_find_ident(dev);
681 device_set_desc(dev, ident->name);
682 return (BUS_PROBE_DEFAULT);
689 alc_get_macaddr(struct alc_softc *sc)
692 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
693 alc_get_macaddr_816x(sc);
695 alc_get_macaddr_813x(sc);
699 alc_get_macaddr_813x(struct alc_softc *sc)
706 opt = CSR_READ_4(sc, ALC_OPT_CFG);
707 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
708 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
710 * EEPROM found, let TWSI reload EEPROM configuration.
711 * This will set ethernet address of controller.
714 switch (sc->alc_ident->deviceid) {
715 case DEVICEID_ATHEROS_AR8131:
716 case DEVICEID_ATHEROS_AR8132:
717 if ((opt & OPT_CFG_CLK_ENB) == 0) {
718 opt |= OPT_CFG_CLK_ENB;
719 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
720 CSR_READ_4(sc, ALC_OPT_CFG);
724 case DEVICEID_ATHEROS_AR8151:
725 case DEVICEID_ATHEROS_AR8151_V2:
726 case DEVICEID_ATHEROS_AR8152_B:
727 case DEVICEID_ATHEROS_AR8152_B2:
728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
729 ALC_MII_DBG_ADDR, 0x00);
730 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
733 ALC_MII_DBG_DATA, val & 0xFF7F);
734 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
735 ALC_MII_DBG_ADDR, 0x3B);
736 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
738 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
739 ALC_MII_DBG_DATA, val | 0x0008);
744 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
745 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
746 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
747 CSR_READ_4(sc, ALC_WOL_CFG);
749 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
750 TWSI_CFG_SW_LD_START);
751 for (i = 100; i > 0; i--) {
753 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
754 TWSI_CFG_SW_LD_START) == 0)
758 device_printf(sc->alc_dev,
759 "reloading EEPROM timeout!\n");
762 device_printf(sc->alc_dev, "EEPROM not found!\n");
765 switch (sc->alc_ident->deviceid) {
766 case DEVICEID_ATHEROS_AR8131:
767 case DEVICEID_ATHEROS_AR8132:
768 if ((opt & OPT_CFG_CLK_ENB) != 0) {
769 opt &= ~OPT_CFG_CLK_ENB;
770 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
771 CSR_READ_4(sc, ALC_OPT_CFG);
775 case DEVICEID_ATHEROS_AR8151:
776 case DEVICEID_ATHEROS_AR8151_V2:
777 case DEVICEID_ATHEROS_AR8152_B:
778 case DEVICEID_ATHEROS_AR8152_B2:
779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
780 ALC_MII_DBG_ADDR, 0x00);
781 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
784 ALC_MII_DBG_DATA, val | 0x0080);
785 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
786 ALC_MII_DBG_ADDR, 0x3B);
787 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
789 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
790 ALC_MII_DBG_DATA, val & 0xFFF7);
796 alc_get_macaddr_par(sc);
800 alc_get_macaddr_816x(struct alc_softc *sc)
806 /* Try to reload station address via TWSI. */
807 for (i = 100; i > 0; i--) {
808 reg = CSR_READ_4(sc, ALC_SLD);
809 if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
814 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
815 for (i = 100; i > 0; i--) {
817 reg = CSR_READ_4(sc, ALC_SLD);
818 if ((reg & SLD_START) == 0)
823 else if (bootverbose)
824 device_printf(sc->alc_dev,
825 "reloading station address via TWSI timed out!\n");
828 /* Try to reload station address from EEPROM or FLASH. */
830 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
831 if ((reg & (EEPROM_LD_EEPROM_EXIST |
832 EEPROM_LD_FLASH_EXIST)) != 0) {
833 for (i = 100; i > 0; i--) {
834 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
835 if ((reg & (EEPROM_LD_PROGRESS |
836 EEPROM_LD_START)) == 0)
841 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
843 for (i = 100; i > 0; i--) {
845 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
846 if ((reg & EEPROM_LD_START) == 0)
849 } else if (bootverbose)
850 device_printf(sc->alc_dev,
851 "reloading EEPROM/FLASH timed out!\n");
855 alc_get_macaddr_par(sc);
859 alc_get_macaddr_par(struct alc_softc *sc)
863 ea[0] = CSR_READ_4(sc, ALC_PAR0);
864 ea[1] = CSR_READ_4(sc, ALC_PAR1);
865 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
866 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
867 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
868 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
869 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
870 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
874 alc_disable_l0s_l1(struct alc_softc *sc)
878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
879 /* Another magic from vendor. */
880 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
881 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
882 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
883 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1);
884 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
885 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB;
886 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
891 alc_phy_reset(struct alc_softc *sc)
894 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
895 alc_phy_reset_816x(sc);
897 alc_phy_reset_813x(sc);
901 alc_phy_reset_813x(struct alc_softc *sc)
905 /* Reset magic from Linux. */
906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
907 CSR_READ_2(sc, ALC_GPHY_CFG);
910 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
911 GPHY_CFG_SEL_ANA_RESET);
912 CSR_READ_2(sc, ALC_GPHY_CFG);
915 /* DSP fixup, Vendor magic. */
916 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
917 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
918 ALC_MII_DBG_ADDR, 0x000A);
919 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
921 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
922 ALC_MII_DBG_DATA, data & 0xDFFF);
924 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
929 ALC_MII_DBG_ADDR, 0x003B);
930 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
932 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
933 ALC_MII_DBG_DATA, data & 0xFFF7);
936 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) {
937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
938 ALC_MII_DBG_ADDR, 0x0029);
939 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
940 ALC_MII_DBG_DATA, 0x929D);
942 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 ||
944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) {
946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
947 ALC_MII_DBG_ADDR, 0x0029);
948 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
949 ALC_MII_DBG_DATA, 0xB6DD);
952 /* Load DSP codes, vendor magic. */
953 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
954 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK);
955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
956 ALC_MII_DBG_ADDR, MII_ANA_CFG18);
957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
958 ALC_MII_DBG_DATA, data);
960 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) |
961 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
964 ALC_MII_DBG_ADDR, MII_ANA_CFG5);
965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
966 ALC_MII_DBG_DATA, data);
968 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) &
969 ANA_LONG_CABLE_TH_100_MASK) |
970 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) &
971 ANA_SHORT_CABLE_TH_100_SHIFT) |
972 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW;
973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
974 ALC_MII_DBG_ADDR, MII_ANA_CFG54);
975 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
976 ALC_MII_DBG_DATA, data);
978 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) |
979 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) |
980 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) |
981 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK);
982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
983 ALC_MII_DBG_ADDR, MII_ANA_CFG4);
984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
985 ALC_MII_DBG_DATA, data);
987 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) |
988 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB |
990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
991 ALC_MII_DBG_ADDR, MII_ANA_CFG0);
992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
993 ALC_MII_DBG_DATA, data);
996 /* Disable hibernation. */
997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
999 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1002 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1005 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
1007 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr,
1010 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
1015 alc_phy_reset_816x(struct alc_softc *sc)
1019 val = CSR_READ_4(sc, ALC_GPHY_CFG);
1020 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1021 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON |
1022 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB);
1023 val |= GPHY_CFG_SEL_ANA_RESET;
1025 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET;
1027 /* Disable PHY hibernation. */
1028 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN);
1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
1032 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
1035 /* Vendor PHY magic. */
1037 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT);
1038 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT);
1039 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS,
1040 EXT_VDRVBIAS_DEFAULT);
1042 /* Disable PHY hibernation. */
1043 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
1044 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB);
1045 alc_miidbg_writereg(sc, MII_DBG_HIBNEG,
1046 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE));
1047 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
1050 /* XXX Disable EEE. */
1051 val = CSR_READ_4(sc, ALC_LPI_CTL);
1052 val &= ~LPI_CTL_ENB;
1053 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
1054 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
1056 /* PHY power saving. */
1057 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
1058 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
1059 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
1060 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
1061 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1062 val &= ~DBG_GREENCFG2_GATE_DFSE_EN;
1063 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1065 /* RTL8139C, 120m issue. */
1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
1067 ANEG_NLP78_120M_DEFAULT);
1068 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
1069 ANEG_S3DIG10_DEFAULT);
1071 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
1072 /* Turn off half amplitude. */
1073 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
1074 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT;
1075 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
1076 /* Turn off Green feature. */
1077 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
1078 val |= DBG_GREENCFG2_BP_GREEN;
1079 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
1080 /* Turn off half bias. */
1081 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
1082 val |= EXT_CLDCTL5_BP_VD_HLFBIAS;
1083 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
1088 alc_phy_down(struct alc_softc *sc)
1092 switch (sc->alc_ident->deviceid) {
1093 case DEVICEID_ATHEROS_AR8161:
1094 case DEVICEID_ATHEROS_E2200:
1095 case DEVICEID_ATHEROS_E2400:
1096 case DEVICEID_ATHEROS_E2500:
1097 case DEVICEID_ATHEROS_AR8162:
1098 case DEVICEID_ATHEROS_AR8171:
1099 case DEVICEID_ATHEROS_AR8172:
1100 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
1101 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE |
1102 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON);
1103 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE |
1104 GPHY_CFG_SEL_ANA_RESET;
1105 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
1106 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
1108 case DEVICEID_ATHEROS_AR8151:
1109 case DEVICEID_ATHEROS_AR8151_V2:
1110 case DEVICEID_ATHEROS_AR8152_B:
1111 case DEVICEID_ATHEROS_AR8152_B2:
1113 * GPHY power down caused more problems on AR8151 v2.0.
1114 * When driver is reloaded after GPHY power down,
1115 * accesses to PHY/MAC registers hung the system. Only
1116 * cold boot recovered from it. I'm not sure whether
1117 * AR8151 v1.0 also requires this one though. I don't
1118 * have AR8151 v1.0 controller in hand.
1119 * The only option left is to isolate the PHY and
1120 * initiates power down the PHY which in turn saves
1121 * more power when driver is unloaded.
1123 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
1124 MII_BMCR, BMCR_ISO | BMCR_PDOWN);
1127 /* Force PHY down. */
1128 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1129 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ |
1130 GPHY_CFG_PWDOWN_HW);
1137 alc_aspm(struct alc_softc *sc, int init, int media)
1140 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1141 alc_aspm_816x(sc, init);
1143 alc_aspm_813x(sc, media);
1147 alc_aspm_813x(struct alc_softc *sc, int media)
1152 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1155 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1156 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
1157 (ALC_FLAG_APS | ALC_FLAG_PCIE))
1158 linkcfg = CSR_READ_2(sc, sc->alc_expcap +
1162 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
1163 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
1164 pmcfg |= PM_CFG_MAC_ASPM_CHK;
1165 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
1166 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1168 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1169 /* Disable extended sync except AR8152 B v1.0 */
1170 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
1171 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1172 sc->alc_rev == ATHEROS_AR8152_B_V10)
1173 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
1174 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
1176 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
1178 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
1179 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1180 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1181 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
1182 PM_CFG_PM_REQ_TIMER_SHIFT);
1183 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
1186 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1187 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1188 pmcfg |= PM_CFG_ASPM_L0S_ENB;
1189 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1190 pmcfg |= PM_CFG_ASPM_L1_ENB;
1191 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1192 if (sc->alc_ident->deviceid ==
1193 DEVICEID_ATHEROS_AR8152_B)
1194 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
1195 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
1196 PM_CFG_SERDES_PLL_L1_ENB |
1197 PM_CFG_SERDES_BUDS_RX_L1_ENB);
1198 pmcfg |= PM_CFG_CLK_SWH_L1;
1199 if (media == IFM_100_TX || media == IFM_1000_T) {
1200 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
1201 switch (sc->alc_ident->deviceid) {
1202 case DEVICEID_ATHEROS_AR8152_B:
1204 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1206 case DEVICEID_ATHEROS_AR8152_B2:
1207 case DEVICEID_ATHEROS_AR8151_V2:
1209 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1213 PM_CFG_L1_ENTRY_TIMER_SHIFT);
1218 pmcfg |= PM_CFG_SERDES_L1_ENB |
1219 PM_CFG_SERDES_PLL_L1_ENB |
1220 PM_CFG_SERDES_BUDS_RX_L1_ENB;
1221 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
1222 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1225 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
1226 PM_CFG_SERDES_PLL_L1_ENB);
1227 pmcfg |= PM_CFG_CLK_SWH_L1;
1228 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1229 pmcfg |= PM_CFG_ASPM_L1_ENB;
1231 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1235 alc_aspm_816x(struct alc_softc *sc, int init)
1239 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1240 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
1241 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
1242 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1243 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
1244 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
1245 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
1246 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
1247 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
1248 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB |
1249 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB |
1250 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB |
1251 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST);
1252 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1253 (sc->alc_rev & 0x01) != 0)
1254 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
1255 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1256 /* Link up, enable both L0s, L1s. */
1257 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1258 PM_CFG_MAC_ASPM_CHK;
1261 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1262 PM_CFG_MAC_ASPM_CHK;
1263 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1264 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
1266 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1270 alc_init_pcie(struct alc_softc *sc)
1272 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" };
1273 uint32_t cap, ctl, val;
1276 /* Clear data link and flow-control protocol error. */
1277 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1278 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP);
1279 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1281 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1282 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1283 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1284 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1285 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1286 PCIE_PHYMISC_FORCE_RCV_DET);
1287 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
1288 sc->alc_rev == ATHEROS_AR8152_B_V10) {
1289 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1290 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK |
1291 PCIE_PHYMISC2_SERDES_TH_MASK);
1292 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
1293 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
1294 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1296 /* Disable ASPM L0S and L1. */
1297 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
1298 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1299 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
1300 if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
1301 sc->alc_rcb = DMA_CFG_RCB_128;
1303 device_printf(sc->alc_dev, "RCB %u bytes\n",
1304 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
1305 state = ctl & PCIEM_LINK_CTL_ASPMC;
1306 if (state & PCIEM_LINK_CTL_ASPMC_L0S)
1307 sc->alc_flags |= ALC_FLAG_L0S;
1308 if (state & PCIEM_LINK_CTL_ASPMC_L1)
1309 sc->alc_flags |= ALC_FLAG_L1S;
1311 device_printf(sc->alc_dev, "ASPM %s %s\n",
1313 state == 0 ? "disabled" : "enabled");
1314 alc_disable_l0s_l1(sc);
1317 device_printf(sc->alc_dev,
1318 "no ASPM support\n");
1321 val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1322 val &= ~PDLL_TRNS1_D3PLLOFF_ENB;
1323 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1324 val = CSR_READ_4(sc, ALC_MASTER_CFG);
1325 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1326 (sc->alc_rev & 0x01) != 0) {
1327 if ((val & MASTER_WAKEN_25M) == 0 ||
1328 (val & MASTER_CLK_SEL_DIS) == 0) {
1329 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS;
1330 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1333 if ((val & MASTER_WAKEN_25M) == 0 ||
1334 (val & MASTER_CLK_SEL_DIS) != 0) {
1335 val |= MASTER_WAKEN_25M;
1336 val &= ~MASTER_CLK_SEL_DIS;
1337 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1341 alc_aspm(sc, 1, IFM_UNKNOWN);
1345 alc_config_msi(struct alc_softc *sc)
1349 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
1351 * It seems interrupt moderation is controlled by
1352 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active.
1353 * Driver uses RX interrupt moderation parameter to
1354 * program ALC_MSI_RETRANS_TIMER register.
1356 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
1357 ctl &= ~MSI_RETRANS_TIMER_MASK;
1358 ctl &= ~MSI_RETRANS_MASK_SEL_LINE;
1359 mod = ALC_USECS(sc->alc_int_rx_mod);
1363 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1364 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1365 MSI_RETRANS_MASK_SEL_STD);
1366 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1367 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1368 MSI_RETRANS_MASK_SEL_LINE);
1370 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
1375 alc_attach(device_t dev)
1377 struct alc_softc *sc;
1379 int base, error, i, msic, msixc;
1383 sc = device_get_softc(dev);
1385 sc->alc_rev = pci_get_revid(dev);
1387 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1389 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
1390 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
1391 sc->alc_ident = alc_find_ident(dev);
1393 /* Map the device. */
1394 pci_enable_busmaster(dev);
1395 sc->alc_res_spec = alc_res_spec_mem;
1396 sc->alc_irq_spec = alc_irq_spec_legacy;
1397 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res);
1399 device_printf(dev, "cannot allocate memory resources.\n");
1403 /* Set PHY address. */
1404 sc->alc_phyaddr = ALC_PHY_ADDR;
1407 * One odd thing is AR8132 uses the same PHY hardware(F1
1408 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports
1409 * the PHY supports 1000Mbps but that's not true. The PHY
1410 * used in AR8132 can't establish gigabit link even if it
1411 * shows the same PHY model/revision number of AR8131.
1413 switch (sc->alc_ident->deviceid) {
1414 case DEVICEID_ATHEROS_E2200:
1415 case DEVICEID_ATHEROS_E2400:
1416 case DEVICEID_ATHEROS_E2500:
1417 sc->alc_flags |= ALC_FLAG_E2X00;
1419 case DEVICEID_ATHEROS_AR8161:
1420 if (pci_get_subvendor(dev) == VENDORID_ATHEROS &&
1421 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0)
1422 sc->alc_flags |= ALC_FLAG_LINK_WAR;
1424 case DEVICEID_ATHEROS_AR8171:
1425 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
1427 case DEVICEID_ATHEROS_AR8162:
1428 case DEVICEID_ATHEROS_AR8172:
1429 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
1431 case DEVICEID_ATHEROS_AR8152_B:
1432 case DEVICEID_ATHEROS_AR8152_B2:
1433 sc->alc_flags |= ALC_FLAG_APS;
1435 case DEVICEID_ATHEROS_AR8132:
1436 sc->alc_flags |= ALC_FLAG_FASTETHER;
1438 case DEVICEID_ATHEROS_AR8151:
1439 case DEVICEID_ATHEROS_AR8151_V2:
1440 sc->alc_flags |= ALC_FLAG_APS;
1445 sc->alc_flags |= ALC_FLAG_JUMBO;
1448 * It seems that AR813x/AR815x has silicon bug for SMB. In
1449 * addition, Atheros said that enabling SMB wouldn't improve
1450 * performance. However I think it's bad to access lots of
1451 * registers to extract MAC statistics.
1453 sc->alc_flags |= ALC_FLAG_SMB_BUG;
1455 * Don't use Tx CMB. It is known to have silicon bug.
1457 sc->alc_flags |= ALC_FLAG_CMB_BUG;
1458 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1459 MASTER_CHIP_REV_SHIFT;
1461 device_printf(dev, "PCI device revision : 0x%04x\n",
1463 device_printf(dev, "Chip id/revision : 0x%04x\n",
1465 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1466 device_printf(dev, "AR816x revision : 0x%x\n",
1467 AR816X_REV(sc->alc_rev));
1469 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n",
1470 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1471 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
1473 /* Initialize DMA parameters. */
1474 sc->alc_dma_rd_burst = 0;
1475 sc->alc_dma_wr_burst = 0;
1476 sc->alc_rcb = DMA_CFG_RCB_64;
1477 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
1478 sc->alc_flags |= ALC_FLAG_PCIE;
1479 sc->alc_expcap = base;
1480 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
1481 sc->alc_dma_rd_burst =
1482 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12;
1483 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5;
1485 device_printf(dev, "Read request size : %u bytes.\n",
1486 alc_dma_burst[sc->alc_dma_rd_burst]);
1487 device_printf(dev, "TLP payload size : %u bytes.\n",
1488 alc_dma_burst[sc->alc_dma_wr_burst]);
1490 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
1491 sc->alc_dma_rd_burst = 3;
1492 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
1493 sc->alc_dma_wr_burst = 3;
1495 * Force maximum payload size to 128 bytes for
1496 * E2200/E2400/E2500.
1497 * Otherwise it triggers DMA write error.
1499 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0)
1500 sc->alc_dma_wr_burst = 0;
1507 /* Reset the ethernet controller. */
1511 /* Allocate IRQ resources. */
1512 msixc = pci_msix_count(dev);
1513 msic = pci_msi_count(dev);
1515 device_printf(dev, "MSIX count : %d\n", msixc);
1516 device_printf(dev, "MSI count : %d\n", msic);
1523 * Prefer MSIX over MSI.
1524 * AR816x controller has a silicon bug that MSI interrupt
1525 * does not assert if PCIM_CMD_INTxDIS bit of command
1526 * register is set. pci(4) was taught to handle that case.
1528 if (msix_disable == 0 || msi_disable == 0) {
1529 if (msix_disable == 0 && msixc > 0 &&
1530 pci_alloc_msix(dev, &msixc) == 0) {
1533 "Using %d MSIX message(s).\n", msixc);
1534 sc->alc_flags |= ALC_FLAG_MSIX;
1535 sc->alc_irq_spec = alc_irq_spec_msix;
1537 pci_release_msi(dev);
1539 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
1540 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
1543 "Using %d MSI message(s).\n", msic);
1544 sc->alc_flags |= ALC_FLAG_MSI;
1545 sc->alc_irq_spec = alc_irq_spec_msi;
1547 pci_release_msi(dev);
1551 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1553 device_printf(dev, "cannot allocate IRQ resources.\n");
1557 /* Create device sysctl node. */
1558 alc_sysctl_node(sc);
1560 if ((error = alc_dma_alloc(sc)) != 0)
1563 /* Load station address. */
1564 alc_get_macaddr(sc);
1566 ifp = sc->alc_ifp = if_alloc(IFT_ETHER);
1568 device_printf(dev, "cannot allocate ifnet structure.\n");
1574 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1575 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1576 ifp->if_ioctl = alc_ioctl;
1577 ifp->if_start = alc_start;
1578 ifp->if_init = alc_init;
1579 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1;
1580 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1581 IFQ_SET_READY(&ifp->if_snd);
1582 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1583 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
1584 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) {
1585 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
1586 sc->alc_flags |= ALC_FLAG_PM;
1587 sc->alc_pmcap = base;
1589 ifp->if_capenable = ifp->if_capabilities;
1591 /* Set up MII bus. */
1592 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange,
1593 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY,
1596 device_printf(dev, "attaching PHYs failed\n");
1600 ether_ifattach(ifp, sc->alc_eaddr);
1602 /* VLAN capability setup. */
1603 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
1604 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
1605 ifp->if_capenable = ifp->if_capabilities;
1608 * It seems enabling Tx checksum offloading makes more trouble.
1609 * Sometimes the controller does not receive any frames when
1610 * Tx checksum offloading is enabled. I'm not sure whether this
1611 * is a bug in Tx checksum offloading logic or I got broken
1612 * sample boards. To safety, don't enable Tx checksum offloading
1613 * by default but give chance to users to toggle it if they know
1614 * their controllers work without problems.
1615 * Fortunately, Tx checksum offloading for AR816x family
1618 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1619 ifp->if_capenable &= ~IFCAP_TXCSUM;
1620 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
1623 /* Tell the upper layer(s) we support long frames. */
1624 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1626 /* Create local taskq. */
1627 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK,
1628 taskqueue_thread_enqueue, &sc->alc_tq);
1629 if (sc->alc_tq == NULL) {
1630 device_printf(dev, "could not create taskqueue.\n");
1631 ether_ifdetach(ifp);
1635 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq",
1636 device_get_nameunit(sc->alc_dev));
1639 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1640 msic = ALC_MSIX_MESSAGES;
1641 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1642 msic = ALC_MSI_MESSAGES;
1645 for (i = 0; i < msic; i++) {
1646 error = bus_setup_intr(dev, sc->alc_irq[i],
1647 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc,
1648 &sc->alc_intrhand[i]);
1653 device_printf(dev, "could not set up interrupt handler.\n");
1654 taskqueue_free(sc->alc_tq);
1656 ether_ifdetach(ifp);
1660 /* Attach driver debugnet methods. */
1661 DEBUGNET_SET(ifp, alc);
1671 alc_detach(device_t dev)
1673 struct alc_softc *sc;
1677 sc = device_get_softc(dev);
1680 if (device_is_attached(dev)) {
1681 ether_ifdetach(ifp);
1685 callout_drain(&sc->alc_tick_ch);
1686 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1689 if (sc->alc_tq != NULL) {
1690 taskqueue_drain(sc->alc_tq, &sc->alc_int_task);
1691 taskqueue_free(sc->alc_tq);
1695 if (sc->alc_miibus != NULL) {
1696 device_delete_child(dev, sc->alc_miibus);
1697 sc->alc_miibus = NULL;
1699 bus_generic_detach(dev);
1707 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1708 msic = ALC_MSIX_MESSAGES;
1709 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1710 msic = ALC_MSI_MESSAGES;
1713 for (i = 0; i < msic; i++) {
1714 if (sc->alc_intrhand[i] != NULL) {
1715 bus_teardown_intr(dev, sc->alc_irq[i],
1716 sc->alc_intrhand[i]);
1717 sc->alc_intrhand[i] = NULL;
1720 if (sc->alc_res[0] != NULL)
1722 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq);
1723 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
1724 pci_release_msi(dev);
1725 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res);
1726 mtx_destroy(&sc->alc_mtx);
1731 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \
1732 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1733 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \
1734 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
1737 alc_sysctl_node(struct alc_softc *sc)
1739 struct sysctl_ctx_list *ctx;
1740 struct sysctl_oid_list *child, *parent;
1741 struct sysctl_oid *tree;
1742 struct alc_hw_stats *stats;
1745 stats = &sc->alc_stats;
1746 ctx = device_get_sysctl_ctx(sc->alc_dev);
1747 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev));
1749 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
1750 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0,
1751 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1752 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
1753 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0,
1754 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1755 /* Pull in device tunables. */
1756 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1757 error = resource_int_value(device_get_name(sc->alc_dev),
1758 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod);
1760 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN ||
1761 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) {
1762 device_printf(sc->alc_dev, "int_rx_mod value out of "
1763 "range; using default: %d\n",
1764 ALC_IM_RX_TIMER_DEFAULT);
1765 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
1768 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1769 error = resource_int_value(device_get_name(sc->alc_dev),
1770 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod);
1772 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN ||
1773 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) {
1774 device_printf(sc->alc_dev, "int_tx_mod value out of "
1775 "range; using default: %d\n",
1776 ALC_IM_TX_TIMER_DEFAULT);
1777 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
1780 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
1781 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0,
1782 sysctl_hw_alc_proc_limit, "I",
1783 "max number of Rx events to process");
1784 /* Pull in device tunables. */
1785 sc->alc_process_limit = ALC_PROC_DEFAULT;
1786 error = resource_int_value(device_get_name(sc->alc_dev),
1787 device_get_unit(sc->alc_dev), "process_limit",
1788 &sc->alc_process_limit);
1790 if (sc->alc_process_limit < ALC_PROC_MIN ||
1791 sc->alc_process_limit > ALC_PROC_MAX) {
1792 device_printf(sc->alc_dev,
1793 "process_limit value out of range; "
1794 "using default: %d\n", ALC_PROC_DEFAULT);
1795 sc->alc_process_limit = ALC_PROC_DEFAULT;
1799 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1800 NULL, "ALC statistics");
1801 parent = SYSCTL_CHILDREN(tree);
1803 /* Rx statistics. */
1804 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1805 NULL, "Rx MAC statistics");
1806 child = SYSCTL_CHILDREN(tree);
1807 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1808 &stats->rx_frames, "Good frames");
1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1810 &stats->rx_bcast_frames, "Good broadcast frames");
1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1812 &stats->rx_mcast_frames, "Good multicast frames");
1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1814 &stats->rx_pause_frames, "Pause control frames");
1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1816 &stats->rx_control_frames, "Control frames");
1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1818 &stats->rx_crcerrs, "CRC errors");
1819 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1820 &stats->rx_lenerrs, "Frames with length mismatched");
1821 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1822 &stats->rx_bytes, "Good octets");
1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1824 &stats->rx_bcast_bytes, "Good broadcast octets");
1825 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1826 &stats->rx_mcast_bytes, "Good multicast octets");
1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts",
1828 &stats->rx_runts, "Too short frames");
1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments",
1830 &stats->rx_fragments, "Fragmented frames");
1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1832 &stats->rx_pkts_64, "64 bytes frames");
1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1834 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1836 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1838 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1840 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1842 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1844 &stats->rx_pkts_1519_max, "1519 to max frames");
1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1846 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1848 &stats->rx_fifo_oflows, "FIFO overflows");
1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
1850 &stats->rx_rrs_errs, "Return status write-back errors");
1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
1852 &stats->rx_alignerrs, "Alignment errors");
1853 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered",
1854 &stats->rx_pkts_filtered,
1855 "Frames dropped due to address filtering");
1857 /* Tx statistics. */
1858 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1859 NULL, "Tx MAC statistics");
1860 child = SYSCTL_CHILDREN(tree);
1861 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1862 &stats->tx_frames, "Good frames");
1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
1864 &stats->tx_bcast_frames, "Good broadcast frames");
1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
1866 &stats->tx_mcast_frames, "Good multicast frames");
1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
1868 &stats->tx_pause_frames, "Pause control frames");
1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
1870 &stats->tx_control_frames, "Control frames");
1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
1872 &stats->tx_excess_defer, "Frames with excessive derferrals");
1873 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers",
1874 &stats->tx_excess_defer, "Frames with derferrals");
1875 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
1876 &stats->tx_bytes, "Good octets");
1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
1878 &stats->tx_bcast_bytes, "Good broadcast octets");
1879 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
1880 &stats->tx_mcast_bytes, "Good multicast octets");
1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
1882 &stats->tx_pkts_64, "64 bytes frames");
1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
1884 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
1886 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
1888 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
1890 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
1892 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
1894 &stats->tx_pkts_1519_max, "1519 to max frames");
1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
1896 &stats->tx_single_colls, "Single collisions");
1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
1898 &stats->tx_multi_colls, "Multiple collisions");
1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
1900 &stats->tx_late_colls, "Late collisions");
1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
1902 &stats->tx_excess_colls, "Excessive collisions");
1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns",
1904 &stats->tx_underrun, "FIFO underruns");
1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
1906 &stats->tx_desc_underrun, "Descriptor write-back errors");
1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
1908 &stats->tx_lenerrs, "Frames with length mismatched");
1909 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
1910 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
1913 #undef ALC_SYSCTL_STAT_ADD32
1914 #undef ALC_SYSCTL_STAT_ADD64
1916 struct alc_dmamap_arg {
1917 bus_addr_t alc_busaddr;
1921 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1923 struct alc_dmamap_arg *ctx;
1928 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1930 ctx = (struct alc_dmamap_arg *)arg;
1931 ctx->alc_busaddr = segs[0].ds_addr;
1935 * Normal and high Tx descriptors shares single Tx high address.
1936 * Four Rx descriptor/return rings and CMB shares the same Rx
1940 alc_check_boundary(struct alc_softc *sc)
1942 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end;
1944 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ;
1945 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ;
1946 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ;
1947 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ;
1949 /* 4GB boundary crossing is not allowed. */
1950 if ((ALC_ADDR_HI(rx_ring_end) !=
1951 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) ||
1952 (ALC_ADDR_HI(rr_ring_end) !=
1953 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) ||
1954 (ALC_ADDR_HI(cmb_end) !=
1955 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) ||
1956 (ALC_ADDR_HI(tx_ring_end) !=
1957 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr)))
1960 * Make sure Rx return descriptor/Rx descriptor/CMB use
1961 * the same high address.
1963 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) ||
1964 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end)))
1971 alc_dma_alloc(struct alc_softc *sc)
1973 struct alc_txdesc *txd;
1974 struct alc_rxdesc *rxd;
1976 struct alc_dmamap_arg ctx;
1979 lowaddr = BUS_SPACE_MAXADDR;
1981 /* Create parent DMA tag. */
1982 error = bus_dma_tag_create(
1983 bus_get_dma_tag(sc->alc_dev), /* parent */
1984 1, 0, /* alignment, boundary */
1985 lowaddr, /* lowaddr */
1986 BUS_SPACE_MAXADDR, /* highaddr */
1987 NULL, NULL, /* filter, filterarg */
1988 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1990 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1992 NULL, NULL, /* lockfunc, lockarg */
1993 &sc->alc_cdata.alc_parent_tag);
1995 device_printf(sc->alc_dev,
1996 "could not create parent DMA tag.\n");
2000 /* Create DMA tag for Tx descriptor ring. */
2001 error = bus_dma_tag_create(
2002 sc->alc_cdata.alc_parent_tag, /* parent */
2003 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
2004 BUS_SPACE_MAXADDR, /* lowaddr */
2005 BUS_SPACE_MAXADDR, /* highaddr */
2006 NULL, NULL, /* filter, filterarg */
2007 ALC_TX_RING_SZ, /* maxsize */
2009 ALC_TX_RING_SZ, /* maxsegsize */
2011 NULL, NULL, /* lockfunc, lockarg */
2012 &sc->alc_cdata.alc_tx_ring_tag);
2014 device_printf(sc->alc_dev,
2015 "could not create Tx ring DMA tag.\n");
2019 /* Create DMA tag for Rx free descriptor ring. */
2020 error = bus_dma_tag_create(
2021 sc->alc_cdata.alc_parent_tag, /* parent */
2022 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
2023 BUS_SPACE_MAXADDR, /* lowaddr */
2024 BUS_SPACE_MAXADDR, /* highaddr */
2025 NULL, NULL, /* filter, filterarg */
2026 ALC_RX_RING_SZ, /* maxsize */
2028 ALC_RX_RING_SZ, /* maxsegsize */
2030 NULL, NULL, /* lockfunc, lockarg */
2031 &sc->alc_cdata.alc_rx_ring_tag);
2033 device_printf(sc->alc_dev,
2034 "could not create Rx ring DMA tag.\n");
2037 /* Create DMA tag for Rx return descriptor ring. */
2038 error = bus_dma_tag_create(
2039 sc->alc_cdata.alc_parent_tag, /* parent */
2040 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
2041 BUS_SPACE_MAXADDR, /* lowaddr */
2042 BUS_SPACE_MAXADDR, /* highaddr */
2043 NULL, NULL, /* filter, filterarg */
2044 ALC_RR_RING_SZ, /* maxsize */
2046 ALC_RR_RING_SZ, /* maxsegsize */
2048 NULL, NULL, /* lockfunc, lockarg */
2049 &sc->alc_cdata.alc_rr_ring_tag);
2051 device_printf(sc->alc_dev,
2052 "could not create Rx return ring DMA tag.\n");
2056 /* Create DMA tag for coalescing message block. */
2057 error = bus_dma_tag_create(
2058 sc->alc_cdata.alc_parent_tag, /* parent */
2059 ALC_CMB_ALIGN, 0, /* alignment, boundary */
2060 BUS_SPACE_MAXADDR, /* lowaddr */
2061 BUS_SPACE_MAXADDR, /* highaddr */
2062 NULL, NULL, /* filter, filterarg */
2063 ALC_CMB_SZ, /* maxsize */
2065 ALC_CMB_SZ, /* maxsegsize */
2067 NULL, NULL, /* lockfunc, lockarg */
2068 &sc->alc_cdata.alc_cmb_tag);
2070 device_printf(sc->alc_dev,
2071 "could not create CMB DMA tag.\n");
2074 /* Create DMA tag for status message block. */
2075 error = bus_dma_tag_create(
2076 sc->alc_cdata.alc_parent_tag, /* parent */
2077 ALC_SMB_ALIGN, 0, /* alignment, boundary */
2078 BUS_SPACE_MAXADDR, /* lowaddr */
2079 BUS_SPACE_MAXADDR, /* highaddr */
2080 NULL, NULL, /* filter, filterarg */
2081 ALC_SMB_SZ, /* maxsize */
2083 ALC_SMB_SZ, /* maxsegsize */
2085 NULL, NULL, /* lockfunc, lockarg */
2086 &sc->alc_cdata.alc_smb_tag);
2088 device_printf(sc->alc_dev,
2089 "could not create SMB DMA tag.\n");
2093 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2094 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag,
2095 (void **)&sc->alc_rdata.alc_tx_ring,
2096 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2097 &sc->alc_cdata.alc_tx_ring_map);
2099 device_printf(sc->alc_dev,
2100 "could not allocate DMA'able memory for Tx ring.\n");
2103 ctx.alc_busaddr = 0;
2104 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag,
2105 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring,
2106 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2107 if (error != 0 || ctx.alc_busaddr == 0) {
2108 device_printf(sc->alc_dev,
2109 "could not load DMA'able memory for Tx ring.\n");
2112 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr;
2114 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2115 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag,
2116 (void **)&sc->alc_rdata.alc_rx_ring,
2117 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2118 &sc->alc_cdata.alc_rx_ring_map);
2120 device_printf(sc->alc_dev,
2121 "could not allocate DMA'able memory for Rx ring.\n");
2124 ctx.alc_busaddr = 0;
2125 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag,
2126 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring,
2127 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2128 if (error != 0 || ctx.alc_busaddr == 0) {
2129 device_printf(sc->alc_dev,
2130 "could not load DMA'able memory for Rx ring.\n");
2133 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr;
2135 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */
2136 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag,
2137 (void **)&sc->alc_rdata.alc_rr_ring,
2138 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2139 &sc->alc_cdata.alc_rr_ring_map);
2141 device_printf(sc->alc_dev,
2142 "could not allocate DMA'able memory for Rx return ring.\n");
2145 ctx.alc_busaddr = 0;
2146 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag,
2147 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring,
2148 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
2149 if (error != 0 || ctx.alc_busaddr == 0) {
2150 device_printf(sc->alc_dev,
2151 "could not load DMA'able memory for Tx ring.\n");
2154 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr;
2156 /* Allocate DMA'able memory and load the DMA map for CMB. */
2157 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag,
2158 (void **)&sc->alc_rdata.alc_cmb,
2159 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2160 &sc->alc_cdata.alc_cmb_map);
2162 device_printf(sc->alc_dev,
2163 "could not allocate DMA'able memory for CMB.\n");
2166 ctx.alc_busaddr = 0;
2167 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag,
2168 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb,
2169 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
2170 if (error != 0 || ctx.alc_busaddr == 0) {
2171 device_printf(sc->alc_dev,
2172 "could not load DMA'able memory for CMB.\n");
2175 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr;
2177 /* Allocate DMA'able memory and load the DMA map for SMB. */
2178 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag,
2179 (void **)&sc->alc_rdata.alc_smb,
2180 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2181 &sc->alc_cdata.alc_smb_map);
2183 device_printf(sc->alc_dev,
2184 "could not allocate DMA'able memory for SMB.\n");
2187 ctx.alc_busaddr = 0;
2188 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag,
2189 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb,
2190 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
2191 if (error != 0 || ctx.alc_busaddr == 0) {
2192 device_printf(sc->alc_dev,
2193 "could not load DMA'able memory for CMB.\n");
2196 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr;
2198 /* Make sure we've not crossed 4GB boundary. */
2199 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
2200 (error = alc_check_boundary(sc)) != 0) {
2201 device_printf(sc->alc_dev, "4GB boundary crossed, "
2202 "switching to 32bit DMA addressing mode.\n");
2205 * Limit max allowable DMA address space to 32bit
2208 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2213 * Create Tx buffer parent tag.
2214 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers
2215 * so it needs separate parent DMA tag as parent DMA address
2216 * space could be restricted to be within 32bit address space
2217 * by 4GB boundary crossing.
2219 error = bus_dma_tag_create(
2220 bus_get_dma_tag(sc->alc_dev), /* parent */
2221 1, 0, /* alignment, boundary */
2222 BUS_SPACE_MAXADDR, /* lowaddr */
2223 BUS_SPACE_MAXADDR, /* highaddr */
2224 NULL, NULL, /* filter, filterarg */
2225 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2227 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2229 NULL, NULL, /* lockfunc, lockarg */
2230 &sc->alc_cdata.alc_buffer_tag);
2232 device_printf(sc->alc_dev,
2233 "could not create parent buffer DMA tag.\n");
2237 /* Create DMA tag for Tx buffers. */
2238 error = bus_dma_tag_create(
2239 sc->alc_cdata.alc_buffer_tag, /* parent */
2240 1, 0, /* alignment, boundary */
2241 BUS_SPACE_MAXADDR, /* lowaddr */
2242 BUS_SPACE_MAXADDR, /* highaddr */
2243 NULL, NULL, /* filter, filterarg */
2244 ALC_TSO_MAXSIZE, /* maxsize */
2245 ALC_MAXTXSEGS, /* nsegments */
2246 ALC_TSO_MAXSEGSIZE, /* maxsegsize */
2248 NULL, NULL, /* lockfunc, lockarg */
2249 &sc->alc_cdata.alc_tx_tag);
2251 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n");
2255 /* Create DMA tag for Rx buffers. */
2256 error = bus_dma_tag_create(
2257 sc->alc_cdata.alc_buffer_tag, /* parent */
2258 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
2259 BUS_SPACE_MAXADDR, /* lowaddr */
2260 BUS_SPACE_MAXADDR, /* highaddr */
2261 NULL, NULL, /* filter, filterarg */
2262 MCLBYTES, /* maxsize */
2264 MCLBYTES, /* maxsegsize */
2266 NULL, NULL, /* lockfunc, lockarg */
2267 &sc->alc_cdata.alc_rx_tag);
2269 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n");
2272 /* Create DMA maps for Tx buffers. */
2273 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2274 txd = &sc->alc_cdata.alc_txdesc[i];
2276 txd->tx_dmamap = NULL;
2277 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
2280 device_printf(sc->alc_dev,
2281 "could not create Tx dmamap.\n");
2285 /* Create DMA maps for Rx buffers. */
2286 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2287 &sc->alc_cdata.alc_rx_sparemap)) != 0) {
2288 device_printf(sc->alc_dev,
2289 "could not create spare Rx dmamap.\n");
2292 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2293 rxd = &sc->alc_cdata.alc_rxdesc[i];
2295 rxd->rx_dmamap = NULL;
2296 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2299 device_printf(sc->alc_dev,
2300 "could not create Rx dmamap.\n");
2310 alc_dma_free(struct alc_softc *sc)
2312 struct alc_txdesc *txd;
2313 struct alc_rxdesc *rxd;
2317 if (sc->alc_cdata.alc_tx_tag != NULL) {
2318 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2319 txd = &sc->alc_cdata.alc_txdesc[i];
2320 if (txd->tx_dmamap != NULL) {
2321 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag,
2323 txd->tx_dmamap = NULL;
2326 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag);
2327 sc->alc_cdata.alc_tx_tag = NULL;
2330 if (sc->alc_cdata.alc_rx_tag != NULL) {
2331 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2332 rxd = &sc->alc_cdata.alc_rxdesc[i];
2333 if (rxd->rx_dmamap != NULL) {
2334 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2336 rxd->rx_dmamap = NULL;
2339 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
2340 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag,
2341 sc->alc_cdata.alc_rx_sparemap);
2342 sc->alc_cdata.alc_rx_sparemap = NULL;
2344 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag);
2345 sc->alc_cdata.alc_rx_tag = NULL;
2347 /* Tx descriptor ring. */
2348 if (sc->alc_cdata.alc_tx_ring_tag != NULL) {
2349 if (sc->alc_rdata.alc_tx_ring_paddr != 0)
2350 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag,
2351 sc->alc_cdata.alc_tx_ring_map);
2352 if (sc->alc_rdata.alc_tx_ring != NULL)
2353 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag,
2354 sc->alc_rdata.alc_tx_ring,
2355 sc->alc_cdata.alc_tx_ring_map);
2356 sc->alc_rdata.alc_tx_ring_paddr = 0;
2357 sc->alc_rdata.alc_tx_ring = NULL;
2358 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag);
2359 sc->alc_cdata.alc_tx_ring_tag = NULL;
2362 if (sc->alc_cdata.alc_rx_ring_tag != NULL) {
2363 if (sc->alc_rdata.alc_rx_ring_paddr != 0)
2364 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag,
2365 sc->alc_cdata.alc_rx_ring_map);
2366 if (sc->alc_rdata.alc_rx_ring != NULL)
2367 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag,
2368 sc->alc_rdata.alc_rx_ring,
2369 sc->alc_cdata.alc_rx_ring_map);
2370 sc->alc_rdata.alc_rx_ring_paddr = 0;
2371 sc->alc_rdata.alc_rx_ring = NULL;
2372 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag);
2373 sc->alc_cdata.alc_rx_ring_tag = NULL;
2375 /* Rx return ring. */
2376 if (sc->alc_cdata.alc_rr_ring_tag != NULL) {
2377 if (sc->alc_rdata.alc_rr_ring_paddr != 0)
2378 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag,
2379 sc->alc_cdata.alc_rr_ring_map);
2380 if (sc->alc_rdata.alc_rr_ring != NULL)
2381 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag,
2382 sc->alc_rdata.alc_rr_ring,
2383 sc->alc_cdata.alc_rr_ring_map);
2384 sc->alc_rdata.alc_rr_ring_paddr = 0;
2385 sc->alc_rdata.alc_rr_ring = NULL;
2386 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag);
2387 sc->alc_cdata.alc_rr_ring_tag = NULL;
2390 if (sc->alc_cdata.alc_cmb_tag != NULL) {
2391 if (sc->alc_rdata.alc_cmb_paddr != 0)
2392 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag,
2393 sc->alc_cdata.alc_cmb_map);
2394 if (sc->alc_rdata.alc_cmb != NULL)
2395 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag,
2396 sc->alc_rdata.alc_cmb,
2397 sc->alc_cdata.alc_cmb_map);
2398 sc->alc_rdata.alc_cmb_paddr = 0;
2399 sc->alc_rdata.alc_cmb = NULL;
2400 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag);
2401 sc->alc_cdata.alc_cmb_tag = NULL;
2404 if (sc->alc_cdata.alc_smb_tag != NULL) {
2405 if (sc->alc_rdata.alc_smb_paddr != 0)
2406 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag,
2407 sc->alc_cdata.alc_smb_map);
2408 if (sc->alc_rdata.alc_smb != NULL)
2409 bus_dmamem_free(sc->alc_cdata.alc_smb_tag,
2410 sc->alc_rdata.alc_smb,
2411 sc->alc_cdata.alc_smb_map);
2412 sc->alc_rdata.alc_smb_paddr = 0;
2413 sc->alc_rdata.alc_smb = NULL;
2414 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag);
2415 sc->alc_cdata.alc_smb_tag = NULL;
2417 if (sc->alc_cdata.alc_buffer_tag != NULL) {
2418 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag);
2419 sc->alc_cdata.alc_buffer_tag = NULL;
2421 if (sc->alc_cdata.alc_parent_tag != NULL) {
2422 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag);
2423 sc->alc_cdata.alc_parent_tag = NULL;
2428 alc_shutdown(device_t dev)
2431 return (alc_suspend(dev));
2435 * Note, this driver resets the link speed to 10/100Mbps by
2436 * restarting auto-negotiation in suspend/shutdown phase but we
2437 * don't know whether that auto-negotiation would succeed or not
2438 * as driver has no control after powering off/suspend operation.
2439 * If the renegotiation fail WOL may not work. Running at 1Gbps
2440 * will draw more power than 375mA at 3.3V which is specified in
2441 * PCI specification and that would result in complete
2442 * shutdowning power to ethernet controller.
2445 * Save current negotiated media speed/duplex/flow-control to
2446 * softc and restore the same link again after resuming. PHY
2447 * handling such as power down/resetting to 100Mbps may be better
2448 * handled in suspend method in phy driver.
2451 alc_setlinkspeed(struct alc_softc *sc)
2453 struct mii_data *mii;
2456 mii = device_get_softc(sc->alc_miibus);
2459 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2460 (IFM_ACTIVE | IFM_AVALID)) {
2461 switch IFM_SUBTYPE(mii->mii_media_active) {
2472 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
2473 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2474 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
2475 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr,
2476 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
2480 * Poll link state until alc(4) get a 10/100Mbps link.
2482 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
2484 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
2485 == (IFM_ACTIVE | IFM_AVALID)) {
2486 switch (IFM_SUBTYPE(
2487 mii->mii_media_active)) {
2497 pause("alclnk", hz);
2500 if (i == MII_ANEGTICKS_GIGE)
2501 device_printf(sc->alc_dev,
2502 "establishing a link failed, WOL may not work!");
2505 * No link, force MAC to have 100Mbps, full-duplex link.
2506 * This is the last resort and may/may not work.
2508 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
2509 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
2514 alc_setwol(struct alc_softc *sc)
2517 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2518 alc_setwol_816x(sc);
2520 alc_setwol_813x(sc);
2524 alc_setwol_813x(struct alc_softc *sc)
2530 ALC_LOCK_ASSERT(sc);
2532 alc_disable_l0s_l1(sc);
2534 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2536 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2537 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2538 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2539 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2540 /* Force PHY power down. */
2542 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2543 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2547 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2548 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2549 alc_setlinkspeed(sc);
2550 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2551 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
2555 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2556 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2557 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2558 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2559 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2561 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2562 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2563 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2564 reg |= MAC_CFG_RX_ENB;
2565 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2567 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
2568 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
2569 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
2570 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
2571 /* WOL disabled, PHY power down. */
2573 CSR_WRITE_4(sc, ALC_MASTER_CFG,
2574 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
2577 pmstat = pci_read_config(sc->alc_dev,
2578 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2579 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2580 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2581 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2582 pci_write_config(sc->alc_dev,
2583 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2587 alc_setwol_816x(struct alc_softc *sc)
2590 uint32_t gphy, mac, master, pmcs, reg;
2593 ALC_LOCK_ASSERT(sc);
2596 master = CSR_READ_4(sc, ALC_MASTER_CFG);
2597 master &= ~MASTER_CLK_SEL_DIS;
2598 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
2599 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB |
2600 GPHY_CFG_PHY_PLL_ON);
2601 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET;
2602 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2603 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2604 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW;
2605 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2607 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2608 gphy |= GPHY_CFG_EXT_RESET;
2609 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2610 alc_setlinkspeed(sc);
2613 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2614 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
2615 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs);
2616 mac = CSR_READ_4(sc, ALC_MAC_CFG);
2617 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
2619 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2620 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
2621 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2622 mac |= MAC_CFG_RX_ENB;
2623 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
2628 reg = CSR_READ_4(sc, ALC_MISC);
2629 reg &= ~MISC_INTNLOSC_OPEN;
2630 CSR_WRITE_4(sc, ALC_MISC, reg);
2631 reg |= MISC_INTNLOSC_OPEN;
2632 CSR_WRITE_4(sc, ALC_MISC, reg);
2633 CSR_WRITE_4(sc, ALC_MASTER_CFG, master);
2634 CSR_WRITE_4(sc, ALC_MAC_CFG, mac);
2635 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
2636 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1);
2637 reg |= PDLL_TRNS1_D3PLLOFF_ENB;
2638 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg);
2640 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2642 pmstat = pci_read_config(sc->alc_dev,
2643 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2644 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2645 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2646 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2647 pci_write_config(sc->alc_dev,
2648 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2653 alc_suspend(device_t dev)
2655 struct alc_softc *sc;
2657 sc = device_get_softc(dev);
2668 alc_resume(device_t dev)
2670 struct alc_softc *sc;
2674 sc = device_get_softc(dev);
2677 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2678 /* Disable PME and clear PME status. */
2679 pmstat = pci_read_config(sc->alc_dev,
2680 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
2681 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2682 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2683 pci_write_config(sc->alc_dev,
2684 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2690 if ((ifp->if_flags & IFF_UP) != 0) {
2691 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2692 alc_init_locked(sc);
2700 alc_encap(struct alc_softc *sc, struct mbuf **m_head)
2702 struct alc_txdesc *txd, *txd_last;
2703 struct tx_desc *desc;
2707 bus_dma_segment_t txsegs[ALC_MAXTXSEGS];
2709 uint32_t cflags, hdrlen, ip_off, poff, vtag;
2710 int error, idx, nsegs, prod;
2712 ALC_LOCK_ASSERT(sc);
2714 M_ASSERTPKTHDR((*m_head));
2720 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
2722 * AR81[3567]x requires offset of TCP/UDP header in its
2723 * Tx descriptor to perform Tx checksum offloading. TSO
2724 * also requires TCP header offset and modification of
2725 * IP/TCP header. This kind of operation takes many CPU
2726 * cycles on FreeBSD so fast host CPU is required to get
2727 * smooth TSO performance.
2729 struct ether_header *eh;
2731 if (M_WRITABLE(m) == 0) {
2732 /* Get a writable copy. */
2733 m = m_dup(*m_head, M_NOWAIT);
2734 /* Release original mbufs. */
2743 ip_off = sizeof(struct ether_header);
2744 m = m_pullup(m, ip_off);
2749 eh = mtod(m, struct ether_header *);
2751 * Check if hardware VLAN insertion is off.
2752 * Additional check for LLC/SNAP frame?
2754 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2755 ip_off = sizeof(struct ether_vlan_header);
2756 m = m_pullup(m, ip_off);
2762 m = m_pullup(m, ip_off + sizeof(struct ip));
2767 ip = (struct ip *)(mtod(m, char *) + ip_off);
2768 poff = ip_off + (ip->ip_hl << 2);
2769 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2770 m = m_pullup(m, poff + sizeof(struct tcphdr));
2775 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2776 m = m_pullup(m, poff + (tcp->th_off << 2));
2782 * Due to strict adherence of Microsoft NDIS
2783 * Large Send specification, hardware expects
2784 * a pseudo TCP checksum inserted by upper
2785 * stack. Unfortunately the pseudo TCP
2786 * checksum that NDIS refers to does not include
2787 * TCP payload length so driver should recompute
2788 * the pseudo checksum here. Hopefully this
2789 * wouldn't be much burden on modern CPUs.
2791 * Reset IP checksum and recompute TCP pseudo
2792 * checksum as NDIS specification said.
2794 ip = (struct ip *)(mtod(m, char *) + ip_off);
2795 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
2797 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
2798 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2803 prod = sc->alc_cdata.alc_tx_prod;
2804 txd = &sc->alc_cdata.alc_txdesc[prod];
2806 map = txd->tx_dmamap;
2808 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2809 *m_head, txsegs, &nsegs, 0);
2810 if (error == EFBIG) {
2811 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS);
2818 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map,
2819 *m_head, txsegs, &nsegs, 0);
2825 } else if (error != 0)
2833 /* Check descriptor overrun. */
2834 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) {
2835 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map);
2838 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE);
2841 cflags = TD_ETHERNET;
2845 /* Configure VLAN hardware tag insertion. */
2846 if ((m->m_flags & M_VLANTAG) != 0) {
2847 vtag = htons(m->m_pkthdr.ether_vtag);
2848 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK;
2849 cflags |= TD_INS_VLAN_TAG;
2851 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2852 /* Request TSO and set MSS. */
2853 cflags |= TD_TSO | TD_TSO_DESCV1;
2854 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) &
2856 /* Set TCP header offset. */
2857 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) &
2858 TD_TCPHDR_OFFSET_MASK;
2860 * AR81[3567]x requires the first buffer should
2861 * only hold IP/TCP header data. Payload should
2862 * be handled in other descriptors.
2864 hdrlen = poff + (tcp->th_off << 2);
2865 desc = &sc->alc_rdata.alc_tx_ring[prod];
2866 desc->len = htole32(TX_BYTES(hdrlen | vtag));
2867 desc->flags = htole32(cflags);
2868 desc->addr = htole64(txsegs[0].ds_addr);
2869 sc->alc_cdata.alc_tx_cnt++;
2870 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2871 if (m->m_len - hdrlen > 0) {
2872 /* Handle remaining payload of the first fragment. */
2873 desc = &sc->alc_rdata.alc_tx_ring[prod];
2874 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) |
2876 desc->flags = htole32(cflags);
2877 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2878 sc->alc_cdata.alc_tx_cnt++;
2879 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2881 /* Handle remaining fragments. */
2883 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2884 /* Configure Tx checksum offload. */
2885 #ifdef ALC_USE_CUSTOM_CSUM
2886 cflags |= TD_CUSTOM_CSUM;
2887 /* Set checksum start offset. */
2888 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) &
2889 TD_PLOAD_OFFSET_MASK;
2890 /* Set checksum insertion position of TCP/UDP. */
2891 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) <<
2892 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK;
2894 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2895 cflags |= TD_IPCSUM;
2896 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2897 cflags |= TD_TCPCSUM;
2898 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2899 cflags |= TD_UDPCSUM;
2900 /* Set TCP/UDP header offset. */
2901 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) &
2902 TD_L4HDR_OFFSET_MASK;
2905 for (; idx < nsegs; idx++) {
2906 desc = &sc->alc_rdata.alc_tx_ring[prod];
2907 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag);
2908 desc->flags = htole32(cflags);
2909 desc->addr = htole64(txsegs[idx].ds_addr);
2910 sc->alc_cdata.alc_tx_cnt++;
2911 ALC_DESC_INC(prod, ALC_TX_RING_CNT);
2913 /* Update producer index. */
2914 sc->alc_cdata.alc_tx_prod = prod;
2916 /* Finally set EOP on the last descriptor. */
2917 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT;
2918 desc = &sc->alc_rdata.alc_tx_ring[prod];
2919 desc->flags |= htole32(TD_EOP);
2921 /* Swap dmamap of the first and the last. */
2922 txd = &sc->alc_cdata.alc_txdesc[prod];
2923 map = txd_last->tx_dmamap;
2924 txd_last->tx_dmamap = txd->tx_dmamap;
2925 txd->tx_dmamap = map;
2932 alc_start(struct ifnet *ifp)
2934 struct alc_softc *sc;
2938 alc_start_locked(ifp);
2943 alc_start_locked(struct ifnet *ifp)
2945 struct alc_softc *sc;
2946 struct mbuf *m_head;
2951 ALC_LOCK_ASSERT(sc);
2953 /* Reclaim transmitted frames. */
2954 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
2957 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2958 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0)
2961 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
2962 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2966 * Pack the data into the transmit ring. If we
2967 * don't have room, set the OACTIVE flag and wait
2968 * for the NIC to drain the ring.
2970 if (alc_encap(sc, &m_head)) {
2973 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2974 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2980 * If there's a BPF listener, bounce a copy of this frame
2983 ETHER_BPF_MTAP(ifp, m_head);
2991 alc_start_tx(struct alc_softc *sc)
2994 /* Sync descriptors. */
2995 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
2996 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
2997 /* Kick. Assume we're using normal Tx priority queue. */
2998 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2999 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
3000 (uint16_t)sc->alc_cdata.alc_tx_prod);
3002 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
3003 (sc->alc_cdata.alc_tx_prod <<
3004 MBOX_TD_PROD_LO_IDX_SHIFT) &
3005 MBOX_TD_PROD_LO_IDX_MASK);
3006 /* Set a timeout in case the chip goes out to lunch. */
3007 sc->alc_watchdog_timer = ALC_TX_TIMEOUT;
3011 alc_watchdog(struct alc_softc *sc)
3015 ALC_LOCK_ASSERT(sc);
3017 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
3021 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
3022 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n");
3023 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3025 alc_init_locked(sc);
3028 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n");
3029 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3030 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3031 alc_init_locked(sc);
3032 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3033 alc_start_locked(ifp);
3037 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3039 struct alc_softc *sc;
3041 struct mii_data *mii;
3045 ifr = (struct ifreq *)data;
3049 if (ifr->ifr_mtu < ETHERMIN ||
3050 ifr->ifr_mtu > (sc->alc_ident->max_framelen -
3051 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) ||
3052 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
3053 ifr->ifr_mtu > ETHERMTU))
3055 else if (ifp->if_mtu != ifr->ifr_mtu) {
3057 ifp->if_mtu = ifr->ifr_mtu;
3058 /* AR81[3567]x has 13 bits MSS field. */
3059 if (ifp->if_mtu > ALC_TSO_MTU &&
3060 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3061 ifp->if_capenable &= ~IFCAP_TSO4;
3062 ifp->if_hwassist &= ~CSUM_TSO;
3063 VLAN_CAPABILITIES(ifp);
3070 if ((ifp->if_flags & IFF_UP) != 0) {
3071 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3072 ((ifp->if_flags ^ sc->alc_if_flags) &
3073 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3076 alc_init_locked(sc);
3077 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3079 sc->alc_if_flags = ifp->if_flags;
3085 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3091 mii = device_get_softc(sc->alc_miibus);
3092 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
3096 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3097 if ((mask & IFCAP_TXCSUM) != 0 &&
3098 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3099 ifp->if_capenable ^= IFCAP_TXCSUM;
3100 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3101 ifp->if_hwassist |= ALC_CSUM_FEATURES;
3103 ifp->if_hwassist &= ~ALC_CSUM_FEATURES;
3105 if ((mask & IFCAP_TSO4) != 0 &&
3106 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3107 ifp->if_capenable ^= IFCAP_TSO4;
3108 if ((ifp->if_capenable & IFCAP_TSO4) != 0) {
3109 /* AR81[3567]x has 13 bits MSS field. */
3110 if (ifp->if_mtu > ALC_TSO_MTU) {
3111 ifp->if_capenable &= ~IFCAP_TSO4;
3112 ifp->if_hwassist &= ~CSUM_TSO;
3114 ifp->if_hwassist |= CSUM_TSO;
3116 ifp->if_hwassist &= ~CSUM_TSO;
3118 if ((mask & IFCAP_WOL_MCAST) != 0 &&
3119 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
3120 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3121 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3122 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3123 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3124 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3125 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3126 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3129 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3130 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3131 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3132 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3133 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3134 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3135 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3136 ifp->if_capenable &=
3137 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
3139 VLAN_CAPABILITIES(ifp);
3142 error = ether_ioctl(ifp, cmd, data);
3150 alc_mac_config(struct alc_softc *sc)
3152 struct mii_data *mii;
3155 ALC_LOCK_ASSERT(sc);
3157 mii = device_get_softc(sc->alc_miibus);
3158 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3159 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
3160 MAC_CFG_SPEED_MASK);
3161 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3162 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
3163 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
3164 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
3165 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
3166 /* Reprogram MAC with resolved speed/duplex. */
3167 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3170 reg |= MAC_CFG_SPEED_10_100;
3173 reg |= MAC_CFG_SPEED_1000;
3176 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
3177 reg |= MAC_CFG_FULL_DUPLEX;
3178 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
3179 reg |= MAC_CFG_TX_FC;
3180 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
3181 reg |= MAC_CFG_RX_FC;
3183 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3187 alc_stats_clear(struct alc_softc *sc)
3189 struct smb sb, *smb;
3193 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3194 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3195 sc->alc_cdata.alc_smb_map,
3196 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3197 smb = sc->alc_rdata.alc_smb;
3198 /* Update done, clear. */
3200 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3201 sc->alc_cdata.alc_smb_map,
3202 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3204 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3206 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3207 i += sizeof(uint32_t);
3209 /* Read Tx statistics. */
3210 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3212 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3213 i += sizeof(uint32_t);
3219 alc_stats_update(struct alc_softc *sc)
3221 struct alc_hw_stats *stat;
3222 struct smb sb, *smb;
3227 ALC_LOCK_ASSERT(sc);
3230 stat = &sc->alc_stats;
3231 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3232 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3233 sc->alc_cdata.alc_smb_map,
3234 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3235 smb = sc->alc_rdata.alc_smb;
3236 if (smb->updated == 0)
3240 /* Read Rx statistics. */
3241 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3243 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
3244 i += sizeof(uint32_t);
3246 /* Read Tx statistics. */
3247 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3249 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
3250 i += sizeof(uint32_t);
3255 stat->rx_frames += smb->rx_frames;
3256 stat->rx_bcast_frames += smb->rx_bcast_frames;
3257 stat->rx_mcast_frames += smb->rx_mcast_frames;
3258 stat->rx_pause_frames += smb->rx_pause_frames;
3259 stat->rx_control_frames += smb->rx_control_frames;
3260 stat->rx_crcerrs += smb->rx_crcerrs;
3261 stat->rx_lenerrs += smb->rx_lenerrs;
3262 stat->rx_bytes += smb->rx_bytes;
3263 stat->rx_runts += smb->rx_runts;
3264 stat->rx_fragments += smb->rx_fragments;
3265 stat->rx_pkts_64 += smb->rx_pkts_64;
3266 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
3267 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
3268 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
3269 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
3270 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
3271 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
3272 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
3273 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
3274 stat->rx_rrs_errs += smb->rx_rrs_errs;
3275 stat->rx_alignerrs += smb->rx_alignerrs;
3276 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
3277 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
3278 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
3281 stat->tx_frames += smb->tx_frames;
3282 stat->tx_bcast_frames += smb->tx_bcast_frames;
3283 stat->tx_mcast_frames += smb->tx_mcast_frames;
3284 stat->tx_pause_frames += smb->tx_pause_frames;
3285 stat->tx_excess_defer += smb->tx_excess_defer;
3286 stat->tx_control_frames += smb->tx_control_frames;
3287 stat->tx_deferred += smb->tx_deferred;
3288 stat->tx_bytes += smb->tx_bytes;
3289 stat->tx_pkts_64 += smb->tx_pkts_64;
3290 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
3291 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
3292 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
3293 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
3294 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
3295 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
3296 stat->tx_single_colls += smb->tx_single_colls;
3297 stat->tx_multi_colls += smb->tx_multi_colls;
3298 stat->tx_late_colls += smb->tx_late_colls;
3299 stat->tx_excess_colls += smb->tx_excess_colls;
3300 stat->tx_underrun += smb->tx_underrun;
3301 stat->tx_desc_underrun += smb->tx_desc_underrun;
3302 stat->tx_lenerrs += smb->tx_lenerrs;
3303 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
3304 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
3305 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
3307 /* Update counters in ifnet. */
3308 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
3310 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
3311 smb->tx_multi_colls * 2 + smb->tx_late_colls +
3312 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
3314 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
3315 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
3317 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
3319 if_inc_counter(ifp, IFCOUNTER_IERRORS,
3320 smb->rx_crcerrs + smb->rx_lenerrs +
3321 smb->rx_runts + smb->rx_pkts_truncated +
3322 smb->rx_fifo_oflows + smb->rx_rrs_errs +
3325 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3326 /* Update done, clear. */
3328 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag,
3329 sc->alc_cdata.alc_smb_map,
3330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3337 struct alc_softc *sc;
3340 sc = (struct alc_softc *)arg;
3342 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3343 if ((status & ALC_INTRS) == 0)
3344 return (FILTER_STRAY);
3345 /* Disable interrupts. */
3346 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
3347 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3349 return (FILTER_HANDLED);
3353 alc_int_task(void *arg, int pending)
3355 struct alc_softc *sc;
3360 sc = (struct alc_softc *)arg;
3363 status = CSR_READ_4(sc, ALC_INTR_STATUS);
3365 if (sc->alc_morework != 0) {
3366 sc->alc_morework = 0;
3367 status |= INTR_RX_PKT;
3369 if ((status & ALC_INTRS) == 0)
3372 /* Acknowledge interrupts but still disable interrupts. */
3373 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
3376 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3377 if ((status & INTR_RX_PKT) != 0) {
3378 more = alc_rxintr(sc, sc->alc_process_limit);
3380 sc->alc_morework = 1;
3381 else if (more == EIO) {
3382 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3383 alc_init_locked(sc);
3388 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |
3389 INTR_TXQ_TO_RST)) != 0) {
3390 if ((status & INTR_DMA_RD_TO_RST) != 0)
3391 device_printf(sc->alc_dev,
3392 "DMA read error! -- resetting\n");
3393 if ((status & INTR_DMA_WR_TO_RST) != 0)
3394 device_printf(sc->alc_dev,
3395 "DMA write error! -- resetting\n");
3396 if ((status & INTR_TXQ_TO_RST) != 0)
3397 device_printf(sc->alc_dev,
3398 "TxQ reset! -- resetting\n");
3399 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3400 alc_init_locked(sc);
3404 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3405 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3406 alc_start_locked(ifp);
3409 if (more == EAGAIN ||
3410 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
3412 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task);
3417 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3418 /* Re-enable interrupts if we're running. */
3419 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
3425 alc_txeof(struct alc_softc *sc)
3428 struct alc_txdesc *txd;
3429 uint32_t cons, prod;
3432 ALC_LOCK_ASSERT(sc);
3436 if (sc->alc_cdata.alc_tx_cnt == 0)
3438 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
3439 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3440 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3441 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3442 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD);
3443 prod = sc->alc_rdata.alc_cmb->cons;
3445 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3446 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
3448 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
3449 /* Assume we're using normal Tx priority queue. */
3450 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >>
3451 MBOX_TD_CONS_LO_IDX_SHIFT;
3454 cons = sc->alc_cdata.alc_tx_cons;
3456 * Go through our Tx list and free mbufs for those
3457 * frames which have been transmitted.
3459 for (prog = 0; cons != prod; prog++,
3460 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) {
3461 if (sc->alc_cdata.alc_tx_cnt <= 0)
3464 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3465 sc->alc_cdata.alc_tx_cnt--;
3466 txd = &sc->alc_cdata.alc_txdesc[cons];
3467 if (txd->tx_m != NULL) {
3468 /* Reclaim transmitted mbufs. */
3469 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
3470 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3471 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
3478 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3479 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag,
3480 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD);
3481 sc->alc_cdata.alc_tx_cons = cons;
3483 * Unarm watchdog timer only when there is no pending
3484 * frames in Tx queue.
3486 if (sc->alc_cdata.alc_tx_cnt == 0)
3487 sc->alc_watchdog_timer = 0;
3491 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
3494 bus_dma_segment_t segs[1];
3498 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3501 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX;
3502 #ifndef __NO_STRICT_ALIGNMENT
3503 m_adj(m, sizeof(uint64_t));
3506 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag,
3507 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3511 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3513 if (rxd->rx_m != NULL) {
3514 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3515 BUS_DMASYNC_POSTREAD);
3516 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap);
3518 map = rxd->rx_dmamap;
3519 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
3520 sc->alc_cdata.alc_rx_sparemap = map;
3521 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap,
3522 BUS_DMASYNC_PREREAD);
3524 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
3529 alc_rxintr(struct alc_softc *sc, int count)
3532 struct rx_rdesc *rrd;
3533 uint32_t nsegs, status;
3536 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3537 sc->alc_cdata.alc_rr_ring_map,
3538 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3539 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3540 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE);
3541 rr_cons = sc->alc_cdata.alc_rr_cons;
3543 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) {
3546 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
3547 status = le32toh(rrd->status);
3548 if ((status & RRD_VALID) == 0)
3550 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo));
3552 /* This should not happen! */
3553 device_printf(sc->alc_dev,
3554 "unexpected segment count -- resetting\n");
3558 /* Clear Rx return status. */
3560 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT);
3561 sc->alc_cdata.alc_rx_cons += nsegs;
3562 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
3567 /* Update the consumer index. */
3568 sc->alc_cdata.alc_rr_cons = rr_cons;
3569 /* Sync Rx return descriptors. */
3570 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
3571 sc->alc_cdata.alc_rr_ring_map,
3572 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3574 * Sync updated Rx descriptors such that controller see
3575 * modified buffer addresses.
3577 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
3578 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
3580 * Let controller know availability of new Rx buffers.
3581 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors
3582 * it may be possible to update ALC_MBOX_RD0_PROD_IDX
3583 * only when Rx buffer pre-fetching is required. In
3584 * addition we already set ALC_RX_RD_FREE_THRESH to
3585 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However
3586 * it still seems that pre-fetching needs more
3589 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3590 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
3591 (uint16_t)sc->alc_cdata.alc_rx_cons);
3593 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
3594 sc->alc_cdata.alc_rx_cons);
3597 return (count > 0 ? 0 : EAGAIN);
3600 #ifndef __NO_STRICT_ALIGNMENT
3601 static struct mbuf *
3602 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m)
3606 uint16_t *src, *dst;
3608 src = mtod(m, uint16_t *);
3611 if (m->m_next == NULL) {
3612 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3618 * Append a new mbuf to received mbuf chain and copy ethernet
3619 * header from the mbuf chain. This can save lots of CPU
3620 * cycles for jumbo frame.
3622 MGETHDR(n, M_NOWAIT, MT_DATA);
3624 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3628 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
3629 m->m_data += ETHER_HDR_LEN;
3630 m->m_len -= ETHER_HDR_LEN;
3631 n->m_len = ETHER_HDR_LEN;
3632 M_MOVE_PKTHDR(n, m);
3638 /* Receive a frame. */
3640 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
3642 struct alc_rxdesc *rxd;
3644 struct mbuf *mp, *m;
3645 uint32_t rdinfo, status, vtag;
3646 int count, nsegs, rx_cons;
3649 status = le32toh(rrd->status);
3650 rdinfo = le32toh(rrd->rdinfo);
3651 rx_cons = RRD_RD_IDX(rdinfo);
3652 nsegs = RRD_RD_CNT(rdinfo);
3654 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
3655 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
3657 * We want to pass the following frames to upper
3658 * layer regardless of error status of Rx return
3661 * o IP/TCP/UDP checksum is bad.
3662 * o frame length and protocol specific length
3665 * Force network stack compute checksum for
3668 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK;
3669 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN |
3670 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
3674 for (count = 0; count < nsegs; count++,
3675 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) {
3676 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
3678 /* Add a new receive buffer to the ring. */
3679 if (alc_newbuf(sc, rxd) != 0) {
3680 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3681 /* Reuse Rx buffers. */
3682 if (sc->alc_cdata.alc_rxhead != NULL)
3683 m_freem(sc->alc_cdata.alc_rxhead);
3688 * Assume we've received a full sized frame.
3689 * Actual size is fixed when we encounter the end of
3690 * multi-segmented frame.
3692 mp->m_len = sc->alc_buf_size;
3694 /* Chain received mbufs. */
3695 if (sc->alc_cdata.alc_rxhead == NULL) {
3696 sc->alc_cdata.alc_rxhead = mp;
3697 sc->alc_cdata.alc_rxtail = mp;
3699 mp->m_flags &= ~M_PKTHDR;
3700 sc->alc_cdata.alc_rxprev_tail =
3701 sc->alc_cdata.alc_rxtail;
3702 sc->alc_cdata.alc_rxtail->m_next = mp;
3703 sc->alc_cdata.alc_rxtail = mp;
3706 if (count == nsegs - 1) {
3707 /* Last desc. for this frame. */
3708 m = sc->alc_cdata.alc_rxhead;
3709 m->m_flags |= M_PKTHDR;
3711 * It seems that L1C/L2C controller has no way
3712 * to tell hardware to strip CRC bytes.
3715 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
3717 /* Set last mbuf size. */
3718 mp->m_len = sc->alc_cdata.alc_rxlen -
3719 (nsegs - 1) * sc->alc_buf_size;
3720 /* Remove the CRC bytes in chained mbufs. */
3721 if (mp->m_len <= ETHER_CRC_LEN) {
3722 sc->alc_cdata.alc_rxtail =
3723 sc->alc_cdata.alc_rxprev_tail;
3724 sc->alc_cdata.alc_rxtail->m_len -=
3725 (ETHER_CRC_LEN - mp->m_len);
3726 sc->alc_cdata.alc_rxtail->m_next = NULL;
3729 mp->m_len -= ETHER_CRC_LEN;
3732 m->m_len = m->m_pkthdr.len;
3733 m->m_pkthdr.rcvif = ifp;
3735 * Due to hardware bugs, Rx checksum offloading
3736 * was intentionally disabled.
3738 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
3739 (status & RRD_VLAN_TAG) != 0) {
3740 vtag = RRD_VLAN(le32toh(rrd->vtag));
3741 m->m_pkthdr.ether_vtag = ntohs(vtag);
3742 m->m_flags |= M_VLANTAG;
3744 #ifndef __NO_STRICT_ALIGNMENT
3745 m = alc_fixup_rx(ifp, m);
3751 (*ifp->if_input)(ifp, m);
3756 /* Reset mbuf chains. */
3757 ALC_RXCHAIN_RESET(sc);
3763 struct alc_softc *sc;
3764 struct mii_data *mii;
3766 sc = (struct alc_softc *)arg;
3768 ALC_LOCK_ASSERT(sc);
3770 mii = device_get_softc(sc->alc_miibus);
3772 alc_stats_update(sc);
3774 * alc(4) does not rely on Tx completion interrupts to reclaim
3775 * transferred buffers. Instead Tx completion interrupts are
3776 * used to hint for scheduling Tx task. So it's necessary to
3777 * release transmitted buffers by kicking Tx completion
3778 * handler. This limits the maximum reclamation delay to a hz.
3782 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
3786 alc_osc_reset(struct alc_softc *sc)
3790 reg = CSR_READ_4(sc, ALC_MISC3);
3791 reg &= ~MISC3_25M_BY_SW;
3792 reg |= MISC3_25M_NOTO_INTNL;
3793 CSR_WRITE_4(sc, ALC_MISC3, reg);
3795 reg = CSR_READ_4(sc, ALC_MISC);
3796 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
3798 * Restore over-current protection default value.
3799 * This value could be reset by MAC reset.
3801 reg &= ~MISC_PSW_OCP_MASK;
3802 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);
3803 reg &= ~MISC_INTNLOSC_OPEN;
3804 CSR_WRITE_4(sc, ALC_MISC, reg);
3805 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3806 reg = CSR_READ_4(sc, ALC_MISC2);
3807 reg &= ~MISC2_CALB_START;
3808 CSR_WRITE_4(sc, ALC_MISC2, reg);
3809 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
3812 reg &= ~MISC_INTNLOSC_OPEN;
3813 /* Disable isolate for revision A devices. */
3814 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3815 reg &= ~MISC_ISO_ENB;
3816 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
3817 CSR_WRITE_4(sc, ALC_MISC, reg);
3824 alc_reset(struct alc_softc *sc)
3826 uint32_t pmcfg, reg;
3830 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3831 /* Reset workaround. */
3832 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
3833 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3834 (sc->alc_rev & 0x01) != 0) {
3835 /* Disable L0s/L1s before reset. */
3836 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
3837 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3839 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
3840 PM_CFG_ASPM_L1_ENB);
3841 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3845 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3846 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;
3847 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3849 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3850 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3852 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
3856 device_printf(sc->alc_dev, "MAC reset timeout!\n");
3858 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3860 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
3864 device_printf(sc->alc_dev, "master reset timeout!\n");
3866 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3867 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3868 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |
3869 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3874 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
3876 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3877 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
3878 (sc->alc_rev & 0x01) != 0) {
3879 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3880 reg |= MASTER_CLK_SEL_DIS;
3881 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
3882 /* Restore L0s/L1s config. */
3883 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
3885 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
3889 reg = CSR_READ_4(sc, ALC_MISC3);
3890 reg &= ~MISC3_25M_BY_SW;
3891 reg |= MISC3_25M_NOTO_INTNL;
3892 CSR_WRITE_4(sc, ALC_MISC3, reg);
3893 reg = CSR_READ_4(sc, ALC_MISC);
3894 reg &= ~MISC_INTNLOSC_OPEN;
3895 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
3896 reg &= ~MISC_ISO_ENB;
3897 CSR_WRITE_4(sc, ALC_MISC, reg);
3900 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3901 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
3902 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2)
3903 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
3904 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
3905 SERDES_PHY_CLK_SLOWDOWN);
3911 struct alc_softc *sc;
3913 sc = (struct alc_softc *)xsc;
3915 alc_init_locked(sc);
3920 alc_init_locked(struct alc_softc *sc)
3923 struct mii_data *mii;
3924 uint8_t eaddr[ETHER_ADDR_LEN];
3926 uint32_t reg, rxf_hi, rxf_lo;
3928 ALC_LOCK_ASSERT(sc);
3931 mii = device_get_softc(sc->alc_miibus);
3933 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3936 * Cancel any pending I/O.
3940 * Reset the chip to a known state.
3944 /* Initialize Rx descriptors. */
3945 if (alc_init_rx_ring(sc) != 0) {
3946 device_printf(sc->alc_dev, "no memory for Rx buffers.\n");
3950 alc_init_rr_ring(sc);
3951 alc_init_tx_ring(sc);
3955 /* Enable all clocks. */
3956 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3957 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
3958 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
3959 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
3960 CLK_GATING_RXMAC_ENB);
3961 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
3962 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
3963 IDLE_DECISN_TIMER_DEFAULT_1MS);
3965 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
3967 /* Reprogram the station address. */
3968 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3969 CSR_WRITE_4(sc, ALC_PAR0,
3970 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
3971 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
3973 * Clear WOL status and disable all WOL feature as WOL
3974 * would interfere Rx operation under normal environments.
3976 CSR_READ_4(sc, ALC_WOL_CFG);
3977 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
3978 /* Set Tx descriptor base addresses. */
3979 paddr = sc->alc_rdata.alc_tx_ring_paddr;
3980 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3981 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3982 /* We don't use high priority ring. */
3983 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
3984 /* Set Tx descriptor counter. */
3985 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
3986 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
3987 /* Set Rx descriptor base addresses. */
3988 paddr = sc->alc_rdata.alc_rx_ring_paddr;
3989 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
3990 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
3991 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3992 /* We use one Rx ring. */
3993 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
3994 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
3995 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
3997 /* Set Rx descriptor counter. */
3998 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
3999 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
4002 * Let hardware split jumbo frames into alc_max_buf_sized chunks.
4003 * if it do not fit the buffer size. Rx return descriptor holds
4004 * a counter that indicates how many fragments were made by the
4005 * hardware. The buffer size should be multiple of 8 bytes.
4006 * Since hardware has limit on the size of buffer size, always
4007 * use the maximum value.
4008 * For strict-alignment architectures make sure to reduce buffer
4009 * size by 8 bytes to make room for alignment fixup.
4011 #ifndef __NO_STRICT_ALIGNMENT
4012 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t);
4014 sc->alc_buf_size = RX_BUF_SIZE_MAX;
4016 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
4018 paddr = sc->alc_rdata.alc_rr_ring_paddr;
4019 /* Set Rx return descriptor base addresses. */
4020 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
4021 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4022 /* We use one Rx return ring. */
4023 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
4024 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
4025 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
4027 /* Set Rx return descriptor counter. */
4028 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
4029 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
4030 paddr = sc->alc_rdata.alc_cmb_paddr;
4031 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4032 paddr = sc->alc_rdata.alc_smb_paddr;
4033 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
4034 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
4036 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) {
4037 /* Reconfigure SRAM - Vendor magic. */
4038 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
4039 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
4040 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
4041 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
4042 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
4043 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
4044 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
4045 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
4048 /* Tell hardware that we're ready to load DMA blocks. */
4049 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
4051 /* Configure interrupt moderation timer. */
4052 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
4053 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
4054 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
4055 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
4057 * We don't want to automatic interrupt clear as task queue
4058 * for the interrupt should know interrupt status.
4060 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
4061 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
4062 reg |= MASTER_SA_TIMER_ENB;
4063 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
4064 reg |= MASTER_IM_RX_TIMER_ENB;
4065 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
4066 ALC_USECS(sc->alc_int_tx_mod) != 0)
4067 reg |= MASTER_IM_TX_TIMER_ENB;
4068 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
4070 * Disable interrupt re-trigger timer. We don't want automatic
4071 * re-triggering of un-ACKed interrupts.
4073 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
4074 /* Configure CMB. */
4075 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4076 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
4077 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
4078 ALC_USECS(sc->alc_int_tx_mod));
4080 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
4081 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
4082 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
4084 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
4087 * Hardware can be configured to issue SMB interrupt based
4088 * on programmed interval. Since there is a callout that is
4089 * invoked for every hz in driver we use that instead of
4090 * relying on periodic SMB interrupt.
4092 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
4093 /* Clear MAC statistics. */
4094 alc_stats_clear(sc);
4097 * Always use maximum frame size that controller can support.
4098 * Otherwise received frames that has larger frame length
4099 * than alc(4) MTU would be silently dropped in hardware. This
4100 * would make path-MTU discovery hard as sender wouldn't get
4101 * any responses from receiver. alc(4) supports
4102 * multi-fragmented frames on Rx path so it has no issue on
4103 * assembling fragmented frames. Using maximum frame size also
4104 * removes the need to reinitialize hardware when interface
4105 * MTU configuration was changed.
4107 * Be conservative in what you do, be liberal in what you
4108 * accept from others - RFC 793.
4110 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
4112 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4113 /* Disable header split(?) */
4114 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
4116 /* Configure IPG/IFG parameters. */
4117 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
4118 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) &
4119 IPG_IFG_IPGT_MASK) |
4120 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) &
4121 IPG_IFG_MIFG_MASK) |
4122 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) &
4123 IPG_IFG_IPG1_MASK) |
4124 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) &
4125 IPG_IFG_IPG2_MASK));
4126 /* Set parameters for half-duplex media. */
4127 CSR_WRITE_4(sc, ALC_HDPX_CFG,
4128 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
4129 HDPX_CFG_LCOL_MASK) |
4130 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
4131 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
4132 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
4133 HDPX_CFG_ABEBT_MASK) |
4134 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
4135 HDPX_CFG_JAMIPG_MASK));
4139 * Set TSO/checksum offload threshold. For frames that is
4140 * larger than this threshold, hardware wouldn't do
4141 * TSO/checksum offloading.
4143 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
4144 TSO_OFFLOAD_THRESH_MASK;
4145 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
4146 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;
4147 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
4148 /* Configure TxQ. */
4149 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
4150 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK;
4151 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B ||
4152 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4154 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &
4155 TXQ_CFG_TD_BURST_MASK;
4156 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;
4157 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
4158 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4159 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |
4160 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT |
4161 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT |
4162 HQTD_CFG_BURST_ENB);
4163 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
4164 reg = WRR_PRI_RESTRICT_NONE;
4165 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |
4166 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT |
4167 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT |
4168 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT);
4169 CSR_WRITE_4(sc, ALC_WRR, reg);
4171 /* Configure Rx free descriptor pre-fetching. */
4172 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
4173 ((RX_RD_FREE_THRESH_HI_DEFAULT <<
4174 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) |
4175 ((RX_RD_FREE_THRESH_LO_DEFAULT <<
4176 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK));
4180 * Configure flow control parameters.
4181 * XON : 80% of Rx FIFO
4182 * XOFF : 30% of Rx FIFO
4184 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4185 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4186 reg &= SRAM_RX_FIFO_LEN_MASK;
4189 reg -= RX_FIFO_PAUSE_816X_RSVD;
4191 reg -= RX_BUF_SIZE_MAX;
4193 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4194 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4195 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4196 (((RX_FIFO_PAUSE_816X_RSVD / 8) <<
4197 RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4198 RX_FIFO_PAUSE_THRESH_HI_MASK));
4199 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 ||
4200 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) {
4201 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
4202 rxf_hi = (reg * 8) / 10;
4203 rxf_lo = (reg * 3) / 10;
4204 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
4205 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
4206 RX_FIFO_PAUSE_THRESH_LO_MASK) |
4207 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
4208 RX_FIFO_PAUSE_THRESH_HI_MASK));
4211 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4212 /* Disable RSS until I understand L1C/L2C's RSS logic. */
4213 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
4214 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
4217 /* Configure RxQ. */
4218 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
4219 RXQ_CFG_RD_BURST_MASK;
4220 reg |= RXQ_CFG_RSS_MODE_DIS;
4221 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4222 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
4223 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
4224 RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
4225 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
4226 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4228 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
4229 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
4230 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
4232 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4234 /* Configure DMA parameters. */
4235 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
4237 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
4238 reg |= DMA_CFG_CMB_ENB;
4239 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
4240 reg |= DMA_CFG_SMB_ENB;
4242 reg |= DMA_CFG_SMB_DIS;
4243 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
4244 DMA_CFG_RD_BURST_SHIFT;
4245 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
4246 DMA_CFG_WR_BURST_SHIFT;
4247 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
4248 DMA_CFG_RD_DELAY_CNT_MASK;
4249 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
4250 DMA_CFG_WR_DELAY_CNT_MASK;
4251 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4252 switch (AR816X_REV(sc->alc_rev)) {
4255 reg |= DMA_CFG_RD_CHNL_SEL_2;
4260 reg |= DMA_CFG_RD_CHNL_SEL_4;
4264 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4267 * Configure Tx/Rx MACs.
4268 * - Auto-padding for short frames.
4269 * - Enable CRC generation.
4270 * Actual reconfiguration of MAC for resolved speed/duplex
4271 * is followed after detection of link establishment.
4272 * AR813x/AR815x always does checksum computation regardless
4273 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to
4274 * have bug in protocol field in Rx return structure so
4275 * these controllers can't handle fragmented frames. Disable
4276 * Rx checksum offloading until there is a newer controller
4277 * that has sane implementation.
4279 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
4280 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
4281 MAC_CFG_PREAMBLE_MASK);
4282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
4283 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 ||
4284 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 ||
4285 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2)
4286 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;
4287 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
4288 reg |= MAC_CFG_SPEED_10_100;
4290 reg |= MAC_CFG_SPEED_1000;
4291 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4293 /* Set up the receive filter. */
4297 /* Acknowledge all pending interrupts and clear it. */
4298 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
4299 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4300 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
4302 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4303 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4305 sc->alc_flags &= ~ALC_FLAG_LINK;
4306 /* Switch to the current media. */
4307 alc_mediachange_locked(sc);
4309 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc);
4313 alc_stop(struct alc_softc *sc)
4316 struct alc_txdesc *txd;
4317 struct alc_rxdesc *rxd;
4321 ALC_LOCK_ASSERT(sc);
4323 * Mark the interface down and cancel the watchdog timer.
4326 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4327 sc->alc_flags &= ~ALC_FLAG_LINK;
4328 callout_stop(&sc->alc_tick_ch);
4329 sc->alc_watchdog_timer = 0;
4330 alc_stats_update(sc);
4331 /* Disable interrupts. */
4332 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
4333 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4335 reg = CSR_READ_4(sc, ALC_DMA_CFG);
4336 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
4337 reg |= DMA_CFG_SMB_DIS;
4338 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
4340 /* Stop Rx/Tx MACs. */
4342 /* Disable interrupts which might be touched in taskq handler. */
4343 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4344 /* Disable L0s/L1s */
4345 alc_aspm(sc, 0, IFM_UNKNOWN);
4346 /* Reclaim Rx buffers that have been processed. */
4347 if (sc->alc_cdata.alc_rxhead != NULL)
4348 m_freem(sc->alc_cdata.alc_rxhead);
4349 ALC_RXCHAIN_RESET(sc);
4351 * Free Tx/Rx mbufs still in the queues.
4353 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4354 rxd = &sc->alc_cdata.alc_rxdesc[i];
4355 if (rxd->rx_m != NULL) {
4356 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag,
4357 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4358 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag,
4364 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4365 txd = &sc->alc_cdata.alc_txdesc[i];
4366 if (txd->tx_m != NULL) {
4367 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag,
4368 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4369 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag,
4378 alc_stop_mac(struct alc_softc *sc)
4384 /* Disable Rx/Tx MAC. */
4385 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4386 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
4387 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
4388 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4390 for (i = ALC_TIMEOUT; i > 0; i--) {
4391 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4392 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
4397 device_printf(sc->alc_dev,
4398 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
4402 alc_start_queue(struct alc_softc *sc)
4407 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB,
4408 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB,
4413 ALC_LOCK_ASSERT(sc);
4416 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
4417 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4418 cfg &= ~RXQ_CFG_ENB;
4421 cfg |= RXQ_CFG_QUEUE0_ENB;
4422 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
4424 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
4426 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
4430 alc_stop_queue(struct alc_softc *sc)
4436 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
4437 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4438 if ((reg & RXQ_CFG_ENB) != 0) {
4439 reg &= ~RXQ_CFG_ENB;
4440 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4443 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
4444 reg &= ~RXQ_CFG_QUEUE0_ENB;
4445 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
4449 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
4450 if ((reg & TXQ_CFG_ENB) != 0) {
4451 reg &= ~TXQ_CFG_ENB;
4452 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
4455 for (i = ALC_TIMEOUT; i > 0; i--) {
4456 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
4457 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
4462 device_printf(sc->alc_dev,
4463 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
4467 alc_init_tx_ring(struct alc_softc *sc)
4469 struct alc_ring_data *rd;
4470 struct alc_txdesc *txd;
4473 ALC_LOCK_ASSERT(sc);
4475 sc->alc_cdata.alc_tx_prod = 0;
4476 sc->alc_cdata.alc_tx_cons = 0;
4477 sc->alc_cdata.alc_tx_cnt = 0;
4479 rd = &sc->alc_rdata;
4480 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ);
4481 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4482 txd = &sc->alc_cdata.alc_txdesc[i];
4486 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag,
4487 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE);
4491 alc_init_rx_ring(struct alc_softc *sc)
4493 struct alc_ring_data *rd;
4494 struct alc_rxdesc *rxd;
4497 ALC_LOCK_ASSERT(sc);
4499 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
4500 sc->alc_morework = 0;
4501 rd = &sc->alc_rdata;
4502 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ);
4503 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4504 rxd = &sc->alc_cdata.alc_rxdesc[i];
4506 rxd->rx_desc = &rd->alc_rx_ring[i];
4507 if (alc_newbuf(sc, rxd) != 0)
4512 * Since controller does not update Rx descriptors, driver
4513 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE
4514 * is enough to ensure coherence.
4516 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag,
4517 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE);
4518 /* Let controller know availability of new Rx buffers. */
4519 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
4525 alc_init_rr_ring(struct alc_softc *sc)
4527 struct alc_ring_data *rd;
4529 ALC_LOCK_ASSERT(sc);
4531 sc->alc_cdata.alc_rr_cons = 0;
4532 ALC_RXCHAIN_RESET(sc);
4534 rd = &sc->alc_rdata;
4535 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ);
4536 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag,
4537 sc->alc_cdata.alc_rr_ring_map,
4538 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4542 alc_init_cmb(struct alc_softc *sc)
4544 struct alc_ring_data *rd;
4546 ALC_LOCK_ASSERT(sc);
4548 rd = &sc->alc_rdata;
4549 bzero(rd->alc_cmb, ALC_CMB_SZ);
4550 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map,
4551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4555 alc_init_smb(struct alc_softc *sc)
4557 struct alc_ring_data *rd;
4559 ALC_LOCK_ASSERT(sc);
4561 rd = &sc->alc_rdata;
4562 bzero(rd->alc_smb, ALC_SMB_SZ);
4563 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map,
4564 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4568 alc_rxvlan(struct alc_softc *sc)
4573 ALC_LOCK_ASSERT(sc);
4576 reg = CSR_READ_4(sc, ALC_MAC_CFG);
4577 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
4578 reg |= MAC_CFG_VLAN_TAG_STRIP;
4580 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
4581 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
4585 alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
4587 uint32_t *mchash = arg;
4590 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
4591 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
4597 alc_rxfilter(struct alc_softc *sc)
4603 ALC_LOCK_ASSERT(sc);
4607 bzero(mchash, sizeof(mchash));
4608 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
4609 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
4610 if ((ifp->if_flags & IFF_BROADCAST) != 0)
4611 rxcfg |= MAC_CFG_BCAST;
4612 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
4613 if ((ifp->if_flags & IFF_PROMISC) != 0)
4614 rxcfg |= MAC_CFG_PROMISC;
4615 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
4616 rxcfg |= MAC_CFG_ALLMULTI;
4617 mchash[0] = 0xFFFFFFFF;
4618 mchash[1] = 0xFFFFFFFF;
4622 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash);
4625 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
4626 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
4627 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
4631 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4637 value = *(int *)arg1;
4638 error = sysctl_handle_int(oidp, &value, 0, req);
4639 if (error || req->newptr == NULL)
4641 if (value < low || value > high)
4643 *(int *)arg1 = value;
4649 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS)
4651 return (sysctl_int_range(oidp, arg1, arg2, req,
4652 ALC_PROC_MIN, ALC_PROC_MAX));
4656 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS)
4659 return (sysctl_int_range(oidp, arg1, arg2, req,
4660 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX));
4665 alc_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
4667 struct alc_softc *sc;
4669 sc = if_getsoftc(ifp);
4670 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size"));
4672 *nrxr = ALC_RX_RING_CNT;
4673 *ncl = DEBUGNET_MAX_IN_FLIGHT;
4678 alc_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused)
4683 alc_debugnet_transmit(struct ifnet *ifp, struct mbuf *m)
4685 struct alc_softc *sc;
4688 sc = if_getsoftc(ifp);
4689 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4693 error = alc_encap(sc, &m);
4700 alc_debugnet_poll(struct ifnet *ifp, int count)
4702 struct alc_softc *sc;
4704 sc = if_getsoftc(ifp);
4705 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4710 return (alc_rxintr(sc, count));
4712 #endif /* DEBUGNET */