2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #define ALC_TX_RING_CNT 256
36 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc)
37 #define ALC_RX_RING_CNT 256
38 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc)
39 #define ALC_RX_BUF_ALIGN 4
40 #define ALC_RR_RING_CNT ALC_RX_RING_CNT
41 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc)
42 #define ALC_CMB_ALIGN 8
43 #define ALC_SMB_ALIGN 8
45 #define ALC_TSO_MAXSEGSIZE 4096
46 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
47 #define ALC_MAXTXSEGS 35
49 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
50 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32)
52 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
54 /* Water mark to kick reclaiming Tx buffers. */
55 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
58 * AR816x controllers support up to 16 messages but this driver
59 * uses single message.
61 #define ALC_MSI_MESSAGES 1
62 #define ALC_MSIX_MESSAGES 1
64 #define ALC_TX_RING_SZ \
65 (sizeof(struct tx_desc) * ALC_TX_RING_CNT)
66 #define ALC_RX_RING_SZ \
67 (sizeof(struct rx_desc) * ALC_RX_RING_CNT)
68 #define ALC_RR_RING_SZ \
69 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
70 #define ALC_CMB_SZ (sizeof(struct cmb))
71 #define ALC_SMB_SZ (sizeof(struct smb))
73 #define ALC_PROC_MIN 16
74 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1)
75 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4)
78 * The number of bits reserved for MSS in AR813x/AR815x controllers
79 * are 13 bits. This limits the maximum interface MTU size in TSO
80 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
81 * stack should not generate TCP segments with MSS greater than the
82 * limit. Also Atheros says that maximum MTU for TSO is 6KB.
84 #define ALC_TSO_MTU (6 * 1024)
88 bus_dmamap_t rx_dmamap;
89 struct rx_desc *rx_desc;
94 bus_dmamap_t tx_dmamap;
97 struct alc_ring_data {
98 struct tx_desc *alc_tx_ring;
99 bus_addr_t alc_tx_ring_paddr;
100 struct rx_desc *alc_rx_ring;
101 bus_addr_t alc_rx_ring_paddr;
102 struct rx_rdesc *alc_rr_ring;
103 bus_addr_t alc_rr_ring_paddr;
105 bus_addr_t alc_cmb_paddr;
107 bus_addr_t alc_smb_paddr;
110 struct alc_chain_data {
111 bus_dma_tag_t alc_parent_tag;
112 bus_dma_tag_t alc_buffer_tag;
113 bus_dma_tag_t alc_tx_tag;
114 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT];
115 bus_dma_tag_t alc_rx_tag;
116 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT];
117 bus_dma_tag_t alc_tx_ring_tag;
118 bus_dmamap_t alc_tx_ring_map;
119 bus_dma_tag_t alc_rx_ring_tag;
120 bus_dmamap_t alc_rx_ring_map;
121 bus_dma_tag_t alc_rr_ring_tag;
122 bus_dmamap_t alc_rr_ring_map;
123 bus_dmamap_t alc_rx_sparemap;
124 bus_dma_tag_t alc_cmb_tag;
125 bus_dmamap_t alc_cmb_map;
126 bus_dma_tag_t alc_smb_tag;
127 bus_dmamap_t alc_smb_map;
136 struct mbuf *alc_rxhead;
137 struct mbuf *alc_rxtail;
138 struct mbuf *alc_rxprev_tail;
141 struct alc_hw_stats {
144 uint32_t rx_bcast_frames;
145 uint32_t rx_mcast_frames;
146 uint32_t rx_pause_frames;
147 uint32_t rx_control_frames;
152 uint32_t rx_fragments;
154 uint32_t rx_pkts_65_127;
155 uint32_t rx_pkts_128_255;
156 uint32_t rx_pkts_256_511;
157 uint32_t rx_pkts_512_1023;
158 uint32_t rx_pkts_1024_1518;
159 uint32_t rx_pkts_1519_max;
160 uint32_t rx_pkts_truncated;
161 uint32_t rx_fifo_oflows;
162 uint32_t rx_rrs_errs;
163 uint32_t rx_alignerrs;
164 uint64_t rx_bcast_bytes;
165 uint64_t rx_mcast_bytes;
166 uint32_t rx_pkts_filtered;
169 uint32_t tx_bcast_frames;
170 uint32_t tx_mcast_frames;
171 uint32_t tx_pause_frames;
172 uint32_t tx_excess_defer;
173 uint32_t tx_control_frames;
174 uint32_t tx_deferred;
177 uint32_t tx_pkts_65_127;
178 uint32_t tx_pkts_128_255;
179 uint32_t tx_pkts_256_511;
180 uint32_t tx_pkts_512_1023;
181 uint32_t tx_pkts_1024_1518;
182 uint32_t tx_pkts_1519_max;
183 uint32_t tx_single_colls;
184 uint32_t tx_multi_colls;
185 uint32_t tx_late_colls;
186 uint32_t tx_excess_colls;
188 uint32_t tx_underrun;
189 uint32_t tx_desc_underrun;
191 uint32_t tx_pkts_truncated;
192 uint64_t tx_bcast_bytes;
193 uint64_t tx_mcast_bytes;
199 uint32_t max_framelen;
204 * Software state per device.
207 struct ifnet *alc_ifp;
210 struct resource *alc_res[1];
211 struct resource_spec *alc_res_spec;
212 struct resource *alc_irq[ALC_MSI_MESSAGES];
213 struct resource_spec *alc_irq_spec;
214 void *alc_intrhand[ALC_MSI_MESSAGES];
215 struct alc_ident *alc_ident;
219 uint8_t alc_eaddr[ETHER_ADDR_LEN];
220 uint32_t alc_dma_rd_burst;
221 uint32_t alc_dma_wr_burst;
226 #define ALC_FLAG_PCIE 0x0001
227 #define ALC_FLAG_PCIX 0x0002
228 #define ALC_FLAG_MSI 0x0004
229 #define ALC_FLAG_MSIX 0x0008
230 #define ALC_FLAG_PM 0x0010
231 #define ALC_FLAG_FASTETHER 0x0020
232 #define ALC_FLAG_JUMBO 0x0040
233 #define ALC_FLAG_CMB_BUG 0x0100
234 #define ALC_FLAG_SMB_BUG 0x0200
235 #define ALC_FLAG_L0S 0x0400
236 #define ALC_FLAG_L1S 0x0800
237 #define ALC_FLAG_APS 0x1000
238 #define ALC_FLAG_AR816X_FAMILY 0x2000
239 #define ALC_FLAG_LINK_WAR 0x4000
240 #define ALC_FLAG_E2X00 0x8000
241 #define ALC_FLAG_LINK 0x10000
242 #define ALC_FLAG_MT 0x20000
244 struct callout alc_tick_ch;
245 struct alc_hw_stats alc_stats;
246 struct alc_chain_data alc_cdata;
247 struct alc_ring_data alc_rdata;
249 int alc_watchdog_timer;
250 int alc_process_limit;
251 volatile int alc_morework;
256 struct task alc_int_task;
257 struct taskqueue *alc_tq;
261 /* Register access macros. */
262 #define CSR_WRITE_4(_sc, reg, val) \
263 bus_write_4((_sc)->alc_res[0], (reg), (val))
264 #define CSR_WRITE_2(_sc, reg, val) \
265 bus_write_2((_sc)->alc_res[0], (reg), (val))
266 #define CSR_WRITE_1(_sc, reg, val) \
267 bus_write_1((_sc)->alc_res[0], (reg), (val))
268 #define CSR_READ_2(_sc, reg) \
269 bus_read_2((_sc)->alc_res[0], (reg))
270 #define CSR_READ_4(_sc, reg) \
271 bus_read_4((_sc)->alc_res[0], (reg))
273 #define ALC_RXCHAIN_RESET(_sc) \
275 (_sc)->alc_cdata.alc_rxhead = NULL; \
276 (_sc)->alc_cdata.alc_rxtail = NULL; \
277 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \
278 (_sc)->alc_cdata.alc_rxlen = 0; \
281 #define ALC_LOCK(_sc) mtx_lock(&(_sc)->alc_mtx)
282 #define ALC_UNLOCK(_sc) mtx_unlock(&(_sc)->alc_mtx)
283 #define ALC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->alc_mtx, MA_OWNED)
285 #define ALC_TX_TIMEOUT 5
286 #define ALC_RESET_TIMEOUT 100
287 #define ALC_TIMEOUT 1000
288 #define ALC_PHY_TIMEOUT 10000
290 #endif /* _IF_ALCVAR_H */