2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_llc.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/if_vlan_var.h>
59 #include <netinet/in.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/ip.h>
62 #include <netinet/tcp.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
73 #include <dev/ale/if_alereg.h>
74 #include <dev/ale/if_alevar.h>
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 /* For more information about Tx checksum offload issues see ale_encap(). */
80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(ale, pci, 1, 1, 1);
83 MODULE_DEPEND(ale, ether, 1, 1, 1);
84 MODULE_DEPEND(ale, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static const struct ale_dev {
96 uint16_t ale_vendorid;
97 uint16_t ale_deviceid;
100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
104 static int ale_attach(device_t);
105 static int ale_check_boundary(struct ale_softc *);
106 static int ale_detach(device_t);
107 static int ale_dma_alloc(struct ale_softc *);
108 static void ale_dma_free(struct ale_softc *);
109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_get_macaddr(struct ale_softc *);
112 static void ale_init(void *);
113 static void ale_init_locked(struct ale_softc *);
114 static void ale_init_rx_pages(struct ale_softc *);
115 static void ale_init_tx_ring(struct ale_softc *);
116 static void ale_int_task(void *, int);
117 static int ale_intr(void *);
118 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
119 static void ale_mac_config(struct ale_softc *);
120 static int ale_miibus_readreg(device_t, int, int);
121 static void ale_miibus_statchg(device_t);
122 static int ale_miibus_writereg(device_t, int, int, int);
123 static int ale_mediachange(struct ifnet *);
124 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
125 static void ale_phy_reset(struct ale_softc *);
126 static int ale_probe(device_t);
127 static void ale_reset(struct ale_softc *);
128 static int ale_resume(device_t);
129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
130 uint32_t, uint32_t *);
131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
132 static int ale_rxeof(struct ale_softc *sc, int);
133 static void ale_rxfilter(struct ale_softc *);
134 static void ale_rxvlan(struct ale_softc *);
135 static void ale_setlinkspeed(struct ale_softc *);
136 static void ale_setwol(struct ale_softc *);
137 static int ale_shutdown(device_t);
138 static void ale_start(struct ifnet *);
139 static void ale_start_locked(struct ifnet *);
140 static void ale_stats_clear(struct ale_softc *);
141 static void ale_stats_update(struct ale_softc *);
142 static void ale_stop(struct ale_softc *);
143 static void ale_stop_mac(struct ale_softc *);
144 static int ale_suspend(device_t);
145 static void ale_sysctl_node(struct ale_softc *);
146 static void ale_tick(void *);
147 static void ale_txeof(struct ale_softc *);
148 static void ale_watchdog(struct ale_softc *);
149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
153 static device_method_t ale_methods[] = {
154 /* Device interface. */
155 DEVMETHOD(device_probe, ale_probe),
156 DEVMETHOD(device_attach, ale_attach),
157 DEVMETHOD(device_detach, ale_detach),
158 DEVMETHOD(device_shutdown, ale_shutdown),
159 DEVMETHOD(device_suspend, ale_suspend),
160 DEVMETHOD(device_resume, ale_resume),
163 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
164 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
165 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
170 static driver_t ale_driver = {
173 sizeof(struct ale_softc)
176 static devclass_t ale_devclass;
178 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL);
179 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL);
181 static struct resource_spec ale_res_spec_mem[] = {
182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
186 static struct resource_spec ale_irq_spec_legacy[] = {
187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
191 static struct resource_spec ale_irq_spec_msi[] = {
192 { SYS_RES_IRQ, 1, RF_ACTIVE },
196 static struct resource_spec ale_irq_spec_msix[] = {
197 { SYS_RES_IRQ, 1, RF_ACTIVE },
202 ale_miibus_readreg(device_t dev, int phy, int reg)
204 struct ale_softc *sc;
208 sc = device_get_softc(dev);
210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
214 v = CSR_READ_4(sc, ALE_MDIO);
215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
228 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
230 struct ale_softc *sc;
234 sc = device_get_softc(dev);
236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
241 v = CSR_READ_4(sc, ALE_MDIO);
242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
253 ale_miibus_statchg(device_t dev)
255 struct ale_softc *sc;
256 struct mii_data *mii;
260 sc = device_get_softc(dev);
261 mii = device_get_softc(sc->ale_miibus);
263 if (mii == NULL || ifp == NULL ||
264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
267 sc->ale_flags &= ~ALE_FLAG_LINK;
268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
269 (IFM_ACTIVE | IFM_AVALID)) {
270 switch (IFM_SUBTYPE(mii->mii_media_active)) {
273 sc->ale_flags |= ALE_FLAG_LINK;
276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
277 sc->ale_flags |= ALE_FLAG_LINK;
284 /* Stop Rx/Tx MACs. */
287 /* Program MACs with resolved speed/duplex/flow-control. */
288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
290 /* Reenable Tx/Rx MACs. */
291 reg = CSR_READ_4(sc, ALE_MAC_CFG);
292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
298 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
300 struct ale_softc *sc;
301 struct mii_data *mii;
305 if ((ifp->if_flags & IFF_UP) == 0) {
309 mii = device_get_softc(sc->ale_miibus);
312 ifmr->ifm_status = mii->mii_media_status;
313 ifmr->ifm_active = mii->mii_media_active;
318 ale_mediachange(struct ifnet *ifp)
320 struct ale_softc *sc;
321 struct mii_data *mii;
322 struct mii_softc *miisc;
327 mii = device_get_softc(sc->ale_miibus);
328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
330 error = mii_mediachg(mii);
337 ale_probe(device_t dev)
339 const struct ale_dev *sp;
341 uint16_t vendor, devid;
343 vendor = pci_get_vendor(dev);
344 devid = pci_get_device(dev);
346 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
347 if (vendor == sp->ale_vendorid &&
348 devid == sp->ale_deviceid) {
349 device_set_desc(dev, sp->ale_name);
350 return (BUS_PROBE_DEFAULT);
359 ale_get_macaddr(struct ale_softc *sc)
364 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
365 if ((reg & SPI_VPD_ENB) != 0) {
367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
372 * PCI VPD capability found, let TWSI reload EEPROM.
373 * This will set ethernet address of controller.
375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
376 TWSI_CTRL_SW_LD_START);
377 for (i = 100; i > 0; i--) {
379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
380 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
384 device_printf(sc->ale_dev,
385 "reloading EEPROM timeout!\n");
388 device_printf(sc->ale_dev,
389 "PCI VPD capability not found!\n");
392 ea[0] = CSR_READ_4(sc, ALE_PAR0);
393 ea[1] = CSR_READ_4(sc, ALE_PAR1);
394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
403 ale_phy_reset(struct ale_softc *sc)
406 /* Reset magic from Linux. */
407 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
409 GPHY_CTRL_PHY_PLL_ON);
411 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
416 #define ATPHY_DBG_ADDR 0x1D
417 #define ATPHY_DBG_DATA 0x1E
419 /* Enable hibernation mode. */
420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
421 ATPHY_DBG_ADDR, 0x0B);
422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
423 ATPHY_DBG_DATA, 0xBC00);
424 /* Set Class A/B for all modes. */
425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
426 ATPHY_DBG_ADDR, 0x00);
427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
428 ATPHY_DBG_DATA, 0x02EF);
429 /* Enable 10BT power saving. */
430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
431 ATPHY_DBG_ADDR, 0x12);
432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
433 ATPHY_DBG_DATA, 0x4C04);
434 /* Adjust 1000T power. */
435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
436 ATPHY_DBG_ADDR, 0x04);
437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
438 ATPHY_DBG_ADDR, 0x8BBB);
439 /* 10BT center tap voltage. */
440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
441 ATPHY_DBG_ADDR, 0x05);
442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
443 ATPHY_DBG_ADDR, 0x2C46);
445 #undef ATPHY_DBG_ADDR
446 #undef ATPHY_DBG_DATA
451 ale_attach(device_t dev)
453 struct ale_softc *sc;
456 int error, i, msic, msixc, pmc;
457 uint32_t rxf_len, txf_len;
460 sc = device_get_softc(dev);
463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
466 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
468 /* Map the device. */
469 pci_enable_busmaster(dev);
470 sc->ale_res_spec = ale_res_spec_mem;
471 sc->ale_irq_spec = ale_irq_spec_legacy;
472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
474 device_printf(dev, "cannot allocate memory resources.\n");
478 /* Set PHY address. */
479 sc->ale_phyaddr = ALE_PHY_ADDR;
484 /* Reset the ethernet controller. */
487 /* Get PCI and chip id/revision. */
488 sc->ale_rev = pci_get_revid(dev);
489 if (sc->ale_rev >= 0xF0) {
490 /* L2E Rev. B. AR8114 */
491 sc->ale_flags |= ALE_FLAG_FASTETHER;
493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
495 sc->ale_flags |= ALE_FLAG_JUMBO;
497 /* L2E Rev. A. AR8113 */
498 sc->ale_flags |= ALE_FLAG_FASTETHER;
502 * All known controllers seems to require 4 bytes alignment
503 * of Tx buffers to make Tx checksum offload with custom
504 * checksum generation method work.
506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
508 * All known controllers seems to have issues on Rx checksum
509 * offload for fragmented IP datagrams.
511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
513 * Don't use Tx CMB. It is known to cause RRS update failure
514 * under certain circumstances. Typical phenomenon of the
515 * issue would be unexpected sequence number encountered in
518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
520 MASTER_CHIP_REV_SHIFT;
522 device_printf(dev, "PCI device revision : 0x%04x\n",
524 device_printf(dev, "Chip id/revision : 0x%04x\n",
527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
530 * Uninitialized hardware returns an invalid chip id/revision
531 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
534 rxf_len == 0xFFFFFFF) {
535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
543 /* Allocate IRQ resources. */
544 msixc = pci_msix_count(dev);
545 msic = pci_msi_count(dev);
547 device_printf(dev, "MSIX count : %d\n", msixc);
548 device_printf(dev, "MSI count : %d\n", msic);
551 /* Prefer MSIX over MSI. */
552 if (msix_disable == 0 || msi_disable == 0) {
553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
554 pci_alloc_msix(dev, &msixc) == 0) {
555 if (msixc == ALE_MSIX_MESSAGES) {
556 device_printf(dev, "Using %d MSIX messages.\n",
558 sc->ale_flags |= ALE_FLAG_MSIX;
559 sc->ale_irq_spec = ale_irq_spec_msix;
561 pci_release_msi(dev);
563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
564 msic == ALE_MSI_MESSAGES &&
565 pci_alloc_msi(dev, &msic) == 0) {
566 if (msic == ALE_MSI_MESSAGES) {
567 device_printf(dev, "Using %d MSI messages.\n",
569 sc->ale_flags |= ALE_FLAG_MSI;
570 sc->ale_irq_spec = ale_irq_spec_msi;
572 pci_release_msi(dev);
576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
578 device_printf(dev, "cannot allocate IRQ resources.\n");
582 /* Get DMA parameters from PCIe device control register. */
583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
584 sc->ale_flags |= ALE_FLAG_PCIE;
585 burst = pci_read_config(dev, i + 0x08, 2);
586 /* Max read request size. */
587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
588 DMA_CFG_RD_BURST_SHIFT;
589 /* Max payload size. */
590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
591 DMA_CFG_WR_BURST_SHIFT;
593 device_printf(dev, "Read request size : %d bytes.\n",
594 128 << ((burst >> 12) & 0x07));
595 device_printf(dev, "TLP payload size : %d bytes.\n",
596 128 << ((burst >> 5) & 0x07));
599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
603 /* Create device sysctl node. */
606 if ((error = ale_dma_alloc(sc) != 0))
609 /* Load station address. */
612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
614 device_printf(dev, "cannot allocate ifnet structure.\n");
620 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
622 ifp->if_ioctl = ale_ioctl;
623 ifp->if_start = ale_start;
624 ifp->if_init = ale_init;
625 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
627 IFQ_SET_READY(&ifp->if_snd);
628 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
629 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
630 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
631 sc->ale_flags |= ALE_FLAG_PMCAP;
632 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
634 ifp->if_capenable = ifp->if_capabilities;
636 /* Set up MII bus. */
637 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
638 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
641 device_printf(dev, "attaching PHYs failed\n");
645 ether_ifattach(ifp, sc->ale_eaddr);
647 /* VLAN capability setup. */
648 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
649 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
650 ifp->if_capenable = ifp->if_capabilities;
652 * Even though controllers supported by ale(3) have Rx checksum
653 * offload bug the workaround for fragmented frames seemed to
654 * work so far. However it seems Rx checksum offload does not
655 * work under certain conditions. So disable Rx checksum offload
656 * until I find more clue about it but allow users to override it.
658 ifp->if_capenable &= ~IFCAP_RXCSUM;
660 /* Tell the upper layer(s) we support long frames. */
661 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
663 /* Create local taskq. */
664 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
665 taskqueue_thread_enqueue, &sc->ale_tq);
666 if (sc->ale_tq == NULL) {
667 device_printf(dev, "could not create taskqueue.\n");
672 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
673 device_get_nameunit(sc->ale_dev));
675 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
676 msic = ALE_MSIX_MESSAGES;
677 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
678 msic = ALE_MSI_MESSAGES;
681 for (i = 0; i < msic; i++) {
682 error = bus_setup_intr(dev, sc->ale_irq[i],
683 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
684 &sc->ale_intrhand[i]);
689 device_printf(dev, "could not set up interrupt handler.\n");
690 taskqueue_free(sc->ale_tq);
704 ale_detach(device_t dev)
706 struct ale_softc *sc;
710 sc = device_get_softc(dev);
713 if (device_is_attached(dev)) {
718 callout_drain(&sc->ale_tick_ch);
719 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
722 if (sc->ale_tq != NULL) {
723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
724 taskqueue_free(sc->ale_tq);
728 if (sc->ale_miibus != NULL) {
729 device_delete_child(dev, sc->ale_miibus);
730 sc->ale_miibus = NULL;
732 bus_generic_detach(dev);
740 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
741 msic = ALE_MSIX_MESSAGES;
742 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
743 msic = ALE_MSI_MESSAGES;
746 for (i = 0; i < msic; i++) {
747 if (sc->ale_intrhand[i] != NULL) {
748 bus_teardown_intr(dev, sc->ale_irq[i],
749 sc->ale_intrhand[i]);
750 sc->ale_intrhand[i] = NULL;
754 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
755 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
756 pci_release_msi(dev);
757 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
758 mtx_destroy(&sc->ale_mtx);
763 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
764 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
766 #if __FreeBSD_version >= 900030
767 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
768 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
769 #elif __FreeBSD_version > 800000
770 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
771 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
773 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
774 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
778 ale_sysctl_node(struct ale_softc *sc)
780 struct sysctl_ctx_list *ctx;
781 struct sysctl_oid_list *child, *parent;
782 struct sysctl_oid *tree;
783 struct ale_hw_stats *stats;
786 stats = &sc->ale_stats;
787 ctx = device_get_sysctl_ctx(sc->ale_dev);
788 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
790 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
791 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
792 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
793 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
794 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
795 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
796 /* Pull in device tunables. */
797 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
798 error = resource_int_value(device_get_name(sc->ale_dev),
799 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
801 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
802 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
803 device_printf(sc->ale_dev, "int_rx_mod value out of "
804 "range; using default: %d\n",
805 ALE_IM_RX_TIMER_DEFAULT);
806 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
809 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
810 error = resource_int_value(device_get_name(sc->ale_dev),
811 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
813 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
814 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
815 device_printf(sc->ale_dev, "int_tx_mod value out of "
816 "range; using default: %d\n",
817 ALE_IM_TX_TIMER_DEFAULT);
818 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
821 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
822 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
823 sysctl_hw_ale_proc_limit, "I",
824 "max number of Rx events to process");
825 /* Pull in device tunables. */
826 sc->ale_process_limit = ALE_PROC_DEFAULT;
827 error = resource_int_value(device_get_name(sc->ale_dev),
828 device_get_unit(sc->ale_dev), "process_limit",
829 &sc->ale_process_limit);
831 if (sc->ale_process_limit < ALE_PROC_MIN ||
832 sc->ale_process_limit > ALE_PROC_MAX) {
833 device_printf(sc->ale_dev,
834 "process_limit value out of range; "
835 "using default: %d\n", ALE_PROC_DEFAULT);
836 sc->ale_process_limit = ALE_PROC_DEFAULT;
840 /* Misc statistics. */
841 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
842 &stats->reset_brk_seq,
843 "Controller resets due to broken Rx sequnce number");
845 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
846 NULL, "ATE statistics");
847 parent = SYSCTL_CHILDREN(tree);
850 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
851 NULL, "Rx MAC statistics");
852 child = SYSCTL_CHILDREN(tree);
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
854 &stats->rx_frames, "Good frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
856 &stats->rx_bcast_frames, "Good broadcast frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
858 &stats->rx_mcast_frames, "Good multicast frames");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
860 &stats->rx_pause_frames, "Pause control frames");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
862 &stats->rx_control_frames, "Control frames");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
864 &stats->rx_crcerrs, "CRC errors");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
866 &stats->rx_lenerrs, "Frames with length mismatched");
867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
868 &stats->rx_bytes, "Good octets");
869 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
870 &stats->rx_bcast_bytes, "Good broadcast octets");
871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
872 &stats->rx_mcast_bytes, "Good multicast octets");
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
874 &stats->rx_runts, "Too short frames");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
876 &stats->rx_fragments, "Fragmented frames");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
878 &stats->rx_pkts_64, "64 bytes frames");
879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
880 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
882 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
884 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
886 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
888 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
890 &stats->rx_pkts_1519_max, "1519 to max frames");
891 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
892 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
893 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
894 &stats->rx_fifo_oflows, "FIFO overflows");
895 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
896 &stats->rx_rrs_errs, "Return status write-back errors");
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
898 &stats->rx_alignerrs, "Alignment errors");
899 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
900 &stats->rx_pkts_filtered,
901 "Frames dropped due to address filtering");
904 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
905 NULL, "Tx MAC statistics");
906 child = SYSCTL_CHILDREN(tree);
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
908 &stats->tx_frames, "Good frames");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
910 &stats->tx_bcast_frames, "Good broadcast frames");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
912 &stats->tx_mcast_frames, "Good multicast frames");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
914 &stats->tx_pause_frames, "Pause control frames");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
916 &stats->tx_control_frames, "Control frames");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
918 &stats->tx_excess_defer, "Frames with excessive derferrals");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
920 &stats->tx_excess_defer, "Frames with derferrals");
921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
922 &stats->tx_bytes, "Good octets");
923 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
924 &stats->tx_bcast_bytes, "Good broadcast octets");
925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
926 &stats->tx_mcast_bytes, "Good multicast octets");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
928 &stats->tx_pkts_64, "64 bytes frames");
929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
930 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
932 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
934 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
936 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
938 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
940 &stats->tx_pkts_1519_max, "1519 to max frames");
941 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
942 &stats->tx_single_colls, "Single collisions");
943 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
944 &stats->tx_multi_colls, "Multiple collisions");
945 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
946 &stats->tx_late_colls, "Late collisions");
947 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
948 &stats->tx_excess_colls, "Excessive collisions");
949 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
950 &stats->tx_abort, "Aborted frames due to Excessive collisions");
951 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
952 &stats->tx_underrun, "FIFO underruns");
953 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
954 &stats->tx_desc_underrun, "Descriptor write-back errors");
955 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
956 &stats->tx_lenerrs, "Frames with length mismatched");
957 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
958 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
961 #undef ALE_SYSCTL_STAT_ADD32
962 #undef ALE_SYSCTL_STAT_ADD64
964 struct ale_dmamap_arg {
965 bus_addr_t ale_busaddr;
969 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
971 struct ale_dmamap_arg *ctx;
976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
978 ctx = (struct ale_dmamap_arg *)arg;
979 ctx->ale_busaddr = segs[0].ds_addr;
983 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
984 * which specifies high address region of DMA blocks. Therefore these
985 * blocks should have the same high address of given 4GB address
986 * space(i.e. crossing 4GB boundary is not allowed).
989 ale_check_boundary(struct ale_softc *sc)
991 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
992 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
994 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
996 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
998 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
999 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
1000 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
1001 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
1003 if ((ALE_ADDR_HI(tx_ring_end) !=
1004 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
1005 (ALE_ADDR_HI(rx_page_end[0]) !=
1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
1007 (ALE_ADDR_HI(rx_page_end[1]) !=
1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
1009 (ALE_ADDR_HI(tx_cmb_end) !=
1010 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
1011 (ALE_ADDR_HI(rx_cmb_end[0]) !=
1012 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
1013 (ALE_ADDR_HI(rx_cmb_end[1]) !=
1014 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
1017 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
1021 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
1028 ale_dma_alloc(struct ale_softc *sc)
1030 struct ale_txdesc *txd;
1032 struct ale_dmamap_arg ctx;
1033 int error, guard_size, i;
1035 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1036 guard_size = ALE_JUMBO_FRAMELEN;
1038 guard_size = ALE_MAX_FRAMELEN;
1039 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1041 lowaddr = BUS_SPACE_MAXADDR;
1043 /* Create parent DMA tag. */
1044 error = bus_dma_tag_create(
1045 bus_get_dma_tag(sc->ale_dev), /* parent */
1046 1, 0, /* alignment, boundary */
1047 lowaddr, /* lowaddr */
1048 BUS_SPACE_MAXADDR, /* highaddr */
1049 NULL, NULL, /* filter, filterarg */
1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1054 NULL, NULL, /* lockfunc, lockarg */
1055 &sc->ale_cdata.ale_parent_tag);
1057 device_printf(sc->ale_dev,
1058 "could not create parent DMA tag.\n");
1062 /* Create DMA tag for Tx descriptor ring. */
1063 error = bus_dma_tag_create(
1064 sc->ale_cdata.ale_parent_tag, /* parent */
1065 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1066 BUS_SPACE_MAXADDR, /* lowaddr */
1067 BUS_SPACE_MAXADDR, /* highaddr */
1068 NULL, NULL, /* filter, filterarg */
1069 ALE_TX_RING_SZ, /* maxsize */
1071 ALE_TX_RING_SZ, /* maxsegsize */
1073 NULL, NULL, /* lockfunc, lockarg */
1074 &sc->ale_cdata.ale_tx_ring_tag);
1076 device_printf(sc->ale_dev,
1077 "could not create Tx ring DMA tag.\n");
1081 /* Create DMA tag for Rx pages. */
1082 for (i = 0; i < ALE_RX_PAGES; i++) {
1083 error = bus_dma_tag_create(
1084 sc->ale_cdata.ale_parent_tag, /* parent */
1085 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1086 BUS_SPACE_MAXADDR, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filter, filterarg */
1089 sc->ale_pagesize, /* maxsize */
1091 sc->ale_pagesize, /* maxsegsize */
1093 NULL, NULL, /* lockfunc, lockarg */
1094 &sc->ale_cdata.ale_rx_page[i].page_tag);
1096 device_printf(sc->ale_dev,
1097 "could not create Rx page %d DMA tag.\n", i);
1102 /* Create DMA tag for Tx coalescing message block. */
1103 error = bus_dma_tag_create(
1104 sc->ale_cdata.ale_parent_tag, /* parent */
1105 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1106 BUS_SPACE_MAXADDR, /* lowaddr */
1107 BUS_SPACE_MAXADDR, /* highaddr */
1108 NULL, NULL, /* filter, filterarg */
1109 ALE_TX_CMB_SZ, /* maxsize */
1111 ALE_TX_CMB_SZ, /* maxsegsize */
1113 NULL, NULL, /* lockfunc, lockarg */
1114 &sc->ale_cdata.ale_tx_cmb_tag);
1116 device_printf(sc->ale_dev,
1117 "could not create Tx CMB DMA tag.\n");
1121 /* Create DMA tag for Rx coalescing message block. */
1122 for (i = 0; i < ALE_RX_PAGES; i++) {
1123 error = bus_dma_tag_create(
1124 sc->ale_cdata.ale_parent_tag, /* parent */
1125 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1126 BUS_SPACE_MAXADDR, /* lowaddr */
1127 BUS_SPACE_MAXADDR, /* highaddr */
1128 NULL, NULL, /* filter, filterarg */
1129 ALE_RX_CMB_SZ, /* maxsize */
1131 ALE_RX_CMB_SZ, /* maxsegsize */
1133 NULL, NULL, /* lockfunc, lockarg */
1134 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1136 device_printf(sc->ale_dev,
1137 "could not create Rx page %d CMB DMA tag.\n", i);
1142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1143 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1144 (void **)&sc->ale_cdata.ale_tx_ring,
1145 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1146 &sc->ale_cdata.ale_tx_ring_map);
1148 device_printf(sc->ale_dev,
1149 "could not allocate DMA'able memory for Tx ring.\n");
1152 ctx.ale_busaddr = 0;
1153 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1154 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1155 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1156 if (error != 0 || ctx.ale_busaddr == 0) {
1157 device_printf(sc->ale_dev,
1158 "could not load DMA'able memory for Tx ring.\n");
1161 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1164 for (i = 0; i < ALE_RX_PAGES; i++) {
1165 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1166 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1167 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1168 &sc->ale_cdata.ale_rx_page[i].page_map);
1170 device_printf(sc->ale_dev,
1171 "could not allocate DMA'able memory for "
1172 "Rx page %d.\n", i);
1175 ctx.ale_busaddr = 0;
1176 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1177 sc->ale_cdata.ale_rx_page[i].page_map,
1178 sc->ale_cdata.ale_rx_page[i].page_addr,
1179 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1180 if (error != 0 || ctx.ale_busaddr == 0) {
1181 device_printf(sc->ale_dev,
1182 "could not load DMA'able memory for "
1183 "Rx page %d.\n", i);
1186 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1190 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1191 (void **)&sc->ale_cdata.ale_tx_cmb,
1192 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1193 &sc->ale_cdata.ale_tx_cmb_map);
1195 device_printf(sc->ale_dev,
1196 "could not allocate DMA'able memory for Tx CMB.\n");
1199 ctx.ale_busaddr = 0;
1200 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1201 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1202 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1203 if (error != 0 || ctx.ale_busaddr == 0) {
1204 device_printf(sc->ale_dev,
1205 "could not load DMA'able memory for Tx CMB.\n");
1208 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1211 for (i = 0; i < ALE_RX_PAGES; i++) {
1212 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1213 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1214 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1215 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1217 device_printf(sc->ale_dev, "could not allocate "
1218 "DMA'able memory for Rx page %d CMB.\n", i);
1221 ctx.ale_busaddr = 0;
1222 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1223 sc->ale_cdata.ale_rx_page[i].cmb_map,
1224 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1225 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1226 if (error != 0 || ctx.ale_busaddr == 0) {
1227 device_printf(sc->ale_dev, "could not load DMA'able "
1228 "memory for Rx page %d CMB.\n", i);
1231 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1235 * Tx descriptors/RXF0/CMB DMA blocks share the same
1236 * high address region of 64bit DMA address space.
1238 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1239 (error = ale_check_boundary(sc)) != 0) {
1240 device_printf(sc->ale_dev, "4GB boundary crossed, "
1241 "switching to 32bit DMA addressing mode.\n");
1244 * Limit max allowable DMA address space to 32bit
1247 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1252 * Create Tx buffer parent tag.
1253 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1254 * needs separate parent DMA tag as parent DMA address space
1255 * could be restricted to be within 32bit address space by
1256 * 4GB boundary crossing.
1258 error = bus_dma_tag_create(
1259 bus_get_dma_tag(sc->ale_dev), /* parent */
1260 1, 0, /* alignment, boundary */
1261 BUS_SPACE_MAXADDR, /* lowaddr */
1262 BUS_SPACE_MAXADDR, /* highaddr */
1263 NULL, NULL, /* filter, filterarg */
1264 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1266 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1268 NULL, NULL, /* lockfunc, lockarg */
1269 &sc->ale_cdata.ale_buffer_tag);
1271 device_printf(sc->ale_dev,
1272 "could not create parent buffer DMA tag.\n");
1276 /* Create DMA tag for Tx buffers. */
1277 error = bus_dma_tag_create(
1278 sc->ale_cdata.ale_buffer_tag, /* parent */
1279 1, 0, /* alignment, boundary */
1280 BUS_SPACE_MAXADDR, /* lowaddr */
1281 BUS_SPACE_MAXADDR, /* highaddr */
1282 NULL, NULL, /* filter, filterarg */
1283 ALE_TSO_MAXSIZE, /* maxsize */
1284 ALE_MAXTXSEGS, /* nsegments */
1285 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1287 NULL, NULL, /* lockfunc, lockarg */
1288 &sc->ale_cdata.ale_tx_tag);
1290 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1294 /* Create DMA maps for Tx buffers. */
1295 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1296 txd = &sc->ale_cdata.ale_txdesc[i];
1298 txd->tx_dmamap = NULL;
1299 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1302 device_printf(sc->ale_dev,
1303 "could not create Tx dmamap.\n");
1313 ale_dma_free(struct ale_softc *sc)
1315 struct ale_txdesc *txd;
1319 if (sc->ale_cdata.ale_tx_tag != NULL) {
1320 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1321 txd = &sc->ale_cdata.ale_txdesc[i];
1322 if (txd->tx_dmamap != NULL) {
1323 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1325 txd->tx_dmamap = NULL;
1328 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1329 sc->ale_cdata.ale_tx_tag = NULL;
1331 /* Tx descriptor ring. */
1332 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1333 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1334 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1335 sc->ale_cdata.ale_tx_ring_map);
1336 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1337 sc->ale_cdata.ale_tx_ring != NULL)
1338 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1339 sc->ale_cdata.ale_tx_ring,
1340 sc->ale_cdata.ale_tx_ring_map);
1341 sc->ale_cdata.ale_tx_ring = NULL;
1342 sc->ale_cdata.ale_tx_ring_map = NULL;
1343 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1344 sc->ale_cdata.ale_tx_ring_tag = NULL;
1346 /* Rx page block. */
1347 for (i = 0; i < ALE_RX_PAGES; i++) {
1348 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1349 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1351 sc->ale_cdata.ale_rx_page[i].page_tag,
1352 sc->ale_cdata.ale_rx_page[i].page_map);
1353 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1354 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1356 sc->ale_cdata.ale_rx_page[i].page_tag,
1357 sc->ale_cdata.ale_rx_page[i].page_addr,
1358 sc->ale_cdata.ale_rx_page[i].page_map);
1359 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1360 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1361 bus_dma_tag_destroy(
1362 sc->ale_cdata.ale_rx_page[i].page_tag);
1363 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1367 for (i = 0; i < ALE_RX_PAGES; i++) {
1368 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1369 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1371 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1372 sc->ale_cdata.ale_rx_page[i].cmb_map);
1373 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1374 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1376 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1377 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1378 sc->ale_cdata.ale_rx_page[i].cmb_map);
1379 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1380 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1381 bus_dma_tag_destroy(
1382 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1383 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1387 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1388 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1389 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1390 sc->ale_cdata.ale_tx_cmb_map);
1391 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1392 sc->ale_cdata.ale_tx_cmb != NULL)
1393 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1394 sc->ale_cdata.ale_tx_cmb,
1395 sc->ale_cdata.ale_tx_cmb_map);
1396 sc->ale_cdata.ale_tx_cmb = NULL;
1397 sc->ale_cdata.ale_tx_cmb_map = NULL;
1398 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1399 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1401 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1402 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1403 sc->ale_cdata.ale_buffer_tag = NULL;
1405 if (sc->ale_cdata.ale_parent_tag != NULL) {
1406 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1407 sc->ale_cdata.ale_parent_tag = NULL;
1412 ale_shutdown(device_t dev)
1415 return (ale_suspend(dev));
1419 * Note, this driver resets the link speed to 10/100Mbps by
1420 * restarting auto-negotiation in suspend/shutdown phase but we
1421 * don't know whether that auto-negotiation would succeed or not
1422 * as driver has no control after powering off/suspend operation.
1423 * If the renegotiation fail WOL may not work. Running at 1Gbps
1424 * will draw more power than 375mA at 3.3V which is specified in
1425 * PCI specification and that would result in complete
1426 * shutdowning power to ethernet controller.
1429 * Save current negotiated media speed/duplex/flow-control to
1430 * softc and restore the same link again after resuming. PHY
1431 * handling such as power down/resetting to 100Mbps may be better
1432 * handled in suspend method in phy driver.
1435 ale_setlinkspeed(struct ale_softc *sc)
1437 struct mii_data *mii;
1440 mii = device_get_softc(sc->ale_miibus);
1443 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1444 (IFM_ACTIVE | IFM_AVALID)) {
1445 switch IFM_SUBTYPE(mii->mii_media_active) {
1456 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1457 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1458 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1459 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1460 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1464 * Poll link state until ale(4) get a 10/100Mbps link.
1466 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1468 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1469 == (IFM_ACTIVE | IFM_AVALID)) {
1470 switch (IFM_SUBTYPE(
1471 mii->mii_media_active)) {
1481 pause("alelnk", hz);
1484 if (i == MII_ANEGTICKS_GIGE)
1485 device_printf(sc->ale_dev,
1486 "establishing a link failed, WOL may not work!");
1489 * No link, force MAC to have 100Mbps, full-duplex link.
1490 * This is the last resort and may/may not work.
1492 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1493 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1498 ale_setwol(struct ale_softc *sc)
1505 ALE_LOCK_ASSERT(sc);
1507 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1509 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1510 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1511 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1512 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1513 /* Force PHY power down. */
1514 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1515 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1516 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1517 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1518 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1523 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1524 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1525 ale_setlinkspeed(sc);
1529 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1530 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1531 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1532 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1533 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1535 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1536 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1537 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1538 reg |= MAC_CFG_RX_ENB;
1539 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1541 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1542 /* WOL disabled, PHY power down. */
1543 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1544 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1545 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1546 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1547 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1548 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1549 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1550 GPHY_CTRL_PWDOWN_HW);
1553 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1554 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1555 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1556 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1557 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1561 ale_suspend(device_t dev)
1563 struct ale_softc *sc;
1565 sc = device_get_softc(dev);
1576 ale_resume(device_t dev)
1578 struct ale_softc *sc;
1583 sc = device_get_softc(dev);
1586 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1587 /* Disable PME and clear PME status. */
1588 pmstat = pci_read_config(sc->ale_dev,
1589 pmc + PCIR_POWER_STATUS, 2);
1590 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1591 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1592 pci_write_config(sc->ale_dev,
1593 pmc + PCIR_POWER_STATUS, pmstat, 2);
1599 if ((ifp->if_flags & IFF_UP) != 0) {
1600 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1601 ale_init_locked(sc);
1609 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1611 struct ale_txdesc *txd, *txd_last;
1612 struct tx_desc *desc;
1616 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1618 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1619 int error, i, nsegs, prod, si;
1621 ALE_LOCK_ASSERT(sc);
1623 M_ASSERTPKTHDR((*m_head));
1630 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1632 * AR81xx requires offset of TCP/UDP payload in its Tx
1633 * descriptor to perform hardware Tx checksum offload.
1634 * Additionally, TSO requires IP/TCP header size and
1635 * modification of IP/TCP header in order to make TSO
1636 * engine work. This kind of operation takes many CPU
1637 * cycles on FreeBSD so fast host CPU is required to
1638 * get smooth TSO performance.
1640 struct ether_header *eh;
1642 if (M_WRITABLE(m) == 0) {
1643 /* Get a writable copy. */
1644 m = m_dup(*m_head, M_NOWAIT);
1645 /* Release original mbufs. */
1655 * Buggy-controller requires 4 byte aligned Tx buffer
1656 * to make custom checksum offload work.
1658 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1659 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1660 (mtod(m, intptr_t) & 3) != 0) {
1661 m = m_defrag(*m_head, M_NOWAIT);
1670 ip_off = sizeof(struct ether_header);
1671 m = m_pullup(m, ip_off);
1676 eh = mtod(m, struct ether_header *);
1678 * Check if hardware VLAN insertion is off.
1679 * Additional check for LLC/SNAP frame?
1681 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1682 ip_off = sizeof(struct ether_vlan_header);
1683 m = m_pullup(m, ip_off);
1689 m = m_pullup(m, ip_off + sizeof(struct ip));
1694 ip = (struct ip *)(mtod(m, char *) + ip_off);
1695 poff = ip_off + (ip->ip_hl << 2);
1696 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1699 * AR81xx requires the first descriptor should
1700 * not include any TCP playload for TSO case.
1701 * (i.e. ethernet header + IP + TCP header only)
1702 * m_pullup(9) above will ensure this too.
1703 * However it's not correct if the first mbuf
1704 * of the chain does not use cluster.
1706 m = m_pullup(m, poff + sizeof(struct tcphdr));
1711 ip = (struct ip *)(mtod(m, char *) + ip_off);
1712 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1713 m = m_pullup(m, poff + (tcp->th_off << 2));
1719 * AR81xx requires IP/TCP header size and offset as
1720 * well as TCP pseudo checksum which complicates
1721 * TSO configuration. I guess this comes from the
1722 * adherence to Microsoft NDIS Large Send
1723 * specification which requires insertion of
1724 * pseudo checksum by upper stack. The pseudo
1725 * checksum that NDIS refers to doesn't include
1726 * TCP payload length so ale(4) should recompute
1727 * the pseudo checksum here. Hopefully this wouldn't
1728 * be much burden on modern CPUs.
1729 * Reset IP checksum and recompute TCP pseudo
1730 * checksum as NDIS specification said.
1733 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1734 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1739 si = prod = sc->ale_cdata.ale_tx_prod;
1740 txd = &sc->ale_cdata.ale_txdesc[prod];
1742 map = txd->tx_dmamap;
1744 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1745 *m_head, txsegs, &nsegs, 0);
1746 if (error == EFBIG) {
1747 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1754 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1755 *m_head, txsegs, &nsegs, 0);
1761 } else if (error != 0)
1769 /* Check descriptor overrun. */
1770 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1771 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1774 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1777 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1778 /* Request TSO and set MSS. */
1779 cflags |= ALE_TD_TSO;
1780 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1781 /* Set IP/TCP header size. */
1782 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1783 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1784 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1786 * AR81xx supports Tx custom checksum offload feature
1787 * that offloads single 16bit checksum computation.
1788 * So you can choose one among IP, TCP and UDP.
1789 * Normally driver sets checksum start/insertion
1790 * position from the information of TCP/UDP frame as
1791 * TCP/UDP checksum takes more time than that of IP.
1792 * However it seems that custom checksum offload
1793 * requires 4 bytes aligned Tx buffers due to hardware
1795 * AR81xx also supports explicit Tx checksum computation
1796 * if it is told that the size of IP header and TCP
1797 * header(for UDP, the header size does not matter
1798 * because it's fixed length). However with this scheme
1799 * TSO does not work so you have to choose one either
1800 * TSO or explicit Tx checksum offload. I chosen TSO
1801 * plus custom checksum offload with work-around which
1802 * will cover most common usage for this consumer
1803 * ethernet controller. The work-around takes a lot of
1804 * CPU cycles if Tx buffer is not aligned on 4 bytes
1807 cflags |= ALE_TD_CXSUM;
1808 /* Set checksum start offset. */
1809 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1810 /* Set checksum insertion position of TCP/UDP. */
1811 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1812 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1815 /* Configure VLAN hardware tag insertion. */
1816 if ((m->m_flags & M_VLANTAG) != 0) {
1817 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1818 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1819 cflags |= ALE_TD_INSERT_VLAN_TAG;
1823 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1825 * Make sure the first fragment contains
1826 * only ethernet and IP/TCP header with options.
1828 hdrlen = poff + (tcp->th_off << 2);
1829 desc = &sc->ale_cdata.ale_tx_ring[prod];
1830 desc->addr = htole64(txsegs[i].ds_addr);
1831 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1832 desc->flags = htole32(cflags);
1833 sc->ale_cdata.ale_tx_cnt++;
1834 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1835 if (m->m_len - hdrlen > 0) {
1836 /* Handle remaining payload of the first fragment. */
1837 desc = &sc->ale_cdata.ale_tx_ring[prod];
1838 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1839 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1841 desc->flags = htole32(cflags);
1842 sc->ale_cdata.ale_tx_cnt++;
1843 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1847 for (; i < nsegs; i++) {
1848 desc = &sc->ale_cdata.ale_tx_ring[prod];
1849 desc->addr = htole64(txsegs[i].ds_addr);
1850 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1851 desc->flags = htole32(cflags);
1852 sc->ale_cdata.ale_tx_cnt++;
1853 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1855 /* Update producer index. */
1856 sc->ale_cdata.ale_tx_prod = prod;
1857 /* Set TSO header on the first descriptor. */
1858 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1859 desc = &sc->ale_cdata.ale_tx_ring[si];
1860 desc->flags |= htole32(ALE_TD_TSO_HDR);
1863 /* Finally set EOP on the last descriptor. */
1864 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1865 desc = &sc->ale_cdata.ale_tx_ring[prod];
1866 desc->flags |= htole32(ALE_TD_EOP);
1868 /* Swap dmamap of the first and the last. */
1869 txd = &sc->ale_cdata.ale_txdesc[prod];
1870 map = txd_last->tx_dmamap;
1871 txd_last->tx_dmamap = txd->tx_dmamap;
1872 txd->tx_dmamap = map;
1875 /* Sync descriptors. */
1876 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1877 sc->ale_cdata.ale_tx_ring_map,
1878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1884 ale_start(struct ifnet *ifp)
1886 struct ale_softc *sc;
1890 ale_start_locked(ifp);
1895 ale_start_locked(struct ifnet *ifp)
1897 struct ale_softc *sc;
1898 struct mbuf *m_head;
1903 ALE_LOCK_ASSERT(sc);
1905 /* Reclaim transmitted frames. */
1906 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1909 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1910 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1913 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1914 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1918 * Pack the data into the transmit ring. If we
1919 * don't have room, set the OACTIVE flag and wait
1920 * for the NIC to drain the ring.
1922 if (ale_encap(sc, &m_head)) {
1925 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1926 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1932 * If there's a BPF listener, bounce a copy of this frame
1935 ETHER_BPF_MTAP(ifp, m_head);
1940 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1941 sc->ale_cdata.ale_tx_prod);
1942 /* Set a timeout in case the chip goes out to lunch. */
1943 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1948 ale_watchdog(struct ale_softc *sc)
1952 ALE_LOCK_ASSERT(sc);
1954 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1958 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1959 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1961 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1962 ale_init_locked(sc);
1965 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1967 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1968 ale_init_locked(sc);
1969 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1970 ale_start_locked(ifp);
1974 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1976 struct ale_softc *sc;
1978 struct mii_data *mii;
1982 ifr = (struct ifreq *)data;
1986 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1987 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1988 ifr->ifr_mtu > ETHERMTU))
1990 else if (ifp->if_mtu != ifr->ifr_mtu) {
1992 ifp->if_mtu = ifr->ifr_mtu;
1993 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1994 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1995 ale_init_locked(sc);
2002 if ((ifp->if_flags & IFF_UP) != 0) {
2003 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2004 if (((ifp->if_flags ^ sc->ale_if_flags)
2005 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2008 ale_init_locked(sc);
2011 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2014 sc->ale_if_flags = ifp->if_flags;
2020 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2026 mii = device_get_softc(sc->ale_miibus);
2027 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2031 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2032 if ((mask & IFCAP_TXCSUM) != 0 &&
2033 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2034 ifp->if_capenable ^= IFCAP_TXCSUM;
2035 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2036 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2038 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2040 if ((mask & IFCAP_RXCSUM) != 0 &&
2041 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2042 ifp->if_capenable ^= IFCAP_RXCSUM;
2043 if ((mask & IFCAP_TSO4) != 0 &&
2044 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2045 ifp->if_capenable ^= IFCAP_TSO4;
2046 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2047 ifp->if_hwassist |= CSUM_TSO;
2049 ifp->if_hwassist &= ~CSUM_TSO;
2052 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2053 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2054 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2055 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2056 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2057 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2058 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2059 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2060 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2061 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2062 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2063 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2064 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2065 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2066 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2067 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2068 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2072 VLAN_CAPABILITIES(ifp);
2075 error = ether_ioctl(ifp, cmd, data);
2083 ale_mac_config(struct ale_softc *sc)
2085 struct mii_data *mii;
2088 ALE_LOCK_ASSERT(sc);
2090 mii = device_get_softc(sc->ale_miibus);
2091 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2092 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2093 MAC_CFG_SPEED_MASK);
2094 /* Reprogram MAC with resolved speed/duplex. */
2095 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2098 reg |= MAC_CFG_SPEED_10_100;
2101 reg |= MAC_CFG_SPEED_1000;
2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2105 reg |= MAC_CFG_FULL_DUPLEX;
2106 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2107 reg |= MAC_CFG_TX_FC;
2108 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2109 reg |= MAC_CFG_RX_FC;
2111 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2115 ale_stats_clear(struct ale_softc *sc)
2121 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2122 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2123 i += sizeof(uint32_t);
2125 /* Read Tx statistics. */
2126 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2127 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2128 i += sizeof(uint32_t);
2133 ale_stats_update(struct ale_softc *sc)
2135 struct ale_hw_stats *stat;
2136 struct smb sb, *smb;
2141 ALE_LOCK_ASSERT(sc);
2144 stat = &sc->ale_stats;
2147 /* Read Rx statistics. */
2148 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2149 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2150 i += sizeof(uint32_t);
2152 /* Read Tx statistics. */
2153 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2154 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2155 i += sizeof(uint32_t);
2159 stat->rx_frames += smb->rx_frames;
2160 stat->rx_bcast_frames += smb->rx_bcast_frames;
2161 stat->rx_mcast_frames += smb->rx_mcast_frames;
2162 stat->rx_pause_frames += smb->rx_pause_frames;
2163 stat->rx_control_frames += smb->rx_control_frames;
2164 stat->rx_crcerrs += smb->rx_crcerrs;
2165 stat->rx_lenerrs += smb->rx_lenerrs;
2166 stat->rx_bytes += smb->rx_bytes;
2167 stat->rx_runts += smb->rx_runts;
2168 stat->rx_fragments += smb->rx_fragments;
2169 stat->rx_pkts_64 += smb->rx_pkts_64;
2170 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2171 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2172 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2173 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2174 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2175 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2176 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2177 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2178 stat->rx_rrs_errs += smb->rx_rrs_errs;
2179 stat->rx_alignerrs += smb->rx_alignerrs;
2180 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2181 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2182 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2185 stat->tx_frames += smb->tx_frames;
2186 stat->tx_bcast_frames += smb->tx_bcast_frames;
2187 stat->tx_mcast_frames += smb->tx_mcast_frames;
2188 stat->tx_pause_frames += smb->tx_pause_frames;
2189 stat->tx_excess_defer += smb->tx_excess_defer;
2190 stat->tx_control_frames += smb->tx_control_frames;
2191 stat->tx_deferred += smb->tx_deferred;
2192 stat->tx_bytes += smb->tx_bytes;
2193 stat->tx_pkts_64 += smb->tx_pkts_64;
2194 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2195 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2196 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2197 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2198 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2199 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2200 stat->tx_single_colls += smb->tx_single_colls;
2201 stat->tx_multi_colls += smb->tx_multi_colls;
2202 stat->tx_late_colls += smb->tx_late_colls;
2203 stat->tx_excess_colls += smb->tx_excess_colls;
2204 stat->tx_abort += smb->tx_abort;
2205 stat->tx_underrun += smb->tx_underrun;
2206 stat->tx_desc_underrun += smb->tx_desc_underrun;
2207 stat->tx_lenerrs += smb->tx_lenerrs;
2208 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2209 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2210 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2212 /* Update counters in ifnet. */
2213 ifp->if_opackets += smb->tx_frames;
2215 ifp->if_collisions += smb->tx_single_colls +
2216 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2217 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2221 * tx_pkts_truncated counter looks suspicious. It constantly
2222 * increments with no sign of Tx errors. This may indicate
2223 * the counter name is not correct one so I've removed the
2224 * counter in output errors.
2226 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2229 ifp->if_ipackets += smb->rx_frames;
2231 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2232 smb->rx_runts + smb->rx_pkts_truncated +
2233 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2240 struct ale_softc *sc;
2243 sc = (struct ale_softc *)arg;
2245 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2246 if ((status & ALE_INTRS) == 0)
2247 return (FILTER_STRAY);
2248 /* Disable interrupts. */
2249 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2250 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2252 return (FILTER_HANDLED);
2256 ale_int_task(void *arg, int pending)
2258 struct ale_softc *sc;
2263 sc = (struct ale_softc *)arg;
2265 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2267 if (sc->ale_morework != 0)
2268 status |= INTR_RX_PKT;
2269 if ((status & ALE_INTRS) == 0)
2272 /* Acknowledge interrupts but still disable interrupts. */
2273 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2277 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2278 more = ale_rxeof(sc, sc->ale_process_limit);
2280 sc->ale_morework = 1;
2281 else if (more == EIO) {
2282 sc->ale_stats.reset_brk_seq++;
2283 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2284 ale_init_locked(sc);
2289 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2290 if ((status & INTR_DMA_RD_TO_RST) != 0)
2291 device_printf(sc->ale_dev,
2292 "DMA read error! -- resetting\n");
2293 if ((status & INTR_DMA_WR_TO_RST) != 0)
2294 device_printf(sc->ale_dev,
2295 "DMA write error! -- resetting\n");
2296 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2297 ale_init_locked(sc);
2301 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2302 ale_start_locked(ifp);
2305 if (more == EAGAIN ||
2306 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2308 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2315 /* Re-enable interrupts. */
2316 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2320 ale_txeof(struct ale_softc *sc)
2323 struct ale_txdesc *txd;
2324 uint32_t cons, prod;
2327 ALE_LOCK_ASSERT(sc);
2331 if (sc->ale_cdata.ale_tx_cnt == 0)
2334 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2335 sc->ale_cdata.ale_tx_ring_map,
2336 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2337 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2338 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2339 sc->ale_cdata.ale_tx_cmb_map,
2340 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2341 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2343 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2344 cons = sc->ale_cdata.ale_tx_cons;
2346 * Go through our Tx list and free mbufs for those
2347 * frames which have been transmitted.
2349 for (prog = 0; cons != prod; prog++,
2350 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2351 if (sc->ale_cdata.ale_tx_cnt <= 0)
2354 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2355 sc->ale_cdata.ale_tx_cnt--;
2356 txd = &sc->ale_cdata.ale_txdesc[cons];
2357 if (txd->tx_m != NULL) {
2358 /* Reclaim transmitted mbufs. */
2359 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2360 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2361 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2369 sc->ale_cdata.ale_tx_cons = cons;
2371 * Unarm watchdog timer only when there is no pending
2372 * Tx descriptors in queue.
2374 if (sc->ale_cdata.ale_tx_cnt == 0)
2375 sc->ale_watchdog_timer = 0;
2380 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2381 uint32_t length, uint32_t *prod)
2383 struct ale_rx_page *rx_page;
2386 /* Update consumer position. */
2387 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2389 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2391 * End of Rx page reached, let hardware reuse
2395 *rx_page->cmb_addr = 0;
2396 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2400 /* Switch to alternate Rx page. */
2401 sc->ale_cdata.ale_rx_curp ^= 1;
2403 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2404 /* Page flipped, sync CMB and Rx page. */
2405 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2407 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2409 /* Sync completed, cache updated producer index. */
2410 *prod = *rx_page->cmb_addr;
2416 * It seems that AR81xx controller can compute partial checksum.
2417 * The partial checksum value can be used to accelerate checksum
2418 * computation for fragmented TCP/UDP packets. Upper network stack
2419 * already takes advantage of the partial checksum value in IP
2420 * reassembly stage. But I'm not sure the correctness of the
2421 * partial hardware checksum assistance due to lack of data sheet.
2422 * In addition, the Rx feature of controller that requires copying
2423 * for every frames effectively nullifies one of most nice offload
2424 * capability of controller.
2427 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2434 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2435 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2436 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2438 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2439 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2440 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2441 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2442 m->m_pkthdr.csum_flags |=
2443 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2444 m->m_pkthdr.csum_data = 0xffff;
2447 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2448 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2449 p = mtod(m, char *);
2451 if ((status & ALE_RD_802_3) != 0)
2452 p += LLC_SNAPFRAMELEN;
2453 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2454 (status & ALE_RD_VLAN) != 0)
2455 p += ETHER_VLAN_ENCAP_LEN;
2456 ip = (struct ip *)p;
2457 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2459 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2461 m->m_pkthdr.csum_data = 0xffff;
2465 * Don't mark bad checksum for TCP/UDP frames
2466 * as fragmented frames may always have set
2467 * bad checksummed bit of frame status.
2471 /* Process received frames. */
2473 ale_rxeof(struct ale_softc *sc, int count)
2475 struct ale_rx_page *rx_page;
2479 uint32_t length, prod, seqno, status, vtags;
2483 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2484 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2485 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2486 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2489 * Don't directly access producer index as hardware may
2490 * update it while Rx handler is in progress. It would
2491 * be even better if there is a way to let hardware
2492 * know how far driver processed its received frames.
2493 * Alternatively, hardware could provide a way to disable
2494 * CMB updates until driver acknowledges the end of CMB
2497 prod = *rx_page->cmb_addr;
2498 for (prog = 0; prog < count; prog++) {
2499 if (rx_page->cons >= prod)
2501 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2502 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2503 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2505 * Normally I believe this should not happen unless
2506 * severe driver bug or corrupted memory. However
2507 * it seems to happen under certain conditions which
2508 * is triggered by abrupt Rx events such as initiation
2509 * of bulk transfer of remote host. It's not easy to
2510 * reproduce this and I doubt it could be related
2511 * with FIFO overflow of hardware or activity of Tx
2512 * CMB updates. I also remember similar behaviour
2513 * seen on RealTek 8139 which uses resembling Rx
2517 device_printf(sc->ale_dev,
2518 "garbled seq: %u, expected: %u -- "
2519 "resetting!\n", seqno,
2520 sc->ale_cdata.ale_rx_seqno);
2523 /* Frame received. */
2524 sc->ale_cdata.ale_rx_seqno++;
2525 length = ALE_RX_BYTES(le32toh(rs->length));
2526 status = le32toh(rs->flags);
2527 if ((status & ALE_RD_ERROR) != 0) {
2529 * We want to pass the following frames to upper
2530 * layer regardless of error status of Rx return
2533 * o IP/TCP/UDP checksum is bad.
2534 * o frame length and protocol specific length
2537 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2538 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2539 ALE_RD_TRUNC)) != 0) {
2540 ale_rx_update_page(sc, &rx_page, length, &prod);
2545 * m_devget(9) is major bottle-neck of ale(4)(It comes
2546 * from hardware limitation). For jumbo frames we could
2547 * get a slightly better performance if driver use
2548 * m_getjcl(9) with proper buffer size argument. However
2549 * that would make code more complicated and I don't
2550 * think users would expect good Rx performance numbers
2551 * on these low-end consumer ethernet controller.
2553 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2554 ETHER_ALIGN, ifp, NULL);
2557 ale_rx_update_page(sc, &rx_page, length, &prod);
2560 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2561 (status & ALE_RD_IPV4) != 0)
2562 ale_rxcsum(sc, m, status);
2563 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2564 (status & ALE_RD_VLAN) != 0) {
2565 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2566 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2567 m->m_flags |= M_VLANTAG;
2570 /* Pass it to upper layer. */
2572 (*ifp->if_input)(ifp, m);
2575 ale_rx_update_page(sc, &rx_page, length, &prod);
2578 return (count > 0 ? 0 : EAGAIN);
2584 struct ale_softc *sc;
2585 struct mii_data *mii;
2587 sc = (struct ale_softc *)arg;
2589 ALE_LOCK_ASSERT(sc);
2591 mii = device_get_softc(sc->ale_miibus);
2593 ale_stats_update(sc);
2595 * Reclaim Tx buffers that have been transferred. It's not
2596 * needed here but it would release allocated mbuf chains
2597 * faster and limit the maximum delay to a hz.
2601 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2605 ale_reset(struct ale_softc *sc)
2610 /* Initialize PCIe module. From Linux. */
2611 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2613 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2614 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2616 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2620 device_printf(sc->ale_dev, "master reset timeout!\n");
2622 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2623 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2629 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2635 struct ale_softc *sc;
2637 sc = (struct ale_softc *)xsc;
2639 ale_init_locked(sc);
2644 ale_init_locked(struct ale_softc *sc)
2647 struct mii_data *mii;
2648 uint8_t eaddr[ETHER_ADDR_LEN];
2650 uint32_t reg, rxf_hi, rxf_lo;
2652 ALE_LOCK_ASSERT(sc);
2655 mii = device_get_softc(sc->ale_miibus);
2657 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2660 * Cancel any pending I/O.
2664 * Reset the chip to a known state.
2667 /* Initialize Tx descriptors, DMA memory blocks. */
2668 ale_init_rx_pages(sc);
2669 ale_init_tx_ring(sc);
2671 /* Reprogram the station address. */
2672 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2673 CSR_WRITE_4(sc, ALE_PAR0,
2674 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2675 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2677 * Clear WOL status and disable all WOL feature as WOL
2678 * would interfere Rx operation under normal environments.
2680 CSR_READ_4(sc, ALE_WOL_CFG);
2681 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2683 * Set Tx descriptor/RXF0/CMB base addresses. They share
2684 * the same high address part of DMAable region.
2686 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2687 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2688 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2689 CSR_WRITE_4(sc, ALE_TPD_CNT,
2690 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2691 /* Set Rx page base address, note we use single queue. */
2692 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2693 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2694 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2695 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2696 /* Set Tx/Rx CMB addresses. */
2697 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2698 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2699 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2700 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2701 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2702 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2703 /* Mark RXF0 is valid. */
2704 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2705 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2707 * No need to initialize RFX1/RXF2/RXF3. We don't use
2711 /* Set Rx page size, excluding guard frame size. */
2712 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2713 /* Tell hardware that we're ready to load DMA blocks. */
2714 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2716 /* Set Rx/Tx interrupt trigger threshold. */
2717 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2718 (4 << INT_TRIG_TX_THRESH_SHIFT));
2721 * Set interrupt trigger timer, its purpose and relation
2722 * with interrupt moderation mechanism is not clear yet.
2724 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2725 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2726 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2728 /* Configure interrupt moderation timer. */
2729 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2730 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2731 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2732 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2733 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2734 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2735 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2736 reg |= MASTER_IM_RX_TIMER_ENB;
2737 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2738 reg |= MASTER_IM_TX_TIMER_ENB;
2739 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2740 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2742 /* Set Maximum frame size of controller. */
2743 if (ifp->if_mtu < ETHERMTU)
2744 sc->ale_max_frame_size = ETHERMTU;
2746 sc->ale_max_frame_size = ifp->if_mtu;
2747 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2749 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2750 /* Configure IPG/IFG parameters. */
2751 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2752 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2753 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2754 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2755 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2756 /* Set parameters for half-duplex media. */
2757 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2758 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2759 HDPX_CFG_LCOL_MASK) |
2760 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2761 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2762 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2763 HDPX_CFG_ABEBT_MASK) |
2764 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2765 HDPX_CFG_JAMIPG_MASK));
2767 /* Configure Tx jumbo frame parameters. */
2768 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2769 if (ifp->if_mtu < ETHERMTU)
2770 reg = sc->ale_max_frame_size;
2771 else if (ifp->if_mtu < 6 * 1024)
2772 reg = (sc->ale_max_frame_size * 2) / 3;
2774 reg = sc->ale_max_frame_size / 2;
2775 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2776 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2777 TX_JUMBO_THRESH_UNIT_SHIFT);
2779 /* Configure TxQ. */
2780 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2781 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2782 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2783 TXQ_CFG_TPD_BURST_MASK;
2784 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2786 /* Configure Rx jumbo frame & flow control parameters. */
2787 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2788 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2789 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2790 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2791 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2792 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2793 RX_JUMBO_LKAH_MASK));
2794 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2795 rxf_hi = (reg * 7) / 10;
2796 rxf_lo = (reg * 3)/ 10;
2797 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2798 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2799 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2800 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2801 RX_FIFO_PAUSE_THRESH_HI_MASK));
2805 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2806 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2808 /* Configure RxQ. */
2809 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2810 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2812 /* Configure DMA parameters. */
2814 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2815 reg |= DMA_CFG_TXCMB_ENB;
2816 CSR_WRITE_4(sc, ALE_DMA_CFG,
2817 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2818 sc->ale_dma_rd_burst | reg |
2819 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2820 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2821 DMA_CFG_RD_DELAY_CNT_MASK) |
2822 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2823 DMA_CFG_WR_DELAY_CNT_MASK));
2826 * Hardware can be configured to issue SMB interrupt based
2827 * on programmed interval. Since there is a callout that is
2828 * invoked for every hz in driver we use that instead of
2829 * relying on periodic SMB interrupt.
2831 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2832 /* Clear MAC statistics. */
2833 ale_stats_clear(sc);
2836 * Configure Tx/Rx MACs.
2837 * - Auto-padding for short frames.
2838 * - Enable CRC generation.
2839 * Actual reconfiguration of MAC for resolved speed/duplex
2840 * is followed after detection of link establishment.
2841 * AR81xx always does checksum computation regardless of
2842 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2843 * cause Rx handling issue for fragmented IP datagrams due
2846 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2847 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2848 MAC_CFG_PREAMBLE_MASK);
2849 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2850 reg |= MAC_CFG_SPEED_10_100;
2852 reg |= MAC_CFG_SPEED_1000;
2853 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2855 /* Set up the receive filter. */
2859 /* Acknowledge all pending interrupts and clear it. */
2860 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2862 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2864 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2867 sc->ale_flags &= ~ALE_FLAG_LINK;
2868 /* Switch to the current media. */
2871 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2875 ale_stop(struct ale_softc *sc)
2878 struct ale_txdesc *txd;
2882 ALE_LOCK_ASSERT(sc);
2884 * Mark the interface down and cancel the watchdog timer.
2887 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2888 sc->ale_flags &= ~ALE_FLAG_LINK;
2889 callout_stop(&sc->ale_tick_ch);
2890 sc->ale_watchdog_timer = 0;
2891 ale_stats_update(sc);
2892 /* Disable interrupts. */
2893 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2894 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2895 /* Disable queue processing and DMA. */
2896 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2897 reg &= ~TXQ_CFG_ENB;
2898 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2899 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2900 reg &= ~RXQ_CFG_ENB;
2901 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2902 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2903 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2904 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2906 /* Stop Rx/Tx MACs. */
2908 /* Disable interrupts which might be touched in taskq handler. */
2909 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2912 * Free TX mbufs still in the queues.
2914 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2915 txd = &sc->ale_cdata.ale_txdesc[i];
2916 if (txd->tx_m != NULL) {
2917 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2918 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2919 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2928 ale_stop_mac(struct ale_softc *sc)
2933 ALE_LOCK_ASSERT(sc);
2935 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2936 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2937 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2938 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2941 for (i = ALE_TIMEOUT; i > 0; i--) {
2942 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2948 device_printf(sc->ale_dev,
2949 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2953 ale_init_tx_ring(struct ale_softc *sc)
2955 struct ale_txdesc *txd;
2958 ALE_LOCK_ASSERT(sc);
2960 sc->ale_cdata.ale_tx_prod = 0;
2961 sc->ale_cdata.ale_tx_cons = 0;
2962 sc->ale_cdata.ale_tx_cnt = 0;
2964 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2965 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2966 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2967 txd = &sc->ale_cdata.ale_txdesc[i];
2970 *sc->ale_cdata.ale_tx_cmb = 0;
2971 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2972 sc->ale_cdata.ale_tx_cmb_map,
2973 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2974 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2975 sc->ale_cdata.ale_tx_ring_map,
2976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2980 ale_init_rx_pages(struct ale_softc *sc)
2982 struct ale_rx_page *rx_page;
2985 ALE_LOCK_ASSERT(sc);
2987 sc->ale_morework = 0;
2988 sc->ale_cdata.ale_rx_seqno = 0;
2989 sc->ale_cdata.ale_rx_curp = 0;
2991 for (i = 0; i < ALE_RX_PAGES; i++) {
2992 rx_page = &sc->ale_cdata.ale_rx_page[i];
2993 bzero(rx_page->page_addr, sc->ale_pagesize);
2994 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2996 *rx_page->cmb_addr = 0;
2997 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2999 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
3000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3005 ale_rxvlan(struct ale_softc *sc)
3010 ALE_LOCK_ASSERT(sc);
3013 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3014 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3015 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3016 reg |= MAC_CFG_VLAN_TAG_STRIP;
3017 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3021 ale_rxfilter(struct ale_softc *sc)
3024 struct ifmultiaddr *ifma;
3029 ALE_LOCK_ASSERT(sc);
3033 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3034 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3035 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3036 rxcfg |= MAC_CFG_BCAST;
3037 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3038 if ((ifp->if_flags & IFF_PROMISC) != 0)
3039 rxcfg |= MAC_CFG_PROMISC;
3040 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3041 rxcfg |= MAC_CFG_ALLMULTI;
3042 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3043 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3044 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3048 /* Program new filter. */
3049 bzero(mchash, sizeof(mchash));
3051 if_maddr_rlock(ifp);
3052 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3053 if (ifma->ifma_addr->sa_family != AF_LINK)
3055 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3056 ifma->ifma_addr), ETHER_ADDR_LEN);
3057 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3059 if_maddr_runlock(ifp);
3061 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3062 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3063 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3067 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3073 value = *(int *)arg1;
3074 error = sysctl_handle_int(oidp, &value, 0, req);
3075 if (error || req->newptr == NULL)
3077 if (value < low || value > high)
3079 *(int *)arg1 = value;
3085 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3087 return (sysctl_int_range(oidp, arg1, arg2, req,
3088 ALE_PROC_MIN, ALE_PROC_MAX));
3092 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3095 return (sysctl_int_range(oidp, arg1, arg2, req,
3096 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));