2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* This is driver for SoftDMA device built using Altera FIFO component. */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/kthread.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/resource.h>
50 #include <machine/bus.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
58 #include <dev/altera/softdma/a_api.h>
60 #include <dev/xdma/xdma.h>
67 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
69 #define dprintf(fmt, ...)
72 #define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16
73 #define SOFTDMA_NCHANNELS 1
74 #define CONTROL_GEN_SOP (1 << 0)
75 #define CONTROL_GEN_EOP (1 << 1)
76 #define CONTROL_OWN (1 << 31)
78 #define SOFTDMA_RX_EVENTS \
79 (A_ONCHIP_FIFO_MEM_CORE_INTR_FULL | \
80 A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
81 A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
82 #define SOFTDMA_TX_EVENTS \
83 (A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY | \
84 A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
85 A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
87 struct softdma_channel {
88 struct softdma_softc *sc;
90 xdma_channel_t *xchan;
97 struct softdma_desc *descs;
100 uint32_t descs_used_count;
103 struct softdma_desc {
107 uint32_t access_width;
112 struct softdma_desc *next;
119 struct softdma_softc {
121 struct resource *res[3];
123 bus_space_handle_t bsh;
124 bus_space_tag_t bst_c;
125 bus_space_handle_t bsh_c;
127 struct softdma_channel channels[SOFTDMA_NCHANNELS];
130 static struct resource_spec softdma_spec[] = {
131 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* fifo */
132 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* core */
133 { SYS_RES_IRQ, 0, RF_ACTIVE },
137 static int softdma_probe(device_t dev);
138 static int softdma_attach(device_t dev);
139 static int softdma_detach(device_t dev);
141 static inline uint32_t
142 softdma_next_desc(struct softdma_channel *chan, uint32_t curidx)
145 return ((curidx + 1) % chan->descs_num);
149 softdma_mem_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
152 bus_write_4(sc->res[0], reg, htole32(val));
156 softdma_mem_read(struct softdma_softc *sc, uint32_t reg)
160 val = bus_read_4(sc->res[0], reg);
162 return (le32toh(val));
166 softdma_memc_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
169 bus_write_4(sc->res[1], reg, htole32(val));
173 softdma_memc_read(struct softdma_softc *sc, uint32_t reg)
177 val = bus_read_4(sc->res[1], reg);
179 return (le32toh(val));
183 softdma_fill_level(struct softdma_softc *sc)
187 val = softdma_memc_read(sc,
188 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL);
194 softdma_intr(void *arg)
196 struct softdma_channel *chan;
197 struct softdma_softc *sc;
203 chan = &sc->channels[0];
205 reg = softdma_memc_read(sc, A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT);
207 if (reg & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW |
208 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
210 err = (((reg & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> \
211 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
215 softdma_memc_write(sc,
216 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, reg);
223 softdma_probe(device_t dev)
226 if (!ofw_bus_status_okay(dev))
229 if (!ofw_bus_is_compatible(dev, "altr,softdma"))
232 device_set_desc(dev, "SoftDMA");
234 return (BUS_PROBE_DEFAULT);
238 softdma_attach(device_t dev)
240 struct softdma_softc *sc;
241 phandle_t xref, node;
244 sc = device_get_softc(dev);
247 if (bus_alloc_resources(dev, softdma_spec, sc->res)) {
249 "could not allocate resources for device\n");
253 /* FIFO memory interface */
254 sc->bst = rman_get_bustag(sc->res[0]);
255 sc->bsh = rman_get_bushandle(sc->res[0]);
257 /* FIFO control memory interface */
258 sc->bst_c = rman_get_bustag(sc->res[1]);
259 sc->bsh_c = rman_get_bushandle(sc->res[1]);
261 /* Setup interrupt handler */
262 err = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
263 NULL, softdma_intr, sc, &sc->ih);
265 device_printf(dev, "Unable to alloc interrupt resource.\n");
269 node = ofw_bus_get_node(dev);
270 xref = OF_xref_from_node(node);
271 OF_device_register_xref(xref, dev);
277 softdma_detach(device_t dev)
279 struct softdma_softc *sc;
281 sc = device_get_softc(dev);
287 softdma_process_tx(struct softdma_channel *chan, struct softdma_desc *desc)
289 struct softdma_softc *sc;
290 uint32_t src_offs, dst_offs;
300 fill_level = softdma_fill_level(sc);
301 while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH)
302 fill_level = softdma_fill_level(sc);
304 /* Set start of packet. */
305 if (desc->control & CONTROL_GEN_SOP) {
307 reg |= A_ONCHIP_FIFO_MEM_CORE_SOP;
308 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA, reg);
311 src_offs = dst_offs = 0;
313 while ((desc->len - c) >= 4) {
314 val = *(uint32_t *)(desc->src_addr + src_offs);
315 bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, val);
322 while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH) {
323 fill_level = softdma_fill_level(sc);
329 leftm = (desc->len - c);
333 val = *(uint8_t *)(desc->src_addr + src_offs);
339 val = *(uint16_t *)(desc->src_addr + src_offs);
344 tmp = *(uint8_t *)(desc->src_addr + src_offs);
354 /* Set end of packet. */
356 if (desc->control & CONTROL_GEN_EOP)
357 reg |= A_ONCHIP_FIFO_MEM_CORE_EOP;
358 reg |= ((4 - leftm) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT);
359 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA, reg);
361 /* Ensure there is a FIFO entry available. */
362 fill_level = softdma_fill_level(sc);
363 while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH)
364 fill_level = softdma_fill_level(sc);
367 bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, val);
373 softdma_process_rx(struct softdma_channel *chan, struct softdma_desc *desc)
375 uint32_t src_offs, dst_offs;
376 struct softdma_softc *sc;
388 src_offs = dst_offs = 0;
391 fill_level = softdma_fill_level(sc);
392 if (fill_level == 0) {
393 /* Nothing to receive. */
402 data = bus_read_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA);
403 meta = softdma_mem_read(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA);
405 if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) {
410 if ((meta & A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK) != 0) {
415 if (meta & A_ONCHIP_FIFO_MEM_CORE_SOP) {
419 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) {
420 empty = (meta & A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >>
421 A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT;
430 *(uint32_t *)(desc->dst_addr + dst_offs) = data;
432 } else if (empty == 1) {
433 *(uint16_t *)(desc->dst_addr + dst_offs) =
434 ((data >> 16) & 0xffff);
437 *(uint8_t *)(desc->dst_addr + dst_offs) =
438 ((data >> 8) & 0xff);
441 panic("empty %d\n", empty);
444 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP)
447 fill_level = softdma_fill_level(sc);
449 while (fill_level == 0 && timeout--)
450 fill_level = softdma_fill_level(sc);
452 /* No EOP received. Broken packet. */
466 softdma_process_descriptors(struct softdma_channel *chan,
467 xdma_transfer_status_t *status)
469 struct xdma_channel *xchan;
470 struct softdma_desc *desc;
471 struct softdma_softc *sc;
472 xdma_transfer_status_t st;
479 desc = &chan->descs[chan->idx_tail];
481 while (desc != NULL) {
483 if ((desc->control & CONTROL_OWN) == 0) {
487 if (desc->direction == XDMA_MEM_TO_DEV) {
488 ret = softdma_process_tx(chan, desc);
490 ret = softdma_process_rx(chan, desc);
492 /* No new data available. */
497 /* Descriptor processed. */
502 st.transferred = ret;
508 xchan_seg_done(xchan, &st);
509 atomic_subtract_int(&chan->descs_used_count, 1);
512 status->transferred += ret;
518 chan->idx_tail = softdma_next_desc(chan, chan->idx_tail);
520 /* Process next descriptor, if any. */
528 softdma_worker(void *arg)
530 xdma_transfer_status_t status;
531 struct softdma_channel *chan;
532 struct softdma_softc *sc;
539 mtx_lock(&chan->mtx);
542 mtx_sleep(chan, &chan->mtx, 0, "softdma_wait", hz / 2);
543 } while (chan->run == 0);
546 status.transferred = 0;
548 softdma_process_descriptors(chan, &status);
550 /* Finish operation */
552 xdma_callback(chan->xchan, &status);
554 mtx_unlock(&chan->mtx);
560 softdma_proc_create(struct softdma_channel *chan)
562 struct softdma_softc *sc;
566 if (chan->p != NULL) {
567 /* Already created */
571 mtx_init(&chan->mtx, "SoftDMA", NULL, MTX_DEF);
573 if (kproc_create(softdma_worker, (void *)chan, &chan->p, 0, 0,
574 "softdma_worker") != 0) {
575 device_printf(sc->dev,
576 "%s: Failed to create worker thread.\n", __func__);
584 softdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
586 struct softdma_channel *chan;
587 struct softdma_softc *sc;
590 sc = device_get_softc(dev);
592 for (i = 0; i < SOFTDMA_NCHANNELS; i++) {
593 chan = &sc->channels[i];
594 if (chan->used == 0) {
596 xchan->chan = (void *)chan;
600 chan->descs_used_count = 0;
601 chan->descs_num = 1024;
604 if (softdma_proc_create(chan) != 0) {
618 softdma_channel_free(device_t dev, struct xdma_channel *xchan)
620 struct softdma_channel *chan;
621 struct softdma_softc *sc;
623 sc = device_get_softc(dev);
625 chan = (struct softdma_channel *)xchan->chan;
627 if (chan->descs != NULL) {
628 free(chan->descs, M_DEVBUF);
637 softdma_desc_alloc(struct xdma_channel *xchan)
639 struct softdma_channel *chan;
642 chan = (struct softdma_channel *)xchan->chan;
644 nsegments = chan->descs_num;
646 chan->descs = malloc(nsegments * sizeof(struct softdma_desc),
647 M_DEVBUF, (M_WAITOK | M_ZERO));
653 softdma_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
655 struct softdma_channel *chan;
656 struct softdma_desc *desc;
657 struct softdma_softc *sc;
661 sc = device_get_softc(dev);
663 chan = (struct softdma_channel *)xchan->chan;
665 ret = softdma_desc_alloc(xchan);
667 device_printf(sc->dev,
668 "%s: Can't allocate descriptors.\n", __func__);
672 for (i = 0; i < chan->descs_num; i++) {
673 desc = &chan->descs[i];
675 if (i == (chan->descs_num - 1)) {
676 desc->next = &chan->descs[0];
678 desc->next = &chan->descs[i+1];
686 softdma_channel_capacity(device_t dev, xdma_channel_t *xchan,
689 struct softdma_channel *chan;
692 chan = (struct softdma_channel *)xchan->chan;
694 /* At least one descriptor must be left empty. */
695 c = (chan->descs_num - chan->descs_used_count - 1);
703 softdma_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
704 struct xdma_sglist *sg, uint32_t sg_n)
706 struct softdma_channel *chan;
707 struct softdma_desc *desc;
708 struct softdma_softc *sc;
715 sc = device_get_softc(dev);
717 chan = (struct softdma_channel *)xchan->chan;
721 for (i = 0; i < sg_n; i++) {
722 len = (uint32_t)sg[i].len;
724 desc = &chan->descs[chan->idx_head];
725 desc->src_addr = sg[i].src_addr;
726 desc->dst_addr = sg[i].dst_addr;
727 if (sg[i].direction == XDMA_MEM_TO_DEV) {
734 desc->direction = sg[i].direction;
735 saved_dir = sg[i].direction;
737 desc->transfered = 0;
742 if (sg[i].first == 1)
743 desc->control |= CONTROL_GEN_SOP;
745 desc->control |= CONTROL_GEN_EOP;
747 tmp = chan->idx_head;
748 chan->idx_head = softdma_next_desc(chan, chan->idx_head);
749 atomic_add_int(&chan->descs_used_count, 1);
750 desc->control |= CONTROL_OWN;
757 if (saved_dir == XDMA_MEM_TO_DEV) {
761 softdma_memc_write(sc,
762 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE,
769 softdma_channel_request(device_t dev, struct xdma_channel *xchan,
770 struct xdma_request *req)
772 struct softdma_channel *chan;
773 struct softdma_desc *desc;
774 struct softdma_softc *sc;
777 sc = device_get_softc(dev);
779 chan = (struct softdma_channel *)xchan->chan;
781 ret = softdma_desc_alloc(xchan);
783 device_printf(sc->dev,
784 "%s: Can't allocate descriptors.\n", __func__);
788 desc = &chan->descs[0];
790 desc->src_addr = req->src_addr;
791 desc->dst_addr = req->dst_addr;
792 desc->len = req->block_len;
801 softdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
803 struct softdma_channel *chan;
804 struct softdma_softc *sc;
806 sc = device_get_softc(dev);
808 chan = (struct softdma_channel *)xchan->chan;
812 case XDMA_CMD_TERMINATE:
814 /* TODO: implement me */
823 softdma_ofw_md_data(device_t dev, pcell_t *cells,
824 int ncells, void **ptr)
831 static device_method_t softdma_methods[] = {
832 /* Device interface */
833 DEVMETHOD(device_probe, softdma_probe),
834 DEVMETHOD(device_attach, softdma_attach),
835 DEVMETHOD(device_detach, softdma_detach),
838 DEVMETHOD(xdma_channel_alloc, softdma_channel_alloc),
839 DEVMETHOD(xdma_channel_free, softdma_channel_free),
840 DEVMETHOD(xdma_channel_request, softdma_channel_request),
841 DEVMETHOD(xdma_channel_control, softdma_channel_control),
843 /* xDMA SG Interface */
844 DEVMETHOD(xdma_channel_prep_sg, softdma_channel_prep_sg),
845 DEVMETHOD(xdma_channel_submit_sg, softdma_channel_submit_sg),
846 DEVMETHOD(xdma_channel_capacity, softdma_channel_capacity),
849 DEVMETHOD(xdma_ofw_md_data, softdma_ofw_md_data),
855 static driver_t softdma_driver = {
858 sizeof(struct softdma_softc),
861 static devclass_t softdma_devclass;
863 EARLY_DRIVER_MODULE(softdma, simplebus, softdma_driver, softdma_devclass, 0, 0,
864 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);