2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* This is driver for SoftDMA device built using Altera FIFO component. */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/kthread.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/resource.h>
50 #include <machine/bus.h>
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
58 #include <dev/altera/softdma/a_api.h>
60 #include <dev/xdma/xdma.h>
67 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
69 #define dprintf(fmt, ...)
72 #define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16
73 #define SOFTDMA_NCHANNELS 1
74 #define CONTROL_GEN_SOP (1 << 0)
75 #define CONTROL_GEN_EOP (1 << 1)
76 #define CONTROL_OWN (1 << 31)
78 #define SOFTDMA_RX_EVENTS \
79 (A_ONCHIP_FIFO_MEM_CORE_INTR_FULL | \
80 A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
81 A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
82 #define SOFTDMA_TX_EVENTS \
83 (A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY | \
84 A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
85 A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
87 struct softdma_channel {
88 struct softdma_softc *sc;
90 xdma_channel_t *xchan;
97 struct softdma_desc *descs;
100 uint32_t descs_used_count;
103 struct softdma_desc {
107 uint32_t access_width;
112 struct softdma_desc *next;
119 struct softdma_softc {
121 struct resource *res[3];
123 bus_space_handle_t bsh;
124 bus_space_tag_t bst_c;
125 bus_space_handle_t bsh_c;
127 struct softdma_channel channels[SOFTDMA_NCHANNELS];
130 static struct resource_spec softdma_spec[] = {
131 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* fifo */
132 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* core */
133 { SYS_RES_IRQ, 0, RF_ACTIVE },
137 static int softdma_probe(device_t dev);
138 static int softdma_attach(device_t dev);
139 static int softdma_detach(device_t dev);
141 static inline uint32_t
142 softdma_next_desc(struct softdma_channel *chan, uint32_t curidx)
145 return ((curidx + 1) % chan->descs_num);
149 softdma_mem_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
152 bus_write_4(sc->res[0], reg, htole32(val));
156 softdma_mem_read(struct softdma_softc *sc, uint32_t reg)
160 val = bus_read_4(sc->res[0], reg);
162 return (le32toh(val));
166 softdma_memc_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
169 bus_write_4(sc->res[1], reg, htole32(val));
173 softdma_memc_read(struct softdma_softc *sc, uint32_t reg)
177 val = bus_read_4(sc->res[1], reg);
179 return (le32toh(val));
183 softdma_fill_level(struct softdma_softc *sc)
187 val = softdma_memc_read(sc,
188 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL);
194 fifo_fill_level_wait(struct softdma_softc *sc)
199 val = softdma_fill_level(sc);
200 while (val == AVALON_FIFO_TX_BASIC_OPTS_DEPTH);
206 softdma_intr(void *arg)
208 struct softdma_channel *chan;
209 struct softdma_softc *sc;
215 chan = &sc->channels[0];
217 reg = softdma_memc_read(sc, A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT);
219 if (reg & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW |
220 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
222 err = (((reg & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> \
223 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
227 softdma_memc_write(sc,
228 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, reg);
235 softdma_probe(device_t dev)
238 if (!ofw_bus_status_okay(dev))
241 if (!ofw_bus_is_compatible(dev, "altr,softdma"))
244 device_set_desc(dev, "SoftDMA");
246 return (BUS_PROBE_DEFAULT);
250 softdma_attach(device_t dev)
252 struct softdma_softc *sc;
253 phandle_t xref, node;
256 sc = device_get_softc(dev);
259 if (bus_alloc_resources(dev, softdma_spec, sc->res)) {
261 "could not allocate resources for device\n");
265 /* FIFO memory interface */
266 sc->bst = rman_get_bustag(sc->res[0]);
267 sc->bsh = rman_get_bushandle(sc->res[0]);
269 /* FIFO control memory interface */
270 sc->bst_c = rman_get_bustag(sc->res[1]);
271 sc->bsh_c = rman_get_bushandle(sc->res[1]);
273 /* Setup interrupt handler */
274 err = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
275 NULL, softdma_intr, sc, &sc->ih);
277 device_printf(dev, "Unable to alloc interrupt resource.\n");
281 node = ofw_bus_get_node(dev);
282 xref = OF_xref_from_node(node);
283 OF_device_register_xref(xref, dev);
289 softdma_detach(device_t dev)
291 struct softdma_softc *sc;
293 sc = device_get_softc(dev);
299 softdma_process_tx(struct softdma_channel *chan, struct softdma_desc *desc)
301 struct softdma_softc *sc;
312 fifo_fill_level_wait(sc);
314 /* Set start of packet. */
315 if (desc->control & CONTROL_GEN_SOP)
316 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA,
317 A_ONCHIP_FIFO_MEM_CORE_SOP);
322 addr = desc->src_addr;
326 buf = (buf << 8) | *(uint8_t *)addr;
332 if (len >= 2 && addr & 2) {
333 buf = (buf << 16) | *(uint16_t *)addr;
340 buf = (buf << 32) | (uint64_t)*(uint32_t *)addr;
343 word = (uint32_t)((buf >> got_bits) & 0xffffffff);
345 fifo_fill_level_wait(sc);
346 if (len == 0 && got_bits == 0 &&
347 (desc->control & CONTROL_GEN_EOP) != 0)
348 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA,
349 A_ONCHIP_FIFO_MEM_CORE_EOP);
350 bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, word);
354 buf = (buf << 16) | *(uint16_t *)addr;
361 buf = (buf << 8) | *(uint8_t *)addr;
367 if (got_bits >= 32) {
369 word = (uint32_t)((buf >> got_bits) & 0xffffffff);
371 fifo_fill_level_wait(sc);
372 if (len == 0 && got_bits == 0 &&
373 (desc->control & CONTROL_GEN_EOP) != 0)
374 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA,
375 A_ONCHIP_FIFO_MEM_CORE_EOP);
376 bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, word);
380 missing = 32 - got_bits;
383 fifo_fill_level_wait(sc);
384 reg = A_ONCHIP_FIFO_MEM_CORE_EOP |
385 ((4 - got_bits) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT);
386 softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA, reg);
387 word = (uint32_t)((buf << missing) & 0xffffffff);
388 bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, word);
395 softdma_process_rx(struct softdma_channel *chan, struct softdma_desc *desc)
397 uint32_t src_offs, dst_offs;
398 struct softdma_softc *sc;
410 src_offs = dst_offs = 0;
413 fill_level = softdma_fill_level(sc);
414 if (fill_level == 0) {
415 /* Nothing to receive. */
424 data = bus_read_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA);
425 meta = softdma_mem_read(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA);
427 if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) {
432 if ((meta & A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK) != 0) {
437 if (meta & A_ONCHIP_FIFO_MEM_CORE_SOP) {
441 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) {
442 empty = (meta & A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >>
443 A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT;
452 *(uint32_t *)(desc->dst_addr + dst_offs) = data;
454 } else if (empty == 1) {
455 *(uint16_t *)(desc->dst_addr + dst_offs) =
456 ((data >> 16) & 0xffff);
459 *(uint8_t *)(desc->dst_addr + dst_offs) =
460 ((data >> 8) & 0xff);
463 panic("empty %d\n", empty);
466 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP)
469 fill_level = softdma_fill_level(sc);
471 while (fill_level == 0 && timeout--)
472 fill_level = softdma_fill_level(sc);
474 /* No EOP received. Broken packet. */
488 softdma_process_descriptors(struct softdma_channel *chan,
489 xdma_transfer_status_t *status)
491 struct xdma_channel *xchan;
492 struct softdma_desc *desc;
493 struct softdma_softc *sc;
494 xdma_transfer_status_t st;
501 desc = &chan->descs[chan->idx_tail];
503 while (desc != NULL) {
505 if ((desc->control & CONTROL_OWN) == 0) {
509 if (desc->direction == XDMA_MEM_TO_DEV) {
510 ret = softdma_process_tx(chan, desc);
512 ret = softdma_process_rx(chan, desc);
514 /* No new data available. */
519 /* Descriptor processed. */
524 st.transferred = ret;
530 xchan_seg_done(xchan, &st);
531 atomic_subtract_int(&chan->descs_used_count, 1);
534 status->transferred += ret;
540 chan->idx_tail = softdma_next_desc(chan, chan->idx_tail);
542 /* Process next descriptor, if any. */
550 softdma_worker(void *arg)
552 xdma_transfer_status_t status;
553 struct softdma_channel *chan;
554 struct softdma_softc *sc;
561 mtx_lock(&chan->mtx);
564 mtx_sleep(chan, &chan->mtx, 0, "softdma_wait", hz / 2);
565 } while (chan->run == 0);
568 status.transferred = 0;
570 softdma_process_descriptors(chan, &status);
572 /* Finish operation */
574 xdma_callback(chan->xchan, &status);
576 mtx_unlock(&chan->mtx);
582 softdma_proc_create(struct softdma_channel *chan)
584 struct softdma_softc *sc;
588 if (chan->p != NULL) {
589 /* Already created */
593 mtx_init(&chan->mtx, "SoftDMA", NULL, MTX_DEF);
595 if (kproc_create(softdma_worker, (void *)chan, &chan->p, 0, 0,
596 "softdma_worker") != 0) {
597 device_printf(sc->dev,
598 "%s: Failed to create worker thread.\n", __func__);
606 softdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
608 struct softdma_channel *chan;
609 struct softdma_softc *sc;
612 sc = device_get_softc(dev);
614 for (i = 0; i < SOFTDMA_NCHANNELS; i++) {
615 chan = &sc->channels[i];
616 if (chan->used == 0) {
618 xchan->chan = (void *)chan;
619 xchan->caps |= XCHAN_CAP_NOBUFS;
620 xchan->caps |= XCHAN_CAP_NOSEG;
624 chan->descs_used_count = 0;
625 chan->descs_num = 1024;
628 if (softdma_proc_create(chan) != 0) {
642 softdma_channel_free(device_t dev, struct xdma_channel *xchan)
644 struct softdma_channel *chan;
645 struct softdma_softc *sc;
647 sc = device_get_softc(dev);
649 chan = (struct softdma_channel *)xchan->chan;
651 if (chan->descs != NULL) {
652 free(chan->descs, M_DEVBUF);
661 softdma_desc_alloc(struct xdma_channel *xchan)
663 struct softdma_channel *chan;
666 chan = (struct softdma_channel *)xchan->chan;
668 nsegments = chan->descs_num;
670 chan->descs = malloc(nsegments * sizeof(struct softdma_desc),
671 M_DEVBUF, (M_WAITOK | M_ZERO));
677 softdma_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
679 struct softdma_channel *chan;
680 struct softdma_desc *desc;
681 struct softdma_softc *sc;
685 sc = device_get_softc(dev);
687 chan = (struct softdma_channel *)xchan->chan;
689 ret = softdma_desc_alloc(xchan);
691 device_printf(sc->dev,
692 "%s: Can't allocate descriptors.\n", __func__);
696 for (i = 0; i < chan->descs_num; i++) {
697 desc = &chan->descs[i];
699 if (i == (chan->descs_num - 1)) {
700 desc->next = &chan->descs[0];
702 desc->next = &chan->descs[i+1];
710 softdma_channel_capacity(device_t dev, xdma_channel_t *xchan,
713 struct softdma_channel *chan;
716 chan = (struct softdma_channel *)xchan->chan;
718 /* At least one descriptor must be left empty. */
719 c = (chan->descs_num - chan->descs_used_count - 1);
727 softdma_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
728 struct xdma_sglist *sg, uint32_t sg_n)
730 struct softdma_channel *chan;
731 struct softdma_desc *desc;
732 struct softdma_softc *sc;
739 sc = device_get_softc(dev);
741 chan = (struct softdma_channel *)xchan->chan;
745 for (i = 0; i < sg_n; i++) {
746 len = (uint32_t)sg[i].len;
748 desc = &chan->descs[chan->idx_head];
749 desc->src_addr = sg[i].src_addr;
750 desc->dst_addr = sg[i].dst_addr;
751 if (sg[i].direction == XDMA_MEM_TO_DEV) {
758 desc->direction = sg[i].direction;
759 saved_dir = sg[i].direction;
761 desc->transfered = 0;
766 if (sg[i].first == 1)
767 desc->control |= CONTROL_GEN_SOP;
769 desc->control |= CONTROL_GEN_EOP;
771 tmp = chan->idx_head;
772 chan->idx_head = softdma_next_desc(chan, chan->idx_head);
773 atomic_add_int(&chan->descs_used_count, 1);
774 desc->control |= CONTROL_OWN;
781 if (saved_dir == XDMA_MEM_TO_DEV) {
785 softdma_memc_write(sc,
786 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE,
793 softdma_channel_request(device_t dev, struct xdma_channel *xchan,
794 struct xdma_request *req)
796 struct softdma_channel *chan;
797 struct softdma_desc *desc;
798 struct softdma_softc *sc;
801 sc = device_get_softc(dev);
803 chan = (struct softdma_channel *)xchan->chan;
805 ret = softdma_desc_alloc(xchan);
807 device_printf(sc->dev,
808 "%s: Can't allocate descriptors.\n", __func__);
812 desc = &chan->descs[0];
814 desc->src_addr = req->src_addr;
815 desc->dst_addr = req->dst_addr;
816 desc->len = req->block_len;
825 softdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
827 struct softdma_channel *chan;
828 struct softdma_softc *sc;
830 sc = device_get_softc(dev);
832 chan = (struct softdma_channel *)xchan->chan;
836 case XDMA_CMD_TERMINATE:
838 /* TODO: implement me */
847 softdma_ofw_md_data(device_t dev, pcell_t *cells,
848 int ncells, void **ptr)
855 static device_method_t softdma_methods[] = {
856 /* Device interface */
857 DEVMETHOD(device_probe, softdma_probe),
858 DEVMETHOD(device_attach, softdma_attach),
859 DEVMETHOD(device_detach, softdma_detach),
862 DEVMETHOD(xdma_channel_alloc, softdma_channel_alloc),
863 DEVMETHOD(xdma_channel_free, softdma_channel_free),
864 DEVMETHOD(xdma_channel_request, softdma_channel_request),
865 DEVMETHOD(xdma_channel_control, softdma_channel_control),
867 /* xDMA SG Interface */
868 DEVMETHOD(xdma_channel_prep_sg, softdma_channel_prep_sg),
869 DEVMETHOD(xdma_channel_submit_sg, softdma_channel_submit_sg),
870 DEVMETHOD(xdma_channel_capacity, softdma_channel_capacity),
873 DEVMETHOD(xdma_ofw_md_data, softdma_ofw_md_data),
879 static driver_t softdma_driver = {
882 sizeof(struct softdma_softc),
885 static devclass_t softdma_devclass;
887 EARLY_DRIVER_MODULE(softdma, simplebus, softdma_driver, softdma_devclass, 0, 0,
888 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);