2 *********************************************************************
4 * BY : C.L. Huang (ching@tekram.com.tw)
5 * Erich Chen (erich@tekram.com.tw)
6 * Description: Device Driver for the amd53c974 PCI Bus Master
7 * SCSI Host adapter found on cards such as
8 * the Tekram DC-390(T).
9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *********************************************************************
39 #define AMD_TRANS_CUR 0x01 /* Modify current neogtiation status */
40 #define AMD_TRANS_ACTIVE 0x03 /* Assume this is the active target */
41 #define AMD_TRANS_GOAL 0x04 /* Modify negotiation goal */
42 #define AMD_TRANS_USER 0x08 /* Modify user negotiation settings */
45 * Per target transfer parameters.
47 struct amd_transinfo {
52 struct amd_target_info {
54 * Records the currently active and user/default settings for
55 * tagged queueing and disconnection for each target.
58 #define AMD_CUR_DISCENB 0x01
59 #define AMD_CUR_TAGENB 0x02
60 #define AMD_USR_DISCENB 0x04
61 #define AMD_USR_TAGENB 0x08
65 u_int8_t sync_period_reg;
66 u_int8_t sync_offset_reg;
69 * Currently active transfer settings.
71 struct amd_transinfo current;
73 * Transfer settings we wish to achieve
74 * through negotiation.
76 struct amd_transinfo goal;
78 * User defined or default transfer settings.
80 struct amd_transinfo user;
84 * Scatter/Gather Segment entry.
92 * Chipset feature limits
95 #define AMD_MAX_SYNC_OFFSET 15
96 #define AMD_TARGET_MAX 7
98 #define AMD_NSEG (btoc(MAXPHYS) + 1)
99 #define AMD_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */
100 #define MAX_DEVICES 10
101 #define MAX_TAGS_CMD_QUEUE 256
102 #define MAX_CMD_PER_LUN 6
103 #define MAX_SRB_CNT 256
104 #define MAX_START_JOB 256
107 * BIT position to integer mapping.
109 #define BIT(N) (0x01 << N)
112 * EEPROM storage offsets and data structures.
114 typedef struct _EEprom {
121 #define EE_ADAPT_SCSI_ID 64
124 #define EE_TAG_CMD_NUM 67
125 #define EE_DATA_SIZE 128
126 #define EE_CHECKSUM 0x1234
129 * EE_MODE1 bits definition
131 #define PARITY_CHK BIT(0)
132 #define SYNC_NEGO BIT(1)
133 #define EN_DISCONNECT BIT(2)
134 #define SEND_START BIT(3)
135 #define TAG_QUEUING BIT(4)
138 * EE_MODE2 bits definition
140 #define MORE2_DRV BIT(0)
141 #define GREATER_1G BIT(1)
142 #define RST_SCSI_BUS BIT(2)
143 #define ACTIVE_NEGATION BIT(3)
144 #define NO_SEEK BIT(4)
145 #define LUN_CHECK BIT(5)
149 #define EEPROM_READ 0x80
151 #define AMD_TAG_WILDCARD ((u_int)(~0))
157 TAILQ_ENTRY(struct amd_srb) links;
158 u_int8_t CmdBlock[12];
161 struct amd_sg *pSGlist;
163 u_int32_t TotalXferredLen;
164 u_int32_t SGPhysAddr; /* a segment starting address */
165 u_int32_t SGToBeXferLen; /* to be xfer length */
166 u_int32_t Segment0[2];
167 u_int32_t Segment1[2];
169 struct amd_sg SGsegment[AMD_NSEG];
170 struct amd_sg Segmentx;/* a one entry of S/G list table */
174 u_int8_t AdaptStatus;
175 u_int8_t TargetStatus;
181 u_int8_t IORBFlag; /* ;81h-Reset, 2-retry */
185 /* ; b0-AutoReqSense,b6-Read,b7-write */
186 /* ; b4-settimeout,b5-Residual valid */
190 TAILQ_HEAD(srb_queue, struct amd_srb);
193 * Per-adapter, software configuration.
198 bus_space_handle_t bsh;
199 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
205 struct amd_srb *active_srb;
206 struct amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
207 struct amd_target_info tinfo[AMD_TARGET_MAX+1];
208 u_int16_t disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
210 struct srb_queue free_srbs;
211 struct srb_queue waiting_srbs;
212 struct srb_queue running_srbs;
214 struct amd_srb *pTmpSRB;
221 /* Hooks into the CAM XPT */
222 struct cam_sim *psim;
223 struct cam_path *ppath;
225 u_int8_t msgin_buf[6];
226 u_int8_t msgout_buf[6];
232 u_int8_t AdaptSCSIID; /* ; Adapter SCSI Target ID */
233 u_int8_t AdaptSCSILUN; /* ; Adapter SCSI LUN */
241 u_int8_t InitDCB_flag[8][8]; /* flag of initDCB for device */
242 struct amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */
243 struct amd_srb TmpSRB;
244 /* Setup data stored in an 93c46 serial eeprom */
245 u_int8_t eepromBuf[EE_DATA_SIZE];
249 * ----SRB State machine definition
252 #define SRB_READY BIT(1)
253 #define SRB_MSGOUT BIT(2) /* ;arbitration+msg_out 1st byte */
254 #define SRB_MSGIN BIT(3)
255 #define SRB_MSGIN_MULTI BIT(4)
256 #define SRB_COMMAND BIT(5)
257 #define SRB_START BIT(6) /* ;arbitration+msg_out+command_out */
258 #define SRB_DISCONNECT BIT(7)
259 #define SRB_DATA_XFER BIT(8)
260 #define SRB_XFERPAD BIT(9)
261 #define SRB_STATUS BIT(10)
262 #define SRB_COMPLETED BIT(11)
263 #define SRB_ABORT_SENT BIT(12)
264 #define DO_SYNC_NEGO BIT(13)
265 #define SRB_UNEXPECT_RESEL BIT(14)
270 #define RESET_DEV BIT(0)
271 #define RESET_DETECT BIT(1)
272 #define RESET_DONE BIT(2)
277 #define ABORT_DEV_ BIT(0)
282 #define SRB_OK BIT(0)
283 #define ABORTION BIT(1)
284 #define OVER_RUN BIT(2)
285 #define UNDER_RUN BIT(3)
286 #define PARITY_ERROR BIT(4)
287 #define SRB_ERROR BIT(5)
292 #define DATAOUT BIT(7)
293 #define DATAIN BIT(6)
294 #define RESIDUAL_VALID BIT(5)
295 #define ENABLE_TIMER BIT(4)
296 #define RESET_DEV0 BIT(2)
297 #define ABORT_DEV BIT(1)
298 #define AUTO_REQSENSE BIT(0)
303 #define H_STATUS_GOOD 0
304 #define H_SEL_TIMEOUT 0x11
305 #define H_OVER_UNDER_RUN 0x12
306 #define H_UNEXP_BUS_FREE 0x13
307 #define H_TARGET_PHASE_F 0x14
308 #define H_INVALID_CCB_OP 0x16
309 #define H_LINK_CCB_BAD 0x17
310 #define H_BAD_TARGET_DIR 0x18
311 #define H_DUPLICATE_CCB 0x19
312 #define H_BAD_CCB_OR_SG 0x1A
313 #define H_ABORT 0x0FF
316 * AMD specific "status" codes returned in the SCSI status byte.
318 #define AMD_SCSI_STAT_UNEXP_BUS_F 0xFD /* ; Unexpect Bus Free */
319 #define AMD_SCSI_STAT_BUS_RST_DETECT 0xFE /* ; Scsi Bus Reset detected */
320 #define AMD_SCSI_STAT_SEL_TIMEOUT 0xFF /* ; Selection Time out */
325 #define SYNC_DISABLE 0
326 #define SYNC_ENABLE BIT(0)
327 #define SYNC_NEGO_DONE BIT(1)
328 #define WIDE_ENABLE BIT(2)
329 #define WIDE_NEGO_DONE BIT(3)
330 #define EN_TAG_QUEUING BIT(4)
331 #define EN_ATN_STOP BIT(5)
333 #define SYNC_NEGO_OFFSET 15
338 #define SCSI_DATA_OUT 0
339 #define SCSI_DATA_IN 1
340 #define SCSI_COMMAND 2
341 #define SCSI_STATUS 3
343 #define SCSI_ARBITRATING 5
344 #define SCSI_MSG_OUT 6
345 #define SCSI_MSG_IN 7
346 #define SCSI_BUS_FREE 8
349 *==========================================================
350 * AMD 53C974 Registers bit Definition
351 *==========================================================
355 * ------SCSI Register-------
358 #define DMA_COMMAND BIT(7)
360 #define CLEAR_FIFO_CMD 1
361 #define RST_DEVICE_CMD 2
362 #define RST_SCSI_BUS_CMD 3
363 #define INFO_XFER_CMD 0x10
364 #define INITIATOR_CMD_CMPLTE 0x11
365 #define MSG_ACCEPTED_CMD 0x12
366 #define XFER_PAD_BYTE 0x18
367 #define SET_ATN_CMD 0x1A
368 #define RESET_ATN_CMD 0x1B
369 #define SEL_W_ATN 0x42
370 #define SEL_W_ATN_STOP 0x43
371 #define EN_SEL_RESEL 0x44
372 #define SEL_W_ATN2 0x46
373 #define DATA_XFER_CMD INFO_XFER_CMD
377 * ------SCSI Register-------
378 * SCSI Status Reg.(+10H)
380 #define INTERRUPT BIT(7)
381 #define ILLEGAL_OP_ERR BIT(6)
382 #define PARITY_ERR BIT(5)
383 #define COUNT_2_ZERO BIT(4)
384 #define GROUP_CODE_VALID BIT(3)
385 #define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0))
388 * ------SCSI Register-------
389 * Interrupt Status Reg.(+14H)
391 #define SCSI_RESET_ BIT(7)
392 #define INVALID_CMD BIT(6)
393 #define DISCONNECTED BIT(5)
394 #define SERVICE_REQUEST BIT(4)
395 #define SUCCESSFUL_OP BIT(3)
396 #define RESELECTED BIT(2)
397 #define SEL_ATTENTION BIT(1)
398 #define SELECTED BIT(0)
401 * ------SCSI Register-------
402 * Internal State Reg.(+18H)
404 #define SYNC_OFFSET_FLAG BIT(3)
405 #define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0))
408 * ------SCSI Register-------
409 * Clock Factor Reg.(+24H)
411 #define CLK_FREQ_40MHZ 0
412 #define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0))
413 #define CLK_FREQ_30MHZ (BIT(2)+BIT(1))
414 #define CLK_FREQ_25MHZ (BIT(2)+BIT(0))
415 #define CLK_FREQ_20MHZ BIT(2)
416 #define CLK_FREQ_15MHZ (BIT(1)+BIT(0))
417 #define CLK_FREQ_10MHZ BIT(1)
420 * ------SCSI Register-------
421 * Control Reg. 1(+20H)
423 #define EXTENDED_TIMING BIT(7)
424 #define DIS_INT_ON_SCSI_RST BIT(6)
425 #define PARITY_ERR_REPO BIT(4)
426 #define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0))
429 * ------SCSI Register-------
430 * Control Reg. 2(+2CH)
432 #define EN_FEATURE BIT(6)
433 #define EN_SCSI2_CMD BIT(3)
436 * ------SCSI Register-------
437 * Control Reg. 3(+30H)
439 #define ID_MSG_CHECK BIT(7)
440 #define EN_QTAG_MSG BIT(6)
441 #define EN_GRP2_CMD BIT(5)
442 #define FAST_SCSI BIT(4) /* ;10MB/SEC */
443 #define FAST_CLK BIT(3) /* ;25 - 40 MHZ */
446 * ------SCSI Register-------
447 * Control Reg. 4(+34H)
450 #define EATER_25NS BIT(7)
451 #define EATER_35NS BIT(6)
452 #define EATER_0NS (BIT(7)+BIT(6))
453 #define NEGATE_REQACKDATA BIT(2)
454 #define NEGATE_REQACK BIT(3)
457 *========================================
459 *========================================
463 * -------DMA Register--------
464 * DMA Command Reg.(+40H)
466 #define READ_DIRECTION BIT(7)
467 #define WRITE_DIRECTION 0
468 #define EN_DMA_INT BIT(6)
469 #define MAP_TO_MDL BIT(5)
470 #define DMA_DIAGNOSTIC BIT(4)
471 #define DMA_IDLE_CMD 0
472 #define DMA_BLAST_CMD BIT(0)
473 #define DMA_ABORT_CMD BIT(1)
474 #define DMA_START_CMD (BIT(1)|BIT(0))
477 * -------DMA Register--------
478 * DMA Status Reg.(+54H)
480 #define PCI_MS_ABORT BIT(6)
481 #define BLAST_COMPLETE BIT(5)
482 #define SCSI_INTERRUPT BIT(4)
483 #define DMA_XFER_DONE BIT(3)
484 #define DMA_XFER_ABORT BIT(2)
485 #define DMA_XFER_ERROR BIT(1)
486 #define POWER_DOWN BIT(0)
489 * -------DMA Register--------
490 * DMA SCSI Bus and Ctrl.(+70H)
491 * EN_INT_ON_PCI_ABORT
495 *==========================================================
496 * SCSI Chip register address offset
497 *==========================================================
499 #define CTCREG_LOW 0x00 /* (R) current transfer count register low */
500 #define STCREG_LOW 0x00 /* (W) start transfer count register low */
502 #define CTCREG_MID 0x04 /* (R) current transfer count register
504 #define STCREG_MID 0x04 /* (W) start transfer count register middle */
506 #define SCSIFIFOREG 0x08 /* (R/W) SCSI FIFO register */
508 #define SCSICMDREG 0x0C /* (R/W) SCSI command register */
510 #define SCSISTATREG 0x10 /* (R) SCSI status register */
511 #define SCSIDESTIDREG 0x10 /* (W) SCSI destination ID register */
513 #define INTSTATREG 0x14 /* (R) interrupt status register */
514 #define SCSITIMEOUTREG 0x14 /* (W) SCSI timeout register */
517 #define INTERNSTATREG 0x18 /* (R) internal state register */
518 #define SYNCPERIOREG 0x18 /* (W) synchronous transfer period register */
520 #define CURRENTFIFOREG 0x1C /* (R) current FIFO/internal state register */
521 #define SYNCOFFREG 0x1C/* (W) synchronous transfer period register */
523 #define CNTLREG1 0x20 /* (R/W) control register 1 */
524 #define CLKFACTREG 0x24 /* (W) clock factor register */
525 #define CNTLREG2 0x2C /* (R/W) control register 2 */
526 #define CNTLREG3 0x30 /* (R/W) control register 3 */
527 #define CNTLREG4 0x34 /* (R/W) control register 4 */
529 #define CURTXTCNTREG 0x38 /* (R) current transfer count register
530 * high/part-unique ID code */
531 #define STCREG_HIGH 0x38 /* (W) Start current transfer count register
535 *********************************************************
539 *********************************************************
541 #define DMA_Cmd 0x40 /* (R/W) command register */
542 #define DMA_XferCnt 0x44 /* (R/W) starting transfer count */
543 #define DMA_XferAddr 0x48 /* (R/W) starting Physical address */
544 #define DMA_Wk_ByteCntr 0x4C /* ( R ) working byte counter */
545 #define DMA_Wk_AddrCntr 0x50 /* ( R ) working address counter */
546 #define DMA_Status 0x54 /* ( R ) status register */
547 #define DMA_MDL_Addr 0x58 /* (R/W) starting memory descriptor list (MDL)
549 #define DMA_Wk_MDL_Cntr 0x5C /* ( R ) working MDL counter */
550 #define DMA_ScsiBusCtrl 0x70 /* (bits R/W) SCSI BUS and control */
552 /* ******************************************************* */
553 #define am_target SCSISTATREG
554 #define am_timeout INTSTATREG
555 #define am_seq_step SYNCPERIOREG
556 #define am_fifo_count SYNCOFFREG
559 #define amd_read8(amd, port) \
560 bus_space_read_1((amd)->tag, (amd)->bsh, port)
562 #define amd_read16(amd, port) \
563 bus_space_read_2((amd)->tag, (amd)->bsh, port)
565 #define amd_read32(amd, port) \
566 bus_space_read_4((amd)->tag, (amd)->bsh, port)
568 #define amd_write8(amd, port, value) \
569 bus_space_write_1((amd)->tag, (amd)->bsh, port, value)
571 #define amd_write8_multi(amd, port, ptr, len) \
572 bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len)
574 #define amd_write16(amd, port, value) \
575 bus_space_write_2((amd)->tag, (amd)->bsh, port, value)
577 #define amd_write32(amd, port, value) \
578 bus_space_write_4((amd)->tag, (amd)->bsh, port, value)