2 * Copyright (c) 2000 Matthew C. Forman
4 * Based (heavily) on alpm.c which is:
6 * Copyright (c) 1998, 1999 Nicolas Souchu
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Power management function/SMBus function support for the AMD 756 chip.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
40 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/systm.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
53 #include <dev/smbus/smbconf.h>
56 #define AMDPM_DEBUG(x) if (amdpm_debug) (x)
59 static int amdpm_debug = 1;
61 static int amdpm_debug = 0;
64 #define AMDPM_VENDORID_AMD 0x1022
65 #define AMDPM_DEVICEID_AMD756PM 0x740b
66 #define AMDPM_DEVICEID_AMD766PM 0x7413
67 #define AMDPM_DEVICEID_AMD768PM 0x7443
68 #define AMDPM_DEVICEID_AMD8111PM 0x746B
70 #define AMDPM_VENDORID_HYGON 0x1d94
72 /* nVidia nForce chipset */
73 #define AMDPM_VENDORID_NVIDIA 0x10de
74 #define AMDPM_DEVICEID_NF_SMB 0x01b4
76 /* PCI Configuration space registers */
77 #define AMDPCI_PMBASE 0x58
78 #define NFPCI_PMBASE 0x14
80 #define AMDPCI_GEN_CONFIG_PM 0x41
81 #define AMDPCI_PMIOEN (1<<7)
83 #define AMDPCI_SCIINT_CONFIG_PM 0x42
84 #define AMDPCI_SCISEL_IRQ11 11
86 #define AMDPCI_REVID 0x08
90 * Base address programmed via AMDPCI_PMBASE.
93 #define AMDSMB_GLOBAL_STATUS (0x00)
94 #define AMDSMB_GS_TO_STS (1<<5)
95 #define AMDSMB_GS_HCYC_STS (1<<4)
96 #define AMDSMB_GS_HST_STS (1<<3)
97 #define AMDSMB_GS_PRERR_STS (1<<2)
98 #define AMDSMB_GS_COL_STS (1<<1)
99 #define AMDSMB_GS_ABRT_STS (1<<0)
100 #define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
102 #define AMDSMB_GLOBAL_ENABLE (0x02)
103 #define AMDSMB_GE_ABORT (1<<5)
104 #define AMDSMB_GE_HCYC_EN (1<<4)
105 #define AMDSMB_GE_HOST_STC (1<<3)
106 #define AMDSMB_GE_CYC_QUICK 0
107 #define AMDSMB_GE_CYC_BYTE 1
108 #define AMDSMB_GE_CYC_BDATA 2
109 #define AMDSMB_GE_CYC_WDATA 3
110 #define AMDSMB_GE_CYC_PROCCALL 4
111 #define AMDSMB_GE_CYC_BLOCK 5
113 #define LSB 0x1 /* XXX: Better name: Read/Write? */
115 #define AMDSMB_HSTADDR (0x04)
116 #define AMDSMB_HSTDATA (0x06)
117 #define AMDSMB_HSTCMD (0x08)
118 #define AMDSMB_HSTDFIFO (0x09)
119 #define AMDSMB_HSLVDATA (0x0A)
120 #define AMDSMB_HSLVDA (0x0C)
121 #define AMDSMB_HSLVDDR (0x0E)
122 #define AMDSMB_SNPADDR (0x0F)
127 struct resource *res;
132 #define AMDPM_LOCK(amdpm) mtx_lock(&(amdpm)->lock)
133 #define AMDPM_UNLOCK(amdpm) mtx_unlock(&(amdpm)->lock)
134 #define AMDPM_LOCK_ASSERT(amdpm) mtx_assert(&(amdpm)->lock, MA_OWNED)
136 #define AMDPM_SMBINB(amdpm,register) \
137 (bus_read_1(amdpm->res, register))
138 #define AMDPM_SMBOUTB(amdpm,register,value) \
139 (bus_write_1(amdpm->res, register, value))
140 #define AMDPM_SMBINW(amdpm,register) \
141 (bus_read_2(amdpm->res, register))
142 #define AMDPM_SMBOUTW(amdpm,register,value) \
143 (bus_write_2(amdpm->res, register, value))
145 static int amdpm_detach(device_t dev);
148 amdpm_probe(device_t dev)
154 vid = pci_get_vendor(dev);
155 did = pci_get_device(dev);
156 if ((vid == AMDPM_VENDORID_AMD) &&
157 ((did == AMDPM_DEVICEID_AMD756PM) ||
158 (did == AMDPM_DEVICEID_AMD766PM) ||
159 (did == AMDPM_DEVICEID_AMD768PM) ||
160 (did == AMDPM_DEVICEID_AMD8111PM))) {
161 device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
164 * We have to do this, since the BIOS won't give us the
165 * resource info (not mine, anyway).
167 base = pci_read_config(dev, AMDPCI_PMBASE, 4);
169 bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
171 return (BUS_PROBE_DEFAULT);
174 if ((vid == AMDPM_VENDORID_NVIDIA) &&
175 (did == AMDPM_DEVICEID_NF_SMB)) {
176 device_set_desc(dev, "nForce SMBus Controller");
179 * We have to do this, since the BIOS won't give us the
180 * resource info (not mine, anyway).
182 base = pci_read_config(dev, NFPCI_PMBASE, 4);
184 bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
187 return (BUS_PROBE_DEFAULT);
194 amdpm_attach(device_t dev)
196 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
199 /* Enable I/O block access */
200 val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
201 pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
203 /* Allocate I/O space */
204 if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD ||
205 pci_get_vendor(dev) == AMDPM_VENDORID_HYGON)
206 amdpm_sc->rid = AMDPCI_PMBASE;
208 amdpm_sc->rid = NFPCI_PMBASE;
209 amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
210 &amdpm_sc->rid, RF_ACTIVE);
212 if (amdpm_sc->res == NULL) {
213 device_printf(dev, "could not map i/o space\n");
217 mtx_init(&amdpm_sc->lock, device_get_nameunit(dev), "amdpm", MTX_DEF);
219 /* Allocate a new smbus device */
220 amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
221 if (!amdpm_sc->smbus) {
226 bus_generic_attach(dev);
232 amdpm_detach(device_t dev)
234 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
236 if (amdpm_sc->smbus) {
237 device_delete_child(dev, amdpm_sc->smbus);
238 amdpm_sc->smbus = NULL;
241 mtx_destroy(&amdpm_sc->lock);
243 bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
250 amdpm_callback(device_t dev, int index, void *data)
255 case SMB_REQUEST_BUS:
256 case SMB_RELEASE_BUS:
266 amdpm_clear(struct amdpm_softc *sc)
269 AMDPM_LOCK_ASSERT(sc);
270 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
278 amdpm_abort(struct amdpm_softc *sc)
282 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
283 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
290 amdpm_idle(struct amdpm_softc *sc)
294 AMDPM_LOCK_ASSERT(sc);
295 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
297 AMDPM_DEBUG(printf("amdpm: busy? STS=0x%x\n", sts));
299 return (~(sts & AMDSMB_GS_HST_STS));
303 * Poll the SMBus controller
306 amdpm_wait(struct amdpm_softc *sc)
312 AMDPM_LOCK_ASSERT(sc);
313 /* Wait for command to complete (SMBus controller is idle) */
316 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
317 if (!(sts & AMDSMB_GS_HST_STS))
321 AMDPM_DEBUG(printf("amdpm: STS=0x%x (count=%d)\n", sts, count));
326 error |= SMB_ETIMEOUT;
328 if (sts & AMDSMB_GS_ABRT_STS)
331 if (sts & AMDSMB_GS_COL_STS)
334 if (sts & AMDSMB_GS_PRERR_STS)
335 error |= SMB_EBUSERR;
337 if (error != SMB_ENOERR)
344 amdpm_quick(device_t dev, u_char slave, int how)
346 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
352 if (!amdpm_idle(sc)) {
359 AMDPM_DEBUG(printf("amdpm: QWRITE to 0x%x", slave));
360 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
363 AMDPM_DEBUG(printf("amdpm: QREAD to 0x%x", slave));
364 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
367 panic("%s: unknown QUICK command (%x)!", __func__, how);
369 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
370 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
372 error = amdpm_wait(sc);
374 AMDPM_DEBUG(printf(", error=0x%x\n", error));
381 amdpm_sendb(device_t dev, u_char slave, char byte)
383 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
389 if (!amdpm_idle(sc)) {
394 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
395 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
396 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
397 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
399 error = amdpm_wait(sc);
401 AMDPM_DEBUG(printf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
408 amdpm_recvb(device_t dev, u_char slave, char *byte)
410 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
416 if (!amdpm_idle(sc)) {
421 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
422 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
423 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
425 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
426 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
428 AMDPM_DEBUG(printf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
435 amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
437 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
443 if (!amdpm_idle(sc)) {
448 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
449 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
450 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
451 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
452 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
454 error = amdpm_wait(sc);
456 AMDPM_DEBUG(printf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
463 amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
465 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
471 if (!amdpm_idle(sc)) {
476 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
477 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
478 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
479 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
481 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
482 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
484 AMDPM_DEBUG(printf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
491 amdpm_writew(device_t dev, u_char slave, char cmd, short word)
493 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
499 if (!amdpm_idle(sc)) {
504 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
505 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
506 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
507 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
508 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
510 error = amdpm_wait(sc);
512 AMDPM_DEBUG(printf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
519 amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
521 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
527 if (!amdpm_idle(sc)) {
532 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
533 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
534 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
535 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
537 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
538 *word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
540 AMDPM_DEBUG(printf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
547 amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
549 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
554 if (count < 1 || count > 32)
559 if (!amdpm_idle(sc)) {
564 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
567 * Do we have to reset the internal 32-byte buffer?
568 * Can't see how to do this from the data sheet.
570 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, count);
572 /* Fill the 32-byte internal buffer */
573 for (i = 0; i < count; i++) {
574 AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[i]);
577 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
578 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
579 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
580 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
582 error = amdpm_wait(sc);
584 AMDPM_DEBUG(printf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
591 amdpm_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
593 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
598 if (*count < 1 || *count > 32)
603 if (!amdpm_idle(sc)) {
608 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
610 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
612 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
613 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
614 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
616 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
619 len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
621 /* Read the 32-byte internal buffer */
622 for (i = 0; i < len; i++) {
623 data = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
631 AMDPM_DEBUG(printf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, *count, cmd, error));
637 static devclass_t amdpm_devclass;
639 static device_method_t amdpm_methods[] = {
640 /* Device interface */
641 DEVMETHOD(device_probe, amdpm_probe),
642 DEVMETHOD(device_attach, amdpm_attach),
643 DEVMETHOD(device_detach, amdpm_detach),
645 /* SMBus interface */
646 DEVMETHOD(smbus_callback, amdpm_callback),
647 DEVMETHOD(smbus_quick, amdpm_quick),
648 DEVMETHOD(smbus_sendb, amdpm_sendb),
649 DEVMETHOD(smbus_recvb, amdpm_recvb),
650 DEVMETHOD(smbus_writeb, amdpm_writeb),
651 DEVMETHOD(smbus_readb, amdpm_readb),
652 DEVMETHOD(smbus_writew, amdpm_writew),
653 DEVMETHOD(smbus_readw, amdpm_readw),
654 DEVMETHOD(smbus_bwrite, amdpm_bwrite),
655 DEVMETHOD(smbus_bread, amdpm_bread),
660 static driver_t amdpm_driver = {
663 sizeof(struct amdpm_softc),
666 DRIVER_MODULE(amdpm, pci, amdpm_driver, amdpm_devclass, 0, 0);
667 DRIVER_MODULE(smbus, amdpm, smbus_driver, smbus_devclass, 0, 0);
669 MODULE_DEPEND(amdpm, pci, 1, 1, 1);
670 MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
671 MODULE_VERSION(amdpm, 1);