2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
32 * Please see the following specifications for the descriptions of the
33 * registers and flags:
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
46 * specifications, but the table hasn't been spotted in the wild yet.
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include <sys/param.h>
53 #include <sys/kernel.h>
54 #include <sys/module.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
58 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <sys/watchdog.h>
63 #include <dev/pci/pcivar.h>
64 #include <dev/amdsbwd/amd_chipset.h>
65 #include <isa/isavar.h>
68 * Registers in the Watchdog IO space.
69 * See SB7xx RRG 2.3.4, WDRT.
71 #define AMDSB_WD_CTRL 0x00
72 #define AMDSB_WD_RUN 0x01
73 #define AMDSB_WD_FIRED 0x02
74 #define AMDSB_WD_SHUTDOWN 0x04
75 #define AMDSB_WD_DISABLE 0x08
76 #define AMDSB_WD_RESERVED 0x70
77 #define AMDSB_WD_RELOAD 0x80
78 #define AMDSB_WD_COUNT 0x04
79 #define AMDSB_WD_COUNT_MASK 0xffff
80 #define AMDSB_WDIO_REG_WIDTH 4
82 #define amdsbwd_verbose_printf(dev, ...) \
85 device_printf(dev, __VA_ARGS__);\
88 struct amdsbwd_softc {
90 eventhandler_tag ev_tag;
91 struct resource *res_ctrl;
92 struct resource *res_count;
101 static void amdsbwd_identify(driver_t *driver, device_t parent);
102 static int amdsbwd_probe(device_t dev);
103 static int amdsbwd_attach(device_t dev);
104 static int amdsbwd_detach(device_t dev);
106 static device_method_t amdsbwd_methods[] = {
107 DEVMETHOD(device_identify, amdsbwd_identify),
108 DEVMETHOD(device_probe, amdsbwd_probe),
109 DEVMETHOD(device_attach, amdsbwd_attach),
110 DEVMETHOD(device_detach, amdsbwd_detach),
112 DEVMETHOD(device_shutdown, amdsbwd_detach),
117 static devclass_t amdsbwd_devclass;
118 static driver_t amdsbwd_driver = {
121 sizeof(struct amdsbwd_softc)
124 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
128 pmio_read(struct resource *res, uint8_t reg)
130 bus_write_1(res, 0, reg); /* Index */
131 return (bus_read_1(res, 1)); /* Data */
135 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
137 bus_write_1(res, 0, reg); /* Index */
138 bus_write_1(res, 1, val); /* Data */
142 wdctrl_read(struct amdsbwd_softc *sc)
144 return (bus_read_4(sc->res_ctrl, 0));
148 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
150 bus_write_4(sc->res_ctrl, 0, val);
153 static __unused uint32_t
154 wdcount_read(struct amdsbwd_softc *sc)
156 return (bus_read_4(sc->res_count, 0));
160 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
162 bus_write_4(sc->res_count, 0, val);
166 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
170 val = wdctrl_read(sc);
172 wdctrl_write(sc, val);
174 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
178 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
182 val = wdctrl_read(sc);
183 val &= ~AMDSB_WD_RUN;
184 wdctrl_write(sc, val);
186 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
190 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
194 val = wdctrl_read(sc);
195 val |= AMDSB_WD_RELOAD;
196 wdctrl_write(sc, val);
200 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
203 timeout &= AMDSB_WD_COUNT_MASK;
204 wdcount_write(sc, timeout);
205 sc->timeout = timeout;
206 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
210 amdsbwd_event(void *arg, unsigned int cmd, int *error)
212 struct amdsbwd_softc *sc = arg;
218 if (cmd >= WD_TO_1MS) {
219 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
220 timeout = timeout / sc->ms_per_tick;
222 /* For a too short timeout use 1 tick. */
225 /* For a too long timeout stop the timer. */
226 if (timeout > sc->max_ticks)
233 if (timeout != sc->timeout)
234 amdsbwd_tmr_set(sc, timeout);
236 amdsbwd_tmr_enable(sc);
237 amdsbwd_tmr_reload(sc);
241 amdsbwd_tmr_disable(sc);
246 amdsbwd_identify(driver_t *driver, device_t parent)
251 if (resource_disabled("amdsbwd", 0))
253 if (device_find_child(parent, "amdsbwd", -1) != NULL)
257 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
258 * that should be present at bus 0, device 20, function 0.
260 smb_dev = pci_find_bsf(0, 20, 0);
263 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
264 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
265 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID)
268 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
270 device_printf(parent, "add amdsbwd child failed\n");
275 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
280 /* Report cause of previous reset for user's convenience. */
281 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
283 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
284 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
286 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
287 if ((val & AMDSB_WD_RST_STS) != 0)
288 device_printf(dev, "Previous Reset was caused by Watchdog\n");
290 /* Find base address of memory mapped WDT registers. */
291 for (*addr = 0, i = 0; i < 4; i++) {
293 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
297 /* Set watchdog timer tick to 1s. */
298 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
299 val &= ~AMDSB_WDT_RES_MASK;
300 val |= AMDSB_WDT_RES_1S;
301 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
303 /* Enable watchdog device (in stopped state). */
304 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
305 val &= ~AMDSB_WDT_DISABLE;
306 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
309 * XXX TODO: Ensure that watchdog decode is enabled
310 * (register 0x41, bit 3).
312 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
316 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
321 /* Report cause of previous reset for user's convenience. */
322 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0);
324 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
325 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1);
327 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
328 if ((val & AMDSB8_WD_RST_STS) != 0)
329 device_printf(dev, "Previous Reset was caused by Watchdog\n");
331 /* Find base address of memory mapped WDT registers. */
332 for (*addr = 0, i = 0; i < 4; i++) {
334 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
338 /* Set watchdog timer tick to 1s. */
339 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
340 val &= ~AMDSB8_WDT_RES_MASK;
341 val |= AMDSB8_WDT_1HZ;
342 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
344 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
345 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
349 * Enable watchdog device (in stopped state)
350 * and decoding of its address.
352 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
353 val &= ~AMDSB8_WDT_DISABLE;
354 val |= AMDSB8_WDT_DEC_EN;
355 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
357 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
358 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
360 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
364 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
368 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
369 if ((val & AMDFCH41_MMIO_EN) != 0) {
370 /* Fixed offset for the watchdog within ACPI MMIO range. */
371 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
372 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
375 * Enable decoding of watchdog MMIO address.
377 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
378 val |= AMDFCH41_WDT_EN;
379 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
381 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
382 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
386 /* Special fixed MMIO range for the watchdog. */
387 *addr = AMDFCH41_WDT_FIXED_ADDR;
391 * Set watchdog timer tick to 1s and
392 * enable the watchdog device (in stopped state).
394 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
395 val &= ~AMDFCH41_WDT_RES_MASK;
396 val |= AMDFCH41_WDT_RES_1S;
397 val &= ~AMDFCH41_WDT_EN_MASK;
398 val |= AMDFCH41_WDT_ENABLE;
399 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
401 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
402 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
405 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer");
409 amdsbwd_probe(device_t dev)
411 struct resource *res;
419 /* Do not claim some ISA PnP device by accident. */
420 if (isa_get_logicalid(dev) != 0)
423 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
426 device_printf(dev, "bus_set_resource for IO failed\n");
430 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
431 RF_ACTIVE | RF_SHAREABLE);
433 device_printf(dev, "bus_alloc_resource for IO failed\n");
437 smb_dev = pci_find_bsf(0, 20, 0);
438 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
439 devid = pci_get_devid(smb_dev);
440 revid = pci_get_revid(smb_dev);
441 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
442 amdsbwd_probe_sb7xx(dev, res, &addr);
443 else if (devid == AMDSB_SMBUS_DEVID ||
444 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
445 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
446 amdsbwd_probe_sb8xx(dev, res, &addr);
448 amdsbwd_probe_fch41(dev, res, &addr);
450 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
451 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
453 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
454 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
455 AMDSB_WDIO_REG_WIDTH);
457 device_printf(dev, "bus_set_resource for control failed\n");
460 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
461 AMDSB_WDIO_REG_WIDTH);
463 device_printf(dev, "bus_set_resource for count failed\n");
471 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
474 sc->max_ticks = UINT16_MAX;
478 sc->ms_per_tick = 1000;
480 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
481 &sc->rid_ctrl, RF_ACTIVE);
482 if (sc->res_ctrl == NULL) {
483 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
486 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
487 &sc->rid_count, RF_ACTIVE);
488 if (sc->res_count == NULL) {
489 device_printf(dev, "bus_alloc_resource for count failed\n");
496 amdsbwd_attach(device_t dev)
498 struct amdsbwd_softc *sc;
501 sc = device_get_softc(dev);
504 rc = amdsbwd_attach_sb(dev, sc);
509 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
510 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
513 /* Setup initial state of Watchdog Control. */
514 wdctrl_write(sc, AMDSB_WD_FIRED);
516 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
517 device_printf(dev, "watchdog hardware is disabled\n");
521 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
522 EVENTHANDLER_PRI_ANY);
532 amdsbwd_detach(device_t dev)
534 struct amdsbwd_softc *sc;
536 sc = device_get_softc(dev);
537 if (sc->ev_tag != NULL)
538 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
541 amdsbwd_tmr_disable(sc);
543 if (sc->res_ctrl != NULL)
544 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
547 if (sc->res_count != NULL)
548 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,