2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
32 * Please see the following specifications for the descriptions of the
33 * registers and flags:
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
46 * specifications, but the table hasn't been spotted in the wild yet.
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include "opt_amdsbwd.h"
54 #include <sys/param.h>
55 #include <sys/eventhandler.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/systm.h>
59 #include <sys/sysctl.h>
61 #include <machine/bus.h>
63 #include <machine/cputypes.h>
64 #include <machine/md_var.h>
65 #include <machine/resource.h>
66 #include <sys/watchdog.h>
68 #include <dev/pci/pcivar.h>
69 #include <dev/amdsbwd/amd_chipset.h>
70 #include <isa/isavar.h>
73 * Registers in the Watchdog IO space.
74 * See SB7xx RRG 2.3.4, WDRT.
76 #define AMDSB_WD_CTRL 0x00
77 #define AMDSB_WD_RUN 0x01
78 #define AMDSB_WD_FIRED 0x02
79 #define AMDSB_WD_SHUTDOWN 0x04
80 #define AMDSB_WD_DISABLE 0x08
81 #define AMDSB_WD_RESERVED 0x70
82 #define AMDSB_WD_RELOAD 0x80
83 #define AMDSB_WD_COUNT 0x04
84 #define AMDSB_WD_COUNT_MASK 0xffff
85 #define AMDSB_WDIO_REG_WIDTH 4
87 #define amdsbwd_verbose_printf(dev, ...) \
90 device_printf(dev, __VA_ARGS__);\
93 struct amdsbwd_softc {
95 eventhandler_tag ev_tag;
96 struct resource *res_ctrl;
97 struct resource *res_count;
103 unsigned int timeout;
106 static void amdsbwd_identify(driver_t *driver, device_t parent);
107 static int amdsbwd_probe(device_t dev);
108 static int amdsbwd_attach(device_t dev);
109 static int amdsbwd_detach(device_t dev);
110 static int amdsbwd_suspend(device_t dev);
111 static int amdsbwd_resume(device_t dev);
113 static device_method_t amdsbwd_methods[] = {
114 DEVMETHOD(device_identify, amdsbwd_identify),
115 DEVMETHOD(device_probe, amdsbwd_probe),
116 DEVMETHOD(device_attach, amdsbwd_attach),
117 DEVMETHOD(device_detach, amdsbwd_detach),
118 DEVMETHOD(device_suspend, amdsbwd_suspend),
119 DEVMETHOD(device_resume, amdsbwd_resume),
121 DEVMETHOD(device_shutdown, amdsbwd_detach),
126 static devclass_t amdsbwd_devclass;
127 static driver_t amdsbwd_driver = {
130 sizeof(struct amdsbwd_softc)
133 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
137 pmio_read(struct resource *res, uint8_t reg)
139 bus_write_1(res, 0, reg); /* Index */
140 return (bus_read_1(res, 1)); /* Data */
144 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
146 bus_write_1(res, 0, reg); /* Index */
147 bus_write_1(res, 1, val); /* Data */
151 wdctrl_read(struct amdsbwd_softc *sc)
153 return (bus_read_4(sc->res_ctrl, 0));
157 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
159 bus_write_4(sc->res_ctrl, 0, val);
162 static __unused uint32_t
163 wdcount_read(struct amdsbwd_softc *sc)
165 return (bus_read_4(sc->res_count, 0));
169 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
171 bus_write_4(sc->res_count, 0, val);
175 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
179 val = wdctrl_read(sc);
181 wdctrl_write(sc, val);
183 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
187 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
191 val = wdctrl_read(sc);
192 val &= ~AMDSB_WD_RUN;
193 wdctrl_write(sc, val);
195 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
199 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
203 val = wdctrl_read(sc);
204 val |= AMDSB_WD_RELOAD;
205 wdctrl_write(sc, val);
209 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
212 timeout &= AMDSB_WD_COUNT_MASK;
213 wdcount_write(sc, timeout);
214 sc->timeout = timeout;
215 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
219 amdsbwd_event(void *arg, unsigned int cmd, int *error)
221 struct amdsbwd_softc *sc = arg;
227 if (cmd >= WD_TO_1MS) {
228 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
229 timeout = timeout / sc->ms_per_tick;
231 /* For a too short timeout use 1 tick. */
234 /* For a too long timeout stop the timer. */
235 if (timeout > sc->max_ticks)
242 if (timeout != sc->timeout)
243 amdsbwd_tmr_set(sc, timeout);
245 amdsbwd_tmr_enable(sc);
246 amdsbwd_tmr_reload(sc);
250 amdsbwd_tmr_disable(sc);
255 amdsbwd_identify(driver_t *driver, device_t parent)
260 if (resource_disabled("amdsbwd", 0))
262 if (device_find_child(parent, "amdsbwd", -1) != NULL)
266 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
267 * that should be present at bus 0, device 20, function 0.
269 smb_dev = pci_find_bsf(0, 20, 0);
272 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
273 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
274 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID &&
275 pci_get_devid(smb_dev) != HYGONCZ_SMBUS_DEVID)
278 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
280 device_printf(parent, "add amdsbwd child failed\n");
285 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
290 /* Report cause of previous reset for user's convenience. */
291 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
293 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
294 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
296 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
297 if ((val & AMDSB_WD_RST_STS) != 0)
298 device_printf(dev, "Previous Reset was caused by Watchdog\n");
300 /* Find base address of memory mapped WDT registers. */
301 for (*addr = 0, i = 0; i < 4; i++) {
303 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
307 /* Set watchdog timer tick to 1s. */
308 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
309 val &= ~AMDSB_WDT_RES_MASK;
310 val |= AMDSB_WDT_RES_1S;
311 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
313 /* Enable watchdog device (in stopped state). */
314 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
315 val &= ~AMDSB_WDT_DISABLE;
316 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
319 * XXX TODO: Ensure that watchdog decode is enabled
320 * (register 0x41, bit 3).
322 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
326 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
331 /* Report cause of previous reset for user's convenience. */
333 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
334 if ((val & AMDSB8_RST_STS_DIS) != 0) {
335 val &= ~AMDSB8_RST_STS_DIS;
336 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
339 for (i = 3; i >= 0; i--) {
341 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
344 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
345 if ((val & AMDSB8_WD_RST_STS) != 0)
346 device_printf(dev, "Previous Reset was caused by Watchdog\n");
348 /* Find base address of memory mapped WDT registers. */
349 for (*addr = 0, i = 0; i < 4; i++) {
351 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
355 /* Set watchdog timer tick to 1s. */
356 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
357 val &= ~AMDSB8_WDT_RES_MASK;
358 val |= AMDSB8_WDT_1HZ;
359 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
361 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
362 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
366 * Enable watchdog device (in stopped state)
367 * and decoding of its address.
369 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
370 val &= ~AMDSB8_WDT_DISABLE;
371 val |= AMDSB8_WDT_DEC_EN;
372 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
374 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
375 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
377 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
381 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
386 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
387 if ((val & AMDFCH41_MMIO_EN) != 0) {
388 /* Fixed offset for the watchdog within ACPI MMIO range. */
389 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
390 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
393 * Enable decoding of watchdog MMIO address.
395 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
396 val |= AMDFCH41_WDT_EN;
397 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
399 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
400 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
404 /* Special fixed MMIO range for the watchdog. */
405 *addr = AMDFCH41_WDT_FIXED_ADDR;
409 * Set watchdog timer tick to 1s and
410 * enable the watchdog device (in stopped state).
412 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
413 val &= ~AMDFCH41_WDT_RES_MASK;
414 val |= AMDFCH41_WDT_RES_1S;
415 val &= ~AMDFCH41_WDT_EN_MASK;
416 val |= AMDFCH41_WDT_ENABLE;
417 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
419 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
420 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
423 snprintf(buf, sizeof(buf), "%s FCH Rev 41h+ Watchdog Timer",
424 cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD");
425 device_set_desc_copy(dev, buf);
429 amdsbwd_probe(device_t dev)
431 struct resource *res;
439 /* Do not claim some ISA PnP device by accident. */
440 if (isa_get_logicalid(dev) != 0)
443 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
446 device_printf(dev, "bus_set_resource for IO failed\n");
450 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
451 RF_ACTIVE | RF_SHAREABLE);
453 device_printf(dev, "bus_alloc_resource for IO failed\n");
457 smb_dev = pci_find_bsf(0, 20, 0);
458 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
459 devid = pci_get_devid(smb_dev);
460 revid = pci_get_revid(smb_dev);
461 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
462 amdsbwd_probe_sb7xx(dev, res, &addr);
463 else if (devid == AMDSB_SMBUS_DEVID ||
464 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
465 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
466 amdsbwd_probe_sb8xx(dev, res, &addr);
468 amdsbwd_probe_fch41(dev, res, &addr);
470 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
471 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
473 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
474 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
475 AMDSB_WDIO_REG_WIDTH);
477 device_printf(dev, "bus_set_resource for control failed\n");
480 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
481 AMDSB_WDIO_REG_WIDTH);
483 device_printf(dev, "bus_set_resource for count failed\n");
491 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
494 sc->max_ticks = UINT16_MAX;
498 sc->ms_per_tick = 1000;
500 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
501 &sc->rid_ctrl, RF_ACTIVE);
502 if (sc->res_ctrl == NULL) {
503 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
506 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
507 &sc->rid_count, RF_ACTIVE);
508 if (sc->res_count == NULL) {
509 device_printf(dev, "bus_alloc_resource for count failed\n");
516 amdsbwd_attach(device_t dev)
518 struct amdsbwd_softc *sc;
521 sc = device_get_softc(dev);
524 rc = amdsbwd_attach_sb(dev, sc);
529 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
530 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
533 /* Setup initial state of Watchdog Control. */
534 wdctrl_write(sc, AMDSB_WD_FIRED);
536 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
537 device_printf(dev, "watchdog hardware is disabled\n");
541 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
542 EVENTHANDLER_PRI_ANY);
552 amdsbwd_detach(device_t dev)
554 struct amdsbwd_softc *sc;
556 sc = device_get_softc(dev);
557 if (sc->ev_tag != NULL)
558 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
561 amdsbwd_tmr_disable(sc);
563 if (sc->res_ctrl != NULL)
564 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
567 if (sc->res_count != NULL)
568 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
575 amdsbwd_suspend(device_t dev)
577 struct amdsbwd_softc *sc;
580 sc = device_get_softc(dev);
581 val = wdctrl_read(sc);
582 val &= ~AMDSB_WD_RUN;
583 wdctrl_write(sc, val);
588 amdsbwd_resume(device_t dev)
590 struct amdsbwd_softc *sc;
592 sc = device_get_softc(dev);
593 wdctrl_write(sc, AMDSB_WD_FIRED);
595 amdsbwd_tmr_set(sc, sc->timeout);
596 amdsbwd_tmr_enable(sc);
597 amdsbwd_tmr_reload(sc);