2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
32 * Please see the following specifications for the descriptions of the
33 * registers and flags:
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
46 * specifications, but the table hasn't been spotted in the wild yet.
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include "opt_amdsbwd.h"
54 #include <sys/param.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/systm.h>
58 #include <sys/sysctl.h>
60 #include <machine/bus.h>
62 #include <machine/resource.h>
63 #include <sys/watchdog.h>
65 #include <dev/pci/pcivar.h>
66 #include <dev/amdsbwd/amd_chipset.h>
67 #include <isa/isavar.h>
70 * Registers in the Watchdog IO space.
71 * See SB7xx RRG 2.3.4, WDRT.
73 #define AMDSB_WD_CTRL 0x00
74 #define AMDSB_WD_RUN 0x01
75 #define AMDSB_WD_FIRED 0x02
76 #define AMDSB_WD_SHUTDOWN 0x04
77 #define AMDSB_WD_DISABLE 0x08
78 #define AMDSB_WD_RESERVED 0x70
79 #define AMDSB_WD_RELOAD 0x80
80 #define AMDSB_WD_COUNT 0x04
81 #define AMDSB_WD_COUNT_MASK 0xffff
82 #define AMDSB_WDIO_REG_WIDTH 4
84 #define amdsbwd_verbose_printf(dev, ...) \
87 device_printf(dev, __VA_ARGS__);\
90 struct amdsbwd_softc {
92 eventhandler_tag ev_tag;
93 struct resource *res_ctrl;
94 struct resource *res_count;
100 unsigned int timeout;
103 static void amdsbwd_identify(driver_t *driver, device_t parent);
104 static int amdsbwd_probe(device_t dev);
105 static int amdsbwd_attach(device_t dev);
106 static int amdsbwd_detach(device_t dev);
107 static int amdsbwd_suspend(device_t dev);
108 static int amdsbwd_resume(device_t dev);
110 static device_method_t amdsbwd_methods[] = {
111 DEVMETHOD(device_identify, amdsbwd_identify),
112 DEVMETHOD(device_probe, amdsbwd_probe),
113 DEVMETHOD(device_attach, amdsbwd_attach),
114 DEVMETHOD(device_detach, amdsbwd_detach),
115 DEVMETHOD(device_suspend, amdsbwd_suspend),
116 DEVMETHOD(device_resume, amdsbwd_resume),
118 DEVMETHOD(device_shutdown, amdsbwd_detach),
123 static devclass_t amdsbwd_devclass;
124 static driver_t amdsbwd_driver = {
127 sizeof(struct amdsbwd_softc)
130 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
134 pmio_read(struct resource *res, uint8_t reg)
136 bus_write_1(res, 0, reg); /* Index */
137 return (bus_read_1(res, 1)); /* Data */
141 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
143 bus_write_1(res, 0, reg); /* Index */
144 bus_write_1(res, 1, val); /* Data */
148 wdctrl_read(struct amdsbwd_softc *sc)
150 return (bus_read_4(sc->res_ctrl, 0));
154 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
156 bus_write_4(sc->res_ctrl, 0, val);
159 static __unused uint32_t
160 wdcount_read(struct amdsbwd_softc *sc)
162 return (bus_read_4(sc->res_count, 0));
166 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
168 bus_write_4(sc->res_count, 0, val);
172 amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
176 val = wdctrl_read(sc);
178 wdctrl_write(sc, val);
180 amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
184 amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
188 val = wdctrl_read(sc);
189 val &= ~AMDSB_WD_RUN;
190 wdctrl_write(sc, val);
192 amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
196 amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
200 val = wdctrl_read(sc);
201 val |= AMDSB_WD_RELOAD;
202 wdctrl_write(sc, val);
206 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
209 timeout &= AMDSB_WD_COUNT_MASK;
210 wdcount_write(sc, timeout);
211 sc->timeout = timeout;
212 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
216 amdsbwd_event(void *arg, unsigned int cmd, int *error)
218 struct amdsbwd_softc *sc = arg;
224 if (cmd >= WD_TO_1MS) {
225 timeout = (uint64_t)1 << (cmd - WD_TO_1MS);
226 timeout = timeout / sc->ms_per_tick;
228 /* For a too short timeout use 1 tick. */
231 /* For a too long timeout stop the timer. */
232 if (timeout > sc->max_ticks)
239 if (timeout != sc->timeout)
240 amdsbwd_tmr_set(sc, timeout);
242 amdsbwd_tmr_enable(sc);
243 amdsbwd_tmr_reload(sc);
247 amdsbwd_tmr_disable(sc);
252 amdsbwd_identify(driver_t *driver, device_t parent)
257 if (resource_disabled("amdsbwd", 0))
259 if (device_find_child(parent, "amdsbwd", -1) != NULL)
263 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device
264 * that should be present at bus 0, device 20, function 0.
266 smb_dev = pci_find_bsf(0, 20, 0);
269 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
270 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
271 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID)
274 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
276 device_printf(parent, "add amdsbwd child failed\n");
281 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
286 /* Report cause of previous reset for user's convenience. */
287 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
289 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
290 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
292 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
293 if ((val & AMDSB_WD_RST_STS) != 0)
294 device_printf(dev, "Previous Reset was caused by Watchdog\n");
296 /* Find base address of memory mapped WDT registers. */
297 for (*addr = 0, i = 0; i < 4; i++) {
299 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
303 /* Set watchdog timer tick to 1s. */
304 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
305 val &= ~AMDSB_WDT_RES_MASK;
306 val |= AMDSB_WDT_RES_1S;
307 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
309 /* Enable watchdog device (in stopped state). */
310 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
311 val &= ~AMDSB_WDT_DISABLE;
312 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
315 * XXX TODO: Ensure that watchdog decode is enabled
316 * (register 0x41, bit 3).
318 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
322 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
327 /* Report cause of previous reset for user's convenience. */
329 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
330 if ((val & AMDSB8_RST_STS_DIS) != 0) {
331 val &= ~AMDSB8_RST_STS_DIS;
332 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
335 for (i = 3; i >= 0; i--) {
337 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
340 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
341 if ((val & AMDSB8_WD_RST_STS) != 0)
342 device_printf(dev, "Previous Reset was caused by Watchdog\n");
344 /* Find base address of memory mapped WDT registers. */
345 for (*addr = 0, i = 0; i < 4; i++) {
347 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
351 /* Set watchdog timer tick to 1s. */
352 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
353 val &= ~AMDSB8_WDT_RES_MASK;
354 val |= AMDSB8_WDT_1HZ;
355 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
357 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
358 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
362 * Enable watchdog device (in stopped state)
363 * and decoding of its address.
365 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
366 val &= ~AMDSB8_WDT_DISABLE;
367 val |= AMDSB8_WDT_DEC_EN;
368 pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
370 val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
371 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
373 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
377 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
381 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
382 if ((val & AMDFCH41_MMIO_EN) != 0) {
383 /* Fixed offset for the watchdog within ACPI MMIO range. */
384 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
385 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
388 * Enable decoding of watchdog MMIO address.
390 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
391 val |= AMDFCH41_WDT_EN;
392 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
394 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
395 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
399 /* Special fixed MMIO range for the watchdog. */
400 *addr = AMDFCH41_WDT_FIXED_ADDR;
404 * Set watchdog timer tick to 1s and
405 * enable the watchdog device (in stopped state).
407 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
408 val &= ~AMDFCH41_WDT_RES_MASK;
409 val |= AMDFCH41_WDT_RES_1S;
410 val &= ~AMDFCH41_WDT_EN_MASK;
411 val |= AMDFCH41_WDT_ENABLE;
412 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
414 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
415 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
418 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer");
422 amdsbwd_probe(device_t dev)
424 struct resource *res;
432 /* Do not claim some ISA PnP device by accident. */
433 if (isa_get_logicalid(dev) != 0)
436 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
439 device_printf(dev, "bus_set_resource for IO failed\n");
443 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
444 RF_ACTIVE | RF_SHAREABLE);
446 device_printf(dev, "bus_alloc_resource for IO failed\n");
450 smb_dev = pci_find_bsf(0, 20, 0);
451 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
452 devid = pci_get_devid(smb_dev);
453 revid = pci_get_revid(smb_dev);
454 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
455 amdsbwd_probe_sb7xx(dev, res, &addr);
456 else if (devid == AMDSB_SMBUS_DEVID ||
457 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
458 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID))
459 amdsbwd_probe_sb8xx(dev, res, &addr);
461 amdsbwd_probe_fch41(dev, res, &addr);
463 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
464 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
466 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
467 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
468 AMDSB_WDIO_REG_WIDTH);
470 device_printf(dev, "bus_set_resource for control failed\n");
473 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
474 AMDSB_WDIO_REG_WIDTH);
476 device_printf(dev, "bus_set_resource for count failed\n");
484 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
487 sc->max_ticks = UINT16_MAX;
491 sc->ms_per_tick = 1000;
493 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
494 &sc->rid_ctrl, RF_ACTIVE);
495 if (sc->res_ctrl == NULL) {
496 device_printf(dev, "bus_alloc_resource for ctrl failed\n");
499 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
500 &sc->rid_count, RF_ACTIVE);
501 if (sc->res_count == NULL) {
502 device_printf(dev, "bus_alloc_resource for count failed\n");
509 amdsbwd_attach(device_t dev)
511 struct amdsbwd_softc *sc;
514 sc = device_get_softc(dev);
517 rc = amdsbwd_attach_sb(dev, sc);
522 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
523 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
526 /* Setup initial state of Watchdog Control. */
527 wdctrl_write(sc, AMDSB_WD_FIRED);
529 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
530 device_printf(dev, "watchdog hardware is disabled\n");
534 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
535 EVENTHANDLER_PRI_ANY);
545 amdsbwd_detach(device_t dev)
547 struct amdsbwd_softc *sc;
549 sc = device_get_softc(dev);
550 if (sc->ev_tag != NULL)
551 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
554 amdsbwd_tmr_disable(sc);
556 if (sc->res_ctrl != NULL)
557 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
560 if (sc->res_count != NULL)
561 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
568 amdsbwd_suspend(device_t dev)
570 struct amdsbwd_softc *sc;
573 sc = device_get_softc(dev);
574 val = wdctrl_read(sc);
575 val &= ~AMDSB_WD_RUN;
576 wdctrl_write(sc, val);
581 amdsbwd_resume(device_t dev)
583 struct amdsbwd_softc *sc;
585 sc = device_get_softc(dev);
586 wdctrl_write(sc, AMDSB_WD_FIRED);
588 amdsbwd_tmr_set(sc, sc->timeout);
589 amdsbwd_tmr_enable(sc);
590 amdsbwd_tmr_reload(sc);