2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
8 * Copyright (c) 2017-2019 Conrad Meyer <cem@FreeBSD.org>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
34 * Driver for the AMD CPU on-die thermal sensors.
35 * Initially based on the k8temp Linux driver.
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/sysctl.h>
47 #include <sys/systm.h>
49 #include <machine/cpufunc.h>
50 #include <machine/md_var.h>
51 #include <machine/specialreg.h>
53 #include <dev/pci/pcivar.h>
54 #include <x86/pci_cfgreg.h>
56 #include <dev/amdsmn/amdsmn.h>
67 struct amdtemp_softc {
71 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
72 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
73 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
75 int32_t (*sc_gettemp)(device_t, amdsensor_t);
76 struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
77 struct intr_config_hook sc_ich;
82 * N.B. The numbers in macro names below are significant and represent CPU
83 * family and model numbers. Do not make up fictitious family or model numbers
84 * when adding support for new devices.
86 #define VENDORID_AMD 0x1022
87 #define DEVICEID_AMD_MISC0F 0x1103
88 #define DEVICEID_AMD_MISC10 0x1203
89 #define DEVICEID_AMD_MISC11 0x1303
90 #define DEVICEID_AMD_MISC14 0x1703
91 #define DEVICEID_AMD_MISC15 0x1603
92 #define DEVICEID_AMD_MISC15_M10H 0x1403
93 #define DEVICEID_AMD_MISC15_M30H 0x141d
94 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
95 #define DEVICEID_AMD_MISC16 0x1533
96 #define DEVICEID_AMD_MISC16_M30H 0x1583
97 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
98 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
99 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480
101 static const struct amdtemp_product {
102 uint16_t amdtemp_vendorid;
103 uint16_t amdtemp_deviceid;
105 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
106 * drivers do not attach to that device.
108 bool amdtemp_has_cpuid;
109 } amdtemp_products[] = {
110 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
111 { VENDORID_AMD, DEVICEID_AMD_MISC10, true },
112 { VENDORID_AMD, DEVICEID_AMD_MISC11, true },
113 { VENDORID_AMD, DEVICEID_AMD_MISC14, true },
114 { VENDORID_AMD, DEVICEID_AMD_MISC15, true },
115 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
116 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
117 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
118 { VENDORID_AMD, DEVICEID_AMD_MISC16, true },
119 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
120 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
121 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
122 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
126 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
128 #define AMDTEMP_REPTMP_CTRL 0xa4
130 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
131 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
132 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
133 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
136 * Reported Temperature, Family 15h, M60+
138 * Same register bit definitions as other Family 15h CPUs, but access is
139 * indirect via SMN, like Family 17h.
141 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
144 * Reported Temperature, Family 17h
146 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
147 * provide the current temp. bit 19, when clear, means the temp is reported in
148 * a range 0.."225C" (probable typo for 255C), and when set changes the range
151 #define AMDTEMP_17H_CUR_TMP 0x59800
152 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19)
155 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
157 #define AMDTEMP_CURTMP_RANGE_ADJUST 490
160 * Thermaltrip Status Register (Family 0Fh only)
162 #define AMDTEMP_THERMTP_STAT 0xe4
163 #define AMDTEMP_TTSR_SELCORE 0x04
164 #define AMDTEMP_TTSR_SELSENSOR 0x40
167 * DRAM Configuration High Register
169 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
170 #define AMDTEMP_DRAM_MODE_DDR3 0x0100
173 * CPU Family/Model Register
175 #define AMDTEMP_CPUID 0xfc
180 static void amdtemp_identify(driver_t *driver, device_t parent);
181 static int amdtemp_probe(device_t dev);
182 static int amdtemp_attach(device_t dev);
183 static void amdtemp_intrhook(void *arg);
184 static int amdtemp_detach(device_t dev);
185 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
186 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
187 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
188 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
189 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
191 static device_method_t amdtemp_methods[] = {
192 /* Device interface */
193 DEVMETHOD(device_identify, amdtemp_identify),
194 DEVMETHOD(device_probe, amdtemp_probe),
195 DEVMETHOD(device_attach, amdtemp_attach),
196 DEVMETHOD(device_detach, amdtemp_detach),
201 static driver_t amdtemp_driver = {
204 sizeof(struct amdtemp_softc),
207 static devclass_t amdtemp_devclass;
208 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL);
209 MODULE_VERSION(amdtemp, 1);
210 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
211 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
212 nitems(amdtemp_products));
215 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
218 uint16_t vendor, devid;
220 vendor = pci_get_vendor(dev);
221 devid = pci_get_device(dev);
223 for (i = 0; i < nitems(amdtemp_products); i++) {
224 if (vendor == amdtemp_products[i].amdtemp_vendorid &&
225 devid == amdtemp_products[i].amdtemp_deviceid) {
226 if (product_out != NULL)
227 *product_out = &amdtemp_products[i];
235 amdtemp_identify(driver_t *driver, device_t parent)
239 /* Make sure we're not being doubly invoked. */
240 if (device_find_child(parent, "amdtemp", -1) != NULL)
243 if (amdtemp_match(parent, NULL)) {
244 child = device_add_child(parent, "amdtemp", -1);
246 device_printf(parent, "add amdtemp child failed\n");
251 amdtemp_probe(device_t dev)
253 uint32_t family, model;
255 if (resource_disabled("amdtemp", 0))
257 if (!amdtemp_match(device_get_parent(dev), NULL))
260 family = CPUID_TO_FAMILY(cpu_id);
261 model = CPUID_TO_MODEL(cpu_id);
265 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
266 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
280 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
282 return (BUS_PROBE_GENERIC);
286 amdtemp_attach(device_t dev)
290 const struct amdtemp_product *product;
291 struct amdtemp_softc *sc;
292 struct sysctl_ctx_list *sysctlctx;
293 struct sysctl_oid *sysctlnode;
294 uint32_t cpuid, family, model;
296 int erratum319, unit;
299 sc = device_get_softc(dev);
303 if (!amdtemp_match(device_get_parent(dev), &product))
307 family = CPUID_TO_FAMILY(cpuid);
308 model = CPUID_TO_MODEL(cpuid);
311 * This checks for the byzantine condition of running a heterogenous
312 * revision multi-socket system where the attach thread is potentially
313 * probing a remote socket's PCI device.
315 * Currently, such scenarios are unsupported on models using the SMN
316 * (because on those models, amdtemp(4) attaches to a different PCI
317 * device than the one that contains AMDTEMP_CPUID).
319 * The ancient 0x0F family of devices only supports this register from
322 if (product->amdtemp_has_cpuid && (family > 0x0f ||
323 (family == 0x0f && model >= 0x40))) {
324 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
326 family = CPUID_TO_FAMILY(cpuid);
327 model = CPUID_TO_MODEL(cpuid);
333 * Thermaltrip Status Register
335 * - ThermSenseCoreSel
337 * Revision F & G: 0 - Core1, 1 - Core0
338 * Other: 0 - Core0, 1 - Core1
342 * Revision G: bits 23-14
345 * XXX According to the BKDG, CurTmp, ThermSenseSel and
346 * ThermSenseCoreSel bits were introduced in Revision F
347 * but CurTmp seems working fine as early as Revision C.
348 * However, it is not clear whether ThermSenseSel and/or
349 * ThermSenseCoreSel work in undocumented cases as well.
350 * In fact, the Linux driver suggests it may not work but
351 * we just assume it does until we find otherwise.
353 * XXX According to Linux, CurTmp starts at -28C on
354 * Socket AM2 Revision G processors, which is not
355 * documented anywhere.
358 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
359 if (model >= 0x60 && model != 0xc1) {
360 do_cpuid(0x80000001, regs);
361 bid = (regs[1] >> 9) & 0x1f;
363 case 0x68: /* Socket S1g1 */
367 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
368 if (bid != 0x0b && bid != 0x0c)
370 AMDTEMP_FLAG_ALT_OFFSET;
372 case 0x6f: /* Socket AM2 and ASB1 (1 core) */
374 if (bid != 0x07 && bid != 0x09 &&
377 AMDTEMP_FLAG_ALT_OFFSET;
380 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
382 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
386 * There are two sensors per core.
390 sc->sc_gettemp = amdtemp_gettemp0f;
394 * Erratum 319 Inaccurate Temperature Measurement
396 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
398 do_cpuid(0x80000001, regs);
399 switch ((regs[1] >> 28) & 0xf) {
400 case 0: /* Socket F */
403 case 1: /* Socket AM2+ or AM3 */
404 if ((pci_cfgregread(pci_get_bus(dev),
405 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
406 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
407 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
409 /* XXX 00100F42h (RB-C2) exists in both formats. */
421 * Some later (60h+) models of family 15h use a similar SMN
422 * network as family 17h. (However, the register index differs
423 * from 17h and the decoding matches other 10h-15h models,
424 * which differ from 17h.)
426 if (family == 0x15 && model >= 0x60) {
427 sc->sc_gettemp = amdtemp_gettemp15hm60h;
430 sc->sc_gettemp = amdtemp_gettemp;
434 sc->sc_gettemp = amdtemp_gettemp17h;
438 device_printf(dev, "Bogus family 0x%x\n", family);
443 sc->sc_smn = device_find_child(
444 device_get_parent(dev), "amdsmn", -1);
445 if (sc->sc_smn == NULL) {
447 device_printf(dev, "No SMN device found\n");
452 /* Find number of cores per package. */
453 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
454 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
455 if (sc->sc_ncores > MAXCPU)
460 "Erratum 319: temperature measurement may be inaccurate\n");
462 device_printf(dev, "Found %d cores and %d sensors.\n",
464 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
467 * dev.amdtemp.N tree.
469 unit = device_get_unit(dev);
470 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
471 TUNABLE_INT_FETCH(tn, &sc->sc_offset);
473 sysctlctx = device_get_sysctl_ctx(dev);
474 SYSCTL_ADD_INT(sysctlctx,
475 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
476 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
477 "Temperature sensor offset");
478 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
480 "core0", CTLFLAG_RD, 0, "Core 0");
482 SYSCTL_ADD_PROC(sysctlctx,
483 SYSCTL_CHILDREN(sysctlnode),
484 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD,
485 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
486 "Core 0 / Sensor 0 temperature");
488 if (sc->sc_ntemps > 1) {
489 SYSCTL_ADD_PROC(sysctlctx,
490 SYSCTL_CHILDREN(sysctlnode),
491 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD,
492 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
493 "Core 0 / Sensor 1 temperature");
495 if (sc->sc_ncores > 1) {
496 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
497 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
498 OID_AUTO, "core1", CTLFLAG_RD, 0, "Core 1");
500 SYSCTL_ADD_PROC(sysctlctx,
501 SYSCTL_CHILDREN(sysctlnode),
502 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD,
503 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
504 "Core 1 / Sensor 0 temperature");
506 SYSCTL_ADD_PROC(sysctlctx,
507 SYSCTL_CHILDREN(sysctlnode),
508 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD,
509 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
510 "Core 1 / Sensor 1 temperature");
515 * Try to create dev.cpu sysctl entries and setup intrhook function.
516 * This is needed because the cpu driver may be loaded late on boot,
519 amdtemp_intrhook(dev);
520 sc->sc_ich.ich_func = amdtemp_intrhook;
521 sc->sc_ich.ich_arg = dev;
522 if (config_intrhook_establish(&sc->sc_ich) != 0) {
523 device_printf(dev, "config_intrhook_establish failed!\n");
531 amdtemp_intrhook(void *arg)
533 struct amdtemp_softc *sc;
534 struct sysctl_ctx_list *sysctlctx;
535 device_t dev = (device_t)arg;
536 device_t acpi, cpu, nexus;
540 sc = device_get_softc(dev);
543 * dev.cpu.N.temperature.
545 nexus = device_find_child(root_bus, "nexus", 0);
546 acpi = device_find_child(nexus, "acpi", 0);
548 for (i = 0; i < sc->sc_ncores; i++) {
549 if (sc->sc_sysctl_cpu[i] != NULL)
551 cpu = device_find_child(acpi, "cpu",
552 device_get_unit(dev) * sc->sc_ncores + i);
554 sysctlctx = device_get_sysctl_ctx(cpu);
556 sensor = sc->sc_ntemps > 1 ?
557 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
558 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
559 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
560 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD,
561 dev, sensor, amdtemp_sysctl, "IK",
562 "Current temparature");
565 if (sc->sc_ich.ich_arg != NULL)
566 config_intrhook_disestablish(&sc->sc_ich);
570 amdtemp_detach(device_t dev)
572 struct amdtemp_softc *sc = device_get_softc(dev);
575 for (i = 0; i < sc->sc_ncores; i++)
576 if (sc->sc_sysctl_cpu[i] != NULL)
577 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
579 /* NewBus removes the dev.amdtemp.N tree by itself. */
585 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
587 device_t dev = (device_t)arg1;
588 struct amdtemp_softc *sc = device_get_softc(dev);
589 amdsensor_t sensor = (amdsensor_t)arg2;
590 int32_t auxtemp[2], temp;
595 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
596 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
597 temp = imax(auxtemp[0], auxtemp[1]);
600 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
601 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
602 temp = imax(auxtemp[0], auxtemp[1]);
605 temp = sc->sc_gettemp(dev, sensor);
608 error = sysctl_handle_int(oidp, &temp, 0, req);
613 #define AMDTEMP_ZERO_C_TO_K 2731
616 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
618 struct amdtemp_softc *sc = device_get_softc(dev);
619 uint32_t mask, offset, temp;
621 /* Set Sensor/Core selector. */
622 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
623 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
626 temp |= AMDTEMP_TTSR_SELSENSOR;
630 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
631 temp |= AMDTEMP_TTSR_SELCORE;
634 temp |= AMDTEMP_TTSR_SELSENSOR;
638 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
639 temp |= AMDTEMP_TTSR_SELCORE;
642 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
644 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
645 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
646 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
647 temp = ((temp >> 14) & mask) * 5 / 2;
648 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
654 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
658 /* Convert raw register subfield units (0.125C) to units of 0.1C. */
659 temp = ((val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT) &
660 AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
663 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
664 * adjusted down by 49.0 degrees Celsius. (This adjustment is not
665 * documented in BKDGs prior to family 15h model 00h.)
667 if (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
668 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
669 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3)
670 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
672 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
677 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
679 struct amdtemp_softc *sc = device_get_softc(dev);
682 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
683 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
687 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
689 struct amdtemp_softc *sc = device_get_softc(dev);
693 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
694 KASSERT(error == 0, ("amdsmn_read"));
695 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
699 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
701 struct amdtemp_softc *sc = device_get_softc(dev);
705 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
706 KASSERT(error == 0, ("amdsmn_read"));
708 temp = ((val >> 21) & 0x7ff) * 5 / 4;
709 if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
710 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
711 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10;