sys/dev/amr/amrreg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-3-Clause
   3  *
   4  * Copyright (c) 1999,2000 Michael Smith
   5  * Copyright (c) 2000 BSDi
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Copyright (c) 2002 Eric Moore
  30  * Copyright (c) 2002 LSI Logic Corporation
  31  * All rights reserved.
  32  *
  33  * Redistribution and use in source and binary forms, with or without
  34  * modification, are permitted provided that the following conditions
  35  * are met:
  36  * 1. Redistributions of source code must retain the above copyright
  37  *    notice, this list of conditions and the following disclaimer.
  38  * 2. Redistributions in binary form must reproduce the above copyright
  39  *    notice, this list of conditions and the following disclaimer in the
  40  *    documentation and/or other materials provided with the distribution.
  41  * 3. The party using or redistributing the source code and binary forms
  42  *    agrees to the disclaimer below and the terms and conditions set forth
  43  *    herein.
  44  *
  45  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  46  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  47  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  48  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  49  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  50  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  51  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  52  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  54  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  55  * SUCH DAMAGE.
  56  *
  57  *
  58  *      $FreeBSD$
  59  */
  60
  61 /********************************************************************************
  62  ********************************************************************************
  63                                                                 Driver parameters
  64  ********************************************************************************
  65  ********************************************************************************/
  66
  67 /*
  68  * We could actually use all 17 segments, but using only 16 means that
  69  * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about
  70  * maps crossing page boundaries.
  71  *
  72  * The AMI documentation says that the limit is 26.  Unfortunately, there's no way to
  73  * cleanly fit more than 16 entries in without a page boundary.  But is this a concern,
  74  * since we allocate the s/g maps contiguously anyway?
  75  */
  76 /*
  77  * emoore - Oct 21, 2002
  78  * firmware doesn't have sglist boundary restrictions.
  79  * The sgelem can be set to 26
  80  */
  81 #define AMR_NSEG                26
  82
  83 #define AMR_MAXCMD              255             /* ident = 0 not allowed */
  84 #define AMR_LIMITCMD            120             /* maximum count of outstanding commands */
  85 #define AMR_MAXLD               40
  86
  87 #define AMR_MAX_CHANNELS        8
  88 #define AMR_MAX_TARGETS         15
  89 #define AMR_MAX_LUNS            7
  90 #define AMR_MAX_SCSI_CMDS       (15 * AMR_MAX_CHANNELS) /* one for every target? */
  91
  92 #define AMR_MAX_CDB_LEN         0x0a
  93 #define AMR_MAX_EXTCDB_LEN      0x10
  94 #define AMR_MAX_REQ_SENSE_LEN   0x20
  95
  96 #define AMR_BLKSIZE             512             /* constant for all controllers */
  97
  98 /*
  99  * Perform at-startup board initialisation.
 100  * At this point in time, this code doesn't work correctly, so leave it disabled.
 101  */
 102 /*#define AMR_BOARD_INIT*/
 103
 104 /********************************************************************************
 105  ********************************************************************************
 106                                                           Interface Magic Numbers
 107  ********************************************************************************
 108  ********************************************************************************/
 109
 110 /*
 111  * Mailbox commands
 112  */
 113 #define AMR_CMD_LREAD           0x01
 114 #define AMR_CMD_LWRITE          0x02
 115 #define AMR_CMD_PASS            0x03
 116 #define AMR_CMD_EXT_ENQUIRY     0x04
 117 #define AMR_CMD_ENQUIRY         0x05
 118 #define AMR_CMD_FLUSH           0x0a
 119 #define AMR_CMD_EXT_ENQUIRY2    0x0c
 120 #define AMR_CONFIG_PRODINFO     0x0e
 121 #define AMR_CMD_GET_MACHINEID   0x36
 122 #define AMR_CMD_GET_INITIATOR   0x7d    /* returns one byte */
 123 #define AMR_CMD_CONFIG          0xa1
 124 #define AMR_CMD_LREAD64         0xa7
 125 #define AMR_CMD_LWRITE64        0xa8
 126 #define AMR_CMD_PASS_64         0xc3
 127 #define AMR_CMD_EXTPASS         0xe3
 128
 129 #define AMR_CONFIG_READ_NVRAM_CONFIG    0x04
 130 #define AMR_CONFIG_WRITE_NVRAM_CONFIG   0x0d
 131 #define AMR_CONFIG_PRODUCT_INFO         0x0e
 132 #define AMR_CONFIG_ENQ3                 0x0f
 133 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY        0x01
 134 #define AMR_CONFIG_ENQ3_SOLICITED_FULL          0x02
 135 #define AMR_CONFIG_ENQ3_UNSOLICITED             0x03
 136
 137 /*
 138  * Command for random deletion of logical drives
 139  */
 140 #define FC_DEL_LOGDRV           0xA4
 141 #define OP_SUP_DEL_LOGDRV       0x2A
 142 #define OP_GET_LDID_MAP         0x18
 143 #define OP_DEL_LOGDRV           0x1C
 144
 145 /*
 146  * Command for random deletion of logical drives
 147  */
 148 #define FC_DEL_LOGDRV           0xA4
 149 #define OP_SUP_DEL_LOGDRV       0x2A
 150 #define OP_GET_LDID_MAP         0x18
 151 #define OP_DEL_LOGDRV           0x1C
 152
 153 /*
 154  * Command results
 155  */
 156 #define AMR_STATUS_SUCCESS      0x00
 157 #define AMR_STATUS_ABORTED      0x02
 158 #define AMR_STATUS_FAILED       0x80
 159
 160 /*
 161  * Physical/logical drive states
 162  */
 163 #define AMR_DRV_CURSTATE(x)     ((x) & 0x0f)
 164 #define AMR_DRV_PREVSTATE(x)    (((x) >> 4) & 0x0f)
 165 #define AMR_DRV_OFFLINE         0x00
 166 #define AMR_DRV_DEGRADED        0x01
 167 #define AMR_DRV_OPTIMAL         0x02
 168 #define AMR_DRV_ONLINE          0x03
 169 #define AMR_DRV_FAILED          0x04
 170 #define AMR_DRV_REBUILD         0x05
 171 #define AMR_DRV_HOTSPARE        0x06
 172
 173 /*
 174  * Logical drive properties
 175  */
 176 #define AMR_DRV_RAID_MASK       0x0f    /* RAID level 0, 1, 3, 5, etc. */
 177 #define AMR_DRV_WRITEBACK       0x10    /* write-back enabled */
 178 #define AMR_DRV_READHEAD        0x20    /* readhead policy enabled */
 179 #define AMR_DRV_ADAPTIVE        0x40    /* adaptive I/O policy enabled */
 180
 181 /*
 182  * Battery status
 183  */
 184 #define AMR_BATT_MODULE_MISSING         0x01
 185 #define AMR_BATT_LOW_VOLTAGE            0x02
 186 #define AMR_BATT_TEMP_HIGH              0x04
 187 #define AMR_BATT_PACK_MISSING           0x08
 188 #define AMR_BATT_CHARGE_MASK            0x30
 189 #define AMR_BATT_CHARGE_DONE            0x00
 190 #define AMR_BATT_CHARGE_INPROG          0x10
 191 #define AMR_BATT_CHARGE_FAIL            0x20
 192 #define AMR_BATT_CYCLES_EXCEEDED        0x40
 193
 194 /********************************************************************************
 195  ********************************************************************************
 196                                                            8LD Firmware Interface
 197  ********************************************************************************
 198  ********************************************************************************/
 199
 200 /*
 201  * Array constraints
 202  */
 203 #define AMR_8LD_MAXDRIVES       8
 204 #define AMR_8LD_MAXCHAN         5
 205 #define AMR_8LD_MAXTARG         15
 206 #define AMR_8LD_MAXPHYSDRIVES   (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
 207
 208 /*
 209  * Adapter Info structure
 210  */
 211 struct amr_adapter_info
 212 {
 213     u_int8_t    aa_maxio;
 214     u_int8_t    aa_rebuild_rate;
 215     u_int8_t    aa_maxtargchan;
 216     u_int8_t    aa_channels;
 217     u_int8_t    aa_firmware[4];
 218     u_int16_t   aa_flashage;
 219     u_int8_t    aa_chipsetvalue;
 220     u_int8_t    aa_memorysize;
 221     u_int8_t    aa_cacheflush;
 222     u_int8_t    aa_bios[4];
 223     u_int8_t    aa_boardtype;
 224     u_int8_t    aa_scsisensealert;
 225     u_int8_t    aa_writeconfigcount;
 226     u_int8_t    aa_driveinsertioncount;
 227     u_int8_t    aa_inserteddrive;
 228     u_int8_t    aa_batterystatus;
 229     u_int8_t    res1;
 230 } __packed;
 231
 232 /*
 233  * Logical Drive info structure
 234  */
 235 struct amr_logdrive_info
 236 {
 237     u_int8_t    al_numdrives;
 238     u_int8_t    res1[3];
 239     u_int32_t   al_size[AMR_8LD_MAXDRIVES];
 240     u_int8_t    al_properties[AMR_8LD_MAXDRIVES];
 241     u_int8_t    al_state[AMR_8LD_MAXDRIVES];
 242 } __packed;
 243
 244 /*
 245  * Physical Drive info structure
 246  */
 247 struct amr_physdrive_info
 248 {
 249     u_int8_t    ap_state[AMR_8LD_MAXPHYSDRIVES];        /* low nibble current state, high nibble previous state */
 250     u_int8_t    ap_predictivefailure;
 251 } __packed;
 252
 253 /*
 254  * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and
 255  * AMR_CMD_EXT_ENQUIRY2.
 256  *                                                              ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2
 257  */
 258 struct amr_enquiry
 259 {
 260     struct amr_adapter_info     ae_adapter;                     /* X      X             X */
 261     struct amr_logdrive_info    ae_ldrv;                        /* X      X             X */
 262     struct amr_physdrive_info   ae_pdrv;                        /* X      X             X */
 263     u_int8_t                    ae_formatting[AMR_8LD_MAXDRIVES];/*       X             X */
 264     u_int8_t                    res1[AMR_8LD_MAXDRIVES];        /*        X             X */
 265     u_int32_t                   ae_extlen;                      /*                      X */
 266     u_int16_t                   ae_subsystem;                   /*                      X */
 267     u_int16_t                   ae_subvendor;                   /*                      X */
 268     u_int32_t                   ae_signature;                   /*                      X */
 269 #define AMR_SIG_431     0xfffe0001
 270 #define AMR_SIG_438     0xfffd0002
 271 #define AMR_SIG_762     0xfffc0003
 272 #define AMR_SIG_T5      0xfffb0004
 273 #define AMR_SIG_466     0xfffa0005
 274 #define AMR_SIG_467     0xfff90006
 275 #define AMR_SIG_T7      0xfff80007
 276 #define AMR_SIG_490     0xfff70008
 277     u_int8_t                    res2[844];                      /*                      X */
 278 } __packed;
 279
 280 /********************************************************************************
 281  ********************************************************************************
 282                                                           40LD Firmware Interface
 283  ********************************************************************************
 284  ********************************************************************************/
 285
 286 /*
 287  * Array constraints
 288  */
 289 #define AMR_40LD_MAXDRIVES      40
 290 #define AMR_40LD_MAXCHAN        16
 291 #define AMR_40LD_MAXTARG        16
 292 #define AMR_40LD_MAXPHYSDRIVES  256
 293
 294 /*
 295  * Product Info structure
 296  */
 297 struct amr_prodinfo
 298 {
 299     u_int32_t   ap_size;                /* current size in bytes (not including resvd) */
 300     u_int32_t   ap_configsig;           /* default is 0x00282008, indicating 0x28 maximum
 301                                          * logical drives, 0x20 maximum stripes and 0x08
 302                                          * maximum spans */
 303     u_int8_t    ap_firmware[16];        /* printable identifiers */
 304     u_int8_t    ap_bios[16];
 305     u_int8_t    ap_product[80];
 306     u_int8_t    ap_maxio;               /* maximum number of concurrent commands supported */
 307     u_int8_t    ap_nschan;              /* number of SCSI channels present */
 308     u_int8_t    ap_fcloops;             /* number of fibre loops present */
 309     u_int8_t    ap_memtype;             /* memory type */
 310     u_int32_t   ap_signature;
 311     u_int16_t   ap_memsize;             /* onboard memory in MB */
 312     u_int16_t   ap_subsystem;           /* subsystem identifier */
 313     u_int16_t   ap_subvendor;           /* subsystem vendor ID */
 314     u_int8_t    ap_numnotifyctr;        /* number of notify counters */
 315 } __packed;
 316
 317 /*
 318  * Notify structure
 319  */
 320 struct amr_notify
 321 {
 322     u_int32_t   an_globalcounter;       /* change counter */
 323
 324     u_int8_t    an_paramcounter;        /* parameter change counter */
 325     u_int8_t    an_paramid;
 326 #define AMR_PARAM_REBUILD_RATE          0x01    /* value = new rebuild rate */
 327 #define AMR_PARAM_FLUSH_INTERVAL        0x02    /* value = new flush interval */
 328 #define AMR_PARAM_SENSE_ALERT           0x03    /* value = last physical drive with check condition set */
 329 #define AMR_PARAM_DRIVE_INSERTED        0x04    /* value = last physical drive inserted */
 330 #define AMR_PARAM_BATTERY_STATUS        0x05    /* value = battery status */
 331     u_int16_t   an_paramval;
 332
 333     u_int8_t    an_writeconfigcounter;  /* write config occurred */
 334     u_int8_t    res1[3];
 335
 336     u_int8_t    an_ldrvopcounter;       /* logical drive operation started/completed */
 337     u_int8_t    an_ldrvopid;
 338     u_int8_t    an_ldrvopcmd;
 339 #define AMR_LDRVOP_CHECK        0x01
 340 #define AMR_LDRVOP_INIT         0x02
 341 #define AMR_LDRVOP_REBUILD      0x03
 342     u_int8_t    an_ldrvopstatus;
 343 #define AMR_LDRVOP_SUCCESS      0x00
 344 #define AMR_LDRVOP_FAILED       0x01
 345 #define AMR_LDRVOP_ABORTED      0x02
 346 #define AMR_LDRVOP_CORRECTED    0x03
 347 #define AMR_LDRVOP_STARTED      0x04
 348
 349     u_int8_t    an_ldrvstatecounter;    /* logical drive state change occurred */
 350     u_int8_t    an_ldrvstateid;
 351     u_int8_t    an_ldrvstatenew;
 352     u_int8_t    an_ldrvstateold;
 353
 354     u_int8_t    an_pdrvstatecounter;    /* physical drive state change occurred */
 355     u_int8_t    an_pdrvstateid;
 356     u_int8_t    an_pdrvstatenew;
 357     u_int8_t    an_pdrvstateold;
 358
 359     u_int8_t    an_pdrvfmtcounter;
 360     u_int8_t    an_pdrvfmtid;
 361     u_int8_t    an_pdrvfmtval;
 362 #define AMR_FORMAT_START        0x01
 363 #define AMR_FORMAT_COMPLETE     0x02
 364     u_int8_t    res2;
 365
 366     u_int8_t    an_targxfercounter;     /* scsi xfer rate change */
 367     u_int8_t    an_targxferid;
 368     u_int8_t    an_targxferval;
 369     u_int8_t    res3;
 370
 371     u_int8_t    an_fcloopidcounter;     /* FC/AL loop ID changed */
 372     u_int8_t    an_fcloopidpdrvid;
 373     u_int8_t    an_fcloopid0;
 374     u_int8_t    an_fcloopid1;
 375
 376     u_int8_t    an_fcloopstatecounter;  /* FC/AL loop status changed */
 377     u_int8_t    an_fcloopstate0;
 378     u_int8_t    an_fcloopstate1;
 379     u_int8_t    res4;
 380 } __packed;
 381
 382 /*
 383  * Enquiry3 structure
 384  */
 385 struct amr_enquiry3
 386 {
 387     u_int32_t   ae_datasize;            /* valid data size in this structure */
 388     union {                             /* event notify structure */
 389         struct amr_notify       n;
 390         u_int8_t                pad[0x80];
 391     }           ae_notify;
 392     u_int8_t    ae_rebuildrate;         /* current rebuild rate in % */
 393     u_int8_t    ae_cacheflush;          /* flush interval in seconds */
 394     u_int8_t    ae_sensealert;
 395     u_int8_t    ae_driveinsertcount;    /* count of inserted drives */
 396     u_int8_t    ae_batterystatus;
 397     u_int8_t    ae_numldrives;
 398     u_int8_t    ae_reconstate[AMR_40LD_MAXDRIVES / 8];  /* reconstruction state */
 399     u_int16_t   ae_opstatus[AMR_40LD_MAXDRIVES / 8];    /* operation status per drive */
 400     u_int32_t   ae_drivesize[AMR_40LD_MAXDRIVES];       /* logical drive size */
 401     u_int8_t    ae_driveprop[AMR_40LD_MAXDRIVES];       /* logical drive properties */
 402     u_int8_t    ae_drivestate[AMR_40LD_MAXDRIVES];      /* logical drive state */
 403     u_int8_t    ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */
 404     u_int16_t   ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES / 16];
 405     u_int8_t    ae_targxfer[80];                        /* physical drive transfer rates */
 406
 407     u_int8_t    res1[263];              /* pad to 1024 bytes */
 408 } __packed;
 409
 410 /********************************************************************************
 411  ********************************************************************************
 412                                                    Mailbox and Command Structures
 413  ********************************************************************************
 414  ********************************************************************************/
 415
 416 #define AMR_MBOX_CMDSIZE        0x10    /* portion worth copying for controller */
 417
 418 struct amr_mailbox
 419 {
 420     u_int8_t    mb_command;
 421     u_int8_t    mb_ident;
 422     u_int16_t   mb_blkcount;            /* u_int8_t opcode */
 423                                         /* u_int8_t subopcode */
 424     u_int32_t   mb_lba;
 425     u_int32_t   mb_physaddr;
 426     u_int8_t    mb_drive;
 427     u_int8_t    mb_nsgelem;             /* u_int8_t rserv[0] */
 428     u_int8_t    res1;                   /* u_int8_t rserv[1] */
 429     u_int8_t    mb_busy;                /* u_int8_t rserv[2] */
 430     u_int8_t    mb_nstatus;
 431     u_int8_t    mb_status;
 432     u_int8_t    mb_completed[46];
 433     u_int8_t    mb_poll;
 434     u_int8_t    mb_ack;
 435     u_int8_t    res2[16];
 436 } __packed;
 437
 438 struct amr_mailbox64
 439 {
 440     u_int8_t    pad[8];         /* Needed for alignment */
 441     u_int32_t   sg64_lo;        /* S/G pointer for 64-bit commands */
 442     u_int32_t   sg64_hi;        /* S/G pointer for 64-bit commands */
 443     struct amr_mailbox  mb;
 444 } __packed;
 445
 446 struct amr_mailbox_ioctl
 447 {
 448     u_int8_t    mb_command;
 449     u_int8_t    mb_ident;
 450     u_int8_t    mb_channel;
 451     u_int8_t    mb_param;
 452     u_int8_t    mb_pad[4];
 453     u_int32_t   mb_physaddr;
 454     u_int8_t    mb_drive;
 455     u_int8_t    mb_nsgelem;
 456     u_int8_t    res1;
 457     u_int8_t    mb_busy;
 458     u_int8_t    mb_nstatus;
 459     u_int8_t    mb_completed[46];
 460     u_int8_t    mb_poll;
 461     u_int8_t    mb_ack;
 462     u_int8_t    res4[16];
 463 } __packed;
 464
 465 struct amr_sgentry
 466 {
 467     u_int32_t   sg_addr;
 468     u_int32_t   sg_count;
 469 } __packed;
 470
 471 struct amr_sg64entry
 472 {
 473     u_int64_t   sg_addr;
 474     u_int32_t   sg_count;
 475 } __packed;
 476
 477 struct amr_passthrough
 478 {
 479     u_int8_t    ap_timeout:3;
 480     u_int8_t    ap_ars:1;
 481     u_int8_t    ap_dummy:3;
 482     u_int8_t    ap_islogical:1;
 483     u_int8_t    ap_logical_drive_no;
 484     u_int8_t    ap_channel;
 485     u_int8_t    ap_scsi_id;
 486     u_int8_t    ap_queue_tag;
 487     u_int8_t    ap_queue_action;
 488     u_int8_t    ap_cdb[AMR_MAX_CDB_LEN];
 489     u_int8_t    ap_cdb_length;
 490     u_int8_t    ap_request_sense_length;
 491     u_int8_t    ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
 492     u_int8_t    ap_no_sg_elements;
 493     u_int8_t    ap_scsi_status;
 494     u_int32_t   ap_data_transfer_address;
 495     u_int32_t   ap_data_transfer_length;
 496 } __packed;
 497
 498 struct amr_ext_passthrough
 499 {
 500     u_int8_t    ap_timeout:3;
 501     u_int8_t    ap_ars:1;
 502     u_int8_t    ap_rsvd1:1;
 503     u_int8_t    ap_cd_rom:1;
 504     u_int8_t    ap_rsvd2:1;
 505     u_int8_t    ap_islogical:1;
 506     u_int8_t    ap_logical_drive_no;
 507     u_int8_t    ap_channel;
 508     u_int8_t    ap_scsi_id;
 509     u_int8_t    ap_queue_tag;
 510     u_int8_t    ap_queue_action;
 511     u_int8_t    ap_cdb_length;
 512     u_int8_t    ap_rsvd3;
 513     u_int8_t    ap_cdb[AMR_MAX_EXTCDB_LEN];
 514     u_int8_t    ap_no_sg_elements;
 515     u_int8_t    ap_scsi_status;
 516     u_int8_t    ap_request_sense_length;
 517     u_int8_t    ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
 518     u_int8_t    ap_rsvd4;
 519     u_int32_t   ap_data_transfer_address;
 520     u_int32_t   ap_data_transfer_length;
 521 } __packed;
 522
 523 struct amr_linux_ioctl {
 524     u_int32_t   inlen;
 525     u_int32_t   outlen;
 526     union {
 527         u_int8_t        fca[16];
 528         struct {
 529             u_int8_t    opcode;
 530             u_int8_t    subopcode;
 531             u_int16_t   adapno;
 532             u_int32_t   buffer;
 533             u_int8_t    pad[4];
 534             u_int32_t   length;
 535         } __packed fcs;
 536     } __packed ui;
 537     u_int8_t    mbox[18];
 538     struct amr_passthrough      pthru;
 539     u_int32_t   data;
 540     u_int8_t    pad[4];
 541 } __packed;
 542
 543 #ifdef _KERNEL
 544 /********************************************************************************
 545  ********************************************************************************
 546                                                "Quartz" i960 PCI bridge interface
 547  ********************************************************************************
 548  ********************************************************************************/
 549
 550 #define AMR_CFG_SIG             0xa0            /* PCI config register for signature */
 551 #define AMR_SIGNATURE_1         0xCCCC          /* i960 signature (older adapters) */
 552 #define AMR_SIGNATURE_2         0x3344          /* i960 signature (newer adapters) */
 553
 554 /*
 555  * Doorbell registers
 556  */
 557 #define AMR_QIDB                0x20
 558 #define AMR_QODB                0x2c
 559 #define AMR_QIDB_SUBMIT         0x00000001      /* mailbox ready for work */
 560 #define AMR_QIDB_ACK            0x00000002      /* mailbox done */
 561 #define AMR_QODB_READY          0x10001234      /* work ready to be processed */
 562
 563 /*
 564  * Initialisation status
 565  */
 566 #define AMR_QINIT_SCAN          0x01    /* init scanning drives */
 567 #define AMR_QINIT_SCANINIT      0x02    /* init scanning initialising */
 568 #define AMR_QINIT_FIRMWARE      0x03    /* init firmware initing */
 569 #define AMR_QINIT_INPROG        0xdc    /* init in progress */
 570 #define AMR_QINIT_SPINUP        0x2c    /* init spinning drives */
 571 #define AMR_QINIT_NOMEM         0xac    /* insufficient memory */
 572 #define AMR_QINIT_CACHEFLUSH    0xbc    /* init flushing cache */
 573 #define AMR_QINIT_DONE          0x9c    /* init successfully done */
 574
 575 /*
 576  * I/O primitives
 577  */
 578 #define AMR_QPUT_IDB(sc, val)   bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val)
 579 #define AMR_QGET_IDB(sc)        bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB)
 580 #define AMR_QPUT_ODB(sc, val)   bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val)
 581 #define AMR_QGET_ODB(sc)        bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB)
 582
 583 #ifdef AMR_BOARD_INIT
 584 #define AMR_QRESET(sc)                                                                                  \
 585         do {                                                                                            \
 586             pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1);   \
 587             pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1);                                           \
 588         } while (0)
 589 #define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1)
 590 #define AMR_QGET_INITCHAN(sc)   pci_read_config((sc)->amr_dev, 0x9f, 1)
 591 #define AMR_QGET_INITTARG(sc)   pci_read_config((sc)->amr_dev, 0x9e, 1)
 592 #endif
 593
 594 /********************************************************************************
 595  ********************************************************************************
 596                                        "Standard" old-style ASIC bridge interface
 597  ********************************************************************************
 598  ********************************************************************************/
 599
 600 /*
 601  * I/O registers
 602  */
 603 #define AMR_SCMD                0x10    /* command/ack register (write) */
 604 #define AMR_SMBOX_BUSY          0x10    /* mailbox status (read) */
 605 #define AMR_STOGGLE             0x11    /* interrupt enable bit here */
 606 #define AMR_SMBOX_0             0x14    /* mailbox physical address low byte */
 607 #define AMR_SMBOX_1             0x15
 608 #define AMR_SMBOX_2             0x16
 609 #define AMR_SMBOX_3             0x17    /*                          high byte */
 610 #define AMR_SMBOX_ENABLE        0x18    /* atomic mailbox address enable */
 611 #define AMR_SINTR               0x1a    /* interrupt status */
 612
 613 /*
 614  * I/O magic numbers
 615  */
 616 #define AMR_SCMD_POST           0x10    /* -> SCMD to initiate action on mailbox */
 617 #define AMR_SCMD_ACKINTR        0x08    /* -> SCMD to ack mailbox retrieved */
 618 #define AMR_STOGL_IENABLE       0xc0    /* in STOGGLE */
 619 #define AMR_SINTR_VALID         0x40    /* in SINTR */
 620 #define AMR_SMBOX_BUSYFLAG      0x10    /* in SMBOX_BUSY */
 621 #define AMR_SMBOX_ADDR          0x00    /* -> SMBOX_ENABLE */
 622
 623 /*
 624  * Initialisation status
 625  */
 626 #define AMR_SINIT_ABEND         0xee    /* init abnormal terminated */
 627 #define AMR_SINIT_NOMEM         0xca    /* insufficient memory */
 628 #define AMR_SINIT_CACHEFLUSH    0xbb    /* firmware flushing cache */
 629 #define AMR_SINIT_INPROG        0x11    /* init in progress */
 630 #define AMR_SINIT_SPINUP        0x22    /* firmware spinning drives */
 631 #define AMR_SINIT_DONE          0x99    /* init successfully done */
 632
 633 /*
 634  * I/O primitives
 635  */
 636 #define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val)
 637 #define AMR_SGET_ISTAT(sc)      bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR)
 638 #define AMR_SACK_INTERRUPT(sc)  bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR)
 639 #define AMR_SPOST_COMMAND(sc)   bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST)
 640 #define AMR_SGET_MBSTAT(sc)     bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY)
 641 #define AMR_SENABLE_INTR(sc)                                                                                    \
 642         bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE,                                           \
 643                           bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE)
 644 #define AMR_SDISABLE_INTR(sc)                                                                                   \
 645         bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE,                                           \
 646                           bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE)
 647 #define AMR_SBYTE_SET(sc, reg, val)     bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val)
 648
 649 #ifdef AMR_BOARD_INIT
 650 #define AMR_SRESET(sc)          bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80)
 651 #define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE)
 652 #define AMR_SGET_FAILDRIVE(sc)  bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1)
 653 #define AMR_SGET_INITCHAN(sc)   bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2)
 654 #define AMR_SGET_INITTARG(sc)   bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3)
 655 #endif
 656
 657 #endif /* _KERNEL */