2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
35 #define AN_TIMEOUT 65536
37 /* Default network name: <empty string> */
38 #define AN_DEFAULT_NETNAME ""
40 /* The nodename must be less than 16 bytes */
41 #define AN_DEFAULT_NODENAME "FreeBSD"
43 #define AN_DEFAULT_IBSS "FreeBSD IBSS"
46 * register space access macros
48 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->port_res, reg, val)
50 #define CSR_READ_2(sc, reg) bus_read_2(sc->port_res, reg)
52 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->port_res, reg, val)
54 #define CSR_READ_1(sc, reg) bus_read_1(sc->port_res, reg)
57 * memory space access macros
59 #define CSR_MEM_WRITE_2(sc, reg, val) bus_write_2(sc->mem_res, reg, val)
61 #define CSR_MEM_READ_2(sc, reg) bus_read_2(sc->mem_res, reg)
63 #define CSR_MEM_WRITE_1(sc, reg, val) bus_write_1(sc->mem_res, reg, val)
65 #define CSR_MEM_READ_1(sc, reg) bus_read_1(sc->mem_res, reg)
68 * aux. memory space access macros
70 #define CSR_MEM_AUX_WRITE_4(sc, reg, val) \
71 bus_write_4(sc->mem_aux_res, reg, val)
73 #define CSR_MEM_AUX_READ_4(sc, reg) \
74 bus_read_4(sc->mem_aux_res, reg)
76 #define CSR_MEM_AUX_WRITE_1(sc, reg, val) \
77 bus_write_1(sc->mem_aux_res, reg, val)
79 #define CSR_MEM_AUX_READ_1(sc, reg) \
80 bus_read_1(sc->mem_aux_res, reg)
83 * Size of Aironet I/O space.
88 * Size of aux. memory space ... probably not needed DJA
90 #define AN_AUX_MEM_SIZE (256 * 1024)
93 * Hermes register definitions and what little I know about them.
96 /* Hermes command/status registers. */
97 #define AN_COMMAND(x) (x ? 0x00 : 0x00)
98 #define AN_PARAM0(x) (x ? 0x04 : 0x02)
99 #define AN_PARAM1(x) (x ? 0x08 : 0x04)
100 #define AN_PARAM2(x) (x ? 0x0c : 0x06)
101 #define AN_STATUS(x) (x ? 0x10 : 0x08)
102 #define AN_RESP0(x) (x ? 0x14 : 0x0A)
103 #define AN_RESP1(x) (x ? 0x18 : 0x0C)
104 #define AN_RESP2(x) (x ? 0x1c : 0x0E)
105 #define AN_LINKSTAT(x) (x ? 0x20 : 0x10)
107 /* Command register */
108 #define AN_CMD_BUSY 0x8000 /* busy bit */
109 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
110 #define AN_CMD_CODE_MASK 0x003F
111 #define AN_CMD_QUAL_MASK 0x7F00
114 #define AN_CMD_NOOP 0x0000 /* no-op */
115 #define AN_CMD_ENABLE 0x0001 /* enable */
116 #define AN_CMD_DISABLE 0x0002 /* disable */
117 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
118 #define AN_CMD_FW_RESTART 0x0004 /* firmware restart */
119 #define AN_CMD_HOST_SLEEP 0x0005
120 #define AN_CMD_MAGIC_PKT 0x0006
121 #define AN_CMD_READCFG 0x0008
122 #define AN_CMD_SET_MODE 0x0009
123 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
124 #define AN_CMD_TX 0x000B /* transmit */
125 #define AN_CMD_DEALLOC_MEM 0x000C
126 #define AN_CMD_NOOP2 0x0010
127 #define AN_CMD_ALLOC_DESC 0x0020
128 #define AN_CMD_ACCESS 0x0021
129 #define AN_CMD_ALLOC_BUF 0x0028
130 #define AN_CMD_PSP_NODES 0x0030
131 #define AN_CMD_SET_PHYREG 0x003E
132 #define AN_CMD_TX_TEST 0x003F
133 #define AN_CMD_SLEEP 0x0085
134 #define AN_CMD_SAVECFG 0x0108
137 * MPI 350 DMA descriptor information
139 #define AN_DESCRIPTOR_TX 0x01
140 #define AN_DESCRIPTOR_RX 0x02
141 #define AN_DESCRIPTOR_TXCMP 0x04
142 #define AN_DESCRIPTOR_HOSTWRITE 0x08
143 #define AN_DESCRIPTOR_HOSTREAD 0x10
144 #define AN_DESCRIPTOR_HOSTRW 0x20
146 #define AN_MAX_RX_DESC 1
147 #define AN_MAX_TX_DESC 1
148 #define AN_HOSTBUFSIZ 1840
150 struct an_card_rid_desc
158 struct an_card_rx_desc
167 struct an_card_tx_desc
169 unsigned an_offset:15;
176 #define AN_RID_BUFFER_SIZE AN_MAX_DATALEN
177 #define AN_RX_BUFFER_SIZE AN_HOSTBUFSIZ
178 #define AN_TX_BUFFER_SIZE AN_HOSTBUFSIZ
179 /*#define AN_HOST_DESC_OFFSET 0xC sort of works */
180 #define AN_HOST_DESC_OFFSET 0x800
181 #define AN_RX_DESC_OFFSET (AN_HOST_DESC_OFFSET + \
182 sizeof(struct an_card_rid_desc))
183 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
184 (AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
201 * Reclaim qualifier bit, applicable to the
204 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */
207 * ACCESS command qualifier bits.
209 #define AN_ACCESS_READ 0x0000
210 #define AN_ACCESS_WRITE 0x0100
213 * PROGRAM command qualifier bits.
215 #define AN_PROGRAM_DISABLE 0x0000
216 #define AN_PROGRAM_ENABLE_RAM 0x0100
217 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
218 #define AN_PROGRAM_NVRAM 0x0300
220 /* Status register values */
221 #define AN_STAT_CMD_CODE 0x003F
222 #define AN_STAT_CMD_RESULT 0x7F00
224 /* Linkstat register */
225 #define AN_LINKSTAT_ASSOCIATED 0x0400
226 #define AN_LINKSTAT_AUTHFAIL 0x0300
227 #define AN_LINKSTAT_ASSOC_FAIL 0x8400
228 #define AN_LINKSTAT_DISASSOC 0x8200
229 #define AN_LINKSTAT_DEAUTH 0x8100
230 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004
231 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
232 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
233 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
234 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
236 /* memory handle management registers */
237 #define AN_RX_FID 0x20
238 #define AN_ALLOC_FID 0x22
239 #define AN_TX_CMP_FID(x) (x ? 0x1a : 0x24)
242 * Buffer Access Path (BAP) registers.
243 * These are I/O channels. I believe you can use each one for
244 * any desired purpose independently of the other. In general
245 * though, we use BAP1 for reading and writing LTV records and
246 * reading received data frames, and BAP0 for writing transmit
247 * frames. This is a convention though, not a rule.
253 #define AN_DATA0 0x36
254 #define AN_DATA1 0x38
255 #define AN_BAP0 AN_DATA0
256 #define AN_BAP1 AN_DATA1
258 #define AN_OFF_BUSY 0x8000
259 #define AN_OFF_ERR 0x4000
260 #define AN_OFF_DONE 0x2000
261 #define AN_OFF_DATAOFF 0x0FFF
263 /* Event registers */
264 #define AN_EVENT_STAT(x) (x ? 0x60 : 0x30) /* Event status */
265 #define AN_INT_EN(x) (x ? 0x64 : 0x32) /* Interrupt enable/
267 #define AN_EVENT_ACK(x) (x ? 0x68 : 0x34) /* Ack event */
270 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
271 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
272 #define AN_EV_MIC 0x1000 /* Message Integrity Check*/
273 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
274 #define AN_EV_LINKSTAT 0x0080 /* link status available */
275 #define AN_EV_CMD 0x0010 /* command completed */
276 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
277 #define AN_EV_TX_CPY 0x0400
278 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
279 #define AN_EV_TX 0x0002 /* async xmit completed succesfully */
280 #define AN_EV_RX 0x0001 /* async rx completed */
282 #define AN_INTRS(x) \
283 ( x ? (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_TX_CPY|AN_EV_ALLOC \
284 |AN_EV_LINKSTAT|AN_EV_MIC) \
286 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC \
287 |AN_EV_LINKSTAT|AN_EV_MIC) \
290 /* Host software registers */
291 #define AN_SW0(x) (x ? 0x50 : 0x28)
292 #define AN_SW1(x) (x ? 0x54 : 0x2A)
293 #define AN_SW2(x) (x ? 0x58 : 0x2C)
294 #define AN_SW3(x) (x ? 0x5c : 0x2E)
298 #define AN_CNTL_AUX_ENA 0xC000
299 #define AN_CNTL_AUX_ENA_STAT 0xC000
300 #define AN_CNTL_AUX_DIS_STAT 0x0000
301 #define AN_CNTL_AUX_ENA_CNTL 0x8000
302 #define AN_CNTL_AUX_DIS_CNTL 0x4000
304 #define AN_AUX_PAGE 0x3A
305 #define AN_AUX_OFFSET 0x3C
306 #define AN_AUX_DATA 0x3E
309 * Length, Type, Value (LTV) record definitions and RID values.
317 #define AN_DEF_SSID_LEN 7
318 #define AN_DEF_SSID "tsunami"
320 #define AN_RXGAP_MAX 8
323 * Transmit frame structure.
326 u_int32_t an_tx_sw; /* 0x00 */
327 u_int16_t an_tx_status; /* 0x04 */
328 u_int16_t an_tx_payload_len; /* 0x06 */
329 u_int16_t an_tx_ctl; /* 0x08 */
330 u_int16_t an_tx_assoc_id; /* 0x0A */
331 u_int16_t an_tx_retry; /* 0x0C */
332 u_int8_t an_tx_assoc_cnt; /* 0x0E */
333 u_int8_t an_tx_rate; /* 0x0F */
334 u_int8_t an_tx_max_long_retries; /* 0x10 */
335 u_int8_t an_tx_max_short_retries; /*0x11 */
336 u_int8_t an_rsvd0[2]; /* 0x12 */
337 u_int16_t an_frame_ctl; /* 0x14 */
338 u_int16_t an_duration; /* 0x16 */
339 u_int8_t an_addr1[6]; /* 0x18 */
340 u_int8_t an_addr2[6]; /* 0x1E */
341 u_int8_t an_addr3[6]; /* 0x24 */
342 u_int16_t an_seq_ctl; /* 0x2A */
343 u_int8_t an_addr4[6]; /* 0x2C */
344 u_int8_t an_gaplen; /* 0x32 */
347 struct an_rxframe_802_3 {
348 u_int16_t an_rx_802_3_status; /* 0x34 */
349 u_int16_t an_rx_802_3_payload_len;/* 0x36 */
350 u_int8_t an_rx_dst_addr[6]; /* 0x38 */
351 u_int8_t an_rx_src_addr[6]; /* 0x3E */
353 #define AN_RXGAP_MAX 8
356 struct an_txframe_802_3 {
358 * Transmit 802.3 header structure.
360 u_int16_t an_tx_802_3_status; /* 0x34 */
361 u_int16_t an_tx_802_3_payload_len;/* 0x36 */
362 u_int8_t an_tx_dst_addr[6]; /* 0x38 */
363 u_int8_t an_tx_src_addr[6]; /* 0x3E */
366 #define AN_TXSTAT_EXCESS_RETRY 0x0002
367 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
368 #define AN_TXSTAT_AID_FAIL 0x0008
369 #define AN_TXSTAT_MAC_DISABLED 0x0010
370 #define AN_TXSTAT_ASSOC_LOST 0x0020
372 #define AN_TXCTL_RSVD 0x0001
373 #define AN_TXCTL_TXOK_INTR 0x0002
374 #define AN_TXCTL_TXERR_INTR 0x0004
375 #define AN_TXCTL_HEADER_TYPE 0x0008
376 #define AN_TXCTL_PAYLOAD_TYPE 0x0010
377 #define AN_TXCTL_NORELEASE 0x0020
378 #define AN_TXCTL_NORETRIES 0x0040
379 #define AN_TXCTL_CLEAR_AID 0x0080
380 #define AN_TXCTL_STRICT_ORDER 0x0100
381 #define AN_TXCTL_USE_RTS 0x0200
383 #define AN_HEADERTYPE_8023 0x0000
384 #define AN_HEADERTYPE_80211 0x0008
386 #define AN_PAYLOADTYPE_ETHER 0x0000
387 #define AN_PAYLOADTYPE_LLC 0x0010
389 #define AN_TXCTL_80211 (AN_HEADERTYPE_80211|AN_PAYLOADTYPE_LLC)
391 #define AN_TXCTL_8023 (AN_HEADERTYPE_8023|AN_PAYLOADTYPE_ETHER)
394 * Additions to transmit control bits for MPI350
396 #define AN_TXCTL_HW(x) \
397 ( x ? (AN_TXCTL_NORELEASE) \
399 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_TXCTL_NORELEASE) \
402 #define AN_TXGAP_80211 0
403 #define AN_TXGAP_8023 0
405 struct an_802_3_hdr {
406 u_int16_t an_8023_status;
407 u_int16_t an_8023_payload_len;
408 u_int8_t an_8023_dst_addr[6];
409 u_int8_t an_8023_src_addr[6];
410 u_int16_t an_8023_dat[3]; /* SNAP header */
411 u_int16_t an_8023_type;
415 u_int16_t an_snap_dat[3]; /* SNAP header */
416 u_int16_t an_snap_type;
419 struct an_dma_alloc {
420 u_int32_t an_dma_paddr;
421 caddr_t an_dma_vaddr;
422 bus_dmamap_t an_dma_map;
423 bus_dma_segment_t an_dma_seg;
424 bus_size_t an_dma_size;
428 #define AN_TX_RING_CNT 4
429 #define AN_INC(x, y) (x) = (x + 1) % y
431 struct an_tx_ring_data {
432 u_int16_t an_tx_fids[AN_TX_RING_CNT];
433 u_int16_t an_tx_ring[AN_TX_RING_CNT];
440 struct ifnet *an_ifp;
442 int port_rid; /* resource id for port range */
443 struct resource* port_res; /* resource for port range */
444 int mem_rid; /* resource id for memory range */
445 int mem_used; /* nonzero if memory used */
446 struct resource* mem_res; /* resource for memory range */
447 int mem_aux_rid; /* resource id for memory range */
448 int mem_aux_used; /* nonzero if memory used */
449 struct resource* mem_aux_res; /* resource for memory range */
450 int irq_rid; /* resource id for irq */
451 void* irq_handle; /* handle for irq handler */
452 struct resource* irq_res; /* resource for irq */
454 bus_space_handle_t an_mem_aux_bhandle;
455 bus_space_tag_t an_mem_aux_btag;
456 bus_dma_tag_t an_dtag;
457 struct an_ltv_genconfig an_config;
458 struct an_ltv_caps an_caps;
459 struct an_ltv_ssidlist_new an_ssidlist;
460 struct an_ltv_aplist an_aplist;
461 struct an_ltv_key an_temp_keys[4];
466 u_int8_t an_txbuf[1536];
467 struct an_tx_ring_data an_rdata;
468 struct an_ltv_stats an_stats;
469 struct an_ltv_status an_status;
470 u_int8_t an_associated;
473 struct an_sigcache an_sigcache[MAXANCACHE];
476 struct an_ltv_rssi_map an_rssimap;
478 struct callout an_stat_ch;
481 struct ifmedia an_ifmedia;
485 u_char buf_802_11[MCLBYTES];
487 unsigned short* an_flash_buffer;
489 struct an_dma_alloc an_rid_buffer;
490 struct an_dma_alloc an_rx_buffer[AN_MAX_RX_DESC];
491 struct an_dma_alloc an_tx_buffer[AN_MAX_TX_DESC];
494 #define AN_LOCK(_sc) mtx_lock(&(_sc)->an_mtx)
495 #define AN_UNLOCK(_sc) mtx_unlock(&(_sc)->an_mtx)
496 #define AN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->an_mtx, MA_OWNED)
498 void an_release_resources (device_t);
499 int an_alloc_port (device_t, int, int);
500 int an_alloc_memory (device_t, int, int);
501 int an_alloc_aux_memory (device_t, int, int);
502 int an_alloc_irq (device_t, int, int);
503 int an_pci_probe (device_t);
504 int an_probe (device_t);
505 int an_shutdown (device_t);
506 void an_resume (device_t);
507 int an_attach (struct an_softc *, int);
508 int an_detach (device_t);
509 void an_stop (struct an_softc *);
511 driver_intr_t an_intr;
513 #define AN_802_3_OFFSET 0x2E
514 #define AN_802_11_OFFSET 0x44
515 #define AN_802_11_OFFSET_RAW 0x3C
517 #define AN_STAT_BADCRC 0x0001
518 #define AN_STAT_UNDECRYPTABLE 0x0002
519 #define AN_STAT_ERRSTAT 0x0003
520 #define AN_STAT_MAC_PORT 0x0700
521 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */
522 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
523 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
524 #define AN_RXSTAT_MSG_TYPE 0xE000
526 #define AN_ENC_TX_802_3 0x00
527 #define AN_ENC_TX_802_11 0x11
528 #define AN_ENC_TX_E_II 0x0E
530 #define AN_ENC_TX_1042 0x00
531 #define AN_ENC_TX_TUNNEL 0xF8
533 #define AN_TXCNTL_MACPORT 0x00FF
534 #define AN_TXCNTL_STRUCTTYPE 0xFF00
537 * SNAP (sub-network access protocol) constants for transmission
538 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
539 * We need these for the LLC/SNAP header fields in the TX/RX frame
542 #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
543 #define AN_SNAP_K2 0x00
544 #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
545 #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
546 #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
547 #define AN_SNAPHDR_LEN 0x6