2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
65 #include <netgraph/ng_message.h>
66 #include <netgraph/netgraph.h>
67 #include <sys/syslog.h>
68 #include <dev/ar/if_ar.h>
70 #include <net/if_sppp.h>
71 #include <net/if_types.h>
75 #include <machine/md_var.h>
77 #include <dev/ic/hd64570.h>
78 #include <dev/ar/if_arregs.h>
88 #define PPP_HEADER_LEN 4
90 devclass_t ar_devclass;
96 int unit; /* With regards to all ar devices */
97 int subunit; /* With regards to this card */
101 u_int txdesc; /* On card address */
102 u_int txstart; /* On card address */
103 u_int txend; /* On card address */
104 u_int txtail; /* Index of first unused buffer */
105 u_int txmax; /* number of usable buffers/descriptors */
106 u_int txeda; /* Error descriptor addresses */
107 }block[AR_TX_BLOCKS];
109 char xmit_busy; /* Transmitter is busy */
110 char txb_inuse; /* Number of tx blocks currently in use */
111 u_char txb_new; /* Index to where new buffer will be added */
112 u_char txb_next_tx; /* Index to next block ready to tx */
114 u_int rxdesc; /* On card address */
115 u_int rxstart; /* On card address */
116 u_int rxend; /* On card address */
117 u_int rxhind; /* Index to the head of the rx buffers. */
118 u_int rxmax; /* number of usable buffers/descriptors */
124 int running; /* something is attached so we are running */
125 int dcd; /* do we have dcd? */
126 /* ---netgraph bits --- */
127 char nodename[NG_NODESIZ]; /* store our node name */
128 int datahooks; /* number of data hooks attached */
129 node_p node; /* netgraph node */
130 hook_p hook; /* data hook */
132 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
133 struct ifqueue xmitq; /* transmit queue */
134 int flags; /* state */
135 #define SCF_RUNNING 0x01 /* board is active */
136 #define SCF_OACTIVE 0x02 /* output is active */
137 int out_dog; /* watchdog cycles output count-down */
138 struct callout_handle handle; /* timeout(9) handle */
139 u_long inbytes, outbytes; /* stats */
140 u_long lastinbytes, lastoutbytes; /* a second ago */
141 u_long inrate, outrate; /* highest rate seen */
142 u_long inlast; /* last input N secs ago */
143 u_long out_deficit; /* output since last input */
144 u_long oerrors, ierrors[6];
145 u_long opackets, ipackets;
146 #endif /* NETGRAPH */
148 #define SC2IFP(sc) (sc)->ifp
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
187 static void arintr(void *arg);
188 static void ar_xmit(struct ar_softc *sc);
190 static void arstart(struct ifnet *ifp);
191 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
192 static void arwatchdog(struct ifnet *ifp);
194 static void arstart(struct ar_softc *sc);
195 static void arwatchdog(struct ar_softc *sc);
196 #endif /* NETGRAPH */
197 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
198 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
199 static void ar_eat_packet(struct ar_softc *sc, int single);
200 static void ar_get_packets(struct ar_softc *sc);
202 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
203 static void ar_up(struct ar_softc *sc);
204 static void ar_down(struct ar_softc *sc);
205 static void arc_init(struct ar_hardc *hc);
206 static void ar_init_sca(struct ar_hardc *hc, int scano);
207 static void ar_init_msci(struct ar_softc *sc);
208 static void ar_init_rx_dmac(struct ar_softc *sc);
209 static void ar_init_tx_dmac(struct ar_softc *sc);
210 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
211 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
212 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
215 static void ngar_watchdog_frame(void * arg);
217 static ng_constructor_t ngar_constructor;
218 static ng_rcvmsg_t ngar_rcvmsg;
219 static ng_shutdown_t ngar_shutdown;
220 static ng_newhook_t ngar_newhook;
221 /*static ng_findhook_t ngar_findhook; */
222 static ng_connect_t ngar_connect;
223 static ng_rcvdata_t ngar_rcvdata;
224 static ng_disconnect_t ngar_disconnect;
226 static struct ng_type typestruct = {
227 .version = NG_ABI_VERSION,
228 .name = NG_AR_NODE_TYPE,
229 .constructor = ngar_constructor,
230 .rcvmsg = ngar_rcvmsg,
231 .shutdown = ngar_shutdown,
232 .newhook = ngar_newhook,
233 .connect = ngar_connect,
234 .rcvdata = ngar_rcvdata,
235 .disconnect = ngar_disconnect,
237 NETGRAPH_INIT_ORDERED(sync_ar, &typestruct, SI_SUB_DRIVERS, SI_ORDER_FIRST);
238 #endif /* NETGRAPH */
241 ar_attach(device_t device)
248 #endif /* NETGRAPH */
251 hc = (struct ar_hardc *)device_get_softc(device);
253 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
261 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
262 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0)
267 for(unit=0;unit<hc->numports;unit+=NCHAN)
268 ar_init_sca(hc, unit / NCHAN);
271 * Now configure each port on the card.
273 for(unit=0;unit<hc->numports;sc++,unit++) {
276 sc->unit = next_ar_unit;
278 sc->scano = unit / NCHAN;
279 sc->scachan = unit%NCHAN;
286 ifp = SC2IFP(sc) = if_alloc(IFT_PPP);
288 if (BUS_TEARDOWN_INTR(device_get_parent(device), device,
289 hc->res_irq, hc->intr_cookie) != 0) {
290 printf("intr teardown failed.. continuing\n");
296 if_initname(ifp, device_get_name(device),
297 device_get_unit(device));
298 ifp->if_mtu = PP_MTU;
299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST |
301 ifp->if_ioctl = arioctl;
302 ifp->if_start = arstart;
303 ifp->if_watchdog = arwatchdog;
305 IFP2SP(sc->ifp)->pp_flags = PP_KEEPALIVE;
307 switch(hc->interface[unit]) {
308 default: iface = "UNKNOWN"; break;
309 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
310 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
311 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
312 case AR_IFACE_X_21: iface = "X.21"; break;
313 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
316 printf("ar%d: Adapter %d, port %d, interface %s.\n",
322 sppp_attach(SC2IFP(sc));
325 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
327 if (ng_make_node_common(&typestruct, &sc->node) != 0)
329 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
330 if (ng_name_node(sc->node, sc->nodename)) {
331 NG_NODE_UNREF(sc->node); /* drop it again */
334 NG_NODE_SET_PRIVATE(sc->node, sc);
335 callout_handle_init(&sc->handle);
336 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
337 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
338 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF);
339 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL,
342 #endif /* NETGRAPH */
345 if(hc->bustype == AR_BUS_ISA)
352 ar_detach(device_t device)
354 device_t parent = device_get_parent(device);
355 struct ar_hardc *hc = device_get_softc(device);
357 if (hc->intr_cookie != NULL) {
358 if (BUS_TEARDOWN_INTR(parent, device,
359 hc->res_irq, hc->intr_cookie) != 0) {
360 printf("intr teardown failed.. continuing\n");
362 hc->intr_cookie = NULL;
366 * deallocate any system resources we may have
367 * allocated on behalf of this driver.
369 FREE(hc->sc, M_DEVBUF);
371 hc->mem_start = NULL;
372 return (ar_deallocate_resources(device));
376 ar_allocate_ioport(device_t device, int rid, u_long size)
378 struct ar_hardc *hc = device_get_softc(device);
380 hc->rid_ioport = rid;
381 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
382 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
383 if (hc->res_ioport == NULL) {
386 hc->bt = rman_get_bustag(hc->res_ioport);
387 hc->bh = rman_get_bushandle(hc->res_ioport);
392 ar_deallocate_resources(device);
397 ar_allocate_irq(device_t device, int rid, u_long size)
399 struct ar_hardc *hc = device_get_softc(device);
402 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
403 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
404 if (hc->res_irq == NULL) {
410 ar_deallocate_resources(device);
415 ar_allocate_memory(device_t device, int rid, u_long size)
417 struct ar_hardc *hc = device_get_softc(device);
419 hc->rid_memory = rid;
420 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
421 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
422 if (hc->res_memory == NULL) {
428 ar_deallocate_resources(device);
433 ar_allocate_plx_memory(device_t device, int rid, u_long size)
435 struct ar_hardc *hc = device_get_softc(device);
437 hc->rid_plx_memory = rid;
438 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
439 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
440 if (hc->res_plx_memory == NULL) {
446 ar_deallocate_resources(device);
451 ar_deallocate_resources(device_t device)
453 struct ar_hardc *hc = device_get_softc(device);
455 if (hc->res_irq != 0) {
456 bus_deactivate_resource(device, SYS_RES_IRQ,
457 hc->rid_irq, hc->res_irq);
458 bus_release_resource(device, SYS_RES_IRQ,
459 hc->rid_irq, hc->res_irq);
462 if (hc->res_ioport != 0) {
463 bus_deactivate_resource(device, SYS_RES_IOPORT,
464 hc->rid_ioport, hc->res_ioport);
465 bus_release_resource(device, SYS_RES_IOPORT,
466 hc->rid_ioport, hc->res_ioport);
469 if (hc->res_memory != 0) {
470 bus_deactivate_resource(device, SYS_RES_MEMORY,
471 hc->rid_memory, hc->res_memory);
472 bus_release_resource(device, SYS_RES_MEMORY,
473 hc->rid_memory, hc->res_memory);
476 if (hc->res_plx_memory != 0) {
477 bus_deactivate_resource(device, SYS_RES_MEMORY,
478 hc->rid_plx_memory, hc->res_plx_memory);
479 bus_release_resource(device, SYS_RES_MEMORY,
480 hc->rid_plx_memory, hc->res_plx_memory);
481 hc->res_plx_memory = 0;
487 * First figure out which SCA gave the interrupt.
489 * See if there is other interrupts pending.
490 * Repeat until there is no more interrupts.
495 struct ar_hardc *hc = (struct ar_hardc *)arg;
497 u_char isr0, isr1, isr2, arisr;
500 /* XXX Use the PCI interrupt score board register later */
501 if(hc->bustype == AR_BUS_PCI)
502 arisr = hc->orbase[AR_ISTAT * 4];
504 arisr = ar_inb(hc, AR_ISTAT);
506 while(arisr & AR_BD_INT) {
507 TRC(printf("arisr = %x\n", arisr));
510 else if(arisr & AR_INT_1)
513 /* XXX Oops this shouldn't happen. */
514 printf("arc%d: Interrupted with no interrupt.\n",
518 sca = hc->sca[scano];
520 if(hc->bustype == AR_BUS_ISA)
521 ARC_SET_SCA(hc, scano);
527 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
533 ar_msci_intr(hc, scano, isr0);
536 ar_dmac_intr(hc, scano, isr1);
539 ar_timer_intr(hc, scano, isr2);
542 * Proccess the second sca's interrupt if available.
543 * Else see if there are any new interrupts.
545 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
548 if(hc->bustype == AR_BUS_PCI)
549 arisr = hc->orbase[AR_ISTAT * 4];
551 arisr = ar_inb(hc, AR_ISTAT);
555 if(hc->bustype == AR_BUS_ISA)
561 * This will only start the transmitter. It is assumed that the data
562 * is already there. It is normally called from arstart() or ar_dmac_intr().
566 ar_xmit(struct ar_softc *sc)
570 #endif /* NETGRAPH */
575 #endif /* NETGRAPH */
576 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
578 if(sc->hc->bustype == AR_BUS_ISA)
579 ARC_SET_SCA(sc->hc, sc->scano);
580 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
582 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
583 dmac->dsr = SCA_DSR_DE;
588 if(sc->txb_next_tx == AR_TX_BLOCKS)
592 ifp->if_timer = 2; /* Value in seconds. */
594 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
595 #endif /* NETGRAPH */
596 if(sc->hc->bustype == AR_BUS_ISA)
601 * This function will be called from the upper level when a user add a
602 * packet to be send, and from the interrupt handler after a finished
605 * NOTE: it should run at spl_imp().
607 * This function only place the data in the oncard buffers. It does not
608 * start the transmition. ar_xmit() does that.
610 * Transmitter idle state is indicated by the IFF_DRV_OACTIVE flag. The
611 * function that clears that should ensure that the transmitter and its
612 * DMA is in a "good" idle state.
616 arstart(struct ifnet *ifp)
618 struct ar_softc *sc = ifp->if_softc;
621 arstart(struct ar_softc *sc)
623 #endif /* NETGRAPH */
627 sca_descriptor *txdesc;
628 struct buf_block *blkp;
631 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING))
635 #endif /* NETGRAPH */
640 * See if we have space for more packets.
642 if(sc->txb_inuse == AR_TX_BLOCKS) {
644 ifp->if_drv_flags |= IFF_DRV_OACTIVE; /* yes, mark active */
646 /*XXX*/ /*ifp->if_drv_flags |= IFF_DRV_OACTIVE;*/ /* yes, mark active */
647 #endif /* NETGRAPH */
652 mtx = sppp_dequeue(ifp);
654 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
656 IF_DEQUEUE(&sc->xmitq, mtx);
658 #endif /* NETGRAPH */
663 * It is OK to set the memory window outside the loop because
664 * all tx buffers and descriptors are assumed to be in the same
667 if(sc->hc->bustype == AR_BUS_ISA)
668 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
671 * We stay in this loop until there is nothing in the
672 * TX queue left or the tx buffer is full.
675 blkp = &sc->block[sc->txb_new];
676 txdesc = (sca_descriptor *)
677 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
678 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
680 len = mtx->m_pkthdr.len;
682 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
685 * We can do this because the tx buffers don't wrap.
687 m_copydata(mtx, 0, len, txdata);
689 while(tlen > AR_BUF_SIZ) {
691 txdesc->len = AR_BUF_SIZ;
694 txdata += AR_BUF_SIZ;
697 /* XXX Move into the loop? */
698 txdesc->stat = SCA_DESC_EOM;
701 txdata += AR_BUF_SIZ;
707 ++SC2IFP(sc)->if_opackets;
712 #endif /* NETGRAPH */
715 * Check if we have space for another mbuf.
716 * XXX This is hardcoded. A packet won't be larger
717 * than 3 buffers (3 x 512).
719 if((i + 3) >= blkp->txmax)
723 mtx = sppp_dequeue(ifp);
725 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
727 IF_DEQUEUE(&sc->xmitq, mtx);
729 #endif /* NETGRAPH */
737 * Mark the last descriptor, so that the SCA know where
741 txdesc->stat |= SCA_DESC_EOT;
743 txdesc = (sca_descriptor *)blkp->txdesc;
744 blkp->txeda = (u_short)((u_int)&txdesc[i]);
747 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
748 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
749 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
750 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
751 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
756 if(sc->txb_new == AR_TX_BLOCKS)
759 if(sc->xmit_busy == 0)
762 if(sc->hc->bustype == AR_BUS_ISA)
770 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
773 int was_up, should_be_up;
774 struct ar_softc *sc = ifp->if_softc;
776 TRC(if_printf(ifp, "arioctl.\n");)
778 was_up = ifp->if_drv_flags & IFF_DRV_RUNNING;
780 error = sppp_ioctl(ifp, cmd, data);
781 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
782 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
786 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
789 TRC(if_printf(ifp, "arioctl %s.\n",
790 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
793 should_be_up = ifp->if_drv_flags & IFF_DRV_RUNNING;
795 if(!was_up && should_be_up) {
796 /* Interface should be up -- start it. */
799 /* XXX Maybe clear the IFF_UP flag so that the link
800 * will only go up after sppp lcp and ipcp negotiation.
802 } else if(was_up && !should_be_up) {
803 /* Interface should be down -- stop it. */
810 #endif /* NETGRAPH */
813 * This is to catch lost tx interrupts.
817 arwatchdog(struct ifnet *ifp)
819 struct ar_softc *sc = ifp->if_softc;
821 arwatchdog(struct ar_softc *sc)
823 #endif /* NETGRAPH */
824 msci_channel *msci = &sc->sca->msci[sc->scachan];
827 if(!(ifp->if_drv_flags & IFF_DRV_RUNNING))
829 #endif /* NETGRAPH */
831 if(sc->hc->bustype == AR_BUS_ISA)
832 ARC_SET_SCA(sc->hc, sc->scano);
834 /* XXX if(SC2IFP(sc)->if_flags & IFF_DEBUG) */
835 printf("ar%d: transmit failed, "
836 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
841 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
843 if(msci->st1 & SCA_ST1_UDRN) {
844 msci->cmd = SCA_CMD_TXABORT;
845 msci->cmd = SCA_CMD_TXENABLE;
846 msci->st1 = SCA_ST1_UDRN;
851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
853 /* XXX ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; */
854 #endif /* NETGRAPH */
856 if(sc->txb_inuse && --sc->txb_inuse)
863 #endif /* NETGRAPH */
867 ar_up(struct ar_softc *sc)
873 msci = &sca->msci[sc->scachan];
875 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
876 sc->unit, sca, msci, sc->scachan));
879 * Enable transmitter and receiver.
883 if(sc->hc->bustype == AR_BUS_ISA)
884 ARC_SET_SCA(sc->hc, sc->scano);
887 * What about using AUTO mode in msci->md0 ???
888 * And what about CTS/DCD etc... ?
890 if(sc->hc->handshake & AR_SHSK_RTS)
891 msci->ctl &= ~SCA_CTL_RTS;
892 if(sc->hc->handshake & AR_SHSK_DTR) {
893 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
894 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
895 if(sc->hc->bustype == AR_BUS_PCI)
896 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
897 sc->hc->txc_dtr[sc->scano];
899 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
900 sc->hc->txc_dtr[sc->scano]);
903 if(sc->scachan == 0) {
911 msci->cmd = SCA_CMD_RXENABLE;
912 if(sc->hc->bustype == AR_BUS_ISA)
913 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
914 msci->cmd = SCA_CMD_TXENABLE;
916 if(sc->hc->bustype == AR_BUS_ISA)
919 untimeout(ngar_watchdog_frame, sc, sc->handle);
920 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
922 #endif /* NETGRAPH */
926 ar_down(struct ar_softc *sc)
932 msci = &sca->msci[sc->scachan];
935 untimeout(ngar_watchdog_frame, sc, sc->handle);
937 #endif /* NETGRAPH */
939 * Disable transmitter and receiver.
941 * Disable interrupts.
943 if(sc->hc->bustype == AR_BUS_ISA)
944 ARC_SET_SCA(sc->hc, sc->scano);
945 msci->cmd = SCA_CMD_RXDISABLE;
946 if(sc->hc->bustype == AR_BUS_ISA)
947 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
948 msci->cmd = SCA_CMD_TXDISABLE;
950 if(sc->hc->handshake & AR_SHSK_RTS)
951 msci->ctl |= SCA_CTL_RTS;
952 if(sc->hc->handshake & AR_SHSK_DTR) {
953 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
954 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
955 if(sc->hc->bustype == AR_BUS_PCI)
956 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
957 sc->hc->txc_dtr[sc->scano];
959 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
960 sc->hc->txc_dtr[sc->scano]);
963 if(sc->scachan == 0) {
971 if(sc->hc->bustype == AR_BUS_ISA)
976 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
978 int ctype, i, val, x;
979 volatile u_char *pimctrl;
984 pimctrl = hc->orbase + AR_PIMCTRL;
988 *pimctrl = AR_PIM_STROBE;
990 /* Check if there is a PIM */
992 *pimctrl = AR_PIM_READ;
994 TRC(printf("x = %x", x));
995 if(x & AR_PIM_DATA) {
996 printf("No PIM installed\n");
997 return (AR_IFACE_UNKNOWN);
1000 x = (x >> 1) & 0x01;
1003 /* Now read the next 15 bits */
1004 for(i = 1; i < 16; i++) {
1005 *pimctrl = AR_PIM_READ;
1006 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1008 TRC(printf(" %x ", x));
1009 x = (x >> 1) & 0x01;
1011 if(i == 8 && (val & 0x000f) == 0x0004) {
1015 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1016 *pimctrl = AR_PIM_A2D_DOUT;
1019 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1020 *pimctrl = AR_PIM_A2D_DOUT;
1023 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1024 *pimctrl = AR_PIM_A2D_DOUT;
1026 /* Select channel */
1027 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1028 *pimctrl = ((channel & 2) << 2);
1029 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1030 *pimctrl = ((channel & 1) << 3);
1032 *pimctrl = AR_PIM_A2D_STROBE;
1036 printf("\nOops A2D start bit not zero (%X)\n", x);
1038 for(ii = 7; ii >= 0; ii--) {
1040 *pimctrl = AR_PIM_A2D_STROBE;
1047 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1048 *pimctrl = AR_PIM_MODEG;
1049 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1051 return (AR_IFACE_UNKNOWN);
1053 return (AR_IFACE_V_35);
1055 return (AR_IFACE_EIA_232);
1057 return (AR_IFACE_X_21);
1059 return (AR_IFACE_EIA_530);
1061 return (AR_IFACE_UNKNOWN);
1063 return (AR_IFACE_LOOPBACK);
1064 return (AR_IFACE_UNKNOWN);
1068 * Initialize the card, allocate memory for the ar_softc structures
1069 * and fill in the pointers.
1072 arc_init(struct ar_hardc *hc)
1074 struct ar_softc *sc;
1083 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1084 M_DEVBUF, M_WAITOK | M_ZERO);
1089 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1090 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1091 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1092 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1093 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1094 if(hc->bustype == AR_BUS_PCI) {
1095 hc->txc_dtr_off[0] *= 4;
1096 hc->txc_dtr_off[1] *= 4;
1100 * reset the card and wait at least 1uS.
1102 if(hc->bustype == AR_BUS_PCI)
1103 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1106 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1109 if(hc->bustype == AR_BUS_PCI)
1110 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1112 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1114 if(hc->bustype == AR_BUS_ISA) {
1116 * Configure the card.
1119 memst = rman_get_start(hc->res_memory);
1121 isr = irqtable[hc->isa_irq] << 1;
1123 printf("ar%d: Warning illegal interrupt %d\n",
1124 hc->cunit, hc->isa_irq);
1125 isr = isr | ((memst & 0xc000) >> 10);
1127 hc->sca[0] = (sca_regs *)hc->mem_start;
1128 hc->sca[1] = (sca_regs *)hc->mem_start;
1130 ar_outb(hc, AR_MEM_SEL, mar);
1131 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1134 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1135 for(x = 0; x < hc->numports; x++)
1136 hc->interface[x] = ar_read_pim_iface(hc, x);
1139 * Set the TX clock direction and enable TX.
1141 for(x=0;x<hc->numports;x++) {
1142 switch(hc->interface[x]) {
1144 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1145 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1146 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1147 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1149 case AR_IFACE_EIA_530:
1150 case AR_IFACE_COMBO:
1152 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1153 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1158 if(hc->bustype == AR_BUS_PCI)
1159 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1161 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1162 if(hc->numports > NCHAN) {
1163 if(hc->bustype == AR_BUS_PCI)
1164 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1166 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1169 chanmem = hc->memsize / hc->numports;
1172 for(x=0;x<hc->numports;x++, sc++) {
1175 sc->sca = hc->sca[x / NCHAN];
1177 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1178 sc->block[blk].txdesc = next;
1179 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1180 descneeded = bufmem / AR_BUF_SIZ;
1181 sc->block[blk].txstart = sc->block[blk].txdesc +
1182 ((((descneeded * sizeof(sca_descriptor)) /
1183 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1184 sc->block[blk].txend = next + bufmem;
1185 sc->block[blk].txmax =
1186 (sc->block[blk].txend - sc->block[blk].txstart)
1190 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1191 "txend %x, txmax %d\n",
1194 sc->block[blk].txdesc,
1195 sc->block[blk].txstart,
1196 sc->block[blk].txend,
1197 sc->block[blk].txmax));
1201 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1202 descneeded = bufmem / AR_BUF_SIZ;
1203 sc->rxstart = sc->rxdesc +
1204 ((((descneeded * sizeof(sca_descriptor)) /
1205 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1206 sc->rxend = next + bufmem;
1207 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1209 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1210 "rxend %x, rxmax %d\n",
1211 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1214 if(hc->bustype == AR_BUS_PCI)
1215 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1220 * The things done here are channel independent.
1222 * Configure the sca waitstates.
1223 * Configure the global interrupt registers.
1224 * Enable master dma enable.
1227 ar_init_sca(struct ar_hardc *hc, int scano)
1231 sca = hc->sca[scano];
1232 if(hc->bustype == AR_BUS_ISA)
1233 ARC_SET_SCA(hc, scano);
1236 * Do the wait registers.
1237 * Set everything to 0 wait states.
1246 * Configure the interrupt registers.
1247 * Most are cleared until the interface is configured.
1249 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1250 sca->ier1 = 0x00; /* DMAC interrupts */
1251 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1252 sca->itcr = 0x00; /* Use ivr and no intr ack */
1253 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1257 * Configure the timers.
1263 * Set the DMA channel priority to rotate between
1264 * all four channels.
1266 * Enable all dma channels.
1268 if(hc->bustype == AR_BUS_PCI) {
1272 * Stupid problem with the PCI interface chip that break
1277 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1278 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1280 sca->pcr = SCA_PCR_PR2;
1281 sca->dmer = SCA_DMER_EN;
1287 * Configure the msci
1289 * NOTE: The serial port configuration is hardcoded at the moment.
1292 ar_init_msci(struct ar_softc *sc)
1296 msci = &sc->sca->msci[sc->scachan];
1298 if(sc->hc->bustype == AR_BUS_ISA)
1299 ARC_SET_SCA(sc->hc, sc->scano);
1301 msci->cmd = SCA_CMD_RESET;
1303 msci->md0 = SCA_MD0_CRC_1 |
1305 SCA_MD0_CRC_ENABLE |
1307 msci->md1 = SCA_MD1_NOADDRCHK;
1308 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1311 * Acording to the manual I should give a reset after changing the
1314 msci->cmd = SCA_CMD_RXRESET;
1315 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1318 * For now all interfaces are programmed to use the RX clock for
1321 switch(sc->hc->interface[sc->subunit]) {
1323 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1324 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1327 case AR_IFACE_EIA_530:
1328 case AR_IFACE_COMBO:
1329 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1330 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1333 msci->tmc = 153; /* This give 64k for loopback */
1336 * Disable all interrupts for now. I think if you are using
1337 * the dmac you don't use these interrupts.
1340 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1347 msci->idl = 0x7E; /* XXX This is what cisco does. */
1350 * This is what the ARNET diags use.
1358 * Configure the rx dma controller.
1361 ar_init_rx_dmac(struct ar_softc *sc)
1364 sca_descriptor *rxd;
1370 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1372 if(sc->hc->bustype == AR_BUS_ISA)
1373 ARC_SET_MEM(sc->hc, sc->rxdesc);
1375 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1376 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1378 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1379 rxda = (u_int)&rxd[1] - rxda_d;
1380 rxd->cp = (u_short)(rxda & 0xfffful);
1384 TRC(printf("Descrp %p, data pt %x, data %x, ",
1387 rxd->bp = (u_short)(rxbuf & 0xfffful);
1388 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1390 rxd->stat = 0xff; /* The sca write here when it is finished. */
1393 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1396 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1400 if(sc->hc->bustype == AR_BUS_ISA)
1401 ARC_SET_SCA(sc->hc, sc->scano);
1403 dmac->dsr = 0; /* Disable DMA transfer */
1404 dmac->dcr = SCA_DCR_ABRT;
1406 /* XXX maybe also SCA_DMR_CNTE */
1407 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1408 dmac->bfl = AR_BUF_SIZ;
1410 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1411 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1413 rxd = (sca_descriptor *)sc->rxstart;
1414 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1418 dmac->dsr = SCA_DSR_DE;
1422 * Configure the TX DMA descriptors.
1423 * Initialize the needed values and chain the descriptors.
1426 ar_init_tx_dmac(struct ar_softc *sc)
1429 struct buf_block *blkp;
1431 sca_descriptor *txd;
1436 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1438 if(sc->hc->bustype == AR_BUS_ISA)
1439 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1441 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1442 blkp = &sc->block[blk];
1443 txd = (sca_descriptor *)(sc->hc->mem_start +
1444 (blkp->txdesc&sc->hc->winmsk));
1445 txda_d = (u_int)sc->hc->mem_start -
1446 (blkp->txdesc & ~sc->hc->winmsk);
1448 txbuf=blkp->txstart;
1449 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1450 txda = (u_int)&txd[1] - txda_d;
1451 txd->cp = (u_short)(txda & 0xfffful);
1453 txd->bp = (u_short)(txbuf & 0xfffful);
1454 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1455 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1456 sc->unit, txbuf, txd->bpb, txd->bp));
1461 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1463 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1464 TRC(printf("TX Descriptors start %x, end %x.\n",
1469 if(sc->hc->bustype == AR_BUS_ISA)
1470 ARC_SET_SCA(sc->hc, sc->scano);
1472 dmac->dsr = 0; /* Disable DMA */
1473 dmac->dcr = SCA_DCR_ABRT;
1474 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1475 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1477 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1482 * Look through the descriptors to see if there is a complete packet
1483 * available. Stop if we get to where the sca is busy.
1485 * Return the length and status of the packet.
1486 * Return nonzero if there is a packet available.
1489 * It seems that we get the interrupt a bit early. The updateing of
1490 * descriptor values is not always completed when this is called.
1493 ar_packet_avail(struct ar_softc *sc,
1498 sca_descriptor *rxdesc;
1499 sca_descriptor *endp;
1500 sca_descriptor *cda;
1502 if(sc->hc->bustype == AR_BUS_ISA)
1503 ARC_SET_SCA(sc->hc, sc->scano);
1504 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1505 cda = (sca_descriptor *)(sc->hc->mem_start +
1506 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1508 if(sc->hc->bustype == AR_BUS_ISA)
1509 ARC_SET_MEM(sc->hc, sc->rxdesc);
1510 rxdesc = (sca_descriptor *)
1511 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1513 rxdesc = &rxdesc[sc->rxhind];
1514 endp = &endp[sc->rxmax];
1518 while(rxdesc != cda) {
1519 *len += rxdesc->len;
1521 if(rxdesc->stat & SCA_DESC_EOM) {
1522 *rxstat = rxdesc->stat;
1523 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1524 sc->unit, *len, *rxstat));
1530 rxdesc = (sca_descriptor *)
1531 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1541 * Copy a packet from the on card memory into a provided mbuf.
1542 * Take into account that buffers wrap and that a packet may
1543 * be larger than a buffer.
1546 ar_copy_rxbuf(struct mbuf *m,
1547 struct ar_softc *sc,
1550 sca_descriptor *rxdesc;
1556 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1557 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1559 rxdesc = (sca_descriptor *)
1560 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1561 rxdesc = &rxdesc[sc->rxhind];
1564 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1565 if(sc->hc->bustype == AR_BUS_ISA)
1566 ARC_SET_MEM(sc->hc, rxdata);
1567 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1568 mtod(m, caddr_t) + off,
1574 if(sc->hc->bustype == AR_BUS_ISA)
1575 ARC_SET_MEM(sc->hc, sc->rxdesc);
1577 rxdesc->stat = 0xff;
1579 rxdata += AR_BUF_SIZ;
1581 if(rxdata == rxmax) {
1582 rxdata = sc->rxstart;
1583 rxdesc = (sca_descriptor *)
1584 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1590 * If single is set, just eat a packet. Otherwise eat everything up to
1591 * where cda points. Update pointers to point to the next packet.
1594 ar_eat_packet(struct ar_softc *sc, int single)
1597 sca_descriptor *rxdesc;
1598 sca_descriptor *endp;
1599 sca_descriptor *cda;
1603 if(sc->hc->bustype == AR_BUS_ISA)
1604 ARC_SET_SCA(sc->hc, sc->scano);
1605 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1606 cda = (sca_descriptor *)(sc->hc->mem_start +
1607 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1610 * Loop until desc->stat == (0xff || EOM)
1611 * Clear the status and length in the descriptor.
1612 * Increment the descriptor.
1614 if(sc->hc->bustype == AR_BUS_ISA)
1615 ARC_SET_MEM(sc->hc, sc->rxdesc);
1616 rxdesc = (sca_descriptor *)
1617 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1619 rxdesc = &rxdesc[sc->rxhind];
1620 endp = &endp[sc->rxmax];
1622 while(rxdesc != cda) {
1624 if(loopcnt > sc->rxmax) {
1625 printf("ar%d: eat pkt %d loop, cda %p, "
1626 "rxdesc %p, stat %x.\n",
1635 stat = rxdesc->stat;
1638 rxdesc->stat = 0xff;
1642 if(rxdesc == endp) {
1643 rxdesc = (sca_descriptor *)
1644 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1648 if(single && (stat == SCA_DESC_EOM))
1653 * Update the eda to the previous descriptor.
1655 if(sc->hc->bustype == AR_BUS_ISA)
1656 ARC_SET_SCA(sc->hc, sc->scano);
1658 rxdesc = (sca_descriptor *)sc->rxdesc;
1659 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1661 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1662 (u_short)((u_int)rxdesc & 0xffff);
1667 * While there is packets available in the rx buffer, read them out
1668 * into mbufs and ship them off.
1671 ar_get_packets(struct ar_softc *sc)
1673 sca_descriptor *rxdesc;
1674 struct mbuf *m = NULL;
1682 while(ar_packet_avail(sc, &len, &rxstat)) {
1683 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1684 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1685 MGETHDR(m, M_DONTWAIT, MT_DATA);
1687 /* eat packet if get mbuf fail!! */
1688 ar_eat_packet(sc, 1);
1692 m->m_pkthdr.rcvif = SC2IFP(sc);
1693 #else /* NETGRAPH */
1694 m->m_pkthdr.rcvif = NULL;
1697 #endif /* NETGRAPH */
1698 m->m_pkthdr.len = m->m_len = len;
1700 MCLGET(m, M_DONTWAIT);
1701 if((m->m_flags & M_EXT) == 0) {
1703 ar_eat_packet(sc, 1);
1707 ar_copy_rxbuf(m, sc, len);
1709 BPF_MTAP(SC2IFP(sc), m);
1710 sppp_input(SC2IFP(sc), m);
1711 SC2IFP(sc)->if_ipackets++;
1712 #else /* NETGRAPH */
1713 NG_SEND_DATA_ONLY(error, sc->hook, m);
1715 #endif /* NETGRAPH */
1718 * Update the eda to the previous descriptor.
1720 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1721 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1723 if(sc->hc->bustype == AR_BUS_ISA)
1724 ARC_SET_SCA(sc->hc, sc->scano);
1726 rxdesc = (sca_descriptor *)sc->rxdesc;
1728 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1730 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1731 (u_short)((u_int)rxdesc & 0xffff);
1735 while((rxstat == 0xff) && --tries)
1736 ar_packet_avail(sc, &len, &rxstat);
1739 * It look like we get an interrupt early
1740 * sometimes and then the status is not
1743 if(tries && (tries != 5))
1746 ar_eat_packet(sc, 1);
1749 SC2IFP(sc)->if_ierrors++;
1750 #else /* NETGRAPH */
1752 #endif /* NETGRAPH */
1754 if(sc->hc->bustype == AR_BUS_ISA)
1755 ARC_SET_SCA(sc->hc, sc->scano);
1757 TRCL(printf("ar%d: Receive error chan %d, "
1758 "stat %x, msci st3 %x,"
1759 "rxhind %d, cda %x, eda %x.\n",
1763 sc->sca->msci[sc->scachan].st3,
1766 DMAC_RXCH(sc->scachan)].cda,
1768 DMAC_RXCH(sc->scachan)].eda));
1775 * All DMA interrupts come here.
1777 * Each channel has two interrupts.
1778 * Interrupt A for errors and Interrupt B for normal stuff like end
1779 * of transmit or receive dmas.
1782 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1785 u_char dotxstart = isr1;
1787 struct ar_softc *sc;
1791 sca = hc->sca[scano];
1794 * Shortcut if there is no interrupts for dma channel 0 or 1
1796 if((isr1 & 0x0F) == 0) {
1802 sc = &hc->sc[mch + (NCHAN * scano)];
1808 dmac = &sca->dmac[DMAC_TXCH(mch)];
1810 if(hc->bustype == AR_BUS_ISA)
1811 ARC_SET_SCA(hc, scano);
1816 /* Counter overflow */
1817 if(dsr & SCA_DSR_COF) {
1818 printf("ar%d: TX DMA Counter overflow, "
1819 "txpacket no %lu.\n",
1822 SC2IFP(sc)->if_opackets);
1823 SC2IFP(sc)->if_oerrors++;
1824 #else /* NETGRAPH */
1827 #endif /* NETGRAPH */
1830 /* Buffer overflow */
1831 if(dsr & SCA_DSR_BOF) {
1832 printf("ar%d: TX DMA Buffer overflow, "
1833 "txpacket no %lu, dsr %02x, "
1834 "cda %04x, eda %04x.\n",
1837 SC2IFP(sc)->if_opackets,
1838 #else /* NETGRAPH */
1840 #endif /* NETGRAPH */
1845 SC2IFP(sc)->if_oerrors++;
1846 #else /* NETGRAPH */
1848 #endif /* NETGRAPH */
1851 /* End of Transfer */
1852 if(dsr & SCA_DSR_EOT) {
1854 * This should be the most common case.
1856 * Clear the IFF_DRV_OACTIVE flag.
1858 * Call arstart to start a new transmit if
1859 * there is data to transmit.
1863 SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE;
1864 SC2IFP(sc)->if_timer = 0;
1865 #else /* NETGRAPH */
1866 /* XXX SC2IFP(sc)->if_drv_flags &= ~IFF_DRV_OACTIVE; */
1867 sc->out_dog = 0; /* XXX */
1868 #endif /* NETGRAPH */
1870 if(sc->txb_inuse && --sc->txb_inuse)
1879 dmac = &sca->dmac[DMAC_RXCH(mch)];
1881 if(hc->bustype == AR_BUS_ISA)
1882 ARC_SET_SCA(hc, scano);
1887 TRC(printf("AR: RX DSR %x\n", dsr));
1890 if(dsr & SCA_DSR_EOM) {
1891 TRC(int tt = SC2IFP(sc)->if_ipackets;)
1892 TRC(int ind = sc->rxhind;)
1896 #define IPACKETS SC2IFP(sc)->if_ipackets
1897 #else /* NETGRAPH */
1898 #define IPACKETS sc->ipackets
1899 #endif /* NETGRAPH */
1900 TRC(if(tt == IPACKETS) {
1901 sca_descriptor *rxdesc;
1904 if(hc->bustype == AR_BUS_ISA)
1905 ARC_SET_SCA(hc, scano);
1906 printf("AR: RXINTR isr1 %x, dsr %x, "
1907 "no data %d pkts, orxhind %d.\n",
1912 printf("AR: rxdesc %x, rxstart %x, "
1913 "rxend %x, rxhind %d, "
1920 printf("AR: cda %x, eda %x.\n",
1924 if(sc->hc->bustype == AR_BUS_ISA)
1927 rxdesc = (sca_descriptor *)
1928 (sc->hc->mem_start +
1929 (sc->rxdesc & sc->hc->winmsk));
1930 rxdesc = &rxdesc[sc->rxhind];
1931 for(i=0;i<3;i++,rxdesc++)
1932 printf("AR: rxdesc->stat %x, "
1939 /* Counter overflow */
1940 if(dsr & SCA_DSR_COF) {
1941 printf("ar%d: RX DMA Counter overflow, "
1945 SC2IFP(sc)->if_ipackets);
1946 SC2IFP(sc)->if_ierrors++;
1947 #else /* NETGRAPH */
1950 #endif /* NETGRAPH */
1953 /* Buffer overflow */
1954 if(dsr & SCA_DSR_BOF) {
1955 if(hc->bustype == AR_BUS_ISA)
1956 ARC_SET_SCA(hc, scano);
1957 printf("ar%d: RX DMA Buffer overflow, "
1958 "rxpkts %lu, rxind %d, "
1959 "cda %x, eda %x, dsr %x.\n",
1962 SC2IFP(sc)->if_ipackets,
1963 #else /* NETGRAPH */
1965 #endif /* NETGRAPH */
1971 * Make sure we eat as many as possible.
1972 * Then get the system running again.
1974 ar_eat_packet(sc, 0);
1976 SC2IFP(sc)->if_ierrors++;
1977 #else /* NETGRAPH */
1979 #endif /* NETGRAPH */
1980 if(hc->bustype == AR_BUS_ISA)
1981 ARC_SET_SCA(hc, scano);
1982 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1983 dmac->dsr = SCA_DSR_DE;
1985 TRC(printf("ar%d: RX DMA Buffer overflow, "
1986 "rxpkts %lu, rxind %d, "
1987 "cda %x, eda %x, dsr %x. After\n",
1989 SC2IFP(sc)->if_ipackets,
1996 /* End of Transfer */
1997 if(dsr & SCA_DSR_EOT) {
1999 * If this happen, it means that we are
2000 * receiving faster than what the processor
2003 * XXX We should enable the dma again.
2005 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2008 SC2IFP(sc)->if_ipackets);
2009 SC2IFP(sc)->if_ierrors++;
2010 #else /* NETGRAPH */
2013 #endif /* NETGRAPH */
2020 }while((mch<NCHAN) && isr1);
2023 * Now that we have done all the urgent things, see if we
2024 * can fill the transmit buffers.
2026 for(mch = 0; mch < NCHAN; mch++) {
2027 if(dotxstart & 0x0C) {
2028 sc = &hc->sc[mch + (NCHAN * scano)];
2030 arstart(SC2IFP(sc));
2031 #else /* NETGRAPH */
2033 #endif /* NETGRAPH */
2040 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2042 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2046 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2048 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2053 /*****************************************
2054 * Device timeout/watchdog routine.
2055 * called once per second.
2056 * checks to see that if activity was expected, that it hapenned.
2057 * At present we only look to see if expected output was completed.
2060 ngar_watchdog_frame(void * arg)
2062 struct ar_softc * sc = arg;
2066 if(sc->running == 0)
2067 return; /* if we are not running let timeouts die */
2069 * calculate the apparent throughputs
2073 speed = sc->inbytes - sc->lastinbytes;
2074 sc->lastinbytes = sc->inbytes;
2075 if ( sc->inrate < speed )
2077 speed = sc->outbytes - sc->lastoutbytes;
2078 sc->lastoutbytes = sc->outbytes;
2079 if ( sc->outrate < speed )
2080 sc->outrate = speed;
2084 if ((sc->inlast > QUITE_A_WHILE)
2085 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2086 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2090 sc->inlast = sc->out_deficit = 0;
2092 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2093 if (sc->out_dog == 0) {
2094 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2103 sc->inlast = sc->out_deficit = 0;
2108 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2111 /***********************************************************************
2112 * This section contains the methods for the Netgraph interface
2113 ***********************************************************************/
2115 * It is not possible or allowable to create a node of this type.
2116 * If the hardware exists, it will already have created it.
2119 ngar_constructor(node_p node)
2125 * give our ok for a hook to be added...
2126 * If we are not running this should kick the device into life.
2127 * The hook's private info points to our stash of info about that
2131 ngar_newhook(node_p node, hook_p hook, const char *name)
2133 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2136 * check if it's our friend the debug hook
2138 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2139 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2140 sc->debug_hook = hook;
2145 * Check for raw mode hook.
2147 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2150 NG_HOOK_SET_PRIVATE(hook, sc);
2158 * incoming messages.
2159 * Just respond to the generic TEXT_STATUS message
2162 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook)
2164 struct ar_softc * sc;
2165 struct ng_mesg *resp = NULL;
2167 struct ng_mesg *msg;
2169 NGI_GET_MSG(item, msg);
2170 sc = NG_NODE_PRIVATE(node);
2171 switch (msg->header.typecookie) {
2175 case NGM_GENERIC_COOKIE:
2176 switch(msg->header.cmd) {
2177 case NGM_TEXT_STATUS: {
2181 int resplen = sizeof(struct ng_mesg) + 512;
2182 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT);
2188 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2189 "highest rate seen: %ld B/S in, %ld B/S out\n",
2190 sc->inbytes, sc->outbytes,
2191 sc->inrate, sc->outrate);
2192 pos += sprintf(arg + pos,
2193 "%ld output errors\n",
2195 pos += sprintf(arg + pos,
2196 "ierrors = %ld, %ld, %ld, %ld\n",
2202 resp->header.arglen = pos + 1;
2214 /* Take care of synchronous response, if any */
2215 NG_RESPOND_MSG(error, node, item, resp);
2221 * get data from another node and transmit it to the correct channel
2224 ngar_rcvdata(hook_p hook, item_p item)
2228 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2229 struct ifqueue *xmitq_p;
2231 struct ng_tag_prio *ptag;
2236 * data doesn't come in from just anywhere (e.g control hook)
2238 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2244 * Now queue the data for when it can be sent
2246 if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE,
2247 NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) )
2248 xmitq_p = (&sc->xmitq_hipri);
2250 xmitq_p = (&sc->xmitq);
2254 if (_IF_QFULL(xmitq_p)) {
2261 _IF_ENQUEUE(xmitq_p, m);
2269 * It was an error case.
2270 * check if we need to free the mbuf, and then return the error
2277 * do local shutdown processing..
2278 * this node will refuse to go away, unless the hardware says to..
2279 * don't unref the node, or remove our name. just clear our links up.
2282 ngar_shutdown(node_p node)
2284 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2287 NG_NODE_UNREF(node);
2288 /* XXX need to drain the output queues! */
2290 /* The node is dead, long live the node! */
2291 /* stolen from the attach routine */
2292 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2294 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2295 if (ng_name_node(sc->node, sc->nodename)) {
2297 printf("node naming failed\n");
2298 NG_NODE_UNREF(sc->node); /* node dissappears */
2301 NG_NODE_SET_PRIVATE(sc->node, sc);
2306 /* already linked */
2308 ngar_connect(hook_p hook)
2310 /* probably not at splnet, force outward queueing */
2311 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
2312 /* be really amiable and just say "YUP that's OK by me! " */
2317 * notify on hook disconnection (destruction)
2319 * Invalidate the private data associated with this dlci.
2320 * For this type, removal of the last link resets tries to destroy the node.
2321 * As the device still exists, the shutdown method will not actually
2322 * destroy the node, but reset the device and leave it 'fresh' :)
2324 * The node removal code will remove all references except that owned by the
2328 ngar_disconnect(hook_p hook)
2330 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2333 * If it's the data hook, then free resources etc.
2335 if (NG_HOOK_PRIVATE(hook)) {
2338 if (sc->datahooks == 0)
2342 sc->debug_hook = NULL;
2346 #endif /* NETGRAPH */
2349 ********************************* END ************************************