2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <machine/bus_pio.h>
62 #include <machine/bus_memio.h>
67 #include <netgraph/ng_message.h>
68 #include <netgraph/netgraph.h>
69 #include <sys/syslog.h>
70 #include <dev/ar/if_ar.h>
72 #include <net/if_sppp.h>
76 #include <machine/md_var.h>
78 #include <dev/ic/hd64570.h>
79 #include <dev/ar/if_arregs.h>
89 #define PPP_HEADER_LEN 4
91 devclass_t ar_devclass;
97 int unit; /* With regards to all ar devices */
98 int subunit; /* With regards to this card */
102 u_int txdesc; /* On card address */
103 u_int txstart; /* On card address */
104 u_int txend; /* On card address */
105 u_int txtail; /* Index of first unused buffer */
106 u_int txmax; /* number of usable buffers/descriptors */
107 u_int txeda; /* Error descriptor addresses */
108 }block[AR_TX_BLOCKS];
110 char xmit_busy; /* Transmitter is busy */
111 char txb_inuse; /* Number of tx blocks currently in use */
112 u_char txb_new; /* Index to where new buffer will be added */
113 u_char txb_next_tx; /* Index to next block ready to tx */
115 u_int rxdesc; /* On card address */
116 u_int rxstart; /* On card address */
117 u_int rxend; /* On card address */
118 u_int rxhind; /* Index to the head of the rx buffers. */
119 u_int rxmax; /* number of usable buffers/descriptors */
125 int running; /* something is attached so we are running */
126 int dcd; /* do we have dcd? */
127 /* ---netgraph bits --- */
128 char nodename[NG_NODESIZ]; /* store our node name */
129 int datahooks; /* number of data hooks attached */
130 node_p node; /* netgraph node */
131 hook_p hook; /* data hook */
133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
134 struct ifqueue xmitq; /* transmit queue */
135 int flags; /* state */
136 #define SCF_RUNNING 0x01 /* board is active */
137 #define SCF_OACTIVE 0x02 /* output is active */
138 int out_dog; /* watchdog cycles output count-down */
139 struct callout_handle handle; /* timeout(9) handle */
140 u_long inbytes, outbytes; /* stats */
141 u_long lastinbytes, lastoutbytes; /* a second ago */
142 u_long inrate, outrate; /* highest rate seen */
143 u_long inlast; /* last input N secs ago */
144 u_long out_deficit; /* output since last input */
145 u_long oerrors, ierrors[6];
146 u_long opackets, ipackets;
147 #endif /* NETGRAPH */
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
186 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
189 static void arintr(void *arg);
190 static void ar_xmit(struct ar_softc *sc);
192 static void arstart(struct ifnet *ifp);
193 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
194 static void arwatchdog(struct ifnet *ifp);
196 static void arstart(struct ar_softc *sc);
197 static void arwatchdog(struct ar_softc *sc);
198 #endif /* NETGRAPH */
199 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
200 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
201 static void ar_eat_packet(struct ar_softc *sc, int single);
202 static void ar_get_packets(struct ar_softc *sc);
204 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
205 static void ar_up(struct ar_softc *sc);
206 static void ar_down(struct ar_softc *sc);
207 static void arc_init(struct ar_hardc *hc);
208 static void ar_init_sca(struct ar_hardc *hc, int scano);
209 static void ar_init_msci(struct ar_softc *sc);
210 static void ar_init_rx_dmac(struct ar_softc *sc);
211 static void ar_init_tx_dmac(struct ar_softc *sc);
212 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
213 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
214 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
217 static void ngar_watchdog_frame(void * arg);
218 static void ngar_init(void* ignored);
220 static ng_constructor_t ngar_constructor;
221 static ng_rcvmsg_t ngar_rcvmsg;
222 static ng_shutdown_t ngar_shutdown;
223 static ng_newhook_t ngar_newhook;
224 /*static ng_findhook_t ngar_findhook; */
225 static ng_connect_t ngar_connect;
226 static ng_rcvdata_t ngar_rcvdata;
227 static ng_disconnect_t ngar_disconnect;
229 static struct ng_type typestruct = {
244 static int ngar_done_init = 0;
245 #endif /* NETGRAPH */
248 ar_attach(device_t device)
255 #endif /* NETGRAPH */
258 hc = (struct ar_hardc *)device_get_softc(device);
260 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
268 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
269 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0)
274 for(unit=0;unit<hc->numports;unit+=NCHAN)
275 ar_init_sca(hc, unit / NCHAN);
278 * Now configure each port on the card.
280 for(unit=0;unit<hc->numports;sc++,unit++) {
283 sc->unit = next_ar_unit;
285 sc->scano = unit / NCHAN;
286 sc->scachan = unit%NCHAN;
293 ifp = &sc->ifsppp.pp_if;
296 if_initname(ifp, device_get_name(device),
297 device_get_unit(device));
298 ifp->if_mtu = PP_MTU;
299 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
300 ifp->if_ioctl = arioctl;
301 ifp->if_start = arstart;
302 ifp->if_watchdog = arwatchdog;
304 sc->ifsppp.pp_flags = PP_KEEPALIVE;
306 switch(hc->interface[unit]) {
307 default: iface = "UNKNOWN"; break;
308 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
309 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
310 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
311 case AR_IFACE_X_21: iface = "X.21"; break;
312 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
315 printf("ar%d: Adapter %d, port %d, interface %s.\n",
321 sppp_attach((struct ifnet *)&sc->ifsppp);
324 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
327 * we have found a node, make sure our 'type' is availabe.
329 if (ngar_done_init == 0) ngar_init(NULL);
330 if (ng_make_node_common(&typestruct, &sc->node) != 0)
332 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
333 if (ng_name_node(sc->node, sc->nodename)) {
334 NG_NODE_UNREF(sc->node); /* drop it again */
337 NG_NODE_SET_PRIVATE(sc->node, sc);
338 callout_handle_init(&sc->handle);
339 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
340 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
341 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF);
342 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL,
345 #endif /* NETGRAPH */
348 if(hc->bustype == AR_BUS_ISA)
355 ar_detach(device_t device)
357 device_t parent = device_get_parent(device);
358 struct ar_hardc *hc = device_get_softc(device);
360 if (hc->intr_cookie != NULL) {
361 if (BUS_TEARDOWN_INTR(parent, device,
362 hc->res_irq, hc->intr_cookie) != 0) {
363 printf("intr teardown failed.. continuing\n");
365 hc->intr_cookie = NULL;
369 * deallocate any system resources we may have
370 * allocated on behalf of this driver.
372 FREE(hc->sc, M_DEVBUF);
374 hc->mem_start = NULL;
375 return (ar_deallocate_resources(device));
379 ar_allocate_ioport(device_t device, int rid, u_long size)
381 struct ar_hardc *hc = device_get_softc(device);
383 hc->rid_ioport = rid;
384 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
385 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
386 if (hc->res_ioport == NULL) {
389 hc->bt = rman_get_bustag(hc->res_ioport);
390 hc->bh = rman_get_bushandle(hc->res_ioport);
395 ar_deallocate_resources(device);
400 ar_allocate_irq(device_t device, int rid, u_long size)
402 struct ar_hardc *hc = device_get_softc(device);
405 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
406 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
407 if (hc->res_irq == NULL) {
413 ar_deallocate_resources(device);
418 ar_allocate_memory(device_t device, int rid, u_long size)
420 struct ar_hardc *hc = device_get_softc(device);
422 hc->rid_memory = rid;
423 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
424 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
425 if (hc->res_memory == NULL) {
431 ar_deallocate_resources(device);
436 ar_allocate_plx_memory(device_t device, int rid, u_long size)
438 struct ar_hardc *hc = device_get_softc(device);
440 hc->rid_plx_memory = rid;
441 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
442 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
443 if (hc->res_plx_memory == NULL) {
449 ar_deallocate_resources(device);
454 ar_deallocate_resources(device_t device)
456 struct ar_hardc *hc = device_get_softc(device);
458 if (hc->res_irq != 0) {
459 bus_deactivate_resource(device, SYS_RES_IRQ,
460 hc->rid_irq, hc->res_irq);
461 bus_release_resource(device, SYS_RES_IRQ,
462 hc->rid_irq, hc->res_irq);
465 if (hc->res_ioport != 0) {
466 bus_deactivate_resource(device, SYS_RES_IOPORT,
467 hc->rid_ioport, hc->res_ioport);
468 bus_release_resource(device, SYS_RES_IOPORT,
469 hc->rid_ioport, hc->res_ioport);
472 if (hc->res_memory != 0) {
473 bus_deactivate_resource(device, SYS_RES_MEMORY,
474 hc->rid_memory, hc->res_memory);
475 bus_release_resource(device, SYS_RES_MEMORY,
476 hc->rid_memory, hc->res_memory);
479 if (hc->res_plx_memory != 0) {
480 bus_deactivate_resource(device, SYS_RES_MEMORY,
481 hc->rid_plx_memory, hc->res_plx_memory);
482 bus_release_resource(device, SYS_RES_MEMORY,
483 hc->rid_plx_memory, hc->res_plx_memory);
484 hc->res_plx_memory = 0;
490 * First figure out which SCA gave the interrupt.
492 * See if there is other interrupts pending.
493 * Repeat until there is no more interrupts.
498 struct ar_hardc *hc = (struct ar_hardc *)arg;
500 u_char isr0, isr1, isr2, arisr;
503 /* XXX Use the PCI interrupt score board register later */
504 if(hc->bustype == AR_BUS_PCI)
505 arisr = hc->orbase[AR_ISTAT * 4];
507 arisr = ar_inb(hc, AR_ISTAT);
509 while(arisr & AR_BD_INT) {
510 TRC(printf("arisr = %x\n", arisr));
513 else if(arisr & AR_INT_1)
516 /* XXX Oops this shouldn't happen. */
517 printf("arc%d: Interrupted with no interrupt.\n",
521 sca = hc->sca[scano];
523 if(hc->bustype == AR_BUS_ISA)
524 ARC_SET_SCA(hc, scano);
530 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
536 ar_msci_intr(hc, scano, isr0);
539 ar_dmac_intr(hc, scano, isr1);
542 ar_timer_intr(hc, scano, isr2);
545 * Proccess the second sca's interrupt if available.
546 * Else see if there are any new interrupts.
548 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
551 if(hc->bustype == AR_BUS_PCI)
552 arisr = hc->orbase[AR_ISTAT * 4];
554 arisr = ar_inb(hc, AR_ISTAT);
558 if(hc->bustype == AR_BUS_ISA)
564 * This will only start the transmitter. It is assumed that the data
565 * is already there. It is normally called from arstart() or ar_dmac_intr().
569 ar_xmit(struct ar_softc *sc)
573 #endif /* NETGRAPH */
577 ifp = &sc->ifsppp.pp_if;
578 #endif /* NETGRAPH */
579 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
581 if(sc->hc->bustype == AR_BUS_ISA)
582 ARC_SET_SCA(sc->hc, sc->scano);
583 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
585 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
586 dmac->dsr = SCA_DSR_DE;
591 if(sc->txb_next_tx == AR_TX_BLOCKS)
595 ifp->if_timer = 2; /* Value in seconds. */
597 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
598 #endif /* NETGRAPH */
599 if(sc->hc->bustype == AR_BUS_ISA)
604 * This function will be called from the upper level when a user add a
605 * packet to be send, and from the interrupt handler after a finished
608 * NOTE: it should run at spl_imp().
610 * This function only place the data in the oncard buffers. It does not
611 * start the transmition. ar_xmit() does that.
613 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
614 * that clears that should ensure that the transmitter and its DMA is
615 * in a "good" idle state.
619 arstart(struct ifnet *ifp)
621 struct ar_softc *sc = ifp->if_softc;
624 arstart(struct ar_softc *sc)
626 #endif /* NETGRAPH */
630 sca_descriptor *txdesc;
631 struct buf_block *blkp;
634 if(!(ifp->if_flags & IFF_RUNNING))
638 #endif /* NETGRAPH */
643 * See if we have space for more packets.
645 if(sc->txb_inuse == AR_TX_BLOCKS) {
647 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
649 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
650 #endif /* NETGRAPH */
655 mtx = sppp_dequeue(ifp);
657 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
659 IF_DEQUEUE(&sc->xmitq, mtx);
661 #endif /* NETGRAPH */
666 * It is OK to set the memory window outside the loop because
667 * all tx buffers and descriptors are assumed to be in the same
670 if(sc->hc->bustype == AR_BUS_ISA)
671 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
674 * We stay in this loop until there is nothing in the
675 * TX queue left or the tx buffer is full.
678 blkp = &sc->block[sc->txb_new];
679 txdesc = (sca_descriptor *)
680 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
681 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
683 len = mtx->m_pkthdr.len;
685 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
688 * We can do this because the tx buffers don't wrap.
690 m_copydata(mtx, 0, len, txdata);
692 while(tlen > AR_BUF_SIZ) {
694 txdesc->len = AR_BUF_SIZ;
697 txdata += AR_BUF_SIZ;
700 /* XXX Move into the loop? */
701 txdesc->stat = SCA_DESC_EOM;
704 txdata += AR_BUF_SIZ;
710 ++sc->ifsppp.pp_if.if_opackets;
715 #endif /* NETGRAPH */
718 * Check if we have space for another mbuf.
719 * XXX This is hardcoded. A packet won't be larger
720 * than 3 buffers (3 x 512).
722 if((i + 3) >= blkp->txmax)
726 mtx = sppp_dequeue(ifp);
728 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
730 IF_DEQUEUE(&sc->xmitq, mtx);
732 #endif /* NETGRAPH */
740 * Mark the last descriptor, so that the SCA know where
744 txdesc->stat |= SCA_DESC_EOT;
746 txdesc = (sca_descriptor *)blkp->txdesc;
747 blkp->txeda = (u_short)((u_int)&txdesc[i]);
750 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
751 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
752 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
753 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
754 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
759 if(sc->txb_new == AR_TX_BLOCKS)
762 if(sc->xmit_busy == 0)
765 if(sc->hc->bustype == AR_BUS_ISA)
773 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
776 int was_up, should_be_up;
777 struct ar_softc *sc = ifp->if_softc;
779 TRC(if_printf(ifp, "arioctl.\n");)
781 was_up = ifp->if_flags & IFF_RUNNING;
783 error = sppp_ioctl(ifp, cmd, data);
784 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
785 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
789 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
792 TRC(if_printf(ifp, "arioctl %s.\n",
793 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
796 should_be_up = ifp->if_flags & IFF_RUNNING;
798 if(!was_up && should_be_up) {
799 /* Interface should be up -- start it. */
802 /* XXX Maybe clear the IFF_UP flag so that the link
803 * will only go up after sppp lcp and ipcp negotiation.
805 } else if(was_up && !should_be_up) {
806 /* Interface should be down -- stop it. */
813 #endif /* NETGRAPH */
816 * This is to catch lost tx interrupts.
820 arwatchdog(struct ifnet *ifp)
822 struct ar_softc *sc = ifp->if_softc;
824 arwatchdog(struct ar_softc *sc)
826 #endif /* NETGRAPH */
827 msci_channel *msci = &sc->sca->msci[sc->scachan];
830 if(!(ifp->if_flags & IFF_RUNNING))
832 #endif /* NETGRAPH */
834 if(sc->hc->bustype == AR_BUS_ISA)
835 ARC_SET_SCA(sc->hc, sc->scano);
837 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
838 printf("ar%d: transmit failed, "
839 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
844 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
846 if(msci->st1 & SCA_ST1_UDRN) {
847 msci->cmd = SCA_CMD_TXABORT;
848 msci->cmd = SCA_CMD_TXENABLE;
849 msci->st1 = SCA_ST1_UDRN;
854 ifp->if_flags &= ~IFF_OACTIVE;
856 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
857 #endif /* NETGRAPH */
859 if(sc->txb_inuse && --sc->txb_inuse)
866 #endif /* NETGRAPH */
870 ar_up(struct ar_softc *sc)
876 msci = &sca->msci[sc->scachan];
878 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
879 sc->unit, sca, msci, sc->scachan));
882 * Enable transmitter and receiver.
886 if(sc->hc->bustype == AR_BUS_ISA)
887 ARC_SET_SCA(sc->hc, sc->scano);
890 * What about using AUTO mode in msci->md0 ???
891 * And what about CTS/DCD etc... ?
893 if(sc->hc->handshake & AR_SHSK_RTS)
894 msci->ctl &= ~SCA_CTL_RTS;
895 if(sc->hc->handshake & AR_SHSK_DTR) {
896 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
897 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
898 if(sc->hc->bustype == AR_BUS_PCI)
899 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
900 sc->hc->txc_dtr[sc->scano];
902 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
903 sc->hc->txc_dtr[sc->scano]);
906 if(sc->scachan == 0) {
914 msci->cmd = SCA_CMD_RXENABLE;
915 if(sc->hc->bustype == AR_BUS_ISA)
916 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
917 msci->cmd = SCA_CMD_TXENABLE;
919 if(sc->hc->bustype == AR_BUS_ISA)
922 untimeout(ngar_watchdog_frame, sc, sc->handle);
923 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
925 #endif /* NETGRAPH */
929 ar_down(struct ar_softc *sc)
935 msci = &sca->msci[sc->scachan];
938 untimeout(ngar_watchdog_frame, sc, sc->handle);
940 #endif /* NETGRAPH */
942 * Disable transmitter and receiver.
944 * Disable interrupts.
946 if(sc->hc->bustype == AR_BUS_ISA)
947 ARC_SET_SCA(sc->hc, sc->scano);
948 msci->cmd = SCA_CMD_RXDISABLE;
949 if(sc->hc->bustype == AR_BUS_ISA)
950 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
951 msci->cmd = SCA_CMD_TXDISABLE;
953 if(sc->hc->handshake & AR_SHSK_RTS)
954 msci->ctl |= SCA_CTL_RTS;
955 if(sc->hc->handshake & AR_SHSK_DTR) {
956 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
957 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
958 if(sc->hc->bustype == AR_BUS_PCI)
959 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
960 sc->hc->txc_dtr[sc->scano];
962 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
963 sc->hc->txc_dtr[sc->scano]);
966 if(sc->scachan == 0) {
974 if(sc->hc->bustype == AR_BUS_ISA)
979 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
981 int ctype, i, val, x;
982 volatile u_char *pimctrl;
987 pimctrl = hc->orbase + AR_PIMCTRL;
991 *pimctrl = AR_PIM_STROBE;
993 /* Check if there is a PIM */
995 *pimctrl = AR_PIM_READ;
997 TRC(printf("x = %x", x));
998 if(x & AR_PIM_DATA) {
999 printf("No PIM installed\n");
1000 return (AR_IFACE_UNKNOWN);
1003 x = (x >> 1) & 0x01;
1006 /* Now read the next 15 bits */
1007 for(i = 1; i < 16; i++) {
1008 *pimctrl = AR_PIM_READ;
1009 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1011 TRC(printf(" %x ", x));
1012 x = (x >> 1) & 0x01;
1014 if(i == 8 && (val & 0x000f) == 0x0004) {
1018 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1019 *pimctrl = AR_PIM_A2D_DOUT;
1022 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1023 *pimctrl = AR_PIM_A2D_DOUT;
1026 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1027 *pimctrl = AR_PIM_A2D_DOUT;
1029 /* Select channel */
1030 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1031 *pimctrl = ((channel & 2) << 2);
1032 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1033 *pimctrl = ((channel & 1) << 3);
1035 *pimctrl = AR_PIM_A2D_STROBE;
1039 printf("\nOops A2D start bit not zero (%X)\n", x);
1041 for(ii = 7; ii >= 0; ii--) {
1043 *pimctrl = AR_PIM_A2D_STROBE;
1050 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1051 *pimctrl = AR_PIM_MODEG;
1052 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1054 return (AR_IFACE_UNKNOWN);
1056 return (AR_IFACE_V_35);
1058 return (AR_IFACE_EIA_232);
1060 return (AR_IFACE_X_21);
1062 return (AR_IFACE_EIA_530);
1064 return (AR_IFACE_UNKNOWN);
1066 return (AR_IFACE_LOOPBACK);
1067 return (AR_IFACE_UNKNOWN);
1071 * Initialize the card, allocate memory for the ar_softc structures
1072 * and fill in the pointers.
1075 arc_init(struct ar_hardc *hc)
1077 struct ar_softc *sc;
1086 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1087 M_DEVBUF, M_WAITOK | M_ZERO);
1092 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1093 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1094 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1095 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1096 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1097 if(hc->bustype == AR_BUS_PCI) {
1098 hc->txc_dtr_off[0] *= 4;
1099 hc->txc_dtr_off[1] *= 4;
1103 * reset the card and wait at least 1uS.
1105 if(hc->bustype == AR_BUS_PCI)
1106 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1109 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1112 if(hc->bustype == AR_BUS_PCI)
1113 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1115 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1117 if(hc->bustype == AR_BUS_ISA) {
1119 * Configure the card.
1122 memst = rman_get_start(hc->res_memory);
1124 isr = irqtable[hc->isa_irq] << 1;
1126 printf("ar%d: Warning illegal interrupt %d\n",
1127 hc->cunit, hc->isa_irq);
1128 isr = isr | ((memst & 0xc000) >> 10);
1130 hc->sca[0] = (sca_regs *)hc->mem_start;
1131 hc->sca[1] = (sca_regs *)hc->mem_start;
1133 ar_outb(hc, AR_MEM_SEL, mar);
1134 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1137 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1138 for(x = 0; x < hc->numports; x++)
1139 hc->interface[x] = ar_read_pim_iface(hc, x);
1142 * Set the TX clock direction and enable TX.
1144 for(x=0;x<hc->numports;x++) {
1145 switch(hc->interface[x]) {
1147 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1148 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1149 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1150 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1152 case AR_IFACE_EIA_530:
1153 case AR_IFACE_COMBO:
1155 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1156 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1161 if(hc->bustype == AR_BUS_PCI)
1162 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1164 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1165 if(hc->numports > NCHAN) {
1166 if(hc->bustype == AR_BUS_PCI)
1167 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1169 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1172 chanmem = hc->memsize / hc->numports;
1175 for(x=0;x<hc->numports;x++, sc++) {
1178 sc->sca = hc->sca[x / NCHAN];
1180 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1181 sc->block[blk].txdesc = next;
1182 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1183 descneeded = bufmem / AR_BUF_SIZ;
1184 sc->block[blk].txstart = sc->block[blk].txdesc +
1185 ((((descneeded * sizeof(sca_descriptor)) /
1186 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1187 sc->block[blk].txend = next + bufmem;
1188 sc->block[blk].txmax =
1189 (sc->block[blk].txend - sc->block[blk].txstart)
1193 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1194 "txend %x, txmax %d\n",
1197 sc->block[blk].txdesc,
1198 sc->block[blk].txstart,
1199 sc->block[blk].txend,
1200 sc->block[blk].txmax));
1204 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1205 descneeded = bufmem / AR_BUF_SIZ;
1206 sc->rxstart = sc->rxdesc +
1207 ((((descneeded * sizeof(sca_descriptor)) /
1208 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1209 sc->rxend = next + bufmem;
1210 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1212 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1213 "rxend %x, rxmax %d\n",
1214 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1217 if(hc->bustype == AR_BUS_PCI)
1218 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1223 * The things done here are channel independent.
1225 * Configure the sca waitstates.
1226 * Configure the global interrupt registers.
1227 * Enable master dma enable.
1230 ar_init_sca(struct ar_hardc *hc, int scano)
1234 sca = hc->sca[scano];
1235 if(hc->bustype == AR_BUS_ISA)
1236 ARC_SET_SCA(hc, scano);
1239 * Do the wait registers.
1240 * Set everything to 0 wait states.
1249 * Configure the interrupt registers.
1250 * Most are cleared until the interface is configured.
1252 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1253 sca->ier1 = 0x00; /* DMAC interrupts */
1254 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1255 sca->itcr = 0x00; /* Use ivr and no intr ack */
1256 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1260 * Configure the timers.
1266 * Set the DMA channel priority to rotate between
1267 * all four channels.
1269 * Enable all dma channels.
1271 if(hc->bustype == AR_BUS_PCI) {
1275 * Stupid problem with the PCI interface chip that break
1280 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1281 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1283 sca->pcr = SCA_PCR_PR2;
1284 sca->dmer = SCA_DMER_EN;
1290 * Configure the msci
1292 * NOTE: The serial port configuration is hardcoded at the moment.
1295 ar_init_msci(struct ar_softc *sc)
1299 msci = &sc->sca->msci[sc->scachan];
1301 if(sc->hc->bustype == AR_BUS_ISA)
1302 ARC_SET_SCA(sc->hc, sc->scano);
1304 msci->cmd = SCA_CMD_RESET;
1306 msci->md0 = SCA_MD0_CRC_1 |
1308 SCA_MD0_CRC_ENABLE |
1310 msci->md1 = SCA_MD1_NOADDRCHK;
1311 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1314 * Acording to the manual I should give a reset after changing the
1317 msci->cmd = SCA_CMD_RXRESET;
1318 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1321 * For now all interfaces are programmed to use the RX clock for
1324 switch(sc->hc->interface[sc->subunit]) {
1326 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1327 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1330 case AR_IFACE_EIA_530:
1331 case AR_IFACE_COMBO:
1332 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1333 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1336 msci->tmc = 153; /* This give 64k for loopback */
1339 * Disable all interrupts for now. I think if you are using
1340 * the dmac you don't use these interrupts.
1343 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1350 msci->idl = 0x7E; /* XXX This is what cisco does. */
1353 * This is what the ARNET diags use.
1361 * Configure the rx dma controller.
1364 ar_init_rx_dmac(struct ar_softc *sc)
1367 sca_descriptor *rxd;
1373 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1375 if(sc->hc->bustype == AR_BUS_ISA)
1376 ARC_SET_MEM(sc->hc, sc->rxdesc);
1378 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1379 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1381 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1382 rxda = (u_int)&rxd[1] - rxda_d;
1383 rxd->cp = (u_short)(rxda & 0xfffful);
1387 TRC(printf("Descrp %p, data pt %x, data %x, ",
1390 rxd->bp = (u_short)(rxbuf & 0xfffful);
1391 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1393 rxd->stat = 0xff; /* The sca write here when it is finished. */
1396 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1399 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1403 if(sc->hc->bustype == AR_BUS_ISA)
1404 ARC_SET_SCA(sc->hc, sc->scano);
1406 dmac->dsr = 0; /* Disable DMA transfer */
1407 dmac->dcr = SCA_DCR_ABRT;
1409 /* XXX maybe also SCA_DMR_CNTE */
1410 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1411 dmac->bfl = AR_BUF_SIZ;
1413 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1414 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1416 rxd = (sca_descriptor *)sc->rxstart;
1417 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1421 dmac->dsr = SCA_DSR_DE;
1425 * Configure the TX DMA descriptors.
1426 * Initialize the needed values and chain the descriptors.
1429 ar_init_tx_dmac(struct ar_softc *sc)
1432 struct buf_block *blkp;
1434 sca_descriptor *txd;
1439 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1441 if(sc->hc->bustype == AR_BUS_ISA)
1442 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1444 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1445 blkp = &sc->block[blk];
1446 txd = (sca_descriptor *)(sc->hc->mem_start +
1447 (blkp->txdesc&sc->hc->winmsk));
1448 txda_d = (u_int)sc->hc->mem_start -
1449 (blkp->txdesc & ~sc->hc->winmsk);
1451 txbuf=blkp->txstart;
1452 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1453 txda = (u_int)&txd[1] - txda_d;
1454 txd->cp = (u_short)(txda & 0xfffful);
1456 txd->bp = (u_short)(txbuf & 0xfffful);
1457 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1458 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1459 sc->unit, txbuf, txd->bpb, txd->bp));
1464 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1466 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1467 TRC(printf("TX Descriptors start %x, end %x.\n",
1472 if(sc->hc->bustype == AR_BUS_ISA)
1473 ARC_SET_SCA(sc->hc, sc->scano);
1475 dmac->dsr = 0; /* Disable DMA */
1476 dmac->dcr = SCA_DCR_ABRT;
1477 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1478 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1480 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1485 * Look through the descriptors to see if there is a complete packet
1486 * available. Stop if we get to where the sca is busy.
1488 * Return the length and status of the packet.
1489 * Return nonzero if there is a packet available.
1492 * It seems that we get the interrupt a bit early. The updateing of
1493 * descriptor values is not always completed when this is called.
1496 ar_packet_avail(struct ar_softc *sc,
1501 sca_descriptor *rxdesc;
1502 sca_descriptor *endp;
1503 sca_descriptor *cda;
1505 if(sc->hc->bustype == AR_BUS_ISA)
1506 ARC_SET_SCA(sc->hc, sc->scano);
1507 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1508 cda = (sca_descriptor *)(sc->hc->mem_start +
1509 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1511 if(sc->hc->bustype == AR_BUS_ISA)
1512 ARC_SET_MEM(sc->hc, sc->rxdesc);
1513 rxdesc = (sca_descriptor *)
1514 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1516 rxdesc = &rxdesc[sc->rxhind];
1517 endp = &endp[sc->rxmax];
1521 while(rxdesc != cda) {
1522 *len += rxdesc->len;
1524 if(rxdesc->stat & SCA_DESC_EOM) {
1525 *rxstat = rxdesc->stat;
1526 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1527 sc->unit, *len, *rxstat));
1533 rxdesc = (sca_descriptor *)
1534 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1544 * Copy a packet from the on card memory into a provided mbuf.
1545 * Take into account that buffers wrap and that a packet may
1546 * be larger than a buffer.
1549 ar_copy_rxbuf(struct mbuf *m,
1550 struct ar_softc *sc,
1553 sca_descriptor *rxdesc;
1559 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1560 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1562 rxdesc = (sca_descriptor *)
1563 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1564 rxdesc = &rxdesc[sc->rxhind];
1567 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1568 if(sc->hc->bustype == AR_BUS_ISA)
1569 ARC_SET_MEM(sc->hc, rxdata);
1570 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1571 mtod(m, caddr_t) + off,
1577 if(sc->hc->bustype == AR_BUS_ISA)
1578 ARC_SET_MEM(sc->hc, sc->rxdesc);
1580 rxdesc->stat = 0xff;
1582 rxdata += AR_BUF_SIZ;
1584 if(rxdata == rxmax) {
1585 rxdata = sc->rxstart;
1586 rxdesc = (sca_descriptor *)
1587 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1593 * If single is set, just eat a packet. Otherwise eat everything up to
1594 * where cda points. Update pointers to point to the next packet.
1597 ar_eat_packet(struct ar_softc *sc, int single)
1600 sca_descriptor *rxdesc;
1601 sca_descriptor *endp;
1602 sca_descriptor *cda;
1606 if(sc->hc->bustype == AR_BUS_ISA)
1607 ARC_SET_SCA(sc->hc, sc->scano);
1608 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1609 cda = (sca_descriptor *)(sc->hc->mem_start +
1610 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1613 * Loop until desc->stat == (0xff || EOM)
1614 * Clear the status and length in the descriptor.
1615 * Increment the descriptor.
1617 if(sc->hc->bustype == AR_BUS_ISA)
1618 ARC_SET_MEM(sc->hc, sc->rxdesc);
1619 rxdesc = (sca_descriptor *)
1620 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1622 rxdesc = &rxdesc[sc->rxhind];
1623 endp = &endp[sc->rxmax];
1625 while(rxdesc != cda) {
1627 if(loopcnt > sc->rxmax) {
1628 printf("ar%d: eat pkt %d loop, cda %p, "
1629 "rxdesc %p, stat %x.\n",
1638 stat = rxdesc->stat;
1641 rxdesc->stat = 0xff;
1645 if(rxdesc == endp) {
1646 rxdesc = (sca_descriptor *)
1647 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1651 if(single && (stat == SCA_DESC_EOM))
1656 * Update the eda to the previous descriptor.
1658 if(sc->hc->bustype == AR_BUS_ISA)
1659 ARC_SET_SCA(sc->hc, sc->scano);
1661 rxdesc = (sca_descriptor *)sc->rxdesc;
1662 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1664 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1665 (u_short)((u_int)rxdesc & 0xffff);
1670 * While there is packets available in the rx buffer, read them out
1671 * into mbufs and ship them off.
1674 ar_get_packets(struct ar_softc *sc)
1676 sca_descriptor *rxdesc;
1677 struct mbuf *m = NULL;
1685 while(ar_packet_avail(sc, &len, &rxstat)) {
1686 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1687 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1688 MGETHDR(m, M_DONTWAIT, MT_DATA);
1690 /* eat packet if get mbuf fail!! */
1691 ar_eat_packet(sc, 1);
1695 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1696 #else /* NETGRAPH */
1697 m->m_pkthdr.rcvif = NULL;
1700 #endif /* NETGRAPH */
1701 m->m_pkthdr.len = m->m_len = len;
1703 MCLGET(m, M_DONTWAIT);
1704 if((m->m_flags & M_EXT) == 0) {
1706 ar_eat_packet(sc, 1);
1710 ar_copy_rxbuf(m, sc, len);
1712 BPF_MTAP(&sc->ifsppp.pp_if, m);
1713 sppp_input(&sc->ifsppp.pp_if, m);
1714 sc->ifsppp.pp_if.if_ipackets++;
1715 #else /* NETGRAPH */
1716 NG_SEND_DATA_ONLY(error, sc->hook, m);
1718 #endif /* NETGRAPH */
1721 * Update the eda to the previous descriptor.
1723 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1724 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1726 if(sc->hc->bustype == AR_BUS_ISA)
1727 ARC_SET_SCA(sc->hc, sc->scano);
1729 rxdesc = (sca_descriptor *)sc->rxdesc;
1731 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1733 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1734 (u_short)((u_int)rxdesc & 0xffff);
1738 while((rxstat == 0xff) && --tries)
1739 ar_packet_avail(sc, &len, &rxstat);
1742 * It look like we get an interrupt early
1743 * sometimes and then the status is not
1746 if(tries && (tries != 5))
1749 ar_eat_packet(sc, 1);
1752 sc->ifsppp.pp_if.if_ierrors++;
1753 #else /* NETGRAPH */
1755 #endif /* NETGRAPH */
1757 if(sc->hc->bustype == AR_BUS_ISA)
1758 ARC_SET_SCA(sc->hc, sc->scano);
1760 TRCL(printf("ar%d: Receive error chan %d, "
1761 "stat %x, msci st3 %x,"
1762 "rxhind %d, cda %x, eda %x.\n",
1766 sc->sca->msci[sc->scachan].st3,
1769 DMAC_RXCH(sc->scachan)].cda,
1771 DMAC_RXCH(sc->scachan)].eda));
1778 * All DMA interrupts come here.
1780 * Each channel has two interrupts.
1781 * Interrupt A for errors and Interrupt B for normal stuff like end
1782 * of transmit or receive dmas.
1785 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1788 u_char dotxstart = isr1;
1790 struct ar_softc *sc;
1794 sca = hc->sca[scano];
1797 * Shortcut if there is no interrupts for dma channel 0 or 1
1799 if((isr1 & 0x0F) == 0) {
1805 sc = &hc->sc[mch + (NCHAN * scano)];
1811 dmac = &sca->dmac[DMAC_TXCH(mch)];
1813 if(hc->bustype == AR_BUS_ISA)
1814 ARC_SET_SCA(hc, scano);
1819 /* Counter overflow */
1820 if(dsr & SCA_DSR_COF) {
1821 printf("ar%d: TX DMA Counter overflow, "
1822 "txpacket no %lu.\n",
1825 sc->ifsppp.pp_if.if_opackets);
1826 sc->ifsppp.pp_if.if_oerrors++;
1827 #else /* NETGRAPH */
1830 #endif /* NETGRAPH */
1833 /* Buffer overflow */
1834 if(dsr & SCA_DSR_BOF) {
1835 printf("ar%d: TX DMA Buffer overflow, "
1836 "txpacket no %lu, dsr %02x, "
1837 "cda %04x, eda %04x.\n",
1840 sc->ifsppp.pp_if.if_opackets,
1841 #else /* NETGRAPH */
1843 #endif /* NETGRAPH */
1848 sc->ifsppp.pp_if.if_oerrors++;
1849 #else /* NETGRAPH */
1851 #endif /* NETGRAPH */
1854 /* End of Transfer */
1855 if(dsr & SCA_DSR_EOT) {
1857 * This should be the most common case.
1859 * Clear the IFF_OACTIVE flag.
1861 * Call arstart to start a new transmit if
1862 * there is data to transmit.
1866 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1867 sc->ifsppp.pp_if.if_timer = 0;
1868 #else /* NETGRAPH */
1869 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1870 sc->out_dog = 0; /* XXX */
1871 #endif /* NETGRAPH */
1873 if(sc->txb_inuse && --sc->txb_inuse)
1882 dmac = &sca->dmac[DMAC_RXCH(mch)];
1884 if(hc->bustype == AR_BUS_ISA)
1885 ARC_SET_SCA(hc, scano);
1890 TRC(printf("AR: RX DSR %x\n", dsr));
1893 if(dsr & SCA_DSR_EOM) {
1894 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1895 TRC(int ind = sc->rxhind;)
1899 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1900 #else /* NETGRAPH */
1901 #define IPACKETS sc->ipackets
1902 #endif /* NETGRAPH */
1903 TRC(if(tt == IPACKETS) {
1904 sca_descriptor *rxdesc;
1907 if(hc->bustype == AR_BUS_ISA)
1908 ARC_SET_SCA(hc, scano);
1909 printf("AR: RXINTR isr1 %x, dsr %x, "
1910 "no data %d pkts, orxhind %d.\n",
1915 printf("AR: rxdesc %x, rxstart %x, "
1916 "rxend %x, rxhind %d, "
1923 printf("AR: cda %x, eda %x.\n",
1927 if(sc->hc->bustype == AR_BUS_ISA)
1930 rxdesc = (sca_descriptor *)
1931 (sc->hc->mem_start +
1932 (sc->rxdesc & sc->hc->winmsk));
1933 rxdesc = &rxdesc[sc->rxhind];
1934 for(i=0;i<3;i++,rxdesc++)
1935 printf("AR: rxdesc->stat %x, "
1942 /* Counter overflow */
1943 if(dsr & SCA_DSR_COF) {
1944 printf("ar%d: RX DMA Counter overflow, "
1948 sc->ifsppp.pp_if.if_ipackets);
1949 sc->ifsppp.pp_if.if_ierrors++;
1950 #else /* NETGRAPH */
1953 #endif /* NETGRAPH */
1956 /* Buffer overflow */
1957 if(dsr & SCA_DSR_BOF) {
1958 if(hc->bustype == AR_BUS_ISA)
1959 ARC_SET_SCA(hc, scano);
1960 printf("ar%d: RX DMA Buffer overflow, "
1961 "rxpkts %lu, rxind %d, "
1962 "cda %x, eda %x, dsr %x.\n",
1965 sc->ifsppp.pp_if.if_ipackets,
1966 #else /* NETGRAPH */
1968 #endif /* NETGRAPH */
1974 * Make sure we eat as many as possible.
1975 * Then get the system running again.
1977 ar_eat_packet(sc, 0);
1979 sc->ifsppp.pp_if.if_ierrors++;
1980 #else /* NETGRAPH */
1982 #endif /* NETGRAPH */
1983 if(hc->bustype == AR_BUS_ISA)
1984 ARC_SET_SCA(hc, scano);
1985 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1986 dmac->dsr = SCA_DSR_DE;
1988 TRC(printf("ar%d: RX DMA Buffer overflow, "
1989 "rxpkts %lu, rxind %d, "
1990 "cda %x, eda %x, dsr %x. After\n",
1992 sc->ifsppp.pp_if.if_ipackets,
1999 /* End of Transfer */
2000 if(dsr & SCA_DSR_EOT) {
2002 * If this happen, it means that we are
2003 * receiving faster than what the processor
2006 * XXX We should enable the dma again.
2008 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2011 sc->ifsppp.pp_if.if_ipackets);
2012 sc->ifsppp.pp_if.if_ierrors++;
2013 #else /* NETGRAPH */
2016 #endif /* NETGRAPH */
2023 }while((mch<NCHAN) && isr1);
2026 * Now that we have done all the urgent things, see if we
2027 * can fill the transmit buffers.
2029 for(mch = 0; mch < NCHAN; mch++) {
2030 if(dotxstart & 0x0C) {
2031 sc = &hc->sc[mch + (NCHAN * scano)];
2033 arstart(&sc->ifsppp.pp_if);
2034 #else /* NETGRAPH */
2036 #endif /* NETGRAPH */
2043 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2045 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2049 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2051 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2056 /*****************************************
2057 * Device timeout/watchdog routine.
2058 * called once per second.
2059 * checks to see that if activity was expected, that it hapenned.
2060 * At present we only look to see if expected output was completed.
2063 ngar_watchdog_frame(void * arg)
2065 struct ar_softc * sc = arg;
2069 if(sc->running == 0)
2070 return; /* if we are not running let timeouts die */
2072 * calculate the apparent throughputs
2076 speed = sc->inbytes - sc->lastinbytes;
2077 sc->lastinbytes = sc->inbytes;
2078 if ( sc->inrate < speed )
2080 speed = sc->outbytes - sc->lastoutbytes;
2081 sc->lastoutbytes = sc->outbytes;
2082 if ( sc->outrate < speed )
2083 sc->outrate = speed;
2087 if ((sc->inlast > QUITE_A_WHILE)
2088 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2089 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2093 sc->inlast = sc->out_deficit = 0;
2095 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2096 if (sc->out_dog == 0) {
2097 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2106 sc->inlast = sc->out_deficit = 0;
2111 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2114 /***********************************************************************
2115 * This section contains the methods for the Netgraph interface
2116 ***********************************************************************/
2118 * It is not possible or allowable to create a node of this type.
2119 * If the hardware exists, it will already have created it.
2122 ngar_constructor(node_p node)
2128 * give our ok for a hook to be added...
2129 * If we are not running this should kick the device into life.
2130 * The hook's private info points to our stash of info about that
2134 ngar_newhook(node_p node, hook_p hook, const char *name)
2136 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2139 * check if it's our friend the debug hook
2141 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2142 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2143 sc->debug_hook = hook;
2148 * Check for raw mode hook.
2150 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2153 NG_HOOK_SET_PRIVATE(hook, sc);
2161 * incoming messages.
2162 * Just respond to the generic TEXT_STATUS message
2165 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook)
2167 struct ar_softc * sc;
2168 struct ng_mesg *resp = NULL;
2170 struct ng_mesg *msg;
2172 NGI_GET_MSG(item, msg);
2173 sc = NG_NODE_PRIVATE(node);
2174 switch (msg->header.typecookie) {
2178 case NGM_GENERIC_COOKIE:
2179 switch(msg->header.cmd) {
2180 case NGM_TEXT_STATUS: {
2184 int resplen = sizeof(struct ng_mesg) + 512;
2185 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT);
2191 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2192 "highest rate seen: %ld B/S in, %ld B/S out\n",
2193 sc->inbytes, sc->outbytes,
2194 sc->inrate, sc->outrate);
2195 pos += sprintf(arg + pos,
2196 "%ld output errors\n",
2198 pos += sprintf(arg + pos,
2199 "ierrors = %ld, %ld, %ld, %ld\n",
2205 resp->header.arglen = pos + 1;
2217 /* Take care of synchronous response, if any */
2218 NG_RESPOND_MSG(error, node, item, resp);
2224 * get data from another node and transmit it to the correct channel
2227 ngar_rcvdata(hook_p hook, item_p item)
2231 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2232 struct ifqueue *xmitq_p;
2237 NGI_GET_META(item, meta);
2240 * data doesn't come in from just anywhere (e.g control hook)
2242 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2248 * Now queue the data for when it can be sent
2250 if (meta && meta->priority > 0) {
2251 xmitq_p = (&sc->xmitq_hipri);
2253 xmitq_p = (&sc->xmitq);
2257 if (_IF_QFULL(xmitq_p)) {
2264 _IF_ENQUEUE(xmitq_p, m);
2272 * It was an error case.
2273 * check if we need to free the mbuf, and then return the error
2281 * do local shutdown processing..
2282 * this node will refuse to go away, unless the hardware says to..
2283 * don't unref the node, or remove our name. just clear our links up.
2286 ngar_shutdown(node_p node)
2288 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2291 NG_NODE_UNREF(node);
2292 /* XXX need to drain the output queues! */
2294 /* The node is dead, long live the node! */
2295 /* stolen from the attach routine */
2296 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2298 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2299 if (ng_name_node(sc->node, sc->nodename)) {
2301 printf("node naming failed\n");
2302 NG_NODE_UNREF(sc->node); /* node dissappears */
2305 NG_NODE_SET_PRIVATE(sc->node, sc);
2310 /* already linked */
2312 ngar_connect(hook_p hook)
2314 /* probably not at splnet, force outward queueing */
2315 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
2316 /* be really amiable and just say "YUP that's OK by me! " */
2321 * notify on hook disconnection (destruction)
2323 * Invalidate the private data associated with this dlci.
2324 * For this type, removal of the last link resets tries to destroy the node.
2325 * As the device still exists, the shutdown method will not actually
2326 * destroy the node, but reset the device and leave it 'fresh' :)
2328 * The node removal code will remove all references except that owned by the
2332 ngar_disconnect(hook_p hook)
2334 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2337 * If it's the data hook, then free resources etc.
2339 if (NG_HOOK_PRIVATE(hook)) {
2342 if (sc->datahooks == 0)
2346 sc->debug_hook = NULL;
2352 * called during bootup
2353 * or LKM loading to put this type into the list of known modules
2356 ngar_init(void *ignored)
2358 if (ng_newtype(&typestruct))
2359 printf("ngar install failed\n");
2362 #endif /* NETGRAPH */
2365 ********************************* END ************************************