2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <machine/bus_pio.h>
62 #include <machine/bus_memio.h>
67 #include <netgraph/ng_message.h>
68 #include <netgraph/netgraph.h>
69 #include <sys/syslog.h>
70 #include <dev/ar/if_ar.h>
72 #include <net/if_sppp.h>
76 #include <machine/md_var.h>
78 #include <dev/ic/hd64570.h>
79 #include <dev/ar/if_arregs.h>
89 #define PPP_HEADER_LEN 4
91 devclass_t ar_devclass;
97 int unit; /* With regards to all ar devices */
98 int subunit; /* With regards to this card */
102 u_int txdesc; /* On card address */
103 u_int txstart; /* On card address */
104 u_int txend; /* On card address */
105 u_int txtail; /* Index of first unused buffer */
106 u_int txmax; /* number of usable buffers/descriptors */
107 u_int txeda; /* Error descriptor addresses */
108 }block[AR_TX_BLOCKS];
110 char xmit_busy; /* Transmitter is busy */
111 char txb_inuse; /* Number of tx blocks currently in use */
112 u_char txb_new; /* Index to where new buffer will be added */
113 u_char txb_next_tx; /* Index to next block ready to tx */
115 u_int rxdesc; /* On card address */
116 u_int rxstart; /* On card address */
117 u_int rxend; /* On card address */
118 u_int rxhind; /* Index to the head of the rx buffers. */
119 u_int rxmax; /* number of usable buffers/descriptors */
125 int running; /* something is attached so we are running */
126 int dcd; /* do we have dcd? */
127 /* ---netgraph bits --- */
128 char nodename[NG_NODESIZ]; /* store our node name */
129 int datahooks; /* number of data hooks attached */
130 node_p node; /* netgraph node */
131 hook_p hook; /* data hook */
133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
134 struct ifqueue xmitq; /* transmit queue */
135 int flags; /* state */
136 #define SCF_RUNNING 0x01 /* board is active */
137 #define SCF_OACTIVE 0x02 /* output is active */
138 int out_dog; /* watchdog cycles output count-down */
139 struct callout_handle handle; /* timeout(9) handle */
140 u_long inbytes, outbytes; /* stats */
141 u_long lastinbytes, lastoutbytes; /* a second ago */
142 u_long inrate, outrate; /* highest rate seen */
143 u_long inlast; /* last input N secs ago */
144 u_long out_deficit; /* output since last input */
145 u_long oerrors, ierrors[6];
146 u_long opackets, ipackets;
147 #endif /* NETGRAPH */
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
187 static void arintr(void *arg);
188 static void ar_xmit(struct ar_softc *sc);
190 static void arstart(struct ifnet *ifp);
191 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
192 static void arwatchdog(struct ifnet *ifp);
194 static void arstart(struct ar_softc *sc);
195 static void arwatchdog(struct ar_softc *sc);
196 #endif /* NETGRAPH */
197 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
198 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
199 static void ar_eat_packet(struct ar_softc *sc, int single);
200 static void ar_get_packets(struct ar_softc *sc);
202 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
203 static void ar_up(struct ar_softc *sc);
204 static void ar_down(struct ar_softc *sc);
205 static void arc_init(struct ar_hardc *hc);
206 static void ar_init_sca(struct ar_hardc *hc, int scano);
207 static void ar_init_msci(struct ar_softc *sc);
208 static void ar_init_rx_dmac(struct ar_softc *sc);
209 static void ar_init_tx_dmac(struct ar_softc *sc);
210 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
211 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
212 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
215 static void ngar_watchdog_frame(void * arg);
217 static ng_constructor_t ngar_constructor;
218 static ng_rcvmsg_t ngar_rcvmsg;
219 static ng_shutdown_t ngar_shutdown;
220 static ng_newhook_t ngar_newhook;
221 /*static ng_findhook_t ngar_findhook; */
222 static ng_connect_t ngar_connect;
223 static ng_rcvdata_t ngar_rcvdata;
224 static ng_disconnect_t ngar_disconnect;
226 static struct ng_type typestruct = {
227 .version = NG_ABI_VERSION,
228 .name = NG_AR_NODE_TYPE,
229 .constructor = ngar_constructor,
230 .rcvmsg = ngar_rcvmsg,
231 .shutdown = ngar_shutdown,
232 .newhook = ngar_newhook,
233 .connect = ngar_connect,
234 .rcvdata = ngar_rcvdata,
235 .disconnect = ngar_disconnect,
237 NETGRAPH_INIT_ORDERED(sync_ar, &typestruct, SI_SUB_DRIVERS, SI_ORDER_FIRST);
238 #endif /* NETGRAPH */
241 ar_attach(device_t device)
248 #endif /* NETGRAPH */
251 hc = (struct ar_hardc *)device_get_softc(device);
253 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
261 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
262 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0)
267 for(unit=0;unit<hc->numports;unit+=NCHAN)
268 ar_init_sca(hc, unit / NCHAN);
271 * Now configure each port on the card.
273 for(unit=0;unit<hc->numports;sc++,unit++) {
276 sc->unit = next_ar_unit;
278 sc->scano = unit / NCHAN;
279 sc->scachan = unit%NCHAN;
286 ifp = &sc->ifsppp.pp_if;
289 if_initname(ifp, device_get_name(device),
290 device_get_unit(device));
291 ifp->if_mtu = PP_MTU;
292 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST |
294 ifp->if_ioctl = arioctl;
295 ifp->if_start = arstart;
296 ifp->if_watchdog = arwatchdog;
298 sc->ifsppp.pp_flags = PP_KEEPALIVE;
300 switch(hc->interface[unit]) {
301 default: iface = "UNKNOWN"; break;
302 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
303 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
304 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
305 case AR_IFACE_X_21: iface = "X.21"; break;
306 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
309 printf("ar%d: Adapter %d, port %d, interface %s.\n",
315 sppp_attach((struct ifnet *)&sc->ifsppp);
318 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
320 if (ng_make_node_common(&typestruct, &sc->node) != 0)
322 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
323 if (ng_name_node(sc->node, sc->nodename)) {
324 NG_NODE_UNREF(sc->node); /* drop it again */
327 NG_NODE_SET_PRIVATE(sc->node, sc);
328 callout_handle_init(&sc->handle);
329 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
330 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
331 mtx_init(&sc->xmitq.ifq_mtx, "ar_xmitq", NULL, MTX_DEF);
332 mtx_init(&sc->xmitq_hipri.ifq_mtx, "ar_xmitq_hipri", NULL,
335 #endif /* NETGRAPH */
338 if(hc->bustype == AR_BUS_ISA)
345 ar_detach(device_t device)
347 device_t parent = device_get_parent(device);
348 struct ar_hardc *hc = device_get_softc(device);
350 if (hc->intr_cookie != NULL) {
351 if (BUS_TEARDOWN_INTR(parent, device,
352 hc->res_irq, hc->intr_cookie) != 0) {
353 printf("intr teardown failed.. continuing\n");
355 hc->intr_cookie = NULL;
359 * deallocate any system resources we may have
360 * allocated on behalf of this driver.
362 FREE(hc->sc, M_DEVBUF);
364 hc->mem_start = NULL;
365 return (ar_deallocate_resources(device));
369 ar_allocate_ioport(device_t device, int rid, u_long size)
371 struct ar_hardc *hc = device_get_softc(device);
373 hc->rid_ioport = rid;
374 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
375 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
376 if (hc->res_ioport == NULL) {
379 hc->bt = rman_get_bustag(hc->res_ioport);
380 hc->bh = rman_get_bushandle(hc->res_ioport);
385 ar_deallocate_resources(device);
390 ar_allocate_irq(device_t device, int rid, u_long size)
392 struct ar_hardc *hc = device_get_softc(device);
395 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
396 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
397 if (hc->res_irq == NULL) {
403 ar_deallocate_resources(device);
408 ar_allocate_memory(device_t device, int rid, u_long size)
410 struct ar_hardc *hc = device_get_softc(device);
412 hc->rid_memory = rid;
413 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
414 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
415 if (hc->res_memory == NULL) {
421 ar_deallocate_resources(device);
426 ar_allocate_plx_memory(device_t device, int rid, u_long size)
428 struct ar_hardc *hc = device_get_softc(device);
430 hc->rid_plx_memory = rid;
431 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
432 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
433 if (hc->res_plx_memory == NULL) {
439 ar_deallocate_resources(device);
444 ar_deallocate_resources(device_t device)
446 struct ar_hardc *hc = device_get_softc(device);
448 if (hc->res_irq != 0) {
449 bus_deactivate_resource(device, SYS_RES_IRQ,
450 hc->rid_irq, hc->res_irq);
451 bus_release_resource(device, SYS_RES_IRQ,
452 hc->rid_irq, hc->res_irq);
455 if (hc->res_ioport != 0) {
456 bus_deactivate_resource(device, SYS_RES_IOPORT,
457 hc->rid_ioport, hc->res_ioport);
458 bus_release_resource(device, SYS_RES_IOPORT,
459 hc->rid_ioport, hc->res_ioport);
462 if (hc->res_memory != 0) {
463 bus_deactivate_resource(device, SYS_RES_MEMORY,
464 hc->rid_memory, hc->res_memory);
465 bus_release_resource(device, SYS_RES_MEMORY,
466 hc->rid_memory, hc->res_memory);
469 if (hc->res_plx_memory != 0) {
470 bus_deactivate_resource(device, SYS_RES_MEMORY,
471 hc->rid_plx_memory, hc->res_plx_memory);
472 bus_release_resource(device, SYS_RES_MEMORY,
473 hc->rid_plx_memory, hc->res_plx_memory);
474 hc->res_plx_memory = 0;
480 * First figure out which SCA gave the interrupt.
482 * See if there is other interrupts pending.
483 * Repeat until there is no more interrupts.
488 struct ar_hardc *hc = (struct ar_hardc *)arg;
490 u_char isr0, isr1, isr2, arisr;
493 /* XXX Use the PCI interrupt score board register later */
494 if(hc->bustype == AR_BUS_PCI)
495 arisr = hc->orbase[AR_ISTAT * 4];
497 arisr = ar_inb(hc, AR_ISTAT);
499 while(arisr & AR_BD_INT) {
500 TRC(printf("arisr = %x\n", arisr));
503 else if(arisr & AR_INT_1)
506 /* XXX Oops this shouldn't happen. */
507 printf("arc%d: Interrupted with no interrupt.\n",
511 sca = hc->sca[scano];
513 if(hc->bustype == AR_BUS_ISA)
514 ARC_SET_SCA(hc, scano);
520 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
526 ar_msci_intr(hc, scano, isr0);
529 ar_dmac_intr(hc, scano, isr1);
532 ar_timer_intr(hc, scano, isr2);
535 * Proccess the second sca's interrupt if available.
536 * Else see if there are any new interrupts.
538 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
541 if(hc->bustype == AR_BUS_PCI)
542 arisr = hc->orbase[AR_ISTAT * 4];
544 arisr = ar_inb(hc, AR_ISTAT);
548 if(hc->bustype == AR_BUS_ISA)
554 * This will only start the transmitter. It is assumed that the data
555 * is already there. It is normally called from arstart() or ar_dmac_intr().
559 ar_xmit(struct ar_softc *sc)
563 #endif /* NETGRAPH */
567 ifp = &sc->ifsppp.pp_if;
568 #endif /* NETGRAPH */
569 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
571 if(sc->hc->bustype == AR_BUS_ISA)
572 ARC_SET_SCA(sc->hc, sc->scano);
573 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
575 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
576 dmac->dsr = SCA_DSR_DE;
581 if(sc->txb_next_tx == AR_TX_BLOCKS)
585 ifp->if_timer = 2; /* Value in seconds. */
587 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
588 #endif /* NETGRAPH */
589 if(sc->hc->bustype == AR_BUS_ISA)
594 * This function will be called from the upper level when a user add a
595 * packet to be send, and from the interrupt handler after a finished
598 * NOTE: it should run at spl_imp().
600 * This function only place the data in the oncard buffers. It does not
601 * start the transmition. ar_xmit() does that.
603 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
604 * that clears that should ensure that the transmitter and its DMA is
605 * in a "good" idle state.
609 arstart(struct ifnet *ifp)
611 struct ar_softc *sc = ifp->if_softc;
614 arstart(struct ar_softc *sc)
616 #endif /* NETGRAPH */
620 sca_descriptor *txdesc;
621 struct buf_block *blkp;
624 if(!(ifp->if_flags & IFF_RUNNING))
628 #endif /* NETGRAPH */
633 * See if we have space for more packets.
635 if(sc->txb_inuse == AR_TX_BLOCKS) {
637 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
639 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
640 #endif /* NETGRAPH */
645 mtx = sppp_dequeue(ifp);
647 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
649 IF_DEQUEUE(&sc->xmitq, mtx);
651 #endif /* NETGRAPH */
656 * It is OK to set the memory window outside the loop because
657 * all tx buffers and descriptors are assumed to be in the same
660 if(sc->hc->bustype == AR_BUS_ISA)
661 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
664 * We stay in this loop until there is nothing in the
665 * TX queue left or the tx buffer is full.
668 blkp = &sc->block[sc->txb_new];
669 txdesc = (sca_descriptor *)
670 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
671 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
673 len = mtx->m_pkthdr.len;
675 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
678 * We can do this because the tx buffers don't wrap.
680 m_copydata(mtx, 0, len, txdata);
682 while(tlen > AR_BUF_SIZ) {
684 txdesc->len = AR_BUF_SIZ;
687 txdata += AR_BUF_SIZ;
690 /* XXX Move into the loop? */
691 txdesc->stat = SCA_DESC_EOM;
694 txdata += AR_BUF_SIZ;
700 ++sc->ifsppp.pp_if.if_opackets;
705 #endif /* NETGRAPH */
708 * Check if we have space for another mbuf.
709 * XXX This is hardcoded. A packet won't be larger
710 * than 3 buffers (3 x 512).
712 if((i + 3) >= blkp->txmax)
716 mtx = sppp_dequeue(ifp);
718 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
720 IF_DEQUEUE(&sc->xmitq, mtx);
722 #endif /* NETGRAPH */
730 * Mark the last descriptor, so that the SCA know where
734 txdesc->stat |= SCA_DESC_EOT;
736 txdesc = (sca_descriptor *)blkp->txdesc;
737 blkp->txeda = (u_short)((u_int)&txdesc[i]);
740 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
741 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
742 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
743 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
744 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
749 if(sc->txb_new == AR_TX_BLOCKS)
752 if(sc->xmit_busy == 0)
755 if(sc->hc->bustype == AR_BUS_ISA)
763 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
766 int was_up, should_be_up;
767 struct ar_softc *sc = ifp->if_softc;
769 TRC(if_printf(ifp, "arioctl.\n");)
771 was_up = ifp->if_flags & IFF_RUNNING;
773 error = sppp_ioctl(ifp, cmd, data);
774 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
775 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
779 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
782 TRC(if_printf(ifp, "arioctl %s.\n",
783 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
786 should_be_up = ifp->if_flags & IFF_RUNNING;
788 if(!was_up && should_be_up) {
789 /* Interface should be up -- start it. */
792 /* XXX Maybe clear the IFF_UP flag so that the link
793 * will only go up after sppp lcp and ipcp negotiation.
795 } else if(was_up && !should_be_up) {
796 /* Interface should be down -- stop it. */
803 #endif /* NETGRAPH */
806 * This is to catch lost tx interrupts.
810 arwatchdog(struct ifnet *ifp)
812 struct ar_softc *sc = ifp->if_softc;
814 arwatchdog(struct ar_softc *sc)
816 #endif /* NETGRAPH */
817 msci_channel *msci = &sc->sca->msci[sc->scachan];
820 if(!(ifp->if_flags & IFF_RUNNING))
822 #endif /* NETGRAPH */
824 if(sc->hc->bustype == AR_BUS_ISA)
825 ARC_SET_SCA(sc->hc, sc->scano);
827 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
828 printf("ar%d: transmit failed, "
829 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
834 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
836 if(msci->st1 & SCA_ST1_UDRN) {
837 msci->cmd = SCA_CMD_TXABORT;
838 msci->cmd = SCA_CMD_TXENABLE;
839 msci->st1 = SCA_ST1_UDRN;
844 ifp->if_flags &= ~IFF_OACTIVE;
846 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
847 #endif /* NETGRAPH */
849 if(sc->txb_inuse && --sc->txb_inuse)
856 #endif /* NETGRAPH */
860 ar_up(struct ar_softc *sc)
866 msci = &sca->msci[sc->scachan];
868 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
869 sc->unit, sca, msci, sc->scachan));
872 * Enable transmitter and receiver.
876 if(sc->hc->bustype == AR_BUS_ISA)
877 ARC_SET_SCA(sc->hc, sc->scano);
880 * What about using AUTO mode in msci->md0 ???
881 * And what about CTS/DCD etc... ?
883 if(sc->hc->handshake & AR_SHSK_RTS)
884 msci->ctl &= ~SCA_CTL_RTS;
885 if(sc->hc->handshake & AR_SHSK_DTR) {
886 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
887 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
888 if(sc->hc->bustype == AR_BUS_PCI)
889 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
890 sc->hc->txc_dtr[sc->scano];
892 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
893 sc->hc->txc_dtr[sc->scano]);
896 if(sc->scachan == 0) {
904 msci->cmd = SCA_CMD_RXENABLE;
905 if(sc->hc->bustype == AR_BUS_ISA)
906 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
907 msci->cmd = SCA_CMD_TXENABLE;
909 if(sc->hc->bustype == AR_BUS_ISA)
912 untimeout(ngar_watchdog_frame, sc, sc->handle);
913 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
915 #endif /* NETGRAPH */
919 ar_down(struct ar_softc *sc)
925 msci = &sca->msci[sc->scachan];
928 untimeout(ngar_watchdog_frame, sc, sc->handle);
930 #endif /* NETGRAPH */
932 * Disable transmitter and receiver.
934 * Disable interrupts.
936 if(sc->hc->bustype == AR_BUS_ISA)
937 ARC_SET_SCA(sc->hc, sc->scano);
938 msci->cmd = SCA_CMD_RXDISABLE;
939 if(sc->hc->bustype == AR_BUS_ISA)
940 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
941 msci->cmd = SCA_CMD_TXDISABLE;
943 if(sc->hc->handshake & AR_SHSK_RTS)
944 msci->ctl |= SCA_CTL_RTS;
945 if(sc->hc->handshake & AR_SHSK_DTR) {
946 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
947 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
948 if(sc->hc->bustype == AR_BUS_PCI)
949 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
950 sc->hc->txc_dtr[sc->scano];
952 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
953 sc->hc->txc_dtr[sc->scano]);
956 if(sc->scachan == 0) {
964 if(sc->hc->bustype == AR_BUS_ISA)
969 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
971 int ctype, i, val, x;
972 volatile u_char *pimctrl;
977 pimctrl = hc->orbase + AR_PIMCTRL;
981 *pimctrl = AR_PIM_STROBE;
983 /* Check if there is a PIM */
985 *pimctrl = AR_PIM_READ;
987 TRC(printf("x = %x", x));
988 if(x & AR_PIM_DATA) {
989 printf("No PIM installed\n");
990 return (AR_IFACE_UNKNOWN);
996 /* Now read the next 15 bits */
997 for(i = 1; i < 16; i++) {
998 *pimctrl = AR_PIM_READ;
999 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1001 TRC(printf(" %x ", x));
1002 x = (x >> 1) & 0x01;
1004 if(i == 8 && (val & 0x000f) == 0x0004) {
1008 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1009 *pimctrl = AR_PIM_A2D_DOUT;
1012 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1013 *pimctrl = AR_PIM_A2D_DOUT;
1016 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1017 *pimctrl = AR_PIM_A2D_DOUT;
1019 /* Select channel */
1020 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1021 *pimctrl = ((channel & 2) << 2);
1022 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1023 *pimctrl = ((channel & 1) << 3);
1025 *pimctrl = AR_PIM_A2D_STROBE;
1029 printf("\nOops A2D start bit not zero (%X)\n", x);
1031 for(ii = 7; ii >= 0; ii--) {
1033 *pimctrl = AR_PIM_A2D_STROBE;
1040 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1041 *pimctrl = AR_PIM_MODEG;
1042 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1044 return (AR_IFACE_UNKNOWN);
1046 return (AR_IFACE_V_35);
1048 return (AR_IFACE_EIA_232);
1050 return (AR_IFACE_X_21);
1052 return (AR_IFACE_EIA_530);
1054 return (AR_IFACE_UNKNOWN);
1056 return (AR_IFACE_LOOPBACK);
1057 return (AR_IFACE_UNKNOWN);
1061 * Initialize the card, allocate memory for the ar_softc structures
1062 * and fill in the pointers.
1065 arc_init(struct ar_hardc *hc)
1067 struct ar_softc *sc;
1076 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1077 M_DEVBUF, M_WAITOK | M_ZERO);
1082 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1083 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1084 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1085 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1086 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1087 if(hc->bustype == AR_BUS_PCI) {
1088 hc->txc_dtr_off[0] *= 4;
1089 hc->txc_dtr_off[1] *= 4;
1093 * reset the card and wait at least 1uS.
1095 if(hc->bustype == AR_BUS_PCI)
1096 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1099 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1102 if(hc->bustype == AR_BUS_PCI)
1103 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1105 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1107 if(hc->bustype == AR_BUS_ISA) {
1109 * Configure the card.
1112 memst = rman_get_start(hc->res_memory);
1114 isr = irqtable[hc->isa_irq] << 1;
1116 printf("ar%d: Warning illegal interrupt %d\n",
1117 hc->cunit, hc->isa_irq);
1118 isr = isr | ((memst & 0xc000) >> 10);
1120 hc->sca[0] = (sca_regs *)hc->mem_start;
1121 hc->sca[1] = (sca_regs *)hc->mem_start;
1123 ar_outb(hc, AR_MEM_SEL, mar);
1124 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1127 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1128 for(x = 0; x < hc->numports; x++)
1129 hc->interface[x] = ar_read_pim_iface(hc, x);
1132 * Set the TX clock direction and enable TX.
1134 for(x=0;x<hc->numports;x++) {
1135 switch(hc->interface[x]) {
1137 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1138 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1139 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1140 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1142 case AR_IFACE_EIA_530:
1143 case AR_IFACE_COMBO:
1145 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1146 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1151 if(hc->bustype == AR_BUS_PCI)
1152 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1154 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1155 if(hc->numports > NCHAN) {
1156 if(hc->bustype == AR_BUS_PCI)
1157 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1159 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1162 chanmem = hc->memsize / hc->numports;
1165 for(x=0;x<hc->numports;x++, sc++) {
1168 sc->sca = hc->sca[x / NCHAN];
1170 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1171 sc->block[blk].txdesc = next;
1172 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1173 descneeded = bufmem / AR_BUF_SIZ;
1174 sc->block[blk].txstart = sc->block[blk].txdesc +
1175 ((((descneeded * sizeof(sca_descriptor)) /
1176 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1177 sc->block[blk].txend = next + bufmem;
1178 sc->block[blk].txmax =
1179 (sc->block[blk].txend - sc->block[blk].txstart)
1183 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1184 "txend %x, txmax %d\n",
1187 sc->block[blk].txdesc,
1188 sc->block[blk].txstart,
1189 sc->block[blk].txend,
1190 sc->block[blk].txmax));
1194 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1195 descneeded = bufmem / AR_BUF_SIZ;
1196 sc->rxstart = sc->rxdesc +
1197 ((((descneeded * sizeof(sca_descriptor)) /
1198 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1199 sc->rxend = next + bufmem;
1200 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1202 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1203 "rxend %x, rxmax %d\n",
1204 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1207 if(hc->bustype == AR_BUS_PCI)
1208 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1213 * The things done here are channel independent.
1215 * Configure the sca waitstates.
1216 * Configure the global interrupt registers.
1217 * Enable master dma enable.
1220 ar_init_sca(struct ar_hardc *hc, int scano)
1224 sca = hc->sca[scano];
1225 if(hc->bustype == AR_BUS_ISA)
1226 ARC_SET_SCA(hc, scano);
1229 * Do the wait registers.
1230 * Set everything to 0 wait states.
1239 * Configure the interrupt registers.
1240 * Most are cleared until the interface is configured.
1242 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1243 sca->ier1 = 0x00; /* DMAC interrupts */
1244 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1245 sca->itcr = 0x00; /* Use ivr and no intr ack */
1246 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1250 * Configure the timers.
1256 * Set the DMA channel priority to rotate between
1257 * all four channels.
1259 * Enable all dma channels.
1261 if(hc->bustype == AR_BUS_PCI) {
1265 * Stupid problem with the PCI interface chip that break
1270 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1271 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1273 sca->pcr = SCA_PCR_PR2;
1274 sca->dmer = SCA_DMER_EN;
1280 * Configure the msci
1282 * NOTE: The serial port configuration is hardcoded at the moment.
1285 ar_init_msci(struct ar_softc *sc)
1289 msci = &sc->sca->msci[sc->scachan];
1291 if(sc->hc->bustype == AR_BUS_ISA)
1292 ARC_SET_SCA(sc->hc, sc->scano);
1294 msci->cmd = SCA_CMD_RESET;
1296 msci->md0 = SCA_MD0_CRC_1 |
1298 SCA_MD0_CRC_ENABLE |
1300 msci->md1 = SCA_MD1_NOADDRCHK;
1301 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1304 * Acording to the manual I should give a reset after changing the
1307 msci->cmd = SCA_CMD_RXRESET;
1308 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1311 * For now all interfaces are programmed to use the RX clock for
1314 switch(sc->hc->interface[sc->subunit]) {
1316 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1317 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1320 case AR_IFACE_EIA_530:
1321 case AR_IFACE_COMBO:
1322 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1323 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1326 msci->tmc = 153; /* This give 64k for loopback */
1329 * Disable all interrupts for now. I think if you are using
1330 * the dmac you don't use these interrupts.
1333 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1340 msci->idl = 0x7E; /* XXX This is what cisco does. */
1343 * This is what the ARNET diags use.
1351 * Configure the rx dma controller.
1354 ar_init_rx_dmac(struct ar_softc *sc)
1357 sca_descriptor *rxd;
1363 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1365 if(sc->hc->bustype == AR_BUS_ISA)
1366 ARC_SET_MEM(sc->hc, sc->rxdesc);
1368 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1369 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1371 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1372 rxda = (u_int)&rxd[1] - rxda_d;
1373 rxd->cp = (u_short)(rxda & 0xfffful);
1377 TRC(printf("Descrp %p, data pt %x, data %x, ",
1380 rxd->bp = (u_short)(rxbuf & 0xfffful);
1381 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1383 rxd->stat = 0xff; /* The sca write here when it is finished. */
1386 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1389 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1393 if(sc->hc->bustype == AR_BUS_ISA)
1394 ARC_SET_SCA(sc->hc, sc->scano);
1396 dmac->dsr = 0; /* Disable DMA transfer */
1397 dmac->dcr = SCA_DCR_ABRT;
1399 /* XXX maybe also SCA_DMR_CNTE */
1400 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1401 dmac->bfl = AR_BUF_SIZ;
1403 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1404 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1406 rxd = (sca_descriptor *)sc->rxstart;
1407 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1411 dmac->dsr = SCA_DSR_DE;
1415 * Configure the TX DMA descriptors.
1416 * Initialize the needed values and chain the descriptors.
1419 ar_init_tx_dmac(struct ar_softc *sc)
1422 struct buf_block *blkp;
1424 sca_descriptor *txd;
1429 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1431 if(sc->hc->bustype == AR_BUS_ISA)
1432 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1434 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1435 blkp = &sc->block[blk];
1436 txd = (sca_descriptor *)(sc->hc->mem_start +
1437 (blkp->txdesc&sc->hc->winmsk));
1438 txda_d = (u_int)sc->hc->mem_start -
1439 (blkp->txdesc & ~sc->hc->winmsk);
1441 txbuf=blkp->txstart;
1442 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1443 txda = (u_int)&txd[1] - txda_d;
1444 txd->cp = (u_short)(txda & 0xfffful);
1446 txd->bp = (u_short)(txbuf & 0xfffful);
1447 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1448 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1449 sc->unit, txbuf, txd->bpb, txd->bp));
1454 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1456 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1457 TRC(printf("TX Descriptors start %x, end %x.\n",
1462 if(sc->hc->bustype == AR_BUS_ISA)
1463 ARC_SET_SCA(sc->hc, sc->scano);
1465 dmac->dsr = 0; /* Disable DMA */
1466 dmac->dcr = SCA_DCR_ABRT;
1467 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1468 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1470 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1475 * Look through the descriptors to see if there is a complete packet
1476 * available. Stop if we get to where the sca is busy.
1478 * Return the length and status of the packet.
1479 * Return nonzero if there is a packet available.
1482 * It seems that we get the interrupt a bit early. The updateing of
1483 * descriptor values is not always completed when this is called.
1486 ar_packet_avail(struct ar_softc *sc,
1491 sca_descriptor *rxdesc;
1492 sca_descriptor *endp;
1493 sca_descriptor *cda;
1495 if(sc->hc->bustype == AR_BUS_ISA)
1496 ARC_SET_SCA(sc->hc, sc->scano);
1497 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1498 cda = (sca_descriptor *)(sc->hc->mem_start +
1499 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1501 if(sc->hc->bustype == AR_BUS_ISA)
1502 ARC_SET_MEM(sc->hc, sc->rxdesc);
1503 rxdesc = (sca_descriptor *)
1504 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1506 rxdesc = &rxdesc[sc->rxhind];
1507 endp = &endp[sc->rxmax];
1511 while(rxdesc != cda) {
1512 *len += rxdesc->len;
1514 if(rxdesc->stat & SCA_DESC_EOM) {
1515 *rxstat = rxdesc->stat;
1516 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1517 sc->unit, *len, *rxstat));
1523 rxdesc = (sca_descriptor *)
1524 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1534 * Copy a packet from the on card memory into a provided mbuf.
1535 * Take into account that buffers wrap and that a packet may
1536 * be larger than a buffer.
1539 ar_copy_rxbuf(struct mbuf *m,
1540 struct ar_softc *sc,
1543 sca_descriptor *rxdesc;
1549 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1550 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1552 rxdesc = (sca_descriptor *)
1553 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1554 rxdesc = &rxdesc[sc->rxhind];
1557 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1558 if(sc->hc->bustype == AR_BUS_ISA)
1559 ARC_SET_MEM(sc->hc, rxdata);
1560 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1561 mtod(m, caddr_t) + off,
1567 if(sc->hc->bustype == AR_BUS_ISA)
1568 ARC_SET_MEM(sc->hc, sc->rxdesc);
1570 rxdesc->stat = 0xff;
1572 rxdata += AR_BUF_SIZ;
1574 if(rxdata == rxmax) {
1575 rxdata = sc->rxstart;
1576 rxdesc = (sca_descriptor *)
1577 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1583 * If single is set, just eat a packet. Otherwise eat everything up to
1584 * where cda points. Update pointers to point to the next packet.
1587 ar_eat_packet(struct ar_softc *sc, int single)
1590 sca_descriptor *rxdesc;
1591 sca_descriptor *endp;
1592 sca_descriptor *cda;
1596 if(sc->hc->bustype == AR_BUS_ISA)
1597 ARC_SET_SCA(sc->hc, sc->scano);
1598 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1599 cda = (sca_descriptor *)(sc->hc->mem_start +
1600 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1603 * Loop until desc->stat == (0xff || EOM)
1604 * Clear the status and length in the descriptor.
1605 * Increment the descriptor.
1607 if(sc->hc->bustype == AR_BUS_ISA)
1608 ARC_SET_MEM(sc->hc, sc->rxdesc);
1609 rxdesc = (sca_descriptor *)
1610 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1612 rxdesc = &rxdesc[sc->rxhind];
1613 endp = &endp[sc->rxmax];
1615 while(rxdesc != cda) {
1617 if(loopcnt > sc->rxmax) {
1618 printf("ar%d: eat pkt %d loop, cda %p, "
1619 "rxdesc %p, stat %x.\n",
1628 stat = rxdesc->stat;
1631 rxdesc->stat = 0xff;
1635 if(rxdesc == endp) {
1636 rxdesc = (sca_descriptor *)
1637 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1641 if(single && (stat == SCA_DESC_EOM))
1646 * Update the eda to the previous descriptor.
1648 if(sc->hc->bustype == AR_BUS_ISA)
1649 ARC_SET_SCA(sc->hc, sc->scano);
1651 rxdesc = (sca_descriptor *)sc->rxdesc;
1652 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1654 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1655 (u_short)((u_int)rxdesc & 0xffff);
1660 * While there is packets available in the rx buffer, read them out
1661 * into mbufs and ship them off.
1664 ar_get_packets(struct ar_softc *sc)
1666 sca_descriptor *rxdesc;
1667 struct mbuf *m = NULL;
1675 while(ar_packet_avail(sc, &len, &rxstat)) {
1676 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1677 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1678 MGETHDR(m, M_DONTWAIT, MT_DATA);
1680 /* eat packet if get mbuf fail!! */
1681 ar_eat_packet(sc, 1);
1685 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1686 #else /* NETGRAPH */
1687 m->m_pkthdr.rcvif = NULL;
1690 #endif /* NETGRAPH */
1691 m->m_pkthdr.len = m->m_len = len;
1693 MCLGET(m, M_DONTWAIT);
1694 if((m->m_flags & M_EXT) == 0) {
1696 ar_eat_packet(sc, 1);
1700 ar_copy_rxbuf(m, sc, len);
1702 BPF_MTAP(&sc->ifsppp.pp_if, m);
1703 sppp_input(&sc->ifsppp.pp_if, m);
1704 sc->ifsppp.pp_if.if_ipackets++;
1705 #else /* NETGRAPH */
1706 NG_SEND_DATA_ONLY(error, sc->hook, m);
1708 #endif /* NETGRAPH */
1711 * Update the eda to the previous descriptor.
1713 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1714 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1716 if(sc->hc->bustype == AR_BUS_ISA)
1717 ARC_SET_SCA(sc->hc, sc->scano);
1719 rxdesc = (sca_descriptor *)sc->rxdesc;
1721 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1723 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1724 (u_short)((u_int)rxdesc & 0xffff);
1728 while((rxstat == 0xff) && --tries)
1729 ar_packet_avail(sc, &len, &rxstat);
1732 * It look like we get an interrupt early
1733 * sometimes and then the status is not
1736 if(tries && (tries != 5))
1739 ar_eat_packet(sc, 1);
1742 sc->ifsppp.pp_if.if_ierrors++;
1743 #else /* NETGRAPH */
1745 #endif /* NETGRAPH */
1747 if(sc->hc->bustype == AR_BUS_ISA)
1748 ARC_SET_SCA(sc->hc, sc->scano);
1750 TRCL(printf("ar%d: Receive error chan %d, "
1751 "stat %x, msci st3 %x,"
1752 "rxhind %d, cda %x, eda %x.\n",
1756 sc->sca->msci[sc->scachan].st3,
1759 DMAC_RXCH(sc->scachan)].cda,
1761 DMAC_RXCH(sc->scachan)].eda));
1768 * All DMA interrupts come here.
1770 * Each channel has two interrupts.
1771 * Interrupt A for errors and Interrupt B for normal stuff like end
1772 * of transmit or receive dmas.
1775 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1778 u_char dotxstart = isr1;
1780 struct ar_softc *sc;
1784 sca = hc->sca[scano];
1787 * Shortcut if there is no interrupts for dma channel 0 or 1
1789 if((isr1 & 0x0F) == 0) {
1795 sc = &hc->sc[mch + (NCHAN * scano)];
1801 dmac = &sca->dmac[DMAC_TXCH(mch)];
1803 if(hc->bustype == AR_BUS_ISA)
1804 ARC_SET_SCA(hc, scano);
1809 /* Counter overflow */
1810 if(dsr & SCA_DSR_COF) {
1811 printf("ar%d: TX DMA Counter overflow, "
1812 "txpacket no %lu.\n",
1815 sc->ifsppp.pp_if.if_opackets);
1816 sc->ifsppp.pp_if.if_oerrors++;
1817 #else /* NETGRAPH */
1820 #endif /* NETGRAPH */
1823 /* Buffer overflow */
1824 if(dsr & SCA_DSR_BOF) {
1825 printf("ar%d: TX DMA Buffer overflow, "
1826 "txpacket no %lu, dsr %02x, "
1827 "cda %04x, eda %04x.\n",
1830 sc->ifsppp.pp_if.if_opackets,
1831 #else /* NETGRAPH */
1833 #endif /* NETGRAPH */
1838 sc->ifsppp.pp_if.if_oerrors++;
1839 #else /* NETGRAPH */
1841 #endif /* NETGRAPH */
1844 /* End of Transfer */
1845 if(dsr & SCA_DSR_EOT) {
1847 * This should be the most common case.
1849 * Clear the IFF_OACTIVE flag.
1851 * Call arstart to start a new transmit if
1852 * there is data to transmit.
1856 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1857 sc->ifsppp.pp_if.if_timer = 0;
1858 #else /* NETGRAPH */
1859 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1860 sc->out_dog = 0; /* XXX */
1861 #endif /* NETGRAPH */
1863 if(sc->txb_inuse && --sc->txb_inuse)
1872 dmac = &sca->dmac[DMAC_RXCH(mch)];
1874 if(hc->bustype == AR_BUS_ISA)
1875 ARC_SET_SCA(hc, scano);
1880 TRC(printf("AR: RX DSR %x\n", dsr));
1883 if(dsr & SCA_DSR_EOM) {
1884 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1885 TRC(int ind = sc->rxhind;)
1889 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1890 #else /* NETGRAPH */
1891 #define IPACKETS sc->ipackets
1892 #endif /* NETGRAPH */
1893 TRC(if(tt == IPACKETS) {
1894 sca_descriptor *rxdesc;
1897 if(hc->bustype == AR_BUS_ISA)
1898 ARC_SET_SCA(hc, scano);
1899 printf("AR: RXINTR isr1 %x, dsr %x, "
1900 "no data %d pkts, orxhind %d.\n",
1905 printf("AR: rxdesc %x, rxstart %x, "
1906 "rxend %x, rxhind %d, "
1913 printf("AR: cda %x, eda %x.\n",
1917 if(sc->hc->bustype == AR_BUS_ISA)
1920 rxdesc = (sca_descriptor *)
1921 (sc->hc->mem_start +
1922 (sc->rxdesc & sc->hc->winmsk));
1923 rxdesc = &rxdesc[sc->rxhind];
1924 for(i=0;i<3;i++,rxdesc++)
1925 printf("AR: rxdesc->stat %x, "
1932 /* Counter overflow */
1933 if(dsr & SCA_DSR_COF) {
1934 printf("ar%d: RX DMA Counter overflow, "
1938 sc->ifsppp.pp_if.if_ipackets);
1939 sc->ifsppp.pp_if.if_ierrors++;
1940 #else /* NETGRAPH */
1943 #endif /* NETGRAPH */
1946 /* Buffer overflow */
1947 if(dsr & SCA_DSR_BOF) {
1948 if(hc->bustype == AR_BUS_ISA)
1949 ARC_SET_SCA(hc, scano);
1950 printf("ar%d: RX DMA Buffer overflow, "
1951 "rxpkts %lu, rxind %d, "
1952 "cda %x, eda %x, dsr %x.\n",
1955 sc->ifsppp.pp_if.if_ipackets,
1956 #else /* NETGRAPH */
1958 #endif /* NETGRAPH */
1964 * Make sure we eat as many as possible.
1965 * Then get the system running again.
1967 ar_eat_packet(sc, 0);
1969 sc->ifsppp.pp_if.if_ierrors++;
1970 #else /* NETGRAPH */
1972 #endif /* NETGRAPH */
1973 if(hc->bustype == AR_BUS_ISA)
1974 ARC_SET_SCA(hc, scano);
1975 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1976 dmac->dsr = SCA_DSR_DE;
1978 TRC(printf("ar%d: RX DMA Buffer overflow, "
1979 "rxpkts %lu, rxind %d, "
1980 "cda %x, eda %x, dsr %x. After\n",
1982 sc->ifsppp.pp_if.if_ipackets,
1989 /* End of Transfer */
1990 if(dsr & SCA_DSR_EOT) {
1992 * If this happen, it means that we are
1993 * receiving faster than what the processor
1996 * XXX We should enable the dma again.
1998 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2001 sc->ifsppp.pp_if.if_ipackets);
2002 sc->ifsppp.pp_if.if_ierrors++;
2003 #else /* NETGRAPH */
2006 #endif /* NETGRAPH */
2013 }while((mch<NCHAN) && isr1);
2016 * Now that we have done all the urgent things, see if we
2017 * can fill the transmit buffers.
2019 for(mch = 0; mch < NCHAN; mch++) {
2020 if(dotxstart & 0x0C) {
2021 sc = &hc->sc[mch + (NCHAN * scano)];
2023 arstart(&sc->ifsppp.pp_if);
2024 #else /* NETGRAPH */
2026 #endif /* NETGRAPH */
2033 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2035 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2039 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2041 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2046 /*****************************************
2047 * Device timeout/watchdog routine.
2048 * called once per second.
2049 * checks to see that if activity was expected, that it hapenned.
2050 * At present we only look to see if expected output was completed.
2053 ngar_watchdog_frame(void * arg)
2055 struct ar_softc * sc = arg;
2059 if(sc->running == 0)
2060 return; /* if we are not running let timeouts die */
2062 * calculate the apparent throughputs
2066 speed = sc->inbytes - sc->lastinbytes;
2067 sc->lastinbytes = sc->inbytes;
2068 if ( sc->inrate < speed )
2070 speed = sc->outbytes - sc->lastoutbytes;
2071 sc->lastoutbytes = sc->outbytes;
2072 if ( sc->outrate < speed )
2073 sc->outrate = speed;
2077 if ((sc->inlast > QUITE_A_WHILE)
2078 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2079 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2083 sc->inlast = sc->out_deficit = 0;
2085 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2086 if (sc->out_dog == 0) {
2087 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2096 sc->inlast = sc->out_deficit = 0;
2101 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2104 /***********************************************************************
2105 * This section contains the methods for the Netgraph interface
2106 ***********************************************************************/
2108 * It is not possible or allowable to create a node of this type.
2109 * If the hardware exists, it will already have created it.
2112 ngar_constructor(node_p node)
2118 * give our ok for a hook to be added...
2119 * If we are not running this should kick the device into life.
2120 * The hook's private info points to our stash of info about that
2124 ngar_newhook(node_p node, hook_p hook, const char *name)
2126 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2129 * check if it's our friend the debug hook
2131 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2132 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2133 sc->debug_hook = hook;
2138 * Check for raw mode hook.
2140 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2143 NG_HOOK_SET_PRIVATE(hook, sc);
2151 * incoming messages.
2152 * Just respond to the generic TEXT_STATUS message
2155 ngar_rcvmsg(node_p node, item_p item, hook_p lasthook)
2157 struct ar_softc * sc;
2158 struct ng_mesg *resp = NULL;
2160 struct ng_mesg *msg;
2162 NGI_GET_MSG(item, msg);
2163 sc = NG_NODE_PRIVATE(node);
2164 switch (msg->header.typecookie) {
2168 case NGM_GENERIC_COOKIE:
2169 switch(msg->header.cmd) {
2170 case NGM_TEXT_STATUS: {
2174 int resplen = sizeof(struct ng_mesg) + 512;
2175 NG_MKRESPONSE(resp, msg, resplen, M_NOWAIT);
2181 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2182 "highest rate seen: %ld B/S in, %ld B/S out\n",
2183 sc->inbytes, sc->outbytes,
2184 sc->inrate, sc->outrate);
2185 pos += sprintf(arg + pos,
2186 "%ld output errors\n",
2188 pos += sprintf(arg + pos,
2189 "ierrors = %ld, %ld, %ld, %ld\n",
2195 resp->header.arglen = pos + 1;
2207 /* Take care of synchronous response, if any */
2208 NG_RESPOND_MSG(error, node, item, resp);
2214 * get data from another node and transmit it to the correct channel
2217 ngar_rcvdata(hook_p hook, item_p item)
2221 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2222 struct ifqueue *xmitq_p;
2224 struct ng_tag_prio *ptag;
2229 * data doesn't come in from just anywhere (e.g control hook)
2231 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2237 * Now queue the data for when it can be sent
2239 if ((ptag = (struct ng_tag_prio *)m_tag_locate(m, NGM_GENERIC_COOKIE,
2240 NG_TAG_PRIO, NULL)) != NULL && (ptag->priority > NG_PRIO_CUTOFF) )
2241 xmitq_p = (&sc->xmitq_hipri);
2243 xmitq_p = (&sc->xmitq);
2247 if (_IF_QFULL(xmitq_p)) {
2254 _IF_ENQUEUE(xmitq_p, m);
2262 * It was an error case.
2263 * check if we need to free the mbuf, and then return the error
2270 * do local shutdown processing..
2271 * this node will refuse to go away, unless the hardware says to..
2272 * don't unref the node, or remove our name. just clear our links up.
2275 ngar_shutdown(node_p node)
2277 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2280 NG_NODE_UNREF(node);
2281 /* XXX need to drain the output queues! */
2283 /* The node is dead, long live the node! */
2284 /* stolen from the attach routine */
2285 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2287 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2288 if (ng_name_node(sc->node, sc->nodename)) {
2290 printf("node naming failed\n");
2291 NG_NODE_UNREF(sc->node); /* node dissappears */
2294 NG_NODE_SET_PRIVATE(sc->node, sc);
2299 /* already linked */
2301 ngar_connect(hook_p hook)
2303 /* probably not at splnet, force outward queueing */
2304 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
2305 /* be really amiable and just say "YUP that's OK by me! " */
2310 * notify on hook disconnection (destruction)
2312 * Invalidate the private data associated with this dlci.
2313 * For this type, removal of the last link resets tries to destroy the node.
2314 * As the device still exists, the shutdown method will not actually
2315 * destroy the node, but reset the device and leave it 'fresh' :)
2317 * The node removal code will remove all references except that owned by the
2321 ngar_disconnect(hook_p hook)
2323 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2326 * If it's the data hook, then free resources etc.
2328 if (NG_HOOK_PRIVATE(hook)) {
2331 if (sc->datahooks == 0)
2335 sc->debug_hook = NULL;
2339 #endif /* NETGRAPH */
2342 ********************************* END ************************************