sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** SPDX-License-Identifier: BSD-3-Clause
  13 **
  14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  15 **
  16 ** Redistribution and use in source and binary forms, with or without
  17 ** modification, are permitted provided that the following conditions
  18 ** are met:
  19 ** 1. Redistributions of source code must retain the above copyright
  20 **    notice, this list of conditions and the following disclaimer.
  21 ** 2. Redistributions in binary form must reproduce the above copyright
  22 **    notice, this list of conditions and the following disclaimer in the
  23 **    documentation and/or other materials provided with the distribution.
  24 ** 3. The name of the author may not be used to endorse or promote products
  25 **    derived from this software without specific prior written permission.
  26 **
  27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 ********************************************************************************
  38 ** History
  39 **
  40 **    REV#         DATE         NAME        DESCRIPTION
  41 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  42 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  43 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  44 **                                          clean unused function
  45 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  46 **                                          firmware version check
  47 **                                          and firmware update notify for hardware bug fix
  48 **                                          handling if none zero high part physical address
  49 **                                          of srb resource
  50 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  51 **                                          add iop message xfer
  52 **                                          with scsi pass-through command
  53 **                                          add new device id of sas raid adapters
  54 **                                          code fit for SPARC64 & PPC
  55 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  56 **                                          and cause g_vfs_done() read write error
  57 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  58 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  59 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  60 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  61 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  62 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  63 **                                          for any one LUN device failed
  64 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  65 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  66 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  67 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  68 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  69 **              02/14/2011  Ching Huang     Modified pktRequestCount
  70 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  71 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  72 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  73 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  74 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  75 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  76 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  77 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  78 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  79 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  80 ** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
  81 ** 1.30.00.00   11/30/2015  Ching Huang     Added support ARC1203
  82 ** 1.40.00.00   07/11/2017  Ching Huang     Added support ARC1884
  83 ** 1.40.00.01   10/30/2017  Ching Huang     Fixed release memory resource
  84 ******************************************************************************************
  85 */
  86
  87 #include <sys/cdefs.h>
  88 __FBSDID("$FreeBSD$");
  89
  90 #if 0
  91 #define ARCMSR_DEBUG1                   1
  92 #endif
  93 #include <sys/param.h>
  94 #include <sys/systm.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/bus.h>
  98 #include <sys/queue.h>
  99 #include <sys/stat.h>
 100 #include <sys/devicestat.h>
 101 #include <sys/kthread.h>
 102 #include <sys/module.h>
 103 #include <sys/proc.h>
 104 #include <sys/lock.h>
 105 #include <sys/sysctl.h>
 106 #include <sys/poll.h>
 107 #include <sys/ioccom.h>
 108 #include <vm/vm.h>
 109 #include <vm/vm_param.h>
 110 #include <vm/pmap.h>
 111
 112 #include <isa/rtc.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <machine/atomic.h>
 117 #include <sys/conf.h>
 118 #include <sys/rman.h>
 119
 120 #include <cam/cam.h>
 121 #include <cam/cam_ccb.h>
 122 #include <cam/cam_sim.h>
 123 #include <cam/cam_periph.h>
 124 #include <cam/cam_xpt_periph.h>
 125 #include <cam/cam_xpt_sim.h>
 126 #include <cam/cam_debug.h>
 127 #include <cam/scsi/scsi_all.h>
 128 #include <cam/scsi/scsi_message.h>
 129 /*
 130 **************************************************************************
 131 **************************************************************************
 132 */
 133 #if __FreeBSD_version >= 500005
 134         #include <sys/selinfo.h>
 135         #include <sys/mutex.h>
 136         #include <sys/endian.h>
 137         #include <dev/pci/pcivar.h>
 138         #include <dev/pci/pcireg.h>
 139 #else
 140         #include <sys/select.h>
 141         #include <pci/pcivar.h>
 142         #include <pci/pcireg.h>
 143 #endif
 144
 145 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
 146 #define CAM_NEW_TRAN_CODE       1
 147 #endif
 148
 149 #if __FreeBSD_version > 500000
 150 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 151 #else
 152 #define arcmsr_callout_init(a)  callout_init(a);
 153 #endif
 154
 155 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.40.00.01 2017-10-30"
 156 #include <dev/arcmsr/arcmsr.h>
 157 /*
 158 **************************************************************************
 159 **************************************************************************
 160 */
 161 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 162 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 163 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 164 static int arcmsr_probe(device_t dev);
 165 static int arcmsr_attach(device_t dev);
 166 static int arcmsr_detach(device_t dev);
 167 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 168 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 169 static int arcmsr_shutdown(device_t dev);
 170 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 171 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 172 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 173 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 174 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 175 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 176 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 177 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 178 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 179 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 180 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 181 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 182 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 183 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 184 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 185 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 186 static int arcmsr_resume(device_t dev);
 187 static int arcmsr_suspend(device_t dev);
 188 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 189 static void arcmsr_polling_devmap(void *arg);
 190 static void arcmsr_srb_timeout(void *arg);
 191 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 192 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
 193 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
 194 #ifdef ARCMSR_DEBUG1
 195 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 196 #endif
 197 /*
 198 **************************************************************************
 199 **************************************************************************
 200 */
 201 static void UDELAY(u_int32_t us) { DELAY(us); }
 202 /*
 203 **************************************************************************
 204 **************************************************************************
 205 */
 206 static bus_dmamap_callback_t arcmsr_map_free_srb;
 207 static bus_dmamap_callback_t arcmsr_execute_srb;
 208 /*
 209 **************************************************************************
 210 **************************************************************************
 211 */
 212 static d_open_t arcmsr_open;
 213 static d_close_t arcmsr_close;
 214 static d_ioctl_t arcmsr_ioctl;
 215
 216 static device_method_t arcmsr_methods[]={
 217         DEVMETHOD(device_probe,         arcmsr_probe),
 218         DEVMETHOD(device_attach,        arcmsr_attach),
 219         DEVMETHOD(device_detach,        arcmsr_detach),
 220         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 221         DEVMETHOD(device_suspend,       arcmsr_suspend),
 222         DEVMETHOD(device_resume,        arcmsr_resume),
 223
 224 #if __FreeBSD_version >= 803000
 225         DEVMETHOD_END
 226 #else
 227         { 0, 0 }
 228 #endif
 229 };
 230
 231 static driver_t arcmsr_driver={
 232         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 233 };
 234
 235 static devclass_t arcmsr_devclass;
 236 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 237 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 238 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 239 #ifndef BUS_DMA_COHERENT
 240         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 241 #endif
 242 #if __FreeBSD_version >= 501000
 243 static struct cdevsw arcmsr_cdevsw={
 244         #if __FreeBSD_version >= 503000
 245                 .d_version = D_VERSION,
 246         #endif
 247         #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
 248                 .d_flags   = D_NEEDGIANT,
 249         #endif
 250                 .d_open    = arcmsr_open,       /* open     */
 251                 .d_close   = arcmsr_close,      /* close    */
 252                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 253                 .d_name    = "arcmsr",          /* name     */
 254         };
 255 #else
 256         #define ARCMSR_CDEV_MAJOR       180
 257
 258 static struct cdevsw arcmsr_cdevsw = {
 259                 arcmsr_open,                    /* open     */
 260                 arcmsr_close,                   /* close    */
 261                 noread,                         /* read     */
 262                 nowrite,                        /* write    */
 263                 arcmsr_ioctl,                   /* ioctl    */
 264                 nopoll,                         /* poll     */
 265                 nommap,                         /* mmap     */
 266                 nostrategy,                     /* strategy */
 267                 "arcmsr",                       /* name     */
 268                 ARCMSR_CDEV_MAJOR,              /* major    */
 269                 nodump,                         /* dump     */
 270                 nopsize,                        /* psize    */
 271                 0                               /* flags    */
 272         };
 273 #endif
 274 /*
 275 **************************************************************************
 276 **************************************************************************
 277 */
 278 #if     __FreeBSD_version < 500005
 279         static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
 280 #else
 281         #if     __FreeBSD_version < 503000
 282         static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
 283         #else
 284         static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 285         #endif
 286 #endif
 287 {
 288         #if     __FreeBSD_version < 503000
 289                 struct AdapterControlBlock *acb = dev->si_drv1;
 290         #else
 291                 int     unit = dev2unit(dev);
 292                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 293         #endif
 294         if(acb == NULL) {
 295                 return ENXIO;
 296         }
 297         return (0);
 298 }
 299 /*
 300 **************************************************************************
 301 **************************************************************************
 302 */
 303 #if     __FreeBSD_version < 500005
 304         static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
 305 #else
 306         #if     __FreeBSD_version < 503000
 307         static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
 308         #else
 309         static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 310         #endif
 311 #endif
 312 {
 313         #if     __FreeBSD_version < 503000
 314                 struct AdapterControlBlock *acb = dev->si_drv1;
 315         #else
 316                 int     unit = dev2unit(dev);
 317                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 318         #endif
 319         if(acb == NULL) {
 320                 return ENXIO;
 321         }
 322         return 0;
 323 }
 324 /*
 325 **************************************************************************
 326 **************************************************************************
 327 */
 328 #if     __FreeBSD_version < 500005
 329         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
 330 #else
 331         #if     __FreeBSD_version < 503000
 332         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 333         #else
 334         static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 335         #endif
 336 #endif
 337 {
 338         #if     __FreeBSD_version < 503000
 339                 struct AdapterControlBlock *acb = dev->si_drv1;
 340         #else
 341                 int     unit = dev2unit(dev);
 342                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 343         #endif
 344
 345         if(acb == NULL) {
 346                 return ENXIO;
 347         }
 348         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 349 }
 350 /*
 351 **********************************************************************
 352 **********************************************************************
 353 */
 354 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 355 {
 356         u_int32_t intmask_org = 0;
 357
 358         switch (acb->adapter_type) {
 359         case ACB_ADAPTER_TYPE_A: {
 360                         /* disable all outbound interrupt */
 361                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 362                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 363                 }
 364                 break;
 365         case ACB_ADAPTER_TYPE_B: {
 366                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 367                         /* disable all outbound interrupt */
 368                         intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
 369                                                 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 370                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
 371                 }
 372                 break;
 373         case ACB_ADAPTER_TYPE_C: {
 374                         /* disable all outbound interrupt */
 375                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 376                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 377                 }
 378                 break;
 379         case ACB_ADAPTER_TYPE_D: {
 380                         /* disable all outbound interrupt */
 381                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 382                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 383                 }
 384                 break;
 385         case ACB_ADAPTER_TYPE_E: {
 386                         /* disable all outbound interrupt */
 387                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 388                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
 389                 }
 390                 break;
 391         }
 392         return (intmask_org);
 393 }
 394 /*
 395 **********************************************************************
 396 **********************************************************************
 397 */
 398 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 399 {
 400         u_int32_t mask;
 401
 402         switch (acb->adapter_type) {
 403         case ACB_ADAPTER_TYPE_A: {
 404                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 405                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 406                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 407                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 408                 }
 409                 break;
 410         case ACB_ADAPTER_TYPE_B: {
 411                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 412                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 413                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 414                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 415                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 416                 }
 417                 break;
 418         case ACB_ADAPTER_TYPE_C: {
 419                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 420                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 421                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 422                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 423                 }
 424                 break;
 425         case ACB_ADAPTER_TYPE_D: {
 426                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 427                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 428                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 429                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 430                         acb->outbound_int_enable = mask;
 431                 }
 432                 break;
 433         case ACB_ADAPTER_TYPE_E: {
 434                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 435                         mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
 436                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
 437                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 438                 }
 439                 break;
 440         }
 441 }
 442 /*
 443 **********************************************************************
 444 **********************************************************************
 445 */
 446 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 447 {
 448         u_int32_t Index;
 449         u_int8_t Retries = 0x00;
 450
 451         do {
 452                 for(Index=0; Index < 100; Index++) {
 453                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 454                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 455                                 return TRUE;
 456                         }
 457                         UDELAY(10000);
 458                 }/*max 1 seconds*/
 459         }while(Retries++ < 20);/*max 20 sec*/
 460         return (FALSE);
 461 }
 462 /*
 463 **********************************************************************
 464 **********************************************************************
 465 */
 466 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 467 {
 468         u_int32_t Index;
 469         u_int8_t Retries = 0x00;
 470         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 471
 472         do {
 473                 for(Index=0; Index < 100; Index++) {
 474                         if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 475                                 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 476                                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 477                                 return TRUE;
 478                         }
 479                         UDELAY(10000);
 480                 }/*max 1 seconds*/
 481         }while(Retries++ < 20);/*max 20 sec*/
 482         return (FALSE);
 483 }
 484 /*
 485 **********************************************************************
 486 **********************************************************************
 487 */
 488 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 489 {
 490         u_int32_t Index;
 491         u_int8_t Retries = 0x00;
 492
 493         do {
 494                 for(Index=0; Index < 100; Index++) {
 495                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 496                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 497                                 return TRUE;
 498                         }
 499                         UDELAY(10000);
 500                 }/*max 1 seconds*/
 501         }while(Retries++ < 20);/*max 20 sec*/
 502         return (FALSE);
 503 }
 504 /*
 505 **********************************************************************
 506 **********************************************************************
 507 */
 508 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 509 {
 510         u_int32_t Index;
 511         u_int8_t Retries = 0x00;
 512
 513         do {
 514                 for(Index=0; Index < 100; Index++) {
 515                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 516                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 517                                 return TRUE;
 518                         }
 519                         UDELAY(10000);
 520                 }/*max 1 seconds*/
 521         }while(Retries++ < 20);/*max 20 sec*/
 522         return (FALSE);
 523 }
 524 /*
 525 **********************************************************************
 526 **********************************************************************
 527 */
 528 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
 529 {
 530         u_int32_t Index, read_doorbell;
 531         u_int8_t Retries = 0x00;
 532
 533         do {
 534                 for(Index=0; Index < 100; Index++) {
 535                         read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
 536                         if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
 537                                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
 538                                 acb->in_doorbell = read_doorbell;
 539                                 return TRUE;
 540                         }
 541                         UDELAY(10000);
 542                 }/*max 1 seconds*/
 543         }while(Retries++ < 20);/*max 20 sec*/
 544         return (FALSE);
 545 }
 546 /*
 547 ************************************************************************
 548 ************************************************************************
 549 */
 550 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 551 {
 552         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 553
 554         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 555         do {
 556                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 557                         break;
 558                 } else {
 559                         retry_count--;
 560                 }
 561         }while(retry_count != 0);
 562 }
 563 /*
 564 ************************************************************************
 565 ************************************************************************
 566 */
 567 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 568 {
 569         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 570         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 571
 572         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 573         do {
 574                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 575                         break;
 576                 } else {
 577                         retry_count--;
 578                 }
 579         }while(retry_count != 0);
 580 }
 581 /*
 582 ************************************************************************
 583 ************************************************************************
 584 */
 585 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 586 {
 587         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 588
 589         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 590         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 591         do {
 592                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 593                         break;
 594                 } else {
 595                         retry_count--;
 596                 }
 597         }while(retry_count != 0);
 598 }
 599 /*
 600 ************************************************************************
 601 ************************************************************************
 602 */
 603 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 604 {
 605         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 606
 607         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 608         do {
 609                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 610                         break;
 611                 } else {
 612                         retry_count--;
 613                 }
 614         }while(retry_count != 0);
 615 }
 616 /*
 617 ************************************************************************
 618 ************************************************************************
 619 */
 620 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
 621 {
 622         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 623
 624         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 625         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 626         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 627         do {
 628                 if(arcmsr_hbe_wait_msgint_ready(acb)) {
 629                         break;
 630                 } else {
 631                         retry_count--;
 632                 }
 633         }while(retry_count != 0);
 634 }
 635 /*
 636 ************************************************************************
 637 ************************************************************************
 638 */
 639 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 640 {
 641         switch (acb->adapter_type) {
 642         case ACB_ADAPTER_TYPE_A: {
 643                         arcmsr_flush_hba_cache(acb);
 644                 }
 645                 break;
 646         case ACB_ADAPTER_TYPE_B: {
 647                         arcmsr_flush_hbb_cache(acb);
 648                 }
 649                 break;
 650         case ACB_ADAPTER_TYPE_C: {
 651                         arcmsr_flush_hbc_cache(acb);
 652                 }
 653                 break;
 654         case ACB_ADAPTER_TYPE_D: {
 655                         arcmsr_flush_hbd_cache(acb);
 656                 }
 657                 break;
 658         case ACB_ADAPTER_TYPE_E: {
 659                         arcmsr_flush_hbe_cache(acb);
 660                 }
 661                 break;
 662         }
 663 }
 664 /*
 665 *******************************************************************************
 666 *******************************************************************************
 667 */
 668 static int arcmsr_suspend(device_t dev)
 669 {
 670         struct AdapterControlBlock      *acb = device_get_softc(dev);
 671
 672         /* flush controller */
 673         arcmsr_iop_parking(acb);
 674         /* disable all outbound interrupt */
 675         arcmsr_disable_allintr(acb);
 676         return(0);
 677 }
 678 /*
 679 *******************************************************************************
 680 *******************************************************************************
 681 */
 682 static int arcmsr_resume(device_t dev)
 683 {
 684         struct AdapterControlBlock      *acb = device_get_softc(dev);
 685
 686         arcmsr_iop_init(acb);
 687         return(0);
 688 }
 689 /*
 690 *********************************************************************************
 691 *********************************************************************************
 692 */
 693 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 694 {
 695         struct AdapterControlBlock *acb;
 696         u_int8_t target_id, target_lun;
 697         struct cam_sim *sim;
 698
 699         sim = (struct cam_sim *) cb_arg;
 700         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 701         switch (code) {
 702         case AC_LOST_DEVICE:
 703                 target_id = xpt_path_target_id(path);
 704                 target_lun = xpt_path_lun_id(path);
 705                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 706                         break;
 707                 }
 708         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 709                 break;
 710         default:
 711                 break;
 712         }
 713 }
 714 /*
 715 **********************************************************************
 716 **********************************************************************
 717 */
 718 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 719 {
 720         union ccb *pccb = srb->pccb;
 721
 722         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 723         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 724         if(pccb->csio.sense_len) {
 725                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 726                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 727                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 728                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 729                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 730         }
 731 }
 732 /*
 733 *********************************************************************
 734 *********************************************************************
 735 */
 736 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 737 {
 738         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 739         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 740                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 741         }
 742 }
 743 /*
 744 *********************************************************************
 745 *********************************************************************
 746 */
 747 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 748 {
 749         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 750         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 751         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 752                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 753         }
 754 }
 755 /*
 756 *********************************************************************
 757 *********************************************************************
 758 */
 759 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 760 {
 761         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 762         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 763         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 764                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 765         }
 766 }
 767 /*
 768 *********************************************************************
 769 *********************************************************************
 770 */
 771 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 772 {
 773         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 774         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 775                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 776         }
 777 }
 778 /*
 779 *********************************************************************
 780 *********************************************************************
 781 */
 782 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
 783 {
 784         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 785         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 786         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 787         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
 788                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 789         }
 790 }
 791 /*
 792 *********************************************************************
 793 *********************************************************************
 794 */
 795 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 796 {
 797         switch (acb->adapter_type) {
 798         case ACB_ADAPTER_TYPE_A: {
 799                         arcmsr_abort_hba_allcmd(acb);
 800                 }
 801                 break;
 802         case ACB_ADAPTER_TYPE_B: {
 803                         arcmsr_abort_hbb_allcmd(acb);
 804                 }
 805                 break;
 806         case ACB_ADAPTER_TYPE_C: {
 807                         arcmsr_abort_hbc_allcmd(acb);
 808                 }
 809                 break;
 810         case ACB_ADAPTER_TYPE_D: {
 811                         arcmsr_abort_hbd_allcmd(acb);
 812                 }
 813                 break;
 814         case ACB_ADAPTER_TYPE_E: {
 815                         arcmsr_abort_hbe_allcmd(acb);
 816                 }
 817                 break;
 818         }
 819 }
 820 /*
 821 **********************************************************************
 822 **********************************************************************
 823 */
 824 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 825 {
 826         struct AdapterControlBlock *acb = srb->acb;
 827         union ccb *pccb = srb->pccb;
 828
 829         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 830                 callout_stop(&srb->ccb_callout);
 831         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 832                 bus_dmasync_op_t op;
 833
 834                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 835                         op = BUS_DMASYNC_POSTREAD;
 836                 } else {
 837                         op = BUS_DMASYNC_POSTWRITE;
 838                 }
 839                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 840                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 841         }
 842         if(stand_flag == 1) {
 843                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 844                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 845                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 846                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 847                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 848                 }
 849         }
 850         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 851                 arcmsr_free_srb(srb);
 852         acb->pktReturnCount++;
 853         xpt_done(pccb);
 854 }
 855 /*
 856 **************************************************************************
 857 **************************************************************************
 858 */
 859 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 860 {
 861         int target, lun;
 862
 863         target = srb->pccb->ccb_h.target_id;
 864         lun = srb->pccb->ccb_h.target_lun;
 865         if(error == FALSE) {
 866                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 867                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 868                 }
 869                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 870                 arcmsr_srb_complete(srb, 1);
 871         } else {
 872                 switch(srb->arcmsr_cdb.DeviceStatus) {
 873                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 874                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 875                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 876                                 }
 877                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 878                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 879                                 arcmsr_srb_complete(srb, 1);
 880                         }
 881                         break;
 882                 case ARCMSR_DEV_ABORTED:
 883                 case ARCMSR_DEV_INIT_FAIL: {
 884                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 885                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 886                                 arcmsr_srb_complete(srb, 1);
 887                         }
 888                         break;
 889                 case SCSISTAT_CHECK_CONDITION: {
 890                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 891                                 arcmsr_report_sense_info(srb);
 892                                 arcmsr_srb_complete(srb, 1);
 893                         }
 894                         break;
 895                 default:
 896                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 897                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 898                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 899                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 900                         /*unknown error or crc error just for retry*/
 901                         arcmsr_srb_complete(srb, 1);
 902                         break;
 903                 }
 904         }
 905 }
 906 /*
 907 **************************************************************************
 908 **************************************************************************
 909 */
 910 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 911 {
 912         struct CommandControlBlock *srb;
 913
 914         /* check if command done with no error*/
 915         switch (acb->adapter_type) {
 916         case ACB_ADAPTER_TYPE_A:
 917         case ACB_ADAPTER_TYPE_B:
 918                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 919                 break;
 920         case ACB_ADAPTER_TYPE_C:
 921         case ACB_ADAPTER_TYPE_D:
 922                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 923                 break;
 924         case ACB_ADAPTER_TYPE_E:
 925                 srb = acb->psrb_pool[flag_srb];
 926                 break;
 927         default:
 928                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 929                 break;
 930         }
 931         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 932                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 933                         arcmsr_free_srb(srb);
 934                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 935                         return;
 936                 }
 937                 printf("arcmsr%d: return srb has been completed\n"
 938                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 939                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 940                 return;
 941         }
 942         arcmsr_report_srb_state(acb, srb, error);
 943 }
 944 /*
 945 **************************************************************************
 946 **************************************************************************
 947 */
 948 static void     arcmsr_srb_timeout(void *arg)
 949 {
 950         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 951         struct AdapterControlBlock *acb;
 952         int target, lun;
 953         u_int8_t cmd;
 954
 955         target = srb->pccb->ccb_h.target_id;
 956         lun = srb->pccb->ccb_h.target_lun;
 957         acb = srb->acb;
 958         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 959         if(srb->srb_state == ARCMSR_SRB_START)
 960         {
 961                 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
 962                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 963                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 964                 arcmsr_srb_complete(srb, 1);
 965                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 966                                  acb->pci_unit, target, lun, cmd, srb);
 967         }
 968         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 969 #ifdef ARCMSR_DEBUG1
 970         arcmsr_dump_data(acb);
 971 #endif
 972 }
 973
 974 /*
 975 **********************************************************************
 976 **********************************************************************
 977 */
 978 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 979 {
 980         int i=0;
 981         u_int32_t flag_srb;
 982         u_int16_t error;
 983
 984         switch (acb->adapter_type) {
 985         case ACB_ADAPTER_TYPE_A: {
 986                         u_int32_t outbound_intstatus;
 987
 988                         /*clear and abort all outbound posted Q*/
 989                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 990                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 991                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 992                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 993                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 994                         }
 995                 }
 996                 break;
 997         case ACB_ADAPTER_TYPE_B: {
 998                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 999
1000                         /*clear all outbound posted Q*/
1001                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
1002                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1003                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
1004                                         phbbmu->done_qbuffer[i] = 0;
1005                                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1006                                         arcmsr_drain_donequeue(acb, flag_srb, error);
1007                                 }
1008                                 phbbmu->post_qbuffer[i] = 0;
1009                         }/*drain reply FIFO*/
1010                         phbbmu->doneq_index = 0;
1011                         phbbmu->postq_index = 0;
1012                 }
1013                 break;
1014         case ACB_ADAPTER_TYPE_C: {
1015
1016                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1017                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1018                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
1019                                 arcmsr_drain_donequeue(acb, flag_srb, error);
1020                         }
1021                 }
1022                 break;
1023         case ACB_ADAPTER_TYPE_D: {
1024                         arcmsr_hbd_postqueue_isr(acb);
1025                 }
1026                 break;
1027         case ACB_ADAPTER_TYPE_E: {
1028                         arcmsr_hbe_postqueue_isr(acb);
1029                 }
1030                 break;
1031         }
1032 }
1033 /*
1034 ****************************************************************************
1035 ****************************************************************************
1036 */
1037 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
1038 {
1039         struct CommandControlBlock *srb;
1040         u_int32_t intmask_org;
1041         u_int32_t i=0;
1042
1043         if(acb->srboutstandingcount>0) {
1044                 /* disable all outbound interrupt */
1045                 intmask_org = arcmsr_disable_allintr(acb);
1046                 /*clear and abort all outbound posted Q*/
1047                 arcmsr_done4abort_postqueue(acb);
1048                 /* talk to iop 331 outstanding command aborted*/
1049                 arcmsr_abort_allcmd(acb);
1050                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
1051                         srb = acb->psrb_pool[i];
1052                         if(srb->srb_state == ARCMSR_SRB_START) {
1053                                 srb->srb_state = ARCMSR_SRB_ABORTED;
1054                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1055                                 arcmsr_srb_complete(srb, 1);
1056                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
1057                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
1058                                                 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
1059                         }
1060                 }
1061                 /* enable all outbound interrupt */
1062                 arcmsr_enable_allintr(acb, intmask_org);
1063         }
1064         acb->srboutstandingcount = 0;
1065         acb->workingsrb_doneindex = 0;
1066         acb->workingsrb_startindex = 0;
1067         acb->pktRequestCount = 0;
1068         acb->pktReturnCount = 0;
1069 }
1070 /*
1071 **********************************************************************
1072 **********************************************************************
1073 */
1074 static void arcmsr_build_srb(struct CommandControlBlock *srb,
1075                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
1076 {
1077         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
1078         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
1079         u_int32_t address_lo, address_hi;
1080         union ccb *pccb = srb->pccb;
1081         struct ccb_scsiio *pcsio = &pccb->csio;
1082         u_int32_t arccdbsize = 0x30;
1083
1084         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1085         arcmsr_cdb->Bus = 0;
1086         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1087         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1088         arcmsr_cdb->Function = 1;
1089         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1090         bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1091         if(nseg != 0) {
1092                 struct AdapterControlBlock *acb = srb->acb;
1093                 bus_dmasync_op_t op;
1094                 u_int32_t length, i, cdb_sgcount = 0;
1095
1096                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1097                         op = BUS_DMASYNC_PREREAD;
1098                 } else {
1099                         op = BUS_DMASYNC_PREWRITE;
1100                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1101                         srb->srb_flags |= SRB_FLAG_WRITE;
1102                 }
1103                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1104                 for(i=0; i < nseg; i++) {
1105                         /* Get the physical address of the current data pointer */
1106                         length = arcmsr_htole32(dm_segs[i].ds_len);
1107                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1108                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1109                         if(address_hi == 0) {
1110                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1111                                 pdma_sg->address = address_lo;
1112                                 pdma_sg->length = length;
1113                                 psge += sizeof(struct SG32ENTRY);
1114                                 arccdbsize += sizeof(struct SG32ENTRY);
1115                         } else {
1116                                 u_int32_t sg64s_size = 0, tmplength = length;
1117
1118                                 while(1) {
1119                                         u_int64_t span4G, length0;
1120                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1121
1122                                         span4G = (u_int64_t)address_lo + tmplength;
1123                                         pdma_sg->addresshigh = address_hi;
1124                                         pdma_sg->address = address_lo;
1125                                         if(span4G > 0x100000000) {
1126                                                 /*see if cross 4G boundary*/
1127                                                 length0 = 0x100000000-address_lo;
1128                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1129                                                 address_hi = address_hi+1;
1130                                                 address_lo = 0;
1131                                                 tmplength = tmplength - (u_int32_t)length0;
1132                                                 sg64s_size += sizeof(struct SG64ENTRY);
1133                                                 psge += sizeof(struct SG64ENTRY);
1134                                                 cdb_sgcount++;
1135                                         } else {
1136                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1137                                                 sg64s_size += sizeof(struct SG64ENTRY);
1138                                                 psge += sizeof(struct SG64ENTRY);
1139                                                 break;
1140                                         }
1141                                 }
1142                                 arccdbsize += sg64s_size;
1143                         }
1144                         cdb_sgcount++;
1145                 }
1146                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1147                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1148                 if( arccdbsize > 256) {
1149                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1150                 }
1151         } else {
1152                 arcmsr_cdb->DataLength = 0;
1153         }
1154         srb->arc_cdb_size = arccdbsize;
1155         arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1156 }
1157 /*
1158 **************************************************************************
1159 **************************************************************************
1160 */
1161 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1162 {
1163         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1164         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1165
1166         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1167         atomic_add_int(&acb->srboutstandingcount, 1);
1168         srb->srb_state = ARCMSR_SRB_START;
1169
1170         switch (acb->adapter_type) {
1171         case ACB_ADAPTER_TYPE_A: {
1172                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1173                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1174                         } else {
1175                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1176                         }
1177                 }
1178                 break;
1179         case ACB_ADAPTER_TYPE_B: {
1180                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1181                         int ending_index, index;
1182
1183                         index = phbbmu->postq_index;
1184                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1185                         phbbmu->post_qbuffer[ending_index] = 0;
1186                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1187                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1188                         } else {
1189                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1190                         }
1191                         index++;
1192                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1193                         phbbmu->postq_index = index;
1194                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1195                 }
1196                 break;
1197         case ACB_ADAPTER_TYPE_C: {
1198                         u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1199
1200                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1201                         ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1202                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1203                         if(cdb_phyaddr_hi32)
1204                         {
1205                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1206                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1207                         }
1208                         else
1209                         {
1210                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1211                         }
1212                 }
1213                 break;
1214         case ACB_ADAPTER_TYPE_D: {
1215                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1216                         u_int16_t index_stripped;
1217                         u_int16_t postq_index;
1218                         struct InBound_SRB *pinbound_srb;
1219
1220                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1221                         postq_index = phbdmu->postq_index;
1222                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1223                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1224                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1225                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1226                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1227                         if (postq_index & 0x4000) {
1228                                 index_stripped = postq_index & 0xFF;
1229                                 index_stripped += 1;
1230                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1231                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1232                         } else {
1233                                 index_stripped = postq_index;
1234                                 index_stripped += 1;
1235                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1236                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1237                         }
1238                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1239                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1240                 }
1241                 break;
1242         case ACB_ADAPTER_TYPE_E: {
1243                         u_int32_t ccb_post_stamp, arc_cdb_size;
1244
1245                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1246                         ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1247                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1248                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1249                 }
1250                 break;
1251         }
1252 }
1253 /*
1254 ************************************************************************
1255 ************************************************************************
1256 */
1257 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1258 {
1259         struct QBUFFER *qbuffer=NULL;
1260
1261         switch (acb->adapter_type) {
1262         case ACB_ADAPTER_TYPE_A: {
1263                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1264
1265                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1266                 }
1267                 break;
1268         case ACB_ADAPTER_TYPE_B: {
1269                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1270
1271                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1272                 }
1273                 break;
1274         case ACB_ADAPTER_TYPE_C: {
1275                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1276
1277                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1278                 }
1279                 break;
1280         case ACB_ADAPTER_TYPE_D: {
1281                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1282
1283                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1284                 }
1285                 break;
1286         case ACB_ADAPTER_TYPE_E: {
1287                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1288
1289                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1290                 }
1291                 break;
1292         }
1293         return(qbuffer);
1294 }
1295 /*
1296 ************************************************************************
1297 ************************************************************************
1298 */
1299 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1300 {
1301         struct QBUFFER *qbuffer = NULL;
1302
1303         switch (acb->adapter_type) {
1304         case ACB_ADAPTER_TYPE_A: {
1305                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1306
1307                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1308                 }
1309                 break;
1310         case ACB_ADAPTER_TYPE_B: {
1311                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1312
1313                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1314                 }
1315                 break;
1316         case ACB_ADAPTER_TYPE_C: {
1317                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1318
1319                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1320                 }
1321                 break;
1322         case ACB_ADAPTER_TYPE_D: {
1323                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1324
1325                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1326                 }
1327                 break;
1328         case ACB_ADAPTER_TYPE_E: {
1329                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1330
1331                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1332                 }
1333                 break;
1334         }
1335         return(qbuffer);
1336 }
1337 /*
1338 **************************************************************************
1339 **************************************************************************
1340 */
1341 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1342 {
1343         switch (acb->adapter_type) {
1344         case ACB_ADAPTER_TYPE_A: {
1345                         /* let IOP know data has been read */
1346                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1347                 }
1348                 break;
1349         case ACB_ADAPTER_TYPE_B: {
1350                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1351                         /* let IOP know data has been read */
1352                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1353                 }
1354                 break;
1355         case ACB_ADAPTER_TYPE_C: {
1356                         /* let IOP know data has been read */
1357                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1358                 }
1359                 break;
1360         case ACB_ADAPTER_TYPE_D: {
1361                         /* let IOP know data has been read */
1362                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1363                 }
1364                 break;
1365         case ACB_ADAPTER_TYPE_E: {
1366                         /* let IOP know data has been read */
1367                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1368                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1369                 }
1370                 break;
1371         }
1372 }
1373 /*
1374 **************************************************************************
1375 **************************************************************************
1376 */
1377 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1378 {
1379         switch (acb->adapter_type) {
1380         case ACB_ADAPTER_TYPE_A: {
1381                         /*
1382                         ** push inbound doorbell tell iop, driver data write ok
1383                         ** and wait reply on next hwinterrupt for next Qbuffer post
1384                         */
1385                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1386                 }
1387                 break;
1388         case ACB_ADAPTER_TYPE_B: {
1389                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1390                         /*
1391                         ** push inbound doorbell tell iop, driver data write ok
1392                         ** and wait reply on next hwinterrupt for next Qbuffer post
1393                         */
1394                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1395                 }
1396                 break;
1397         case ACB_ADAPTER_TYPE_C: {
1398                         /*
1399                         ** push inbound doorbell tell iop, driver data write ok
1400                         ** and wait reply on next hwinterrupt for next Qbuffer post
1401                         */
1402                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1403                 }
1404                 break;
1405         case ACB_ADAPTER_TYPE_D: {
1406                         /*
1407                         ** push inbound doorbell tell iop, driver data write ok
1408                         ** and wait reply on next hwinterrupt for next Qbuffer post
1409                         */
1410                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1411                 }
1412                 break;
1413         case ACB_ADAPTER_TYPE_E: {
1414                         /*
1415                         ** push inbound doorbell tell iop, driver data write ok
1416                         ** and wait reply on next hwinterrupt for next Qbuffer post
1417                         */
1418                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1419                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1420                 }
1421                 break;
1422         }
1423 }
1424 /*
1425 ************************************************************************
1426 ************************************************************************
1427 */
1428 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1429 {
1430         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1431         CHIP_REG_WRITE32(HBA_MessageUnit,
1432                 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1433         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1434                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1435                         , acb->pci_unit);
1436         }
1437 }
1438 /*
1439 ************************************************************************
1440 ************************************************************************
1441 */
1442 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1443 {
1444         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1445         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1446         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1447         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1448                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1449                         , acb->pci_unit);
1450         }
1451 }
1452 /*
1453 ************************************************************************
1454 ************************************************************************
1455 */
1456 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1457 {
1458         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1459         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1460         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1461         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1462                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1463         }
1464 }
1465 /*
1466 ************************************************************************
1467 ************************************************************************
1468 */
1469 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1470 {
1471         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1472         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1473         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1474                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1475         }
1476 }
1477 /*
1478 ************************************************************************
1479 ************************************************************************
1480 */
1481 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1482 {
1483         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1484         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1485         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1486         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1487         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1488                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1489         }
1490 }
1491 /*
1492 ************************************************************************
1493 ************************************************************************
1494 */
1495 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1496 {
1497         switch (acb->adapter_type) {
1498         case ACB_ADAPTER_TYPE_A: {
1499                         arcmsr_stop_hba_bgrb(acb);
1500                 }
1501                 break;
1502         case ACB_ADAPTER_TYPE_B: {
1503                         arcmsr_stop_hbb_bgrb(acb);
1504                 }
1505                 break;
1506         case ACB_ADAPTER_TYPE_C: {
1507                         arcmsr_stop_hbc_bgrb(acb);
1508                 }
1509                 break;
1510         case ACB_ADAPTER_TYPE_D: {
1511                         arcmsr_stop_hbd_bgrb(acb);
1512                 }
1513                 break;
1514         case ACB_ADAPTER_TYPE_E: {
1515                         arcmsr_stop_hbe_bgrb(acb);
1516                 }
1517                 break;
1518         }
1519 }
1520 /*
1521 ************************************************************************
1522 ************************************************************************
1523 */
1524 static void arcmsr_poll(struct cam_sim *psim)
1525 {
1526         struct AdapterControlBlock *acb;
1527         int     mutex;
1528
1529         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1530         mutex = mtx_owned(&acb->isr_lock);
1531         if( mutex == 0 )
1532                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1533         arcmsr_interrupt(acb);
1534         if( mutex == 0 )
1535                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1536 }
1537 /*
1538 **************************************************************************
1539 **************************************************************************
1540 */
1541 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1542         struct QBUFFER *prbuffer) {
1543
1544         u_int8_t *pQbuffer;
1545         u_int8_t *buf1 = NULL;
1546         u_int32_t *iop_data, *buf2 = NULL;
1547         u_int32_t iop_len, data_len;
1548
1549         iop_data = (u_int32_t *)prbuffer->data;
1550         iop_len = (u_int32_t)prbuffer->data_len;
1551         if ( iop_len > 0 )
1552         {
1553                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1554                 buf2 = (u_int32_t *)buf1;
1555                 if( buf1 == NULL)
1556                         return (0);
1557                 data_len = iop_len;
1558                 while(data_len >= 4)
1559                 {
1560                         *buf2++ = *iop_data++;
1561                         data_len -= 4;
1562                 }
1563                 if(data_len)
1564                         *buf2 = *iop_data;
1565                 buf2 = (u_int32_t *)buf1;
1566         }
1567         while (iop_len > 0) {
1568                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1569                 *pQbuffer = *buf1;
1570                 acb->rqbuf_lastindex++;
1571                 /* if last, index number set it to 0 */
1572                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1573                 buf1++;
1574                 iop_len--;
1575         }
1576         if(buf2)
1577                 free( (u_int8_t *)buf2, M_DEVBUF);
1578         /* let IOP know data has been read */
1579         arcmsr_iop_message_read(acb);
1580         return (1);
1581 }
1582 /*
1583 **************************************************************************
1584 **************************************************************************
1585 */
1586 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1587         struct QBUFFER *prbuffer) {
1588
1589         u_int8_t *pQbuffer;
1590         u_int8_t *iop_data;
1591         u_int32_t iop_len;
1592
1593         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1594                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1595         }
1596         iop_data = (u_int8_t *)prbuffer->data;
1597         iop_len = (u_int32_t)prbuffer->data_len;
1598         while (iop_len > 0) {
1599                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1600                 *pQbuffer = *iop_data;
1601                 acb->rqbuf_lastindex++;
1602                 /* if last, index number set it to 0 */
1603                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1604                 iop_data++;
1605                 iop_len--;
1606         }
1607         /* let IOP know data has been read */
1608         arcmsr_iop_message_read(acb);
1609         return (1);
1610 }
1611 /*
1612 **************************************************************************
1613 **************************************************************************
1614 */
1615 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1616 {
1617         struct QBUFFER *prbuffer;
1618         int my_empty_len;
1619
1620         /*check this iop data if overflow my rqbuffer*/
1621         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1622         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1623         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1624                 (ARCMSR_MAX_QBUFFER-1);
1625         if(my_empty_len >= prbuffer->data_len) {
1626                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1627                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1628         } else {
1629                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1630         }
1631         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1632 }
1633 /*
1634 **********************************************************************
1635 **********************************************************************
1636 */
1637 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1638 {
1639         u_int8_t *pQbuffer;
1640         struct QBUFFER *pwbuffer;
1641         u_int8_t *buf1 = NULL;
1642         u_int32_t *iop_data, *buf2 = NULL;
1643         u_int32_t allxfer_len = 0, data_len;
1644
1645         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1646                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1647                 buf2 = (u_int32_t *)buf1;
1648                 if( buf1 == NULL)
1649                         return;
1650
1651                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1652                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1653                 iop_data = (u_int32_t *)pwbuffer->data;
1654                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1655                         && (allxfer_len < 124)) {
1656                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1657                         *buf1 = *pQbuffer;
1658                         acb->wqbuf_firstindex++;
1659                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1660                         buf1++;
1661                         allxfer_len++;
1662                 }
1663                 pwbuffer->data_len = allxfer_len;
1664                 data_len = allxfer_len;
1665                 buf1 = (u_int8_t *)buf2;
1666                 while(data_len >= 4)
1667                 {
1668                         *iop_data++ = *buf2++;
1669                         data_len -= 4;
1670                 }
1671                 if(data_len)
1672                         *iop_data = *buf2;
1673                 free( buf1, M_DEVBUF);
1674                 arcmsr_iop_message_wrote(acb);
1675         }
1676 }
1677 /*
1678 **********************************************************************
1679 **********************************************************************
1680 */
1681 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1682 {
1683         u_int8_t *pQbuffer;
1684         struct QBUFFER *pwbuffer;
1685         u_int8_t *iop_data;
1686         int32_t allxfer_len=0;
1687
1688         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1689                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1690                 return;
1691         }
1692         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1693                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1694                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1695                 iop_data = (u_int8_t *)pwbuffer->data;
1696                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1697                         && (allxfer_len < 124)) {
1698                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1699                         *iop_data = *pQbuffer;
1700                         acb->wqbuf_firstindex++;
1701                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1702                         iop_data++;
1703                         allxfer_len++;
1704                 }
1705                 pwbuffer->data_len = allxfer_len;
1706                 arcmsr_iop_message_wrote(acb);
1707         }
1708 }
1709 /*
1710 **************************************************************************
1711 **************************************************************************
1712 */
1713 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1714 {
1715         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1716         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1717         /*
1718         *****************************************************************
1719         **   check if there are any mail packages from user space program
1720         **   in my post bag, now is the time to send them into Areca's firmware
1721         *****************************************************************
1722         */
1723         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1724                 arcmsr_Write_data_2iop_wqbuffer(acb);
1725         }
1726         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1727                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1728         }
1729         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1730 }
1731 /*
1732 **************************************************************************
1733 **************************************************************************
1734 */
1735 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1736 {
1737 /*
1738         if (ccb->ccb_h.status != CAM_REQ_CMP)
1739                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1740                         "failure status=%x\n", ccb->ccb_h.target_id,
1741                         ccb->ccb_h.target_lun, ccb->ccb_h.status);
1742         else
1743                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1744 */
1745         xpt_free_path(ccb->ccb_h.path);
1746         xpt_free_ccb(ccb);
1747 }
1748
1749 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1750 {
1751         struct cam_path     *path;
1752         union ccb           *ccb;
1753
1754         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1755                         return;
1756         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1757         {
1758                 xpt_free_ccb(ccb);
1759                 return;
1760         }
1761 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1762         bzero(ccb, sizeof(union ccb));
1763         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1764         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1765         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1766         ccb->crcn.flags = CAM_FLAG_NONE;
1767         xpt_action(ccb);
1768 }
1769
1770
1771 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1772 {
1773         struct CommandControlBlock *srb;
1774         u_int32_t intmask_org;
1775         int i;
1776
1777         /* disable all outbound interrupts */
1778         intmask_org = arcmsr_disable_allintr(acb);
1779         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1780         {
1781                 srb = acb->psrb_pool[i];
1782                 if (srb->srb_state == ARCMSR_SRB_START)
1783                 {
1784                         if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1785                         {
1786                                 srb->srb_state = ARCMSR_SRB_ABORTED;
1787                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1788                                 arcmsr_srb_complete(srb, 1);
1789                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1790                         }
1791                 }
1792         }
1793         /* enable outbound Post Queue, outbound doorbell Interrupt */
1794         arcmsr_enable_allintr(acb, intmask_org);
1795 }
1796 /*
1797 **************************************************************************
1798 **************************************************************************
1799 */
1800 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1801         u_int32_t       devicemap;
1802         u_int32_t       target, lun;
1803         u_int32_t       deviceMapCurrent[4]={0};
1804         u_int8_t        *pDevMap;
1805
1806         switch (acb->adapter_type) {
1807         case ACB_ADAPTER_TYPE_A:
1808                 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1809                 for (target = 0; target < 4; target++)
1810                 {
1811                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1812                         devicemap += 4;
1813                 }
1814                 break;
1815
1816         case ACB_ADAPTER_TYPE_B:
1817                 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1818                 for (target = 0; target < 4; target++)
1819                 {
1820                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1821                         devicemap += 4;
1822                 }
1823                 break;
1824
1825         case ACB_ADAPTER_TYPE_C:
1826                 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1827                 for (target = 0; target < 4; target++)
1828                 {
1829                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1830                         devicemap += 4;
1831                 }
1832                 break;
1833         case ACB_ADAPTER_TYPE_D:
1834                 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1835                 for (target = 0; target < 4; target++)
1836                 {
1837                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1838                         devicemap += 4;
1839                 }
1840                 break;
1841         case ACB_ADAPTER_TYPE_E:
1842                 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1843                 for (target = 0; target < 4; target++)
1844                 {
1845                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1846                         devicemap += 4;
1847                 }
1848                 break;
1849         }
1850
1851         if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1852         {
1853                 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1854         }
1855         /*
1856         ** adapter posted CONFIG message
1857         ** copy the new map, note if there are differences with the current map
1858         */
1859         pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1860         for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1861         {
1862                 if (*pDevMap != acb->device_map[target])
1863                 {
1864                         u_int8_t difference, bit_check;
1865
1866                         difference = *pDevMap ^ acb->device_map[target];
1867                         for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1868                         {
1869                                 bit_check = (1 << lun);         /*check bit from 0....31*/
1870                                 if(difference & bit_check)
1871                                 {
1872                                         if(acb->device_map[target] & bit_check)
1873                                         {/* unit departed */
1874                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1875                                                 arcmsr_abort_dr_ccbs(acb, target, lun);
1876                                                 arcmsr_rescan_lun(acb, target, lun);
1877                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1878                                         }
1879                                         else
1880                                         {/* unit arrived */
1881                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1882                                                 arcmsr_rescan_lun(acb, target, lun);
1883                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1884                                         }
1885                                 }
1886                         }
1887 /*                      printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1888                         acb->device_map[target] = *pDevMap;
1889                 }
1890                 pDevMap++;
1891         }
1892 }
1893 /*
1894 **************************************************************************
1895 **************************************************************************
1896 */
1897 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1898         u_int32_t outbound_message;
1899
1900         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1901         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1902         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1903                 arcmsr_dr_handle( acb );
1904 }
1905 /*
1906 **************************************************************************
1907 **************************************************************************
1908 */
1909 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1910         u_int32_t outbound_message;
1911         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1912
1913         /* clear interrupts */
1914         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1915         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1916         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1917                 arcmsr_dr_handle( acb );
1918 }
1919 /*
1920 **************************************************************************
1921 **************************************************************************
1922 */
1923 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1924         u_int32_t outbound_message;
1925
1926         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1927         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1928         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1929                 arcmsr_dr_handle( acb );
1930 }
1931 /*
1932 **************************************************************************
1933 **************************************************************************
1934 */
1935 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1936         u_int32_t outbound_message;
1937
1938         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1939         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1940         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1941                 arcmsr_dr_handle( acb );
1942 }
1943 /*
1944 **************************************************************************
1945 **************************************************************************
1946 */
1947 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1948         u_int32_t outbound_message;
1949
1950         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1951         outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1952         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1953                 arcmsr_dr_handle( acb );
1954 }
1955 /*
1956 **************************************************************************
1957 **************************************************************************
1958 */
1959 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1960 {
1961         u_int32_t doorbell_status;
1962
1963         /*
1964         *******************************************************************
1965         **  Maybe here we need to check wrqbuffer_lock is lock or not
1966         **  DOORBELL: din! don!
1967         **  check if there are any mail need to pack from firmware
1968         *******************************************************************
1969         */
1970         doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1971         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1972         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1973                 arcmsr_iop2drv_data_wrote_handle(acb);
1974         }
1975         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1976                 arcmsr_iop2drv_data_read_handle(acb);
1977         }
1978 }
1979 /*
1980 **************************************************************************
1981 **************************************************************************
1982 */
1983 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1984 {
1985         u_int32_t doorbell_status;
1986
1987         /*
1988         *******************************************************************
1989         **  Maybe here we need to check wrqbuffer_lock is lock or not
1990         **  DOORBELL: din! don!
1991         **  check if there are any mail need to pack from firmware
1992         *******************************************************************
1993         */
1994         doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1995         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1996         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1997                 arcmsr_iop2drv_data_wrote_handle(acb);
1998         }
1999         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
2000                 arcmsr_iop2drv_data_read_handle(acb);
2001         }
2002         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2003                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
2004         }
2005 }
2006 /*
2007 **************************************************************************
2008 **************************************************************************
2009 */
2010 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
2011 {
2012         u_int32_t doorbell_status;
2013
2014         /*
2015         *******************************************************************
2016         **  Maybe here we need to check wrqbuffer_lock is lock or not
2017         **  DOORBELL: din! don!
2018         **  check if there are any mail need to pack from firmware
2019         *******************************************************************
2020         */
2021         doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
2022         if(doorbell_status)
2023                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
2024         while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
2025                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
2026                         arcmsr_iop2drv_data_wrote_handle(acb);
2027                 }
2028                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
2029                         arcmsr_iop2drv_data_read_handle(acb);
2030                 }
2031                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
2032                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
2033                 }
2034                 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
2035                 if(doorbell_status)
2036                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
2037         }
2038 }
2039 /*
2040 **************************************************************************
2041 **************************************************************************
2042 */
2043 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
2044 {
2045         u_int32_t doorbell_status, in_doorbell;
2046
2047         /*
2048         *******************************************************************
2049         **  Maybe here we need to check wrqbuffer_lock is lock or not
2050         **  DOORBELL: din! don!
2051         **  check if there are any mail need to pack from firmware
2052         *******************************************************************
2053         */
2054         in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2055         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2056         doorbell_status = in_doorbell ^ acb->in_doorbell;
2057         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2058                 arcmsr_iop2drv_data_wrote_handle(acb);
2059         }
2060         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2061                 arcmsr_iop2drv_data_read_handle(acb);
2062         }
2063         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2064                 arcmsr_hbe_message_isr(acb);    /* messenger of "driver to iop commands" */
2065         }
2066         acb->in_doorbell = in_doorbell;
2067 }
2068 /*
2069 **************************************************************************
2070 **************************************************************************
2071 */
2072 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
2073 {
2074         u_int32_t flag_srb;
2075         u_int16_t error;
2076
2077         /*
2078         *****************************************************************************
2079         **               areca cdb command done
2080         *****************************************************************************
2081         */
2082         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2083                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2084         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2085                 0, outbound_queueport)) != 0xFFFFFFFF) {
2086                 /* check if command done with no error*/
2087         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2088                 arcmsr_drain_donequeue(acb, flag_srb, error);
2089         }       /*drain reply FIFO*/
2090 }
2091 /*
2092 **************************************************************************
2093 **************************************************************************
2094 */
2095 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2096 {
2097         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2098         u_int32_t flag_srb;
2099         int index;
2100         u_int16_t error;
2101
2102         /*
2103         *****************************************************************************
2104         **               areca cdb command done
2105         *****************************************************************************
2106         */
2107         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2108                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2109         index = phbbmu->doneq_index;
2110         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2111                 phbbmu->done_qbuffer[index] = 0;
2112                 index++;
2113                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
2114                 phbbmu->doneq_index = index;
2115                 /* check if command done with no error*/
2116         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2117                 arcmsr_drain_donequeue(acb, flag_srb, error);
2118         }       /*drain reply FIFO*/
2119 }
2120 /*
2121 **************************************************************************
2122 **************************************************************************
2123 */
2124 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2125 {
2126         u_int32_t flag_srb,throttling = 0;
2127         u_int16_t error;
2128
2129         /*
2130         *****************************************************************************
2131         **               areca cdb command done
2132         *****************************************************************************
2133         */
2134         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2135         do {
2136                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2137                 if (flag_srb == 0xFFFFFFFF)
2138                         break;
2139                 /* check if command done with no error*/
2140                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2141                 arcmsr_drain_donequeue(acb, flag_srb, error);
2142                 throttling++;
2143                 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2144                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2145                         throttling = 0;
2146                 }
2147         } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2148 }
2149 /*
2150 **********************************************************************
2151 **
2152 **********************************************************************
2153 */
2154 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2155 {
2156         uint16_t doneq_index, index_stripped;
2157
2158         doneq_index = phbdmu->doneq_index;
2159         if (doneq_index & 0x4000) {
2160                 index_stripped = doneq_index & 0xFF;
2161                 index_stripped += 1;
2162                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2163                 phbdmu->doneq_index = index_stripped ?
2164                     (index_stripped | 0x4000) : index_stripped;
2165         } else {
2166                 index_stripped = doneq_index;
2167                 index_stripped += 1;
2168                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2169                 phbdmu->doneq_index = index_stripped ?
2170                     index_stripped : (index_stripped | 0x4000);
2171         }
2172         return (phbdmu->doneq_index);
2173 }
2174 /*
2175 **************************************************************************
2176 **************************************************************************
2177 */
2178 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2179 {
2180         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2181         u_int32_t outbound_write_pointer;
2182         u_int32_t addressLow;
2183         uint16_t doneq_index;
2184         u_int16_t error;
2185         /*
2186         *****************************************************************************
2187         **               areca cdb command done
2188         *****************************************************************************
2189         */
2190         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2191                 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2192                 return;
2193         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2194                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2195         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2196         doneq_index = phbdmu->doneq_index;
2197         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2198                 doneq_index = arcmsr_get_doneq_index(phbdmu);
2199                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2200                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2201                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2202                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2203                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2204         }
2205         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2206         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2207 }
2208 /*
2209 **************************************************************************
2210 **************************************************************************
2211 */
2212 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2213 {
2214         u_int16_t error;
2215         uint32_t doneq_index;
2216         uint16_t cmdSMID;
2217
2218         /*
2219         *****************************************************************************
2220         **               areca cdb command done
2221         *****************************************************************************
2222         */
2223         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2224         doneq_index = acb->doneq_index;
2225         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2226                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2227                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2228                 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2229                 doneq_index++;
2230                 if (doneq_index >= acb->completionQ_entry)
2231                         doneq_index = 0;
2232         }
2233         acb->doneq_index = doneq_index;
2234         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2235 }
2236 /*
2237 **********************************************************************
2238 **********************************************************************
2239 */
2240 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2241 {
2242         u_int32_t outbound_intStatus;
2243         /*
2244         *********************************************
2245         **   check outbound intstatus
2246         *********************************************
2247         */
2248         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2249         if(!outbound_intStatus) {
2250                 /*it must be share irq*/
2251                 return;
2252         }
2253         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2254         /* MU doorbell interrupts*/
2255         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2256                 arcmsr_hba_doorbell_isr(acb);
2257         }
2258         /* MU post queue interrupts*/
2259         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2260                 arcmsr_hba_postqueue_isr(acb);
2261         }
2262         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2263                 arcmsr_hba_message_isr(acb);
2264         }
2265 }
2266 /*
2267 **********************************************************************
2268 **********************************************************************
2269 */
2270 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2271 {
2272         u_int32_t outbound_doorbell;
2273         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2274         /*
2275         *********************************************
2276         **   check outbound intstatus
2277         *********************************************
2278         */
2279         outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2280         if(!outbound_doorbell) {
2281                 /*it must be share irq*/
2282                 return;
2283         }
2284         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2285         READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2286         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2287         /* MU ioctl transfer doorbell interrupts*/
2288         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2289                 arcmsr_iop2drv_data_wrote_handle(acb);
2290         }
2291         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2292                 arcmsr_iop2drv_data_read_handle(acb);
2293         }
2294         /* MU post queue interrupts*/
2295         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2296                 arcmsr_hbb_postqueue_isr(acb);
2297         }
2298         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2299                 arcmsr_hbb_message_isr(acb);
2300         }
2301 }
2302 /*
2303 **********************************************************************
2304 **********************************************************************
2305 */
2306 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2307 {
2308         u_int32_t host_interrupt_status;
2309         /*
2310         *********************************************
2311         **   check outbound intstatus
2312         *********************************************
2313         */
2314         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2315                 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2316                 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2317         if(!host_interrupt_status) {
2318                 /*it must be share irq*/
2319                 return;
2320         }
2321         do {
2322                 /* MU doorbell interrupts*/
2323                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2324                         arcmsr_hbc_doorbell_isr(acb);
2325                 }
2326                 /* MU post queue interrupts*/
2327                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2328                         arcmsr_hbc_postqueue_isr(acb);
2329                 }
2330                 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2331         } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2332 }
2333 /*
2334 **********************************************************************
2335 **********************************************************************
2336 */
2337 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2338 {
2339         u_int32_t host_interrupt_status;
2340         u_int32_t intmask_org;
2341         /*
2342         *********************************************
2343         **   check outbound intstatus
2344         *********************************************
2345         */
2346         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2347         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2348                 /*it must be share irq*/
2349                 return;
2350         }
2351         /* disable outbound interrupt */
2352         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2353         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2354         /* MU doorbell interrupts*/
2355         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2356                 arcmsr_hbd_doorbell_isr(acb);
2357         }
2358         /* MU post queue interrupts*/
2359         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2360                 arcmsr_hbd_postqueue_isr(acb);
2361         }
2362         /* enable all outbound interrupt */
2363         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2364 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2365 }
2366 /*
2367 **********************************************************************
2368 **********************************************************************
2369 */
2370 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2371 {
2372         u_int32_t host_interrupt_status;
2373         /*
2374         *********************************************
2375         **   check outbound intstatus
2376         *********************************************
2377         */
2378         host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2379                 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2380                 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2381         if(!host_interrupt_status) {
2382                 /*it must be share irq*/
2383                 return;
2384         }
2385         do {
2386                 /* MU doorbell interrupts*/
2387                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2388                         arcmsr_hbe_doorbell_isr(acb);
2389                 }
2390                 /* MU post queue interrupts*/
2391                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2392                         arcmsr_hbe_postqueue_isr(acb);
2393                 }
2394                 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2395         } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2396 }
2397 /*
2398 ******************************************************************************
2399 ******************************************************************************
2400 */
2401 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2402 {
2403         switch (acb->adapter_type) {
2404         case ACB_ADAPTER_TYPE_A:
2405                 arcmsr_handle_hba_isr(acb);
2406                 break;
2407         case ACB_ADAPTER_TYPE_B:
2408                 arcmsr_handle_hbb_isr(acb);
2409                 break;
2410         case ACB_ADAPTER_TYPE_C:
2411                 arcmsr_handle_hbc_isr(acb);
2412                 break;
2413         case ACB_ADAPTER_TYPE_D:
2414                 arcmsr_handle_hbd_isr(acb);
2415                 break;
2416         case ACB_ADAPTER_TYPE_E:
2417                 arcmsr_handle_hbe_isr(acb);
2418                 break;
2419         default:
2420                 printf("arcmsr%d: interrupt service,"
2421                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2422                 break;
2423         }
2424 }
2425 /*
2426 **********************************************************************
2427 **********************************************************************
2428 */
2429 static void arcmsr_intr_handler(void *arg)
2430 {
2431         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2432
2433         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2434         arcmsr_interrupt(acb);
2435         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2436 }
2437 /*
2438 ******************************************************************************
2439 ******************************************************************************
2440 */
2441 static void     arcmsr_polling_devmap(void *arg)
2442 {
2443         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2444         switch (acb->adapter_type) {
2445         case ACB_ADAPTER_TYPE_A:
2446                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2447                 break;
2448
2449         case ACB_ADAPTER_TYPE_B: {
2450                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2451                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2452                 }
2453                 break;
2454
2455         case ACB_ADAPTER_TYPE_C:
2456                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2457                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2458                 break;
2459
2460         case ACB_ADAPTER_TYPE_D:
2461                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2462                 break;
2463
2464         case ACB_ADAPTER_TYPE_E:
2465                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2466                 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2467                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2468                 break;
2469         }
2470
2471         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2472         {
2473                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2474         }
2475 }
2476
2477 /*
2478 *******************************************************************************
2479 **
2480 *******************************************************************************
2481 */
2482 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2483 {
2484         u_int32_t intmask_org;
2485
2486         if(acb != NULL) {
2487                 /* stop adapter background rebuild */
2488                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2489                         intmask_org = arcmsr_disable_allintr(acb);
2490                         arcmsr_stop_adapter_bgrb(acb);
2491                         arcmsr_flush_adapter_cache(acb);
2492                         arcmsr_enable_allintr(acb, intmask_org);
2493                 }
2494         }
2495 }
2496 /*
2497 ***********************************************************************
2498 **
2499 ************************************************************************
2500 */
2501 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2502 {
2503         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2504         u_int32_t retvalue = EINVAL;
2505
2506         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2507         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2508                 return retvalue;
2509         }
2510         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2511         switch(ioctl_cmd) {
2512         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2513                         u_int8_t *pQbuffer;
2514                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2515                         u_int32_t allxfer_len=0;
2516
2517                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2518                                 && (allxfer_len < 1031)) {
2519                                 /*copy READ QBUFFER to srb*/
2520                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2521                                 *ptmpQbuffer = *pQbuffer;
2522                                 acb->rqbuf_firstindex++;
2523                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2524                                 /*if last index number set it to 0 */
2525                                 ptmpQbuffer++;
2526                                 allxfer_len++;
2527                         }
2528                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2529                                 struct QBUFFER *prbuffer;
2530
2531                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2532                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2533                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2534                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2535                         }
2536                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2537                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2538                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2539                 }
2540                 break;
2541         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2542                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2543                         u_int8_t *pQbuffer;
2544                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2545
2546                         user_len = pcmdmessagefld->cmdmessage.Length;
2547                         /*check if data xfer length of this request will overflow my array qbuffer */
2548                         wqbuf_lastindex = acb->wqbuf_lastindex;
2549                         wqbuf_firstindex = acb->wqbuf_firstindex;
2550                         if(wqbuf_lastindex != wqbuf_firstindex) {
2551                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2552                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2553                         } else {
2554                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2555                                         (ARCMSR_MAX_QBUFFER - 1);
2556                                 if(my_empty_len >= user_len) {
2557                                         while(user_len > 0) {
2558                                                 /*copy srb data to wqbuffer*/
2559                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2560                                                 *pQbuffer = *ptmpuserbuffer;
2561                                                 acb->wqbuf_lastindex++;
2562                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2563                                                 /*if last index number set it to 0 */
2564                                                 ptmpuserbuffer++;
2565                                                 user_len--;
2566                                         }
2567                                         /*post fist Qbuffer*/
2568                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2569                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2570                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2571                                         }
2572                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2573                                 } else {
2574                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2575                                 }
2576                         }
2577                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2578                 }
2579                 break;
2580         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2581                         u_int8_t *pQbuffer = acb->rqbuffer;
2582
2583                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2584                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2585                                 arcmsr_iop_message_read(acb);
2586                                 /*signature, let IOP know data has been readed */
2587                         }
2588                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2589                         acb->rqbuf_firstindex = 0;
2590                         acb->rqbuf_lastindex = 0;
2591                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2592                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2593                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2594                 }
2595                 break;
2596         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2597                 {
2598                         u_int8_t *pQbuffer = acb->wqbuffer;
2599
2600                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2601                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2602                                 arcmsr_iop_message_read(acb);
2603                                 /*signature, let IOP know data has been readed */
2604                         }
2605                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2606                         acb->wqbuf_firstindex = 0;
2607                         acb->wqbuf_lastindex = 0;
2608                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2609                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2610                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2611                 }
2612                 break;
2613         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2614                         u_int8_t *pQbuffer;
2615
2616                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2617                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2618                                 arcmsr_iop_message_read(acb);
2619                                 /*signature, let IOP know data has been readed */
2620                         }
2621                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2622                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2623                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2624                         acb->rqbuf_firstindex = 0;
2625                         acb->rqbuf_lastindex = 0;
2626                         acb->wqbuf_firstindex = 0;
2627                         acb->wqbuf_lastindex = 0;
2628                         pQbuffer = acb->rqbuffer;
2629                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2630                         pQbuffer = acb->wqbuffer;
2631                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2632                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2633                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2634                 }
2635                 break;
2636         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2637                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2638                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2639                 }
2640                 break;
2641         case ARCMSR_MESSAGE_SAY_HELLO: {
2642                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2643                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2644
2645                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2646                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2647                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2648                                 return ENOIOCTL;
2649                         }
2650                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2651                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2652                 }
2653                 break;
2654         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2655                         arcmsr_iop_parking(acb);
2656                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2657                 }
2658                 break;
2659         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2660                         arcmsr_flush_adapter_cache(acb);
2661                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2662                 }
2663                 break;
2664         }
2665         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2666         return (retvalue);
2667 }
2668 /*
2669 **************************************************************************
2670 **************************************************************************
2671 */
2672 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2673 {
2674         struct AdapterControlBlock      *acb;
2675
2676         acb = srb->acb;
2677         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2678         srb->srb_state = ARCMSR_SRB_DONE;
2679         srb->srb_flags = 0;
2680         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2681         acb->workingsrb_doneindex++;
2682         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2683         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2684 }
2685 /*
2686 **************************************************************************
2687 **************************************************************************
2688 */
2689 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2690 {
2691         struct CommandControlBlock *srb = NULL;
2692         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2693
2694         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2695         workingsrb_doneindex = acb->workingsrb_doneindex;
2696         workingsrb_startindex = acb->workingsrb_startindex;
2697         srb = acb->srbworkingQ[workingsrb_startindex];
2698         workingsrb_startindex++;
2699         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2700         if(workingsrb_doneindex != workingsrb_startindex) {
2701                 acb->workingsrb_startindex = workingsrb_startindex;
2702         } else {
2703                 srb = NULL;
2704         }
2705         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2706         return(srb);
2707 }
2708 /*
2709 **************************************************************************
2710 **************************************************************************
2711 */
2712 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2713 {
2714         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2715         int retvalue = 0, transfer_len = 0;
2716         char *buffer;
2717         uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2718         u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2719                                 (u_int32_t ) ptr[6] << 16 |
2720                                 (u_int32_t ) ptr[7] << 8  |
2721                                 (u_int32_t ) ptr[8];
2722                                         /* 4 bytes: Areca io control code */
2723         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2724                 buffer = pccb->csio.data_ptr;
2725                 transfer_len = pccb->csio.dxfer_len;
2726         } else {
2727                 retvalue = ARCMSR_MESSAGE_FAIL;
2728                 goto message_out;
2729         }
2730         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2731                 retvalue = ARCMSR_MESSAGE_FAIL;
2732                 goto message_out;
2733         }
2734         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2735         switch(controlcode) {
2736         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2737                         u_int8_t *pQbuffer;
2738                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2739                         int32_t allxfer_len = 0;
2740
2741                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2742                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2743                                 && (allxfer_len < 1031)) {
2744                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2745                                 *ptmpQbuffer = *pQbuffer;
2746                                 acb->rqbuf_firstindex++;
2747                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2748                                 ptmpQbuffer++;
2749                                 allxfer_len++;
2750                         }
2751                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2752                                 struct QBUFFER  *prbuffer;
2753
2754                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2755                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2756                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2757                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2758                         }
2759                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2760                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2761                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2762                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2763                 }
2764                 break;
2765         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2766                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2767                         u_int8_t *pQbuffer;
2768                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2769
2770                         user_len = pcmdmessagefld->cmdmessage.Length;
2771                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2772                         wqbuf_lastindex = acb->wqbuf_lastindex;
2773                         wqbuf_firstindex = acb->wqbuf_firstindex;
2774                         if (wqbuf_lastindex != wqbuf_firstindex) {
2775                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2776                                 /* has error report sensedata */
2777                                 if(pccb->csio.sense_len) {
2778                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2779                                 /* Valid,ErrorCode */
2780                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2781                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2782                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2783                                 /* AdditionalSenseLength */
2784                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2785                                 /* AdditionalSenseCode */
2786                                 }
2787                                 retvalue = ARCMSR_MESSAGE_FAIL;
2788                         } else {
2789                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2790                                                 &(ARCMSR_MAX_QBUFFER - 1);
2791                                 if (my_empty_len >= user_len) {
2792                                         while (user_len > 0) {
2793                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2794                                                 *pQbuffer = *ptmpuserbuffer;
2795                                                 acb->wqbuf_lastindex++;
2796                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2797                                                 ptmpuserbuffer++;
2798                                                 user_len--;
2799                                         }
2800                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2801                                                 acb->acb_flags &=
2802                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2803                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2804                                         }
2805                                 } else {
2806                                         /* has error report sensedata */
2807                                         if(pccb->csio.sense_len) {
2808                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2809                                         /* Valid,ErrorCode */
2810                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2811                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2812                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2813                                         /* AdditionalSenseLength */
2814                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2815                                         /* AdditionalSenseCode */
2816                                         }
2817                                         retvalue = ARCMSR_MESSAGE_FAIL;
2818                                 }
2819                         }
2820                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2821                 }
2822                 break;
2823         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2824                         u_int8_t *pQbuffer = acb->rqbuffer;
2825
2826                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2827                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2828                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2829                                 arcmsr_iop_message_read(acb);
2830                         }
2831                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2832                         acb->rqbuf_firstindex = 0;
2833                         acb->rqbuf_lastindex = 0;
2834                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2835                         pcmdmessagefld->cmdmessage.ReturnCode =
2836                             ARCMSR_MESSAGE_RETURNCODE_OK;
2837                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2838                 }
2839                 break;
2840         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2841                         u_int8_t *pQbuffer = acb->wqbuffer;
2842
2843                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2844                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2845                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2846                                 arcmsr_iop_message_read(acb);
2847                         }
2848                         acb->acb_flags |=
2849                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2850                                         ACB_F_MESSAGE_WQBUFFER_READ);
2851                         acb->wqbuf_firstindex = 0;
2852                         acb->wqbuf_lastindex = 0;
2853                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2854                         pcmdmessagefld->cmdmessage.ReturnCode =
2855                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2856                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2857                 }
2858                 break;
2859         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2860                         u_int8_t *pQbuffer;
2861
2862                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2863                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2864                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2865                                 arcmsr_iop_message_read(acb);
2866                         }
2867                         acb->acb_flags |=
2868                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2869                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2870                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2871                         acb->rqbuf_firstindex = 0;
2872                         acb->rqbuf_lastindex = 0;
2873                         acb->wqbuf_firstindex = 0;
2874                         acb->wqbuf_lastindex = 0;
2875                         pQbuffer = acb->rqbuffer;
2876                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2877                         pQbuffer = acb->wqbuffer;
2878                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2879                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2880                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2881                 }
2882                 break;
2883         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2884                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2885                 }
2886                 break;
2887         case ARCMSR_MESSAGE_SAY_HELLO: {
2888                         int8_t *hello_string = "Hello! I am ARCMSR";
2889
2890                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2891                                 , (int16_t)strlen(hello_string));
2892                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2893                 }
2894                 break;
2895         case ARCMSR_MESSAGE_SAY_GOODBYE:
2896                 arcmsr_iop_parking(acb);
2897                 break;
2898         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2899                 arcmsr_flush_adapter_cache(acb);
2900                 break;
2901         default:
2902                 retvalue = ARCMSR_MESSAGE_FAIL;
2903         }
2904 message_out:
2905         return (retvalue);
2906 }
2907 /*
2908 *********************************************************************
2909 *********************************************************************
2910 */
2911 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2912 {
2913         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2914         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2915         union ccb *pccb;
2916         int target, lun;
2917
2918         pccb = srb->pccb;
2919         target = pccb->ccb_h.target_id;
2920         lun = pccb->ccb_h.target_lun;
2921         acb->pktRequestCount++;
2922         if(error != 0) {
2923                 if(error != EFBIG) {
2924                         printf("arcmsr%d: unexpected error %x"
2925                                 " returned from 'bus_dmamap_load' \n"
2926                                 , acb->pci_unit, error);
2927                 }
2928                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2929                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2930                 }
2931                 arcmsr_srb_complete(srb, 0);
2932                 return;
2933         }
2934         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2935                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2936                 arcmsr_srb_complete(srb, 0);
2937                 return;
2938         }
2939         if(acb->acb_flags & ACB_F_BUS_RESET) {
2940                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2941                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2942                 arcmsr_srb_complete(srb, 0);
2943                 return;
2944         }
2945         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2946                 u_int8_t block_cmd, cmd;
2947
2948                 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
2949                 block_cmd = cmd & 0x0f;
2950                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2951                         printf("arcmsr%d:block 'read/write' command "
2952                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2953                                 , acb->pci_unit, cmd, target, lun);
2954                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2955                         arcmsr_srb_complete(srb, 0);
2956                         return;
2957                 }
2958         }
2959         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2960                 if(nseg != 0) {
2961                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2962                 }
2963                 arcmsr_srb_complete(srb, 0);
2964                 return;
2965         }
2966         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2967                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2968                 {
2969                         xpt_freeze_simq(acb->psim, 1);
2970                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2971                 }
2972                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2973                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2974                 arcmsr_srb_complete(srb, 0);
2975                 return;
2976         }
2977         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2978         arcmsr_build_srb(srb, dm_segs, nseg);
2979         arcmsr_post_srb(acb, srb);
2980         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2981         {
2982                 arcmsr_callout_init(&srb->ccb_callout);
2983                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2984                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2985                     arcmsr_srb_timeout, srb, 0);
2986                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2987         }
2988 }
2989 /*
2990 *****************************************************************************************
2991 *****************************************************************************************
2992 */
2993 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2994 {
2995         struct CommandControlBlock *srb;
2996         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2997         u_int32_t intmask_org;
2998         int i = 0;
2999
3000         acb->num_aborts++;
3001         /*
3002         ***************************************************************************
3003         ** It is the upper layer do abort command this lock just prior to calling us.
3004         ** First determine if we currently own this command.
3005         ** Start by searching the device queue. If not found
3006         ** at all, and the system wanted us to just abort the
3007         ** command return success.
3008         ***************************************************************************
3009         */
3010         if(acb->srboutstandingcount != 0) {
3011                 /* disable all outbound interrupt */
3012                 intmask_org = arcmsr_disable_allintr(acb);
3013                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3014                         srb = acb->psrb_pool[i];
3015                         if(srb->srb_state == ARCMSR_SRB_START) {
3016                                 if(srb->pccb == abortccb) {
3017                                         srb->srb_state = ARCMSR_SRB_ABORTED;
3018                                         printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
3019                                                 "outstanding command \n"
3020                                                 , acb->pci_unit, abortccb->ccb_h.target_id
3021                                                 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
3022                                         arcmsr_polling_srbdone(acb, srb);
3023                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
3024                                         arcmsr_enable_allintr(acb, intmask_org);
3025                                         return (TRUE);
3026                                 }
3027                         }
3028                 }
3029                 /* enable outbound Post Queue, outbound doorbell Interrupt */
3030                 arcmsr_enable_allintr(acb, intmask_org);
3031         }
3032         return(FALSE);
3033 }
3034 /*
3035 ****************************************************************************
3036 ****************************************************************************
3037 */
3038 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
3039 {
3040         int retry = 0;
3041
3042         acb->num_resets++;
3043         acb->acb_flags |= ACB_F_BUS_RESET;
3044         while(acb->srboutstandingcount != 0 && retry < 400) {
3045                 arcmsr_interrupt(acb);
3046                 UDELAY(25000);
3047                 retry++;
3048         }
3049         arcmsr_iop_reset(acb);
3050         acb->acb_flags &= ~ACB_F_BUS_RESET;
3051 }
3052 /*
3053 **************************************************************************
3054 **************************************************************************
3055 */
3056 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3057                 union ccb *pccb)
3058 {
3059         if (pccb->ccb_h.target_lun) {
3060                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3061                 xpt_done(pccb);
3062                 return;
3063         }
3064         pccb->ccb_h.status |= CAM_REQ_CMP;
3065         switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
3066         case INQUIRY: {
3067                 unsigned char inqdata[36];
3068                 char *buffer = pccb->csio.data_ptr;
3069
3070                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
3071                 inqdata[1] = 0;                 /* rem media bit & Dev Type Modifier */
3072                 inqdata[2] = 0;                 /* ISO, ECMA, & ANSI versions */
3073                 inqdata[3] = 0;
3074                 inqdata[4] = 31;                /* length of additional data */
3075                 inqdata[5] = 0;
3076                 inqdata[6] = 0;
3077                 inqdata[7] = 0;
3078                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
3079                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
3080                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3081                 memcpy(buffer, inqdata, sizeof(inqdata));
3082                 xpt_done(pccb);
3083         }
3084         break;
3085         case WRITE_BUFFER:
3086         case READ_BUFFER: {
3087                 if (arcmsr_iop_message_xfer(acb, pccb)) {
3088                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3089                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3090                 }
3091                 xpt_done(pccb);
3092         }
3093         break;
3094         default:
3095                 xpt_done(pccb);
3096         }
3097 }
3098 /*
3099 *********************************************************************
3100 *********************************************************************
3101 */
3102 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3103 {
3104         struct AdapterControlBlock *acb;
3105
3106         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3107         if(acb == NULL) {
3108                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3109                 xpt_done(pccb);
3110                 return;
3111         }
3112         switch (pccb->ccb_h.func_code) {
3113         case XPT_SCSI_IO: {
3114                         struct CommandControlBlock *srb;
3115                         int target = pccb->ccb_h.target_id;
3116                         int error;
3117
3118                         if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3119                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3120                                 xpt_done(pccb);
3121                                 return;
3122                         }
3123
3124                         if(target == 16) {
3125                                 /* virtual device for iop message transfer */
3126                                 arcmsr_handle_virtual_command(acb, pccb);
3127                                 return;
3128                         }
3129                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3130                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3131                                 xpt_done(pccb);
3132                                 return;
3133                         }
3134                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3135                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3136                         srb->pccb = pccb;
3137                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3138                                 , srb->dm_segs_dmamap
3139                                 , pccb
3140                                 , arcmsr_execute_srb, srb, /*flags*/0);
3141                         if(error == EINPROGRESS) {
3142                                 xpt_freeze_simq(acb->psim, 1);
3143                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3144                         }
3145                         break;
3146                 }
3147         case XPT_PATH_INQ: {
3148                         struct ccb_pathinq *cpi = &pccb->cpi;
3149
3150                         cpi->version_num = 1;
3151                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3152                         cpi->target_sprt = 0;
3153                         cpi->hba_misc = 0;
3154                         cpi->hba_eng_cnt = 0;
3155                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
3156                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
3157                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3158                         cpi->bus_id = cam_sim_bus(psim);
3159                         strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3160                         strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3161                         strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3162                         cpi->unit_number = cam_sim_unit(psim);
3163                 #ifdef  CAM_NEW_TRAN_CODE
3164                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3165                                 cpi->base_transfer_speed = 1200000;
3166                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3167                                 cpi->base_transfer_speed = 600000;
3168                         else
3169                                 cpi->base_transfer_speed = 300000;
3170                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3171                            (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3172                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3173                            (acb->vendor_device_id == PCIDevVenIDARC1214))
3174                         {
3175                                 cpi->transport = XPORT_SAS;
3176                                 cpi->transport_version = 0;
3177                                 cpi->protocol_version = SCSI_REV_SPC2;
3178                         }
3179                         else
3180                         {
3181                                 cpi->transport = XPORT_SPI;
3182                                 cpi->transport_version = 2;
3183                                 cpi->protocol_version = SCSI_REV_2;
3184                         }
3185                         cpi->protocol = PROTO_SCSI;
3186                 #endif
3187                         cpi->ccb_h.status |= CAM_REQ_CMP;
3188                         xpt_done(pccb);
3189                         break;
3190                 }
3191         case XPT_ABORT: {
3192                         union ccb *pabort_ccb;
3193
3194                         pabort_ccb = pccb->cab.abort_ccb;
3195                         switch (pabort_ccb->ccb_h.func_code) {
3196                         case XPT_ACCEPT_TARGET_IO:
3197                         case XPT_CONT_TARGET_IO:
3198                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3199                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3200                                         xpt_done(pabort_ccb);
3201                                         pccb->ccb_h.status |= CAM_REQ_CMP;
3202                                 } else {
3203                                         xpt_print_path(pabort_ccb->ccb_h.path);
3204                                         printf("Not found\n");
3205                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
3206                                 }
3207                                 break;
3208                         case XPT_SCSI_IO:
3209                                 pccb->ccb_h.status |= CAM_UA_ABORT;
3210                                 break;
3211                         default:
3212                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3213                                 break;
3214                         }
3215                         xpt_done(pccb);
3216                         break;
3217                 }
3218         case XPT_RESET_BUS:
3219         case XPT_RESET_DEV: {
3220                         u_int32_t       i;
3221
3222                         arcmsr_bus_reset(acb);
3223                         for (i=0; i < 500; i++) {
3224                                 DELAY(1000);
3225                         }
3226                         pccb->ccb_h.status |= CAM_REQ_CMP;
3227                         xpt_done(pccb);
3228                         break;
3229                 }
3230         case XPT_TERM_IO: {
3231                         pccb->ccb_h.status |= CAM_REQ_INVALID;
3232                         xpt_done(pccb);
3233                         break;
3234                 }
3235         case XPT_GET_TRAN_SETTINGS: {
3236                         struct ccb_trans_settings *cts;
3237
3238                         if(pccb->ccb_h.target_id == 16) {
3239                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3240                                 xpt_done(pccb);
3241                                 break;
3242                         }
3243                         cts = &pccb->cts;
3244                 #ifdef  CAM_NEW_TRAN_CODE
3245                         {
3246                                 struct ccb_trans_settings_scsi *scsi;
3247                                 struct ccb_trans_settings_spi *spi;
3248                                 struct ccb_trans_settings_sas *sas;
3249
3250                                 scsi = &cts->proto_specific.scsi;
3251                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3252                                 scsi->valid = CTS_SCSI_VALID_TQ;
3253                                 cts->protocol = PROTO_SCSI;
3254
3255                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3256                                    (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3257                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3258                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
3259                                 {
3260                                         cts->protocol_version = SCSI_REV_SPC2;
3261                                         cts->transport_version = 0;
3262                                         cts->transport = XPORT_SAS;
3263                                         sas = &cts->xport_specific.sas;
3264                                         sas->valid = CTS_SAS_VALID_SPEED;
3265                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3266                                                 sas->bitrate = 1200000;
3267                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3268                                                 sas->bitrate = 600000;
3269                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3270                                                 sas->bitrate = 300000;
3271                                 }
3272                                 else
3273                                 {
3274                                         cts->protocol_version = SCSI_REV_2;
3275                                         cts->transport_version = 2;
3276                                         cts->transport = XPORT_SPI;
3277                                         spi = &cts->xport_specific.spi;
3278                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3279                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3280                                                 spi->sync_period = 1;
3281                                         else
3282                                                 spi->sync_period = 2;
3283                                         spi->sync_offset = 32;
3284                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3285                                         spi->valid = CTS_SPI_VALID_DISC
3286                                                 | CTS_SPI_VALID_SYNC_RATE
3287                                                 | CTS_SPI_VALID_SYNC_OFFSET
3288                                                 | CTS_SPI_VALID_BUS_WIDTH;
3289                                 }
3290                         }
3291                 #else
3292                         {
3293                                 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3294                                 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3295                                         cts->sync_period = 1;
3296                                 else
3297                                         cts->sync_period = 2;
3298                                 cts->sync_offset = 32;
3299                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3300                                 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3301                                 CCB_TRANS_SYNC_OFFSET_VALID |
3302                                 CCB_TRANS_BUS_WIDTH_VALID |
3303                                 CCB_TRANS_DISC_VALID |
3304                                 CCB_TRANS_TQ_VALID;
3305                         }
3306                 #endif
3307                         pccb->ccb_h.status |= CAM_REQ_CMP;
3308                         xpt_done(pccb);
3309                         break;
3310                 }
3311         case XPT_SET_TRAN_SETTINGS: {
3312                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3313                         xpt_done(pccb);
3314                         break;
3315                 }
3316         case XPT_CALC_GEOMETRY:
3317                         if(pccb->ccb_h.target_id == 16) {
3318                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3319                                 xpt_done(pccb);
3320                                 break;
3321                         }
3322 #if __FreeBSD_version >= 500000
3323                         cam_calc_geometry(&pccb->ccg, 1);
3324 #else
3325                         {
3326                         struct ccb_calc_geometry *ccg;
3327                         u_int32_t size_mb;
3328                         u_int32_t secs_per_cylinder;
3329
3330                         ccg = &pccb->ccg;
3331                         if (ccg->block_size == 0) {
3332                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3333                                 xpt_done(pccb);
3334                                 break;
3335                         }
3336                         if(((1024L * 1024L)/ccg->block_size) < 0) {
3337                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3338                                 xpt_done(pccb);
3339                                 break;
3340                         }
3341                         size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3342                         if(size_mb > 1024 ) {
3343                                 ccg->heads = 255;
3344                                 ccg->secs_per_track = 63;
3345                         } else {
3346                                 ccg->heads = 64;
3347                                 ccg->secs_per_track = 32;
3348                         }
3349                         secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3350                         ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3351                         pccb->ccb_h.status |= CAM_REQ_CMP;
3352                         }
3353 #endif
3354                         xpt_done(pccb);
3355                         break;
3356         default:
3357                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3358                 xpt_done(pccb);
3359                 break;
3360         }
3361 }
3362 /*
3363 **********************************************************************
3364 **********************************************************************
3365 */
3366 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3367 {
3368         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3369         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3370         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3371                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3372         }
3373 }
3374 /*
3375 **********************************************************************
3376 **********************************************************************
3377 */
3378 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3379 {
3380         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3381         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3382         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3383         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3384                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3385         }
3386 }
3387 /*
3388 **********************************************************************
3389 **********************************************************************
3390 */
3391 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3392 {
3393         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3394         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3395         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3396         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3397                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3398         }
3399 }
3400 /*
3401 **********************************************************************
3402 **********************************************************************
3403 */
3404 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3405 {
3406         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3407         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3408         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3409                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3410         }
3411 }
3412 /*
3413 **********************************************************************
3414 **********************************************************************
3415 */
3416 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3417 {
3418         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3419         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3420         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3421         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3422         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3423                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3424         }
3425 }
3426 /*
3427 **********************************************************************
3428 **********************************************************************
3429 */
3430 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3431 {
3432         switch (acb->adapter_type) {
3433         case ACB_ADAPTER_TYPE_A:
3434                 arcmsr_start_hba_bgrb(acb);
3435                 break;
3436         case ACB_ADAPTER_TYPE_B:
3437                 arcmsr_start_hbb_bgrb(acb);
3438                 break;
3439         case ACB_ADAPTER_TYPE_C:
3440                 arcmsr_start_hbc_bgrb(acb);
3441                 break;
3442         case ACB_ADAPTER_TYPE_D:
3443                 arcmsr_start_hbd_bgrb(acb);
3444                 break;
3445         case ACB_ADAPTER_TYPE_E:
3446                 arcmsr_start_hbe_bgrb(acb);
3447                 break;
3448         }
3449 }
3450 /*
3451 **********************************************************************
3452 **
3453 **********************************************************************
3454 */
3455 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3456 {
3457         struct CommandControlBlock *srb;
3458         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3459         u_int16_t       error;
3460
3461 polling_ccb_retry:
3462         poll_count++;
3463         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3464         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3465         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3466         while(1) {
3467                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3468                         0, outbound_queueport)) == 0xFFFFFFFF) {
3469                         if(poll_srb_done) {
3470                                 break;/*chip FIFO no ccb for completion already*/
3471                         } else {
3472                                 UDELAY(25000);
3473                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3474                                         break;
3475                                 }
3476                                 goto polling_ccb_retry;
3477                         }
3478                 }
3479                 /* check if command done with no error*/
3480                 srb = (struct CommandControlBlock *)
3481                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3482                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3483                 poll_srb_done = (srb == poll_srb) ? 1:0;
3484                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3485                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3486                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3487                                         "poll command abort successfully \n"
3488                                         , acb->pci_unit
3489                                         , srb->pccb->ccb_h.target_id
3490                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3491                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3492                                 arcmsr_srb_complete(srb, 1);
3493                                 continue;
3494                         }
3495                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3496                                 "srboutstandingcount=%d \n"
3497                                 , acb->pci_unit
3498                                 , srb, acb->srboutstandingcount);
3499                         continue;
3500                 }
3501                 arcmsr_report_srb_state(acb, srb, error);
3502         }       /*drain reply FIFO*/
3503 }
3504 /*
3505 **********************************************************************
3506 **
3507 **********************************************************************
3508 */
3509 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3510 {
3511         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3512         struct CommandControlBlock *srb;
3513         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3514         int index;
3515         u_int16_t       error;
3516
3517 polling_ccb_retry:
3518         poll_count++;
3519         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3520         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3521         while(1) {
3522                 index = phbbmu->doneq_index;
3523                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3524                         if(poll_srb_done) {
3525                                 break;/*chip FIFO no ccb for completion already*/
3526                         } else {
3527                                 UDELAY(25000);
3528                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3529                                         break;
3530                                 }
3531                                 goto polling_ccb_retry;
3532                         }
3533                 }
3534                 phbbmu->done_qbuffer[index] = 0;
3535                 index++;
3536                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3537                 phbbmu->doneq_index = index;
3538                 /* check if command done with no error*/
3539                 srb = (struct CommandControlBlock *)
3540                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3541                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3542                 poll_srb_done = (srb == poll_srb) ? 1:0;
3543                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3544                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3545                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3546                                         "poll command abort successfully \n"
3547                                         , acb->pci_unit
3548                                         , srb->pccb->ccb_h.target_id
3549                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3550                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3551                                 arcmsr_srb_complete(srb, 1);
3552                                 continue;
3553                         }
3554                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3555                                 "srboutstandingcount=%d \n"
3556                                 , acb->pci_unit
3557                                 , srb, acb->srboutstandingcount);
3558                         continue;
3559                 }
3560                 arcmsr_report_srb_state(acb, srb, error);
3561         }       /*drain reply FIFO*/
3562 }
3563 /*
3564 **********************************************************************
3565 **
3566 **********************************************************************
3567 */
3568 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3569 {
3570         struct CommandControlBlock *srb;
3571         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3572         u_int16_t       error;
3573
3574 polling_ccb_retry:
3575         poll_count++;
3576         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3577         while(1) {
3578                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3579                         if(poll_srb_done) {
3580                                 break;/*chip FIFO no ccb for completion already*/
3581                         } else {
3582                                 UDELAY(25000);
3583                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3584                                         break;
3585                                 }
3586                                 if (acb->srboutstandingcount == 0) {
3587                                     break;
3588                                 }
3589                                 goto polling_ccb_retry;
3590                         }
3591                 }
3592                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3593                 /* check if command done with no error*/
3594                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3595                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3596                 if (poll_srb != NULL)
3597                         poll_srb_done = (srb == poll_srb) ? 1:0;
3598                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3599                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3600                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3601                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3602                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3603                                 arcmsr_srb_complete(srb, 1);
3604                                 continue;
3605                         }
3606                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3607                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3608                         continue;
3609                 }
3610                 arcmsr_report_srb_state(acb, srb, error);
3611         }       /*drain reply FIFO*/
3612 }
3613 /*
3614 **********************************************************************
3615 **
3616 **********************************************************************
3617 */
3618 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3619 {
3620         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3621         struct CommandControlBlock *srb;
3622         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3623         u_int32_t outbound_write_pointer;
3624         u_int16_t       error, doneq_index;
3625
3626 polling_ccb_retry:
3627         poll_count++;
3628         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3629         while(1) {
3630                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3631                 doneq_index = phbdmu->doneq_index;
3632                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3633                         if(poll_srb_done) {
3634                                 break;/*chip FIFO no ccb for completion already*/
3635                         } else {
3636                                 UDELAY(25000);
3637                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3638                                         break;
3639                                 }
3640                                 if (acb->srboutstandingcount == 0) {
3641                                         break;
3642                                 }
3643                                 goto polling_ccb_retry;
3644                         }
3645                 }
3646                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3647                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3648                 /* check if command done with no error*/
3649                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3650                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3651                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3652                 if (poll_srb != NULL)
3653                         poll_srb_done = (srb == poll_srb) ? 1:0;
3654                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3655                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3656                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3657                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3658                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3659                                 arcmsr_srb_complete(srb, 1);
3660                                 continue;
3661                         }
3662                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3663                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3664                         continue;
3665                 }
3666                 arcmsr_report_srb_state(acb, srb, error);
3667         }       /*drain reply FIFO*/
3668 }
3669 /*
3670 **********************************************************************
3671 **
3672 **********************************************************************
3673 */
3674 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3675 {
3676         struct CommandControlBlock *srb;
3677         u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3678         u_int16_t       error, cmdSMID;
3679
3680 polling_ccb_retry:
3681         poll_count++;
3682         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3683         while(1) {
3684                 doneq_index = acb->doneq_index;
3685                 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3686                         if(poll_srb_done) {
3687                                 break;/*chip FIFO no ccb for completion already*/
3688                         } else {
3689                                 UDELAY(25000);
3690                             if ((poll_count > 100) && (poll_srb != NULL)) {
3691                                         break;
3692                                 }
3693                             if (acb->srboutstandingcount == 0) {
3694                                     break;
3695                             }
3696                                 goto polling_ccb_retry;
3697                         }
3698                 }
3699                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3700                 doneq_index++;
3701                 if (doneq_index >= acb->completionQ_entry)
3702                         doneq_index = 0;
3703                 acb->doneq_index = doneq_index;
3704                 srb = acb->psrb_pool[cmdSMID];
3705                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3706                 if (poll_srb != NULL)
3707                         poll_srb_done = (srb == poll_srb) ? 1:0;
3708                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3709                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3710                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3711                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3712                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3713                                 arcmsr_srb_complete(srb, 1);
3714                                 continue;
3715                         }
3716                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3717                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3718                         continue;
3719                 }
3720                 arcmsr_report_srb_state(acb, srb, error);
3721         }       /*drain reply FIFO*/
3722         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3723 }
3724 /*
3725 **********************************************************************
3726 **********************************************************************
3727 */
3728 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3729 {
3730         switch (acb->adapter_type) {
3731         case ACB_ADAPTER_TYPE_A: {
3732                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3733                 }
3734                 break;
3735         case ACB_ADAPTER_TYPE_B: {
3736                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3737                 }
3738                 break;
3739         case ACB_ADAPTER_TYPE_C: {
3740                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3741                 }
3742                 break;
3743         case ACB_ADAPTER_TYPE_D: {
3744                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3745                 }
3746                 break;
3747         case ACB_ADAPTER_TYPE_E: {
3748                         arcmsr_polling_hbe_srbdone(acb, poll_srb);
3749                 }
3750                 break;
3751         }
3752 }
3753 /*
3754 **********************************************************************
3755 **********************************************************************
3756 */
3757 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3758 {
3759         char *acb_firm_model = acb->firm_model;
3760         char *acb_firm_version = acb->firm_version;
3761         char *acb_device_map = acb->device_map;
3762         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3763         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3764         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3765         int i;
3766
3767         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3768         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3769                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3770         }
3771         i = 0;
3772         while(i < 8) {
3773                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3774                 /* 8 bytes firm_model, 15, 60-67*/
3775                 acb_firm_model++;
3776                 i++;
3777         }
3778         i=0;
3779         while(i < 16) {
3780                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3781                 /* 16 bytes firm_version, 17, 68-83*/
3782                 acb_firm_version++;
3783                 i++;
3784         }
3785         i=0;
3786         while(i < 16) {
3787                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3788                 acb_device_map++;
3789                 i++;
3790         }
3791         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3792         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3793         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3794         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3795         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3796         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3797         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3798                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3799         else
3800                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3801 }
3802 /*
3803 **********************************************************************
3804 **********************************************************************
3805 */
3806 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3807 {
3808         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3809         char *acb_firm_model = acb->firm_model;
3810         char *acb_firm_version = acb->firm_version;
3811         char *acb_device_map = acb->device_map;
3812         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3813         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3814         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3815         int i;
3816
3817         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3818         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3819                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3820         }
3821         i = 0;
3822         while(i < 8) {
3823                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3824                 /* 8 bytes firm_model, 15, 60-67*/
3825                 acb_firm_model++;
3826                 i++;
3827         }
3828         i = 0;
3829         while(i < 16) {
3830                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3831                 /* 16 bytes firm_version, 17, 68-83*/
3832                 acb_firm_version++;
3833                 i++;
3834         }
3835         i = 0;
3836         while(i < 16) {
3837                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3838                 acb_device_map++;
3839                 i++;
3840         }
3841         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3842         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3843         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3844         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3845         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3846         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3847         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3848                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3849         else
3850                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3851 }
3852 /*
3853 **********************************************************************
3854 **********************************************************************
3855 */
3856 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3857 {
3858         char *acb_firm_model = acb->firm_model;
3859         char *acb_firm_version = acb->firm_version;
3860         char *acb_device_map = acb->device_map;
3861         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3862         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3863         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3864         int i;
3865
3866         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3867         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3868         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3869                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3870         }
3871         i = 0;
3872         while(i < 8) {
3873                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3874                 /* 8 bytes firm_model, 15, 60-67*/
3875                 acb_firm_model++;
3876                 i++;
3877         }
3878         i = 0;
3879         while(i < 16) {
3880                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3881                 /* 16 bytes firm_version, 17, 68-83*/
3882                 acb_firm_version++;
3883                 i++;
3884         }
3885         i = 0;
3886         while(i < 16) {
3887                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3888                 acb_device_map++;
3889                 i++;
3890         }
3891         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3892         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3893         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3894         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3895         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3896         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3897         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3898                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3899         else
3900                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3901 }
3902 /*
3903 **********************************************************************
3904 **********************************************************************
3905 */
3906 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3907 {
3908         char *acb_firm_model = acb->firm_model;
3909         char *acb_firm_version = acb->firm_version;
3910         char *acb_device_map = acb->device_map;
3911         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3912         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3913         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3914         int i;
3915
3916         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3917                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3918         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3919         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3920                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3921         }
3922         i = 0;
3923         while(i < 8) {
3924                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3925                 /* 8 bytes firm_model, 15, 60-67*/
3926                 acb_firm_model++;
3927                 i++;
3928         }
3929         i = 0;
3930         while(i < 16) {
3931                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3932                 /* 16 bytes firm_version, 17, 68-83*/
3933                 acb_firm_version++;
3934                 i++;
3935         }
3936         i = 0;
3937         while(i < 16) {
3938                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3939                 acb_device_map++;
3940                 i++;
3941         }
3942         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3943         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3944         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3945         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3946         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3947         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3948         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3949                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3950         else
3951                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3952 }
3953 /*
3954 **********************************************************************
3955 **********************************************************************
3956 */
3957 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3958 {
3959         char *acb_firm_model = acb->firm_model;
3960         char *acb_firm_version = acb->firm_version;
3961         char *acb_device_map = acb->device_map;
3962         size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3963         size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3964         size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3965         int i;
3966
3967         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3968         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3969         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3970         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3971                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3972         }
3973
3974         i = 0;
3975         while(i < 8) {
3976                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3977                 /* 8 bytes firm_model, 15, 60-67*/
3978                 acb_firm_model++;
3979                 i++;
3980         }
3981         i = 0;
3982         while(i < 16) {
3983                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3984                 /* 16 bytes firm_version, 17, 68-83*/
3985                 acb_firm_version++;
3986                 i++;
3987         }
3988         i = 0;
3989         while(i < 16) {
3990                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3991                 acb_device_map++;
3992                 i++;
3993         }
3994         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3995         acb->firm_request_len   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3996         acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3997         acb->firm_sdram_size    = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3998         acb->firm_ide_channels  = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3999         acb->firm_cfg_version   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
4000         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4001                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4002         else
4003                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4004 }
4005 /*
4006 **********************************************************************
4007 **********************************************************************
4008 */
4009 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4010 {
4011         switch (acb->adapter_type) {
4012         case ACB_ADAPTER_TYPE_A: {
4013                         arcmsr_get_hba_config(acb);
4014                 }
4015                 break;
4016         case ACB_ADAPTER_TYPE_B: {
4017                         arcmsr_get_hbb_config(acb);
4018                 }
4019                 break;
4020         case ACB_ADAPTER_TYPE_C: {
4021                         arcmsr_get_hbc_config(acb);
4022                 }
4023                 break;
4024         case ACB_ADAPTER_TYPE_D: {
4025                         arcmsr_get_hbd_config(acb);
4026                 }
4027                 break;
4028         case ACB_ADAPTER_TYPE_E: {
4029                         arcmsr_get_hbe_config(acb);
4030                 }
4031                 break;
4032         }
4033 }
4034 /*
4035 **********************************************************************
4036 **********************************************************************
4037 */
4038 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4039 {
4040         int     timeout=0;
4041
4042         switch (acb->adapter_type) {
4043         case ACB_ADAPTER_TYPE_A: {
4044                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
4045                         {
4046                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4047                                 {
4048                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
4049                                         return;
4050                                 }
4051                                 UDELAY(15000); /* wait 15 milli-seconds */
4052                         }
4053                 }
4054                 break;
4055         case ACB_ADAPTER_TYPE_B: {
4056                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4057                         while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
4058                         {
4059                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4060                                 {
4061                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
4062                                         return;
4063                                 }
4064                                 UDELAY(15000); /* wait 15 milli-seconds */
4065                         }
4066                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
4067                 }
4068                 break;
4069         case ACB_ADAPTER_TYPE_C: {
4070                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
4071                         {
4072                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4073                                 {
4074                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4075                                         return;
4076                                 }
4077                                 UDELAY(15000); /* wait 15 milli-seconds */
4078                         }
4079                 }
4080                 break;
4081         case ACB_ADAPTER_TYPE_D: {
4082                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
4083                         {
4084                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4085                                 {
4086                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4087                                         return;
4088                                 }
4089                                 UDELAY(15000); /* wait 15 milli-seconds */
4090                         }
4091                 }
4092                 break;
4093         case ACB_ADAPTER_TYPE_E: {
4094                         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4095                         {
4096                                 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4097                                 {
4098                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4099                                         return;
4100                                 }
4101                                 UDELAY(15000); /* wait 15 milli-seconds */
4102                         }
4103                 }
4104                 break;
4105         }
4106 }
4107 /*
4108 **********************************************************************
4109 **********************************************************************
4110 */
4111 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
4112 {
4113         u_int32_t outbound_doorbell;
4114
4115         switch (acb->adapter_type) {
4116         case ACB_ADAPTER_TYPE_A: {
4117                         /* empty doorbell Qbuffer if door bell ringed */
4118                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
4119                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
4120                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
4121                 }
4122                 break;
4123         case ACB_ADAPTER_TYPE_B: {
4124                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4125                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
4126                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
4127                         /* let IOP know data has been read */
4128                 }
4129                 break;
4130         case ACB_ADAPTER_TYPE_C: {
4131                         /* empty doorbell Qbuffer if door bell ringed */
4132                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4133                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
4134                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4135                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4136                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4137                 }
4138                 break;
4139         case ACB_ADAPTER_TYPE_D: {
4140                         /* empty doorbell Qbuffer if door bell ringed */
4141                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4142                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
4143                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4144                 }
4145                 break;
4146         case ACB_ADAPTER_TYPE_E: {
4147                         /* empty doorbell Qbuffer if door bell ringed */
4148                         acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4149                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);       /*clear doorbell interrupt */
4150                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4151                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4152                 }
4153                 break;
4154         }
4155 }
4156 /*
4157 ************************************************************************
4158 ************************************************************************
4159 */
4160 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4161 {
4162         unsigned long srb_phyaddr;
4163         u_int32_t srb_phyaddr_hi32;
4164         u_int32_t srb_phyaddr_lo32;
4165
4166         /*
4167         ********************************************************************
4168         ** here we need to tell iop 331 our freesrb.HighPart
4169         ** if freesrb.HighPart is not zero
4170         ********************************************************************
4171         */
4172         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4173         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4174         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4175         switch (acb->adapter_type) {
4176         case ACB_ADAPTER_TYPE_A: {
4177                         if(srb_phyaddr_hi32 != 0) {
4178                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4179                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4180                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4181                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4182                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4183                                         return FALSE;
4184                                 }
4185                         }
4186                 }
4187                 break;
4188                 /*
4189                 ***********************************************************************
4190                 **    if adapter type B, set window of "post command Q"
4191                 ***********************************************************************
4192                 */
4193         case ACB_ADAPTER_TYPE_B: {
4194                         u_int32_t post_queue_phyaddr;
4195                         struct HBB_MessageUnit *phbbmu;
4196
4197                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4198                         phbbmu->postq_index = 0;
4199                         phbbmu->doneq_index = 0;
4200                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4201                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4202                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4203                                 return FALSE;
4204                         }
4205                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4206                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4207                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4208                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4209                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4210                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4211                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4212                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4213                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4214                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4215                                 return FALSE;
4216                         }
4217                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4218                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4219                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4220                                 return FALSE;
4221                         }
4222                 }
4223                 break;
4224         case ACB_ADAPTER_TYPE_C: {
4225                         if(srb_phyaddr_hi32 != 0) {
4226                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4227                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4228                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4229                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4230                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4231                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4232                                         return FALSE;
4233                                 }
4234                         }
4235                 }
4236                 break;
4237         case ACB_ADAPTER_TYPE_D: {
4238                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4239                         struct HBD_MessageUnit0 *phbdmu;
4240
4241                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4242                         phbdmu->postq_index = 0;
4243                         phbdmu->doneq_index = 0x40FF;
4244                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4245                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4246                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4247                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4248                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4249                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4250                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4251                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4252                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4253                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4254                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4255                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4256                                 return FALSE;
4257                         }
4258                 }
4259                 break;
4260         case ACB_ADAPTER_TYPE_E: {
4261                         u_int32_t cdb_phyaddr_lo32;
4262                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4263                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4264                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4265                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4266                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4267                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4268                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4269                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4270                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4271                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4272                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4273                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4274                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4275                         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4276                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4277                                 return FALSE;
4278                         }
4279                 }
4280                 break;
4281         }
4282         return (TRUE);
4283 }
4284 /*
4285 ************************************************************************
4286 ************************************************************************
4287 */
4288 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4289 {
4290         if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4291         {
4292                 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4293                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4294                 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4295                         printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4296                         return;
4297                 }
4298         }
4299 }
4300 /*
4301 **********************************************************************
4302 **********************************************************************
4303 */
4304 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4305 {
4306         u_int32_t intmask_org;
4307
4308         /* disable all outbound interrupt */
4309         intmask_org = arcmsr_disable_allintr(acb);
4310         arcmsr_wait_firmware_ready(acb);
4311         arcmsr_iop_confirm(acb);
4312         arcmsr_get_firmware_spec(acb);
4313         /*start background rebuild*/
4314         arcmsr_start_adapter_bgrb(acb);
4315         /* empty doorbell Qbuffer if door bell ringed */
4316         arcmsr_clear_doorbell_queue_buffer(acb);
4317         arcmsr_enable_eoi_mode(acb);
4318         /* enable outbound Post Queue, outbound doorbell Interrupt */
4319         arcmsr_enable_allintr(acb, intmask_org);
4320         acb->acb_flags |= ACB_F_IOP_INITED;
4321 }
4322 /*
4323 **********************************************************************
4324 **********************************************************************
4325 */
4326 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4327 {
4328         struct AdapterControlBlock *acb = arg;
4329         struct CommandControlBlock *srb_tmp;
4330         u_int32_t i;
4331         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4332
4333         acb->srb_phyaddr.phyaddr = srb_phyaddr;
4334         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4335         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4336                 if(bus_dmamap_create(acb->dm_segs_dmat,
4337                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4338                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4339                         printf("arcmsr%d:"
4340                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4341                         return;
4342                 }
4343                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4344                          || (acb->adapter_type == ACB_ADAPTER_TYPE_E))
4345                 {
4346                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4347                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4348                 }
4349                 else
4350                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4351                 srb_tmp->acb = acb;
4352                 srb_tmp->smid = i << 16;
4353                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4354                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4355                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4356         }
4357         if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4358                 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4359         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4360 }
4361 /*
4362 ************************************************************************
4363 ************************************************************************
4364 */
4365 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4366 {
4367         /* remove the control device */
4368         if(acb->ioctl_dev != NULL) {
4369                 destroy_dev(acb->ioctl_dev);
4370         }
4371         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4372         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4373         bus_dma_tag_destroy(acb->srb_dmat);
4374         bus_dma_tag_destroy(acb->dm_segs_dmat);
4375         bus_dma_tag_destroy(acb->parent_dmat);
4376 }
4377 /*
4378 ************************************************************************
4379 ************************************************************************
4380 */
4381 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4382 {
4383         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4384         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4385         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4386         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4387 }
4388 /*
4389 ************************************************************************
4390 ************************************************************************
4391 */
4392 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4393 {
4394         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4395         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4396         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4397         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4398 }
4399 /*
4400 ************************************************************************
4401 ************************************************************************
4402 */
4403 static u_int32_t arcmsr_initialize(device_t dev)
4404 {
4405         struct AdapterControlBlock *acb = device_get_softc(dev);
4406         u_int16_t pci_command;
4407         int i, j,max_coherent_size;
4408         u_int32_t vendor_dev_id;
4409
4410         vendor_dev_id = pci_get_devid(dev);
4411         acb->vendor_device_id = vendor_dev_id;
4412         acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4413         switch (vendor_dev_id) {
4414         case PCIDevVenIDARC1880:
4415         case PCIDevVenIDARC1882:
4416         case PCIDevVenIDARC1213:
4417         case PCIDevVenIDARC1223: {
4418                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
4419                         if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4420                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4421                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4422                                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4423                         else
4424                                 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4425                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4426                 }
4427                 break;
4428         case PCIDevVenIDARC1884:
4429                 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4430                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4431                 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4432                 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4433                 break;
4434         case PCIDevVenIDARC1214: {
4435                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
4436                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4437                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4438                 }
4439                 break;
4440         case PCIDevVenIDARC1200:
4441         case PCIDevVenIDARC1201: {
4442                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4443                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4444                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4445                 }
4446                 break;
4447         case PCIDevVenIDARC1203: {
4448                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4449                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4450                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4451                 }
4452                 break;
4453         case PCIDevVenIDARC1110:
4454         case PCIDevVenIDARC1120:
4455         case PCIDevVenIDARC1130:
4456         case PCIDevVenIDARC1160:
4457         case PCIDevVenIDARC1170:
4458         case PCIDevVenIDARC1210:
4459         case PCIDevVenIDARC1220:
4460         case PCIDevVenIDARC1230:
4461         case PCIDevVenIDARC1231:
4462         case PCIDevVenIDARC1260:
4463         case PCIDevVenIDARC1261:
4464         case PCIDevVenIDARC1270:
4465         case PCIDevVenIDARC1280:
4466         case PCIDevVenIDARC1212:
4467         case PCIDevVenIDARC1222:
4468         case PCIDevVenIDARC1380:
4469         case PCIDevVenIDARC1381:
4470         case PCIDevVenIDARC1680:
4471         case PCIDevVenIDARC1681: {
4472                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4473                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4474                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4475                 }
4476                 break;
4477         default: {
4478                         printf("arcmsr%d:"
4479                         " unknown RAID adapter type \n", device_get_unit(dev));
4480                         return ENOMEM;
4481                 }
4482         }
4483 #if __FreeBSD_version >= 700000
4484         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4485 #else
4486         if(bus_dma_tag_create(  /*PCI parent*/          NULL,
4487 #endif
4488                                 /*alignemnt*/           1,
4489                                 /*boundary*/            0,
4490                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4491                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4492                                 /*filter*/              NULL,
4493                                 /*filterarg*/           NULL,
4494                                 /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4495                                 /*nsegments*/           BUS_SPACE_UNRESTRICTED,
4496                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4497                                 /*flags*/               0,
4498 #if __FreeBSD_version >= 501102
4499                                 /*lockfunc*/            NULL,
4500                                 /*lockarg*/             NULL,
4501 #endif
4502                                                         &acb->parent_dmat) != 0)
4503         {
4504                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4505                 return ENOMEM;
4506         }
4507
4508         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4509         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4510                                 /*alignment*/           1,
4511                                 /*boundary*/            0,
4512 #ifdef PAE
4513                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4514 #else
4515                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4516 #endif
4517                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4518                                 /*filter*/              NULL,
4519                                 /*filterarg*/           NULL,
4520                                 /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4521                                 /*nsegments*/           ARCMSR_MAX_SG_ENTRIES,
4522                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4523                                 /*flags*/               0,
4524 #if __FreeBSD_version >= 501102
4525                                 /*lockfunc*/            busdma_lock_mutex,
4526                                 /*lockarg*/             &acb->isr_lock,
4527 #endif
4528                                                         &acb->dm_segs_dmat) != 0)
4529         {
4530                 bus_dma_tag_destroy(acb->parent_dmat);
4531                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4532                 return ENOMEM;
4533         }
4534
4535         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4536         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4537                                 /*alignment*/           0x20,
4538                                 /*boundary*/            0,
4539                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4540                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4541                                 /*filter*/              NULL,
4542                                 /*filterarg*/           NULL,
4543                                 /*maxsize*/             max_coherent_size,
4544                                 /*nsegments*/           1,
4545                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4546                                 /*flags*/               0,
4547 #if __FreeBSD_version >= 501102
4548                                 /*lockfunc*/            NULL,
4549                                 /*lockarg*/             NULL,
4550 #endif
4551                                                         &acb->srb_dmat) != 0)
4552         {
4553                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4554                 bus_dma_tag_destroy(acb->parent_dmat);
4555                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4556                 return ENXIO;
4557         }
4558         /* Allocation for our srbs */
4559         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4560                 bus_dma_tag_destroy(acb->srb_dmat);
4561                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4562                 bus_dma_tag_destroy(acb->parent_dmat);
4563                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4564                 return ENXIO;
4565         }
4566         /* And permanently map them */
4567         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4568                 bus_dma_tag_destroy(acb->srb_dmat);
4569                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4570                 bus_dma_tag_destroy(acb->parent_dmat);
4571                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4572                 return ENXIO;
4573         }
4574         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4575         pci_command |= PCIM_CMD_BUSMASTEREN;
4576         pci_command |= PCIM_CMD_PERRESPEN;
4577         pci_command |= PCIM_CMD_MWRICEN;
4578         /* Enable Busmaster */
4579         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4580         switch(acb->adapter_type) {
4581         case ACB_ADAPTER_TYPE_A: {
4582                 u_int32_t rid0 = PCIR_BAR(0);
4583                 vm_offset_t     mem_base0;
4584
4585                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4586                 if(acb->sys_res_arcmsr[0] == NULL) {
4587                         arcmsr_free_resource(acb);
4588                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4589                         return ENOMEM;
4590                 }
4591                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4592                         arcmsr_free_resource(acb);
4593                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4594                         return ENXIO;
4595                 }
4596                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4597                 if(mem_base0 == 0) {
4598                         arcmsr_free_resource(acb);
4599                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4600                         return ENXIO;
4601                 }
4602                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4603                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4604                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4605                 acb->rid[0] = rid0;
4606                 }
4607                 break;
4608         case ACB_ADAPTER_TYPE_B: {
4609                 struct HBB_MessageUnit *phbbmu;
4610                 struct CommandControlBlock *freesrb;
4611                 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4612                 vm_offset_t     mem_base[]={0,0};
4613                 for(i=0; i < 2; i++) {
4614                         acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4615                         if(acb->sys_res_arcmsr[i] == NULL) {
4616                                 arcmsr_free_resource(acb);
4617                                 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4618                                 return ENOMEM;
4619                         }
4620                         if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4621                                 arcmsr_free_resource(acb);
4622                                 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4623                                 return ENXIO;
4624                         }
4625                         mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4626                         if(mem_base[i] == 0) {
4627                                 arcmsr_free_resource(acb);
4628                                 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4629                                 return ENXIO;
4630                         }
4631                         acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4632                         acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4633                 }
4634                 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4635                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4636                 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4637                 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4638                 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4639                 if (vendor_dev_id == PCIDevVenIDARC1203) {
4640                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4641                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4642                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4643                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4644                 } else {
4645                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4646                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4647                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4648                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4649                 }
4650                 acb->rid[0] = rid[0];
4651                 acb->rid[1] = rid[1];
4652                 }
4653                 break;
4654         case ACB_ADAPTER_TYPE_C: {
4655                 u_int32_t rid0 = PCIR_BAR(1);
4656                 vm_offset_t     mem_base0;
4657
4658                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4659                 if(acb->sys_res_arcmsr[0] == NULL) {
4660                         arcmsr_free_resource(acb);
4661                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4662                         return ENOMEM;
4663                 }
4664                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4665                         arcmsr_free_resource(acb);
4666                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4667                         return ENXIO;
4668                 }
4669                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4670                 if(mem_base0 == 0) {
4671                         arcmsr_free_resource(acb);
4672                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4673                         return ENXIO;
4674                 }
4675                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4676                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4677                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4678                 acb->rid[0] = rid0;
4679                 }
4680                 break;
4681         case ACB_ADAPTER_TYPE_D: {
4682                 struct HBD_MessageUnit0 *phbdmu;
4683                 u_int32_t rid0 = PCIR_BAR(0);
4684                 vm_offset_t     mem_base0;
4685
4686                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4687                 if(acb->sys_res_arcmsr[0] == NULL) {
4688                         arcmsr_free_resource(acb);
4689                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4690                         return ENOMEM;
4691                 }
4692                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4693                         arcmsr_free_resource(acb);
4694                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4695                         return ENXIO;
4696                 }
4697                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4698                 if(mem_base0 == 0) {
4699                         arcmsr_free_resource(acb);
4700                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4701                         return ENXIO;
4702                 }
4703                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4704                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4705                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4706                 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4707                 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4708                 acb->rid[0] = rid0;
4709                 }
4710                 break;
4711         case ACB_ADAPTER_TYPE_E: {
4712                 u_int32_t rid0 = PCIR_BAR(1);
4713                 vm_offset_t     mem_base0;
4714
4715                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4716                 if(acb->sys_res_arcmsr[0] == NULL) {
4717                         arcmsr_free_resource(acb);
4718                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4719                         return ENOMEM;
4720                 }
4721                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4722                         arcmsr_free_resource(acb);
4723                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4724                         return ENXIO;
4725                 }
4726                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4727                 if(mem_base0 == 0) {
4728                         arcmsr_free_resource(acb);
4729                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4730                         return ENXIO;
4731                 }
4732                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4733                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4734                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4735                 acb->doneq_index = 0;
4736                 acb->in_doorbell = 0;
4737                 acb->out_doorbell = 0;
4738                 acb->rid[0] = rid0;
4739                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4740                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4741                 }
4742                 break;
4743         }
4744         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4745                 arcmsr_free_resource(acb);
4746                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4747                 return ENXIO;
4748         }
4749         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4750         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4751         /*
4752         ********************************************************************
4753         ** init raid volume state
4754         ********************************************************************
4755         */
4756         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4757                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4758                         acb->devstate[i][j] = ARECA_RAID_GONE;
4759                 }
4760         }
4761         arcmsr_iop_init(acb);
4762         return(0);
4763 }
4764
4765 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4766 {
4767         int i;
4768
4769         for (i = 0; i < acb->msix_vectors; i++) {
4770                 acb->irq_id[i] = 1 + i;
4771                 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4772                     SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4773                 if (acb->irqres[i] == NULL) {
4774                         printf("arcmsr: Can't allocate MSI-X resource\n");
4775                         goto irq_alloc_failed;
4776                 }
4777                 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4778                     INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4779                     acb, &acb->ih[i])) {
4780                         printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4781                         goto irq_alloc_failed;
4782                 }
4783         }
4784         printf("arcmsr: MSI-X INT enabled\n");
4785         acb->acb_flags |= ACB_F_MSIX_ENABLED;
4786         return TRUE;
4787
4788 irq_alloc_failed:
4789         arcmsr_teardown_intr(acb->pci_dev, acb);
4790         return FALSE;
4791 }
4792
4793 /*
4794 ************************************************************************
4795 ************************************************************************
4796 */
4797 static int arcmsr_attach(device_t dev)
4798 {
4799         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4800         u_int32_t unit=device_get_unit(dev);
4801         struct ccb_setasync csa;
4802         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4803         struct resource *irqres;
4804
4805         if(acb == NULL) {
4806                 printf("arcmsr%d: cannot allocate softc\n", unit);
4807                 return (ENOMEM);
4808         }
4809         arcmsr_mutex_init(acb);
4810         acb->pci_dev = dev;
4811         acb->pci_unit = unit;
4812         if(arcmsr_initialize(dev)) {
4813                 printf("arcmsr%d: initialize failure!\n", unit);
4814                 goto initialize_failed;
4815         }
4816         /* After setting up the adapter, map our interrupt */
4817         acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4818         if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4819                 if (arcmsr_setup_msix(acb) == TRUE)
4820                         goto irqx;
4821         }
4822         acb->irq_id[0] = 0;
4823         irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4824         if(irqres == NULL ||
4825 #if __FreeBSD_version >= 700025
4826                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4827 #else
4828                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih[0])) {
4829 #endif
4830                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4831                 goto setup_intr_failed;
4832         }
4833         acb->irqres[0] = irqres;
4834 irqx:
4835         /*
4836          * Now let the CAM generic SCSI layer find the SCSI devices on
4837          * the bus *  start queue to reset to the idle loop. *
4838          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4839          * max_sim_transactions
4840         */
4841         devq = cam_simq_alloc(acb->maxOutstanding);
4842         if(devq == NULL) {
4843                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4844                 goto simq_alloc_failed;
4845         }
4846 #if __FreeBSD_version >= 700025
4847         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4848 #else
4849         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4850 #endif
4851         if(acb->psim == NULL) {
4852                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4853                 goto sim_alloc_failed;
4854         }
4855         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4856 #if __FreeBSD_version >= 700044
4857         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4858 #else
4859         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4860 #endif
4861                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4862                 goto xpt_bus_failed;
4863         }
4864         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4865                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4866                 goto xpt_path_failed;
4867         }
4868         /*
4869         ****************************************************
4870         */
4871         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4872         csa.ccb_h.func_code = XPT_SASYNC_CB;
4873         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4874         csa.callback = arcmsr_async;
4875         csa.callback_arg = acb->psim;
4876         xpt_action((union ccb *)&csa);
4877         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4878         /* Create the control device.  */
4879         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4880
4881 #if __FreeBSD_version < 503000
4882         acb->ioctl_dev->si_drv1 = acb;
4883 #endif
4884 #if __FreeBSD_version > 500005
4885         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4886 #endif
4887         arcmsr_callout_init(&acb->devmap_callout);
4888         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4889         return (0);
4890 xpt_path_failed:
4891         xpt_bus_deregister(cam_sim_path(acb->psim));
4892 xpt_bus_failed:
4893         cam_sim_free(acb->psim, /* free_simq */ TRUE);
4894 sim_alloc_failed:
4895         cam_simq_free(devq);
4896 simq_alloc_failed:
4897         arcmsr_teardown_intr(dev, acb);
4898 setup_intr_failed:
4899         arcmsr_free_resource(acb);
4900 initialize_failed:
4901         arcmsr_mutex_destroy(acb);
4902         return ENXIO;
4903 }
4904
4905 /*
4906 ************************************************************************
4907 ************************************************************************
4908 */
4909 static int arcmsr_probe(device_t dev)
4910 {
4911         u_int32_t id;
4912         u_int16_t sub_device_id;
4913         static char buf[256];
4914         char x_type[]={"unknown"};
4915         char *type;
4916         int raid6 = 1;
4917
4918         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4919                 return (ENXIO);
4920         }
4921         sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4922         switch(id = pci_get_devid(dev)) {
4923         case PCIDevVenIDARC1110:
4924         case PCIDevVenIDARC1200:
4925         case PCIDevVenIDARC1201:
4926         case PCIDevVenIDARC1210:
4927                 raid6 = 0;
4928                 /*FALLTHRU*/
4929         case PCIDevVenIDARC1120:
4930         case PCIDevVenIDARC1130:
4931         case PCIDevVenIDARC1160:
4932         case PCIDevVenIDARC1170:
4933         case PCIDevVenIDARC1220:
4934         case PCIDevVenIDARC1230:
4935         case PCIDevVenIDARC1231:
4936         case PCIDevVenIDARC1260:
4937         case PCIDevVenIDARC1261:
4938         case PCIDevVenIDARC1270:
4939         case PCIDevVenIDARC1280:
4940                 type = "SATA 3G";
4941                 break;
4942         case PCIDevVenIDARC1212:
4943         case PCIDevVenIDARC1222:
4944         case PCIDevVenIDARC1380:
4945         case PCIDevVenIDARC1381:
4946         case PCIDevVenIDARC1680:
4947         case PCIDevVenIDARC1681:
4948                 type = "SAS 3G";
4949                 break;
4950         case PCIDevVenIDARC1880:
4951         case PCIDevVenIDARC1882:
4952         case PCIDevVenIDARC1213:
4953         case PCIDevVenIDARC1223:
4954                 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4955                     (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4956                     (sub_device_id == ARECA_SUB_DEV_ID_1226))
4957                         type = "SAS 12G";
4958                 else
4959                         type = "SAS 6G";
4960                 break;
4961         case PCIDevVenIDARC1884:
4962                 type = "SAS 12G";
4963                 break;
4964         case PCIDevVenIDARC1214:
4965         case PCIDevVenIDARC1203:
4966                 type = "SATA 6G";
4967                 break;
4968         default:
4969                 type = x_type;
4970                 raid6 = 0;
4971                 break;
4972         }
4973         if(type == x_type)
4974                 return(ENXIO);
4975         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4976                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4977         device_set_desc_copy(dev, buf);
4978         return (BUS_PROBE_DEFAULT);
4979 }
4980 /*
4981 ************************************************************************
4982 ************************************************************************
4983 */
4984 static int arcmsr_shutdown(device_t dev)
4985 {
4986         u_int32_t  i;
4987         u_int32_t intmask_org;
4988         struct CommandControlBlock *srb;
4989         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4990
4991         /* stop adapter background rebuild */
4992         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4993         /* disable all outbound interrupt */
4994         intmask_org = arcmsr_disable_allintr(acb);
4995         arcmsr_stop_adapter_bgrb(acb);
4996         arcmsr_flush_adapter_cache(acb);
4997         /* abort all outstanding command */
4998         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4999         acb->acb_flags &= ~ACB_F_IOP_INITED;
5000         if(acb->srboutstandingcount != 0) {
5001                 /*clear and abort all outbound posted Q*/
5002                 arcmsr_done4abort_postqueue(acb);
5003                 /* talk to iop 331 outstanding command aborted*/
5004                 arcmsr_abort_allcmd(acb);
5005                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
5006                         srb = acb->psrb_pool[i];
5007                         if(srb->srb_state == ARCMSR_SRB_START) {
5008                                 srb->srb_state = ARCMSR_SRB_ABORTED;
5009                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
5010                                 arcmsr_srb_complete(srb, 1);
5011                         }
5012                 }
5013         }
5014         acb->srboutstandingcount = 0;
5015         acb->workingsrb_doneindex = 0;
5016         acb->workingsrb_startindex = 0;
5017         acb->pktRequestCount = 0;
5018         acb->pktReturnCount = 0;
5019         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5020         return (0);
5021 }
5022 /*
5023 ************************************************************************
5024 ************************************************************************
5025 */
5026 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
5027 {
5028         int i;
5029
5030         if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
5031                 for (i = 0; i < acb->msix_vectors; i++) {
5032                         if (acb->ih[i])
5033                                 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
5034                         if (acb->irqres[i] != NULL)
5035                                 bus_release_resource(dev, SYS_RES_IRQ,
5036                                     acb->irq_id[i], acb->irqres[i]);
5037
5038                         acb->ih[i] = NULL;
5039                 }
5040                 pci_release_msi(dev);
5041         } else {
5042                 if (acb->ih[0])
5043                         bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
5044                 if (acb->irqres[0] != NULL)
5045                         bus_release_resource(dev, SYS_RES_IRQ,
5046                             acb->irq_id[0], acb->irqres[0]);
5047                 acb->ih[0] = NULL;
5048         }
5049
5050 }
5051 /*
5052 ************************************************************************
5053 ************************************************************************
5054 */
5055 static int arcmsr_detach(device_t dev)
5056 {
5057         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5058         int i;
5059
5060         callout_stop(&acb->devmap_callout);
5061         arcmsr_teardown_intr(dev, acb);
5062         arcmsr_shutdown(dev);
5063         arcmsr_free_resource(acb);
5064         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
5065                 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
5066         }
5067         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5068         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
5069         xpt_free_path(acb->ppath);
5070         xpt_bus_deregister(cam_sim_path(acb->psim));
5071         cam_sim_free(acb->psim, TRUE);
5072         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5073         arcmsr_mutex_destroy(acb);
5074         return (0);
5075 }
5076
5077 #ifdef ARCMSR_DEBUG1
5078 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
5079 {
5080         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
5081                 return;
5082         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
5083         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
5084         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
5085         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
5086 }
5087 #endif