sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** SPDX-License-Identifier: BSD-3-Clause
  13 **
  14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  15 **
  16 ** Redistribution and use in source and binary forms, with or without
  17 ** modification, are permitted provided that the following conditions
  18 ** are met:
  19 ** 1. Redistributions of source code must retain the above copyright
  20 **    notice, this list of conditions and the following disclaimer.
  21 ** 2. Redistributions in binary form must reproduce the above copyright
  22 **    notice, this list of conditions and the following disclaimer in the
  23 **    documentation and/or other materials provided with the distribution.
  24 ** 3. The name of the author may not be used to endorse or promote products
  25 **    derived from this software without specific prior written permission.
  26 **
  27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 ********************************************************************************
  38 ** History
  39 **
  40 **    REV#         DATE         NAME        DESCRIPTION
  41 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  42 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  43 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  44 **                                          clean unused function
  45 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  46 **                                          firmware version check
  47 **                                          and firmware update notify for hardware bug fix
  48 **                                          handling if none zero high part physical address
  49 **                                          of srb resource
  50 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  51 **                                          add iop message xfer
  52 **                                          with scsi pass-through command
  53 **                                          add new device id of sas raid adapters
  54 **                                          code fit for SPARC64 & PPC
  55 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  56 **                                          and cause g_vfs_done() read write error
  57 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  58 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  59 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  60 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  61 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  62 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  63 **                                          for any one LUN device failed
  64 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  65 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  66 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  67 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  68 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  69 **              02/14/2011  Ching Huang     Modified pktRequestCount
  70 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  71 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  72 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  73 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  74 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  75 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  76 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  77 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  78 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  79 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  80 ** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
  81 ** 1.30.00.00   11/30/2015  Ching Huang     Added support ARC1203
  82 ** 1.40.00.00   07/11/2017  Ching Huang     Added support ARC1884
  83 ** 1.40.00.01   10/30/2017  Ching Huang     Fixed release memory resource
  84 ** 1.50.00.00   09/30/2020  Ching Huang     Added support ARC-1886, NVMe/SAS/SATA controller
  85 ******************************************************************************************
  86 */
  87
  88 #include <sys/cdefs.h>
  89 __FBSDID("$FreeBSD$");
  90
  91 #if 0
  92 #define ARCMSR_DEBUG1                   1
  93 #endif
  94 #include <sys/param.h>
  95 #include <sys/systm.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/bus.h>
  99 #include <sys/queue.h>
 100 #include <sys/stat.h>
 101 #include <sys/devicestat.h>
 102 #include <sys/kthread.h>
 103 #include <sys/module.h>
 104 #include <sys/proc.h>
 105 #include <sys/lock.h>
 106 #include <sys/sysctl.h>
 107 #include <sys/poll.h>
 108 #include <sys/ioccom.h>
 109 #include <vm/vm.h>
 110 #include <vm/vm_param.h>
 111 #include <vm/pmap.h>
 112
 113 #include <isa/rtc.h>
 114
 115 #include <machine/bus.h>
 116 #include <machine/resource.h>
 117 #include <machine/atomic.h>
 118 #include <sys/conf.h>
 119 #include <sys/rman.h>
 120
 121 #include <cam/cam.h>
 122 #include <cam/cam_ccb.h>
 123 #include <cam/cam_sim.h>
 124 #include <cam/cam_periph.h>
 125 #include <cam/cam_xpt_periph.h>
 126 #include <cam/cam_xpt_sim.h>
 127 #include <cam/cam_debug.h>
 128 #include <cam/scsi/scsi_all.h>
 129 #include <cam/scsi/scsi_message.h>
 130 /*
 131 **************************************************************************
 132 **************************************************************************
 133 */
 134 #include <sys/selinfo.h>
 135 #include <sys/mutex.h>
 136 #include <sys/endian.h>
 137 #include <dev/pci/pcivar.h>
 138 #include <dev/pci/pcireg.h>
 139
 140 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 141
 142 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.50.00.00 2020-09-30"
 143 #include <dev/arcmsr/arcmsr.h>
 144 /*
 145 **************************************************************************
 146 **************************************************************************
 147 */
 148 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 149 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 150 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 151 static int arcmsr_probe(device_t dev);
 152 static int arcmsr_attach(device_t dev);
 153 static int arcmsr_detach(device_t dev);
 154 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 155 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 156 static int arcmsr_shutdown(device_t dev);
 157 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 158 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 159 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 160 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 161 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 162 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 163 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 164 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 165 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 166 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 167 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 168 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 169 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 170 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 171 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 172 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 173 static int arcmsr_resume(device_t dev);
 174 static int arcmsr_suspend(device_t dev);
 175 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 176 static void arcmsr_polling_devmap(void *arg);
 177 static void arcmsr_srb_timeout(void *arg);
 178 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 179 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
 180 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
 181 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
 182 #ifdef ARCMSR_DEBUG1
 183 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 184 #endif
 185 /*
 186 **************************************************************************
 187 **************************************************************************
 188 */
 189 static void UDELAY(u_int32_t us) { DELAY(us); }
 190 /*
 191 **************************************************************************
 192 **************************************************************************
 193 */
 194 static bus_dmamap_callback_t arcmsr_map_free_srb;
 195 static bus_dmamap_callback_t arcmsr_execute_srb;
 196 /*
 197 **************************************************************************
 198 **************************************************************************
 199 */
 200 static d_open_t arcmsr_open;
 201 static d_close_t arcmsr_close;
 202 static d_ioctl_t arcmsr_ioctl;
 203
 204 static device_method_t arcmsr_methods[]={
 205         DEVMETHOD(device_probe,         arcmsr_probe),
 206         DEVMETHOD(device_attach,        arcmsr_attach),
 207         DEVMETHOD(device_detach,        arcmsr_detach),
 208         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 209         DEVMETHOD(device_suspend,       arcmsr_suspend),
 210         DEVMETHOD(device_resume,        arcmsr_resume),
 211         DEVMETHOD_END
 212 };
 213
 214 static driver_t arcmsr_driver={
 215         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 216 };
 217
 218 static devclass_t arcmsr_devclass;
 219 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 220 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 221 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 222 #ifndef BUS_DMA_COHERENT
 223         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 224 #endif
 225 static struct cdevsw arcmsr_cdevsw={
 226                 .d_version = D_VERSION,
 227                 .d_open    = arcmsr_open,       /* open     */
 228                 .d_close   = arcmsr_close,      /* close    */
 229                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 230                 .d_name    = "arcmsr",          /* name     */
 231         };
 232 /*
 233 **************************************************************************
 234 **************************************************************************
 235 */
 236 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 237 {
 238         int     unit = dev2unit(dev);
 239         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 240
 241         if (acb == NULL) {
 242                 return ENXIO;
 243         }
 244         return (0);
 245 }
 246 /*
 247 **************************************************************************
 248 **************************************************************************
 249 */
 250 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 251 {
 252         int     unit = dev2unit(dev);
 253         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 254
 255         if (acb == NULL) {
 256                 return ENXIO;
 257         }
 258         return 0;
 259 }
 260 /*
 261 **************************************************************************
 262 **************************************************************************
 263 */
 264 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 265 {
 266         int     unit = dev2unit(dev);
 267         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 268
 269         if (acb == NULL) {
 270                 return ENXIO;
 271         }
 272         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 273 }
 274 /*
 275 **********************************************************************
 276 **********************************************************************
 277 */
 278 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 279 {
 280         u_int32_t intmask_org = 0;
 281
 282         switch (acb->adapter_type) {
 283         case ACB_ADAPTER_TYPE_A: {
 284                         /* disable all outbound interrupt */
 285                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 286                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 287                 }
 288                 break;
 289         case ACB_ADAPTER_TYPE_B: {
 290                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 291                         /* disable all outbound interrupt */
 292                         intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
 293                                                 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 294                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
 295                 }
 296                 break;
 297         case ACB_ADAPTER_TYPE_C: {
 298                         /* disable all outbound interrupt */
 299                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
 300                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 301                 }
 302                 break;
 303         case ACB_ADAPTER_TYPE_D: {
 304                         /* disable all outbound interrupt */
 305                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
 306                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 307                 }
 308                 break;
 309         case ACB_ADAPTER_TYPE_E:
 310         case ACB_ADAPTER_TYPE_F: {
 311                         /* disable all outbound interrupt */
 312                         intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
 313                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
 314                 }
 315                 break;
 316         }
 317         return (intmask_org);
 318 }
 319 /*
 320 **********************************************************************
 321 **********************************************************************
 322 */
 323 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 324 {
 325         u_int32_t mask;
 326
 327         switch (acb->adapter_type) {
 328         case ACB_ADAPTER_TYPE_A: {
 329                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 330                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 331                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 332                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 333                 }
 334                 break;
 335         case ACB_ADAPTER_TYPE_B: {
 336                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 337                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 338                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 339                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 340                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 341                 }
 342                 break;
 343         case ACB_ADAPTER_TYPE_C: {
 344                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 345                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 346                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 347                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 348                 }
 349                 break;
 350         case ACB_ADAPTER_TYPE_D: {
 351                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 352                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 353                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 354                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 355                         acb->outbound_int_enable = mask;
 356                 }
 357                 break;
 358         case ACB_ADAPTER_TYPE_E:
 359         case ACB_ADAPTER_TYPE_F: {
 360                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 361                         mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
 362                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
 363                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 364                 }
 365                 break;
 366         }
 367 }
 368 /*
 369 **********************************************************************
 370 **********************************************************************
 371 */
 372 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 373 {
 374         u_int32_t Index;
 375         u_int8_t Retries = 0x00;
 376
 377         do {
 378                 for(Index=0; Index < 100; Index++) {
 379                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 380                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 381                                 return TRUE;
 382                         }
 383                         UDELAY(10000);
 384                 }/*max 1 seconds*/
 385         }while(Retries++ < 20);/*max 20 sec*/
 386         return (FALSE);
 387 }
 388 /*
 389 **********************************************************************
 390 **********************************************************************
 391 */
 392 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 393 {
 394         u_int32_t Index;
 395         u_int8_t Retries = 0x00;
 396         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 397
 398         do {
 399                 for(Index=0; Index < 100; Index++) {
 400                         if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 401                                 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 402                                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 403                                 return TRUE;
 404                         }
 405                         UDELAY(10000);
 406                 }/*max 1 seconds*/
 407         }while(Retries++ < 20);/*max 20 sec*/
 408         return (FALSE);
 409 }
 410 /*
 411 **********************************************************************
 412 **********************************************************************
 413 */
 414 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 415 {
 416         u_int32_t Index;
 417         u_int8_t Retries = 0x00;
 418
 419         do {
 420                 for(Index=0; Index < 100; Index++) {
 421                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 422                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 423                                 return TRUE;
 424                         }
 425                         UDELAY(10000);
 426                 }/*max 1 seconds*/
 427         }while(Retries++ < 20);/*max 20 sec*/
 428         return (FALSE);
 429 }
 430 /*
 431 **********************************************************************
 432 **********************************************************************
 433 */
 434 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 435 {
 436         u_int32_t Index;
 437         u_int8_t Retries = 0x00;
 438
 439         do {
 440                 for(Index=0; Index < 100; Index++) {
 441                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 442                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 443                                 return TRUE;
 444                         }
 445                         UDELAY(10000);
 446                 }/*max 1 seconds*/
 447         }while(Retries++ < 20);/*max 20 sec*/
 448         return (FALSE);
 449 }
 450 /*
 451 **********************************************************************
 452 **********************************************************************
 453 */
 454 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
 455 {
 456         u_int32_t Index, read_doorbell;
 457         u_int8_t Retries = 0x00;
 458
 459         do {
 460                 for(Index=0; Index < 100; Index++) {
 461                         read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
 462                         if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
 463                                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
 464                                 acb->in_doorbell = read_doorbell;
 465                                 return TRUE;
 466                         }
 467                         UDELAY(10000);
 468                 }/*max 1 seconds*/
 469         }while(Retries++ < 20);/*max 20 sec*/
 470         return (FALSE);
 471 }
 472 /*
 473 ************************************************************************
 474 ************************************************************************
 475 */
 476 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 477 {
 478         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 479
 480         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 481         do {
 482                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 483                         break;
 484                 } else {
 485                         retry_count--;
 486                 }
 487         }while(retry_count != 0);
 488 }
 489 /*
 490 ************************************************************************
 491 ************************************************************************
 492 */
 493 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 494 {
 495         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 496         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 497
 498         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 499         do {
 500                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 501                         break;
 502                 } else {
 503                         retry_count--;
 504                 }
 505         }while(retry_count != 0);
 506 }
 507 /*
 508 ************************************************************************
 509 ************************************************************************
 510 */
 511 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 512 {
 513         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 514
 515         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 516         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 517         do {
 518                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 519                         break;
 520                 } else {
 521                         retry_count--;
 522                 }
 523         }while(retry_count != 0);
 524 }
 525 /*
 526 ************************************************************************
 527 ************************************************************************
 528 */
 529 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 530 {
 531         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 532
 533         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 534         do {
 535                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 536                         break;
 537                 } else {
 538                         retry_count--;
 539                 }
 540         }while(retry_count != 0);
 541 }
 542 /*
 543 ************************************************************************
 544 ************************************************************************
 545 */
 546 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
 547 {
 548         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 549
 550         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 551         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 552         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 553         do {
 554                 if(arcmsr_hbe_wait_msgint_ready(acb)) {
 555                         break;
 556                 } else {
 557                         retry_count--;
 558                 }
 559         }while(retry_count != 0);
 560 }
 561 /*
 562 ************************************************************************
 563 ************************************************************************
 564 */
 565 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 566 {
 567         switch (acb->adapter_type) {
 568         case ACB_ADAPTER_TYPE_A: {
 569                         arcmsr_flush_hba_cache(acb);
 570                 }
 571                 break;
 572         case ACB_ADAPTER_TYPE_B: {
 573                         arcmsr_flush_hbb_cache(acb);
 574                 }
 575                 break;
 576         case ACB_ADAPTER_TYPE_C: {
 577                         arcmsr_flush_hbc_cache(acb);
 578                 }
 579                 break;
 580         case ACB_ADAPTER_TYPE_D: {
 581                         arcmsr_flush_hbd_cache(acb);
 582                 }
 583                 break;
 584         case ACB_ADAPTER_TYPE_E:
 585         case ACB_ADAPTER_TYPE_F: {
 586                         arcmsr_flush_hbe_cache(acb);
 587                 }
 588                 break;
 589         }
 590 }
 591 /*
 592 *******************************************************************************
 593 *******************************************************************************
 594 */
 595 static int arcmsr_suspend(device_t dev)
 596 {
 597         struct AdapterControlBlock      *acb = device_get_softc(dev);
 598
 599         /* flush controller */
 600         arcmsr_iop_parking(acb);
 601         /* disable all outbound interrupt */
 602         arcmsr_disable_allintr(acb);
 603         return(0);
 604 }
 605 /*
 606 *******************************************************************************
 607 *******************************************************************************
 608 */
 609 static int arcmsr_resume(device_t dev)
 610 {
 611         struct AdapterControlBlock      *acb = device_get_softc(dev);
 612
 613         arcmsr_iop_init(acb);
 614         return(0);
 615 }
 616 /*
 617 *********************************************************************************
 618 *********************************************************************************
 619 */
 620 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 621 {
 622         struct AdapterControlBlock *acb;
 623         u_int8_t target_id, target_lun;
 624         struct cam_sim *sim;
 625
 626         sim = (struct cam_sim *) cb_arg;
 627         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 628         switch (code) {
 629         case AC_LOST_DEVICE:
 630                 target_id = xpt_path_target_id(path);
 631                 target_lun = xpt_path_lun_id(path);
 632                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 633                         break;
 634                 }
 635         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 636                 break;
 637         default:
 638                 break;
 639         }
 640 }
 641 /*
 642 **********************************************************************
 643 **********************************************************************
 644 */
 645 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 646 {
 647         union ccb *pccb = srb->pccb;
 648
 649         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 650         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 651         if(pccb->csio.sense_len) {
 652                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 653                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 654                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 655                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 656                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 657         }
 658 }
 659 /*
 660 *********************************************************************
 661 *********************************************************************
 662 */
 663 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 664 {
 665         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 666         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 667                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 668         }
 669 }
 670 /*
 671 *********************************************************************
 672 *********************************************************************
 673 */
 674 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 675 {
 676         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 677         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 678         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 679                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 680         }
 681 }
 682 /*
 683 *********************************************************************
 684 *********************************************************************
 685 */
 686 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 687 {
 688         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 689         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 690         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 691                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 692         }
 693 }
 694 /*
 695 *********************************************************************
 696 *********************************************************************
 697 */
 698 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 699 {
 700         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 701         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 702                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 703         }
 704 }
 705 /*
 706 *********************************************************************
 707 *********************************************************************
 708 */
 709 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
 710 {
 711         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 712         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 713         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 714         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
 715                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 716         }
 717 }
 718 /*
 719 *********************************************************************
 720 *********************************************************************
 721 */
 722 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 723 {
 724         switch (acb->adapter_type) {
 725         case ACB_ADAPTER_TYPE_A: {
 726                         arcmsr_abort_hba_allcmd(acb);
 727                 }
 728                 break;
 729         case ACB_ADAPTER_TYPE_B: {
 730                         arcmsr_abort_hbb_allcmd(acb);
 731                 }
 732                 break;
 733         case ACB_ADAPTER_TYPE_C: {
 734                         arcmsr_abort_hbc_allcmd(acb);
 735                 }
 736                 break;
 737         case ACB_ADAPTER_TYPE_D: {
 738                         arcmsr_abort_hbd_allcmd(acb);
 739                 }
 740                 break;
 741         case ACB_ADAPTER_TYPE_E:
 742         case ACB_ADAPTER_TYPE_F: {
 743                         arcmsr_abort_hbe_allcmd(acb);
 744                 }
 745                 break;
 746         }
 747 }
 748 /*
 749 **********************************************************************
 750 **********************************************************************
 751 */
 752 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 753 {
 754         struct AdapterControlBlock *acb = srb->acb;
 755         union ccb *pccb = srb->pccb;
 756
 757         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 758                 callout_stop(&srb->ccb_callout);
 759         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 760                 bus_dmasync_op_t op;
 761
 762                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 763                         op = BUS_DMASYNC_POSTREAD;
 764                 } else {
 765                         op = BUS_DMASYNC_POSTWRITE;
 766                 }
 767                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 768                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 769         }
 770         if(stand_flag == 1) {
 771                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 772                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 773                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 774                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 775                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 776                 }
 777         }
 778         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 779                 arcmsr_free_srb(srb);
 780         acb->pktReturnCount++;
 781         xpt_done(pccb);
 782 }
 783 /*
 784 **************************************************************************
 785 **************************************************************************
 786 */
 787 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 788 {
 789         int target, lun;
 790
 791         target = srb->pccb->ccb_h.target_id;
 792         lun = srb->pccb->ccb_h.target_lun;
 793         if(error == FALSE) {
 794                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 795                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 796                 }
 797                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 798                 arcmsr_srb_complete(srb, 1);
 799         } else {
 800                 switch(srb->arcmsr_cdb.DeviceStatus) {
 801                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 802                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 803                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 804                                 }
 805                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 806                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 807                                 arcmsr_srb_complete(srb, 1);
 808                         }
 809                         break;
 810                 case ARCMSR_DEV_ABORTED:
 811                 case ARCMSR_DEV_INIT_FAIL: {
 812                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 813                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 814                                 arcmsr_srb_complete(srb, 1);
 815                         }
 816                         break;
 817                 case SCSISTAT_CHECK_CONDITION: {
 818                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 819                                 arcmsr_report_sense_info(srb);
 820                                 arcmsr_srb_complete(srb, 1);
 821                         }
 822                         break;
 823                 default:
 824                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 825                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 826                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 827                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 828                         /*unknown error or crc error just for retry*/
 829                         arcmsr_srb_complete(srb, 1);
 830                         break;
 831                 }
 832         }
 833 }
 834 /*
 835 **************************************************************************
 836 **************************************************************************
 837 */
 838 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 839 {
 840         struct CommandControlBlock *srb;
 841
 842         /* check if command done with no error*/
 843         switch (acb->adapter_type) {
 844         case ACB_ADAPTER_TYPE_A:
 845         case ACB_ADAPTER_TYPE_B:
 846                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 847                 break;
 848         case ACB_ADAPTER_TYPE_C:
 849         case ACB_ADAPTER_TYPE_D:
 850                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 851                 break;
 852         case ACB_ADAPTER_TYPE_E:
 853         case ACB_ADAPTER_TYPE_F:
 854                 srb = acb->psrb_pool[flag_srb];
 855                 break;
 856         default:
 857                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 858                 break;
 859         }
 860         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 861                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 862                         arcmsr_free_srb(srb);
 863                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 864                         return;
 865                 }
 866                 printf("arcmsr%d: return srb has been completed\n"
 867                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 868                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 869                 return;
 870         }
 871         arcmsr_report_srb_state(acb, srb, error);
 872 }
 873 /*
 874 **************************************************************************
 875 **************************************************************************
 876 */
 877 static void     arcmsr_srb_timeout(void *arg)
 878 {
 879         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 880         struct AdapterControlBlock *acb;
 881         int target, lun;
 882         u_int8_t cmd;
 883
 884         target = srb->pccb->ccb_h.target_id;
 885         lun = srb->pccb->ccb_h.target_lun;
 886         acb = srb->acb;
 887         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 888         if(srb->srb_state == ARCMSR_SRB_START)
 889         {
 890                 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
 891                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 892                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 893                 arcmsr_srb_complete(srb, 1);
 894                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 895                                  acb->pci_unit, target, lun, cmd, srb);
 896         }
 897         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 898 #ifdef ARCMSR_DEBUG1
 899         arcmsr_dump_data(acb);
 900 #endif
 901 }
 902
 903 /*
 904 **********************************************************************
 905 **********************************************************************
 906 */
 907 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 908 {
 909         int i=0;
 910         u_int32_t flag_srb;
 911         u_int16_t error;
 912
 913         switch (acb->adapter_type) {
 914         case ACB_ADAPTER_TYPE_A: {
 915                         u_int32_t outbound_intstatus;
 916
 917                         /*clear and abort all outbound posted Q*/
 918                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 919                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 920                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 921                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 922                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 923                         }
 924                 }
 925                 break;
 926         case ACB_ADAPTER_TYPE_B: {
 927                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 928
 929                         /*clear all outbound posted Q*/
 930                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 931                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 932                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 933                                         phbbmu->done_qbuffer[i] = 0;
 934                                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 935                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 936                                 }
 937                                 phbbmu->post_qbuffer[i] = 0;
 938                         }/*drain reply FIFO*/
 939                         phbbmu->doneq_index = 0;
 940                         phbbmu->postq_index = 0;
 941                 }
 942                 break;
 943         case ACB_ADAPTER_TYPE_C: {
 944                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 945                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 946                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 947                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 948                         }
 949                 }
 950                 break;
 951         case ACB_ADAPTER_TYPE_D:
 952                 arcmsr_hbd_postqueue_isr(acb);
 953                 break;
 954         case ACB_ADAPTER_TYPE_E:
 955                 arcmsr_hbe_postqueue_isr(acb);
 956                 break;
 957         case ACB_ADAPTER_TYPE_F:
 958                 arcmsr_hbf_postqueue_isr(acb);
 959                 break;
 960         }
 961 }
 962 /*
 963 ****************************************************************************
 964 ****************************************************************************
 965 */
 966 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 967 {
 968         struct CommandControlBlock *srb;
 969         u_int32_t intmask_org;
 970         u_int32_t i=0;
 971
 972         if(acb->srboutstandingcount>0) {
 973                 /* disable all outbound interrupt */
 974                 intmask_org = arcmsr_disable_allintr(acb);
 975                 /*clear and abort all outbound posted Q*/
 976                 arcmsr_done4abort_postqueue(acb);
 977                 /* talk to iop 331 outstanding command aborted*/
 978                 arcmsr_abort_allcmd(acb);
 979                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 980                         srb = acb->psrb_pool[i];
 981                         if(srb->srb_state == ARCMSR_SRB_START) {
 982                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 983                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 984                                 arcmsr_srb_complete(srb, 1);
 985                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
 986                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 987                                                 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 988                         }
 989                 }
 990                 /* enable all outbound interrupt */
 991                 arcmsr_enable_allintr(acb, intmask_org);
 992         }
 993         acb->srboutstandingcount = 0;
 994         acb->workingsrb_doneindex = 0;
 995         acb->workingsrb_startindex = 0;
 996         acb->pktRequestCount = 0;
 997         acb->pktReturnCount = 0;
 998 }
 999 /*
1000 **********************************************************************
1001 **********************************************************************
1002 */
1003 static void arcmsr_build_srb(struct CommandControlBlock *srb,
1004                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
1005 {
1006         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
1007         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
1008         u_int32_t address_lo, address_hi;
1009         union ccb *pccb = srb->pccb;
1010         struct ccb_scsiio *pcsio = &pccb->csio;
1011         u_int32_t arccdbsize = 0x30;
1012
1013         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1014         arcmsr_cdb->Bus = 0;
1015         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1016         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1017         arcmsr_cdb->Function = 1;
1018         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1019         bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1020         if(nseg != 0) {
1021                 struct AdapterControlBlock *acb = srb->acb;
1022                 bus_dmasync_op_t op;
1023                 u_int32_t length, i, cdb_sgcount = 0;
1024
1025                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1026                         op = BUS_DMASYNC_PREREAD;
1027                 } else {
1028                         op = BUS_DMASYNC_PREWRITE;
1029                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1030                         srb->srb_flags |= SRB_FLAG_WRITE;
1031                 }
1032                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1033                 for(i=0; i < nseg; i++) {
1034                         /* Get the physical address of the current data pointer */
1035                         length = arcmsr_htole32(dm_segs[i].ds_len);
1036                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1037                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1038                         if(address_hi == 0) {
1039                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1040                                 pdma_sg->address = address_lo;
1041                                 pdma_sg->length = length;
1042                                 psge += sizeof(struct SG32ENTRY);
1043                                 arccdbsize += sizeof(struct SG32ENTRY);
1044                         } else {
1045                                 u_int32_t sg64s_size = 0, tmplength = length;
1046
1047                                 while(1) {
1048                                         u_int64_t span4G, length0;
1049                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1050
1051                                         span4G = (u_int64_t)address_lo + tmplength;
1052                                         pdma_sg->addresshigh = address_hi;
1053                                         pdma_sg->address = address_lo;
1054                                         if(span4G > 0x100000000) {
1055                                                 /*see if cross 4G boundary*/
1056                                                 length0 = 0x100000000-address_lo;
1057                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1058                                                 address_hi = address_hi+1;
1059                                                 address_lo = 0;
1060                                                 tmplength = tmplength - (u_int32_t)length0;
1061                                                 sg64s_size += sizeof(struct SG64ENTRY);
1062                                                 psge += sizeof(struct SG64ENTRY);
1063                                                 cdb_sgcount++;
1064                                         } else {
1065                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1066                                                 sg64s_size += sizeof(struct SG64ENTRY);
1067                                                 psge += sizeof(struct SG64ENTRY);
1068                                                 break;
1069                                         }
1070                                 }
1071                                 arccdbsize += sg64s_size;
1072                         }
1073                         cdb_sgcount++;
1074                 }
1075                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1076                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1077                 if( arccdbsize > 256) {
1078                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1079                 }
1080         } else {
1081                 arcmsr_cdb->DataLength = 0;
1082         }
1083         srb->arc_cdb_size = arccdbsize;
1084         arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1085 }
1086 /*
1087 **************************************************************************
1088 **************************************************************************
1089 */
1090 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1091 {
1092         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1093         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1094
1095         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1096         atomic_add_int(&acb->srboutstandingcount, 1);
1097         srb->srb_state = ARCMSR_SRB_START;
1098
1099         switch (acb->adapter_type) {
1100         case ACB_ADAPTER_TYPE_A: {
1101                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1102                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1103                         } else {
1104                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1105                         }
1106                 }
1107                 break;
1108         case ACB_ADAPTER_TYPE_B: {
1109                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1110                         int ending_index, index;
1111
1112                         index = phbbmu->postq_index;
1113                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1114                         phbbmu->post_qbuffer[ending_index] = 0;
1115                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1116                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1117                         } else {
1118                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1119                         }
1120                         index++;
1121                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1122                         phbbmu->postq_index = index;
1123                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1124                 }
1125                 break;
1126         case ACB_ADAPTER_TYPE_C: {
1127                         u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1128
1129                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1130                         ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1131                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1132                         if(cdb_phyaddr_hi32)
1133                         {
1134                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1135                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1136                         }
1137                         else
1138                         {
1139                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1140                         }
1141                 }
1142                 break;
1143         case ACB_ADAPTER_TYPE_D: {
1144                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1145                         u_int16_t index_stripped;
1146                         u_int16_t postq_index;
1147                         struct InBound_SRB *pinbound_srb;
1148
1149                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1150                         postq_index = phbdmu->postq_index;
1151                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1152                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1153                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1154                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1155                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1156                         if (postq_index & 0x4000) {
1157                                 index_stripped = postq_index & 0xFF;
1158                                 index_stripped += 1;
1159                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1160                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1161                         } else {
1162                                 index_stripped = postq_index;
1163                                 index_stripped += 1;
1164                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1165                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1166                         }
1167                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1168                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1169                 }
1170                 break;
1171         case ACB_ADAPTER_TYPE_E: {
1172                         u_int32_t ccb_post_stamp, arc_cdb_size;
1173
1174                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1175                         ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1176                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1177                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1178                 }
1179                 break;
1180         case ACB_ADAPTER_TYPE_F: {
1181                         u_int32_t ccb_post_stamp, arc_cdb_size;
1182
1183                         if (srb->arc_cdb_size <= 0x300)
1184                                 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
1185                         else
1186                                 arc_cdb_size = (((srb->arc_cdb_size + 0xff) >> 8) + 2) << 1 | 1;
1187                         ccb_post_stamp = (srb->smid | arc_cdb_size);
1188                         CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
1189                         CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1190                 }
1191                 break;
1192         }
1193 }
1194 /*
1195 ************************************************************************
1196 ************************************************************************
1197 */
1198 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1199 {
1200         struct QBUFFER *qbuffer=NULL;
1201
1202         switch (acb->adapter_type) {
1203         case ACB_ADAPTER_TYPE_A: {
1204                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1205
1206                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1207                 }
1208                 break;
1209         case ACB_ADAPTER_TYPE_B: {
1210                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1211
1212                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1213                 }
1214                 break;
1215         case ACB_ADAPTER_TYPE_C: {
1216                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1217
1218                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1219                 }
1220                 break;
1221         case ACB_ADAPTER_TYPE_D: {
1222                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1223
1224                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1225                 }
1226                 break;
1227         case ACB_ADAPTER_TYPE_E: {
1228                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1229
1230                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1231                 }
1232                 break;
1233         case ACB_ADAPTER_TYPE_F:
1234                 qbuffer = (struct QBUFFER *)acb->message_rbuffer;
1235                 break;
1236         }
1237         return(qbuffer);
1238 }
1239 /*
1240 ************************************************************************
1241 ************************************************************************
1242 */
1243 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1244 {
1245         struct QBUFFER *qbuffer = NULL;
1246
1247         switch (acb->adapter_type) {
1248         case ACB_ADAPTER_TYPE_A: {
1249                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1250
1251                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1252                 }
1253                 break;
1254         case ACB_ADAPTER_TYPE_B: {
1255                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1256
1257                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1258                 }
1259                 break;
1260         case ACB_ADAPTER_TYPE_C: {
1261                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1262
1263                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1264                 }
1265                 break;
1266         case ACB_ADAPTER_TYPE_D: {
1267                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1268
1269                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1270                 }
1271                 break;
1272         case ACB_ADAPTER_TYPE_E: {
1273                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1274
1275                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1276                 }
1277                 break;
1278         case ACB_ADAPTER_TYPE_F:
1279                 qbuffer = (struct QBUFFER *)acb->message_wbuffer;
1280                 break;
1281         }
1282         return(qbuffer);
1283 }
1284 /*
1285 **************************************************************************
1286 **************************************************************************
1287 */
1288 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1289 {
1290         switch (acb->adapter_type) {
1291         case ACB_ADAPTER_TYPE_A: {
1292                         /* let IOP know data has been read */
1293                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1294                 }
1295                 break;
1296         case ACB_ADAPTER_TYPE_B: {
1297                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1298                         /* let IOP know data has been read */
1299                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1300                 }
1301                 break;
1302         case ACB_ADAPTER_TYPE_C: {
1303                         /* let IOP know data has been read */
1304                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1305                 }
1306                 break;
1307         case ACB_ADAPTER_TYPE_D: {
1308                         /* let IOP know data has been read */
1309                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1310                 }
1311                 break;
1312         case ACB_ADAPTER_TYPE_E:
1313         case ACB_ADAPTER_TYPE_F: {
1314                         /* let IOP know data has been read */
1315                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1316                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1317                 }
1318                 break;
1319         }
1320 }
1321 /*
1322 **************************************************************************
1323 **************************************************************************
1324 */
1325 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1326 {
1327         switch (acb->adapter_type) {
1328         case ACB_ADAPTER_TYPE_A: {
1329                         /*
1330                         ** push inbound doorbell tell iop, driver data write ok
1331                         ** and wait reply on next hwinterrupt for next Qbuffer post
1332                         */
1333                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1334                 }
1335                 break;
1336         case ACB_ADAPTER_TYPE_B: {
1337                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1338                         /*
1339                         ** push inbound doorbell tell iop, driver data write ok
1340                         ** and wait reply on next hwinterrupt for next Qbuffer post
1341                         */
1342                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1343                 }
1344                 break;
1345         case ACB_ADAPTER_TYPE_C: {
1346                         /*
1347                         ** push inbound doorbell tell iop, driver data write ok
1348                         ** and wait reply on next hwinterrupt for next Qbuffer post
1349                         */
1350                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1351                 }
1352                 break;
1353         case ACB_ADAPTER_TYPE_D: {
1354                         /*
1355                         ** push inbound doorbell tell iop, driver data write ok
1356                         ** and wait reply on next hwinterrupt for next Qbuffer post
1357                         */
1358                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1359                 }
1360                 break;
1361         case ACB_ADAPTER_TYPE_E:
1362         case ACB_ADAPTER_TYPE_F: {
1363                         /*
1364                         ** push inbound doorbell tell iop, driver data write ok
1365                         ** and wait reply on next hwinterrupt for next Qbuffer post
1366                         */
1367                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1368                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1369                 }
1370                 break;
1371         }
1372 }
1373 /*
1374 ************************************************************************
1375 ************************************************************************
1376 */
1377 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1378 {
1379         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1380         CHIP_REG_WRITE32(HBA_MessageUnit,
1381                 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1382         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1383                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1384                         , acb->pci_unit);
1385         }
1386 }
1387 /*
1388 ************************************************************************
1389 ************************************************************************
1390 */
1391 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1392 {
1393         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1394         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1395         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1396         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1397                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1398                         , acb->pci_unit);
1399         }
1400 }
1401 /*
1402 ************************************************************************
1403 ************************************************************************
1404 */
1405 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1406 {
1407         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1408         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1409         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1410         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1411                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1412         }
1413 }
1414 /*
1415 ************************************************************************
1416 ************************************************************************
1417 */
1418 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1419 {
1420         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1421         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1422         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1423                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1424         }
1425 }
1426 /*
1427 ************************************************************************
1428 ************************************************************************
1429 */
1430 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1431 {
1432         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1433         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1434         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1435         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1436         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1437                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1438         }
1439 }
1440 /*
1441 ************************************************************************
1442 ************************************************************************
1443 */
1444 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1445 {
1446         switch (acb->adapter_type) {
1447         case ACB_ADAPTER_TYPE_A: {
1448                         arcmsr_stop_hba_bgrb(acb);
1449                 }
1450                 break;
1451         case ACB_ADAPTER_TYPE_B: {
1452                         arcmsr_stop_hbb_bgrb(acb);
1453                 }
1454                 break;
1455         case ACB_ADAPTER_TYPE_C: {
1456                         arcmsr_stop_hbc_bgrb(acb);
1457                 }
1458                 break;
1459         case ACB_ADAPTER_TYPE_D: {
1460                         arcmsr_stop_hbd_bgrb(acb);
1461                 }
1462                 break;
1463         case ACB_ADAPTER_TYPE_E:
1464         case ACB_ADAPTER_TYPE_F: {
1465                         arcmsr_stop_hbe_bgrb(acb);
1466                 }
1467                 break;
1468         }
1469 }
1470 /*
1471 ************************************************************************
1472 ************************************************************************
1473 */
1474 static void arcmsr_poll(struct cam_sim *psim)
1475 {
1476         struct AdapterControlBlock *acb;
1477         int     mutex;
1478
1479         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1480         mutex = mtx_owned(&acb->isr_lock);
1481         if( mutex == 0 )
1482                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1483         arcmsr_interrupt(acb);
1484         if( mutex == 0 )
1485                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1486 }
1487 /*
1488 **************************************************************************
1489 **************************************************************************
1490 */
1491 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1492         struct QBUFFER *prbuffer) {
1493         u_int8_t *pQbuffer;
1494         u_int8_t *buf1 = NULL;
1495         u_int32_t *iop_data, *buf2 = NULL;
1496         u_int32_t iop_len, data_len;
1497
1498         iop_data = (u_int32_t *)prbuffer->data;
1499         iop_len = (u_int32_t)prbuffer->data_len;
1500         if ( iop_len > 0 )
1501         {
1502                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1503                 buf2 = (u_int32_t *)buf1;
1504                 if( buf1 == NULL)
1505                         return (0);
1506                 data_len = iop_len;
1507                 while(data_len >= 4)
1508                 {
1509                         *buf2++ = *iop_data++;
1510                         data_len -= 4;
1511                 }
1512                 if(data_len)
1513                         *buf2 = *iop_data;
1514                 buf2 = (u_int32_t *)buf1;
1515         }
1516         while (iop_len > 0) {
1517                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1518                 *pQbuffer = *buf1;
1519                 acb->rqbuf_lastindex++;
1520                 /* if last, index number set it to 0 */
1521                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1522                 buf1++;
1523                 iop_len--;
1524         }
1525         if(buf2)
1526                 free( (u_int8_t *)buf2, M_DEVBUF);
1527         /* let IOP know data has been read */
1528         arcmsr_iop_message_read(acb);
1529         return (1);
1530 }
1531 /*
1532 **************************************************************************
1533 **************************************************************************
1534 */
1535 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1536         struct QBUFFER *prbuffer) {
1537         u_int8_t *pQbuffer;
1538         u_int8_t *iop_data;
1539         u_int32_t iop_len;
1540
1541         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1542                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1543         }
1544         iop_data = (u_int8_t *)prbuffer->data;
1545         iop_len = (u_int32_t)prbuffer->data_len;
1546         while (iop_len > 0) {
1547                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1548                 *pQbuffer = *iop_data;
1549                 acb->rqbuf_lastindex++;
1550                 /* if last, index number set it to 0 */
1551                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1552                 iop_data++;
1553                 iop_len--;
1554         }
1555         /* let IOP know data has been read */
1556         arcmsr_iop_message_read(acb);
1557         return (1);
1558 }
1559 /*
1560 **************************************************************************
1561 **************************************************************************
1562 */
1563 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1564 {
1565         struct QBUFFER *prbuffer;
1566         int my_empty_len;
1567
1568         /*check this iop data if overflow my rqbuffer*/
1569         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1570         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1571         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1572                 (ARCMSR_MAX_QBUFFER-1);
1573         if(my_empty_len >= prbuffer->data_len) {
1574                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1575                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1576         } else {
1577                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1578         }
1579         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1580 }
1581 /*
1582 **********************************************************************
1583 **********************************************************************
1584 */
1585 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1586 {
1587         u_int8_t *pQbuffer;
1588         struct QBUFFER *pwbuffer;
1589         u_int8_t *buf1 = NULL;
1590         u_int32_t *iop_data, *buf2 = NULL;
1591         u_int32_t allxfer_len = 0, data_len;
1592
1593         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1594                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1595                 buf2 = (u_int32_t *)buf1;
1596                 if( buf1 == NULL)
1597                         return;
1598
1599                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1600                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1601                 iop_data = (u_int32_t *)pwbuffer->data;
1602                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1603                         && (allxfer_len < 124)) {
1604                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1605                         *buf1 = *pQbuffer;
1606                         acb->wqbuf_firstindex++;
1607                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1608                         buf1++;
1609                         allxfer_len++;
1610                 }
1611                 pwbuffer->data_len = allxfer_len;
1612                 data_len = allxfer_len;
1613                 buf1 = (u_int8_t *)buf2;
1614                 while(data_len >= 4)
1615                 {
1616                         *iop_data++ = *buf2++;
1617                         data_len -= 4;
1618                 }
1619                 if(data_len)
1620                         *iop_data = *buf2;
1621                 free( buf1, M_DEVBUF);
1622                 arcmsr_iop_message_wrote(acb);
1623         }
1624 }
1625 /*
1626 **********************************************************************
1627 **********************************************************************
1628 */
1629 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1630 {
1631         u_int8_t *pQbuffer;
1632         struct QBUFFER *pwbuffer;
1633         u_int8_t *iop_data;
1634         int32_t allxfer_len=0;
1635
1636         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1637                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1638                 return;
1639         }
1640         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1641                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1642                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1643                 iop_data = (u_int8_t *)pwbuffer->data;
1644                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1645                         && (allxfer_len < 124)) {
1646                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1647                         *iop_data = *pQbuffer;
1648                         acb->wqbuf_firstindex++;
1649                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1650                         iop_data++;
1651                         allxfer_len++;
1652                 }
1653                 pwbuffer->data_len = allxfer_len;
1654                 arcmsr_iop_message_wrote(acb);
1655         }
1656 }
1657 /*
1658 **************************************************************************
1659 **************************************************************************
1660 */
1661 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1662 {
1663         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1664         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1665         /*
1666         *****************************************************************
1667         **   check if there are any mail packages from user space program
1668         **   in my post bag, now is the time to send them into Areca's firmware
1669         *****************************************************************
1670         */
1671         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1672                 arcmsr_Write_data_2iop_wqbuffer(acb);
1673         }
1674         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1675                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1676         }
1677         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1678 }
1679 /*
1680 **************************************************************************
1681 **************************************************************************
1682 */
1683 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1684 {
1685 /*
1686         if (ccb->ccb_h.status != CAM_REQ_CMP)
1687                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1688                         "failure status=%x\n", ccb->ccb_h.target_id,
1689                         ccb->ccb_h.target_lun, ccb->ccb_h.status);
1690         else
1691                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1692 */
1693         xpt_free_path(ccb->ccb_h.path);
1694         xpt_free_ccb(ccb);
1695 }
1696
1697 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1698 {
1699         struct cam_path     *path;
1700         union ccb           *ccb;
1701
1702         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1703                 return;
1704         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1705         {
1706                 xpt_free_ccb(ccb);
1707                 return;
1708         }
1709 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1710         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1711         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1712         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1713         ccb->crcn.flags = CAM_FLAG_NONE;
1714         xpt_action(ccb);
1715 }
1716
1717 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1718 {
1719         struct CommandControlBlock *srb;
1720         u_int32_t intmask_org;
1721         int i;
1722
1723         /* disable all outbound interrupts */
1724         intmask_org = arcmsr_disable_allintr(acb);
1725         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1726         {
1727                 srb = acb->psrb_pool[i];
1728                 if (srb->srb_state == ARCMSR_SRB_START)
1729                 {
1730                         if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1731                         {
1732                                 srb->srb_state = ARCMSR_SRB_ABORTED;
1733                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1734                                 arcmsr_srb_complete(srb, 1);
1735                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1736                         }
1737                 }
1738         }
1739         /* enable outbound Post Queue, outbound doorbell Interrupt */
1740         arcmsr_enable_allintr(acb, intmask_org);
1741 }
1742 /*
1743 **************************************************************************
1744 **************************************************************************
1745 */
1746 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1747         u_int32_t       devicemap;
1748         u_int32_t       target, lun;
1749         u_int32_t       deviceMapCurrent[4]={0};
1750         u_int8_t        *pDevMap;
1751
1752         switch (acb->adapter_type) {
1753         case ACB_ADAPTER_TYPE_A:
1754                 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1755                 for (target = 0; target < 4; target++)
1756                 {
1757                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1758                         devicemap += 4;
1759                 }
1760                 break;
1761
1762         case ACB_ADAPTER_TYPE_B:
1763                 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1764                 for (target = 0; target < 4; target++)
1765                 {
1766                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1767                         devicemap += 4;
1768                 }
1769                 break;
1770
1771         case ACB_ADAPTER_TYPE_C:
1772                 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1773                 for (target = 0; target < 4; target++)
1774                 {
1775                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1776                         devicemap += 4;
1777                 }
1778                 break;
1779         case ACB_ADAPTER_TYPE_D:
1780                 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1781                 for (target = 0; target < 4; target++)
1782                 {
1783                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1784                         devicemap += 4;
1785                 }
1786                 break;
1787         case ACB_ADAPTER_TYPE_E:
1788                 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1789                 for (target = 0; target < 4; target++)
1790                 {
1791                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1792                         devicemap += 4;
1793                 }
1794                 break;
1795         case ACB_ADAPTER_TYPE_F:
1796                 devicemap = ARCMSR_FW_DEVMAP_OFFSET;
1797                 for (target = 0; target < 4; target++)
1798                 {
1799                         deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
1800                         devicemap += 1;
1801                 }
1802                 break;
1803         }
1804
1805         if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1806         {
1807                 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1808         }
1809         /*
1810         ** adapter posted CONFIG message
1811         ** copy the new map, note if there are differences with the current map
1812         */
1813         pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1814         for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1815         {
1816                 if (*pDevMap != acb->device_map[target])
1817                 {
1818                         u_int8_t difference, bit_check;
1819
1820                         difference = *pDevMap ^ acb->device_map[target];
1821                         for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1822                         {
1823                                 bit_check = (1 << lun);         /*check bit from 0....31*/
1824                                 if(difference & bit_check)
1825                                 {
1826                                         if(acb->device_map[target] & bit_check)
1827                                         {/* unit departed */
1828                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1829                                                 arcmsr_abort_dr_ccbs(acb, target, lun);
1830                                                 arcmsr_rescan_lun(acb, target, lun);
1831                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1832                                         }
1833                                         else
1834                                         {/* unit arrived */
1835                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1836                                                 arcmsr_rescan_lun(acb, target, lun);
1837                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1838                                         }
1839                                 }
1840                         }
1841 /*                      printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1842                         acb->device_map[target] = *pDevMap;
1843                 }
1844                 pDevMap++;
1845         }
1846 }
1847 /*
1848 **************************************************************************
1849 **************************************************************************
1850 */
1851 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1852         u_int32_t outbound_message;
1853
1854         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1855         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1856         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1857                 arcmsr_dr_handle( acb );
1858 }
1859 /*
1860 **************************************************************************
1861 **************************************************************************
1862 */
1863 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1864         u_int32_t outbound_message;
1865         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1866
1867         /* clear interrupts */
1868         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1869         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1870         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1871                 arcmsr_dr_handle( acb );
1872 }
1873 /*
1874 **************************************************************************
1875 **************************************************************************
1876 */
1877 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1878         u_int32_t outbound_message;
1879
1880         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1881         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1882         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1883                 arcmsr_dr_handle( acb );
1884 }
1885 /*
1886 **************************************************************************
1887 **************************************************************************
1888 */
1889 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1890         u_int32_t outbound_message;
1891
1892         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1893         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1894         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1895                 arcmsr_dr_handle( acb );
1896 }
1897 /*
1898 **************************************************************************
1899 **************************************************************************
1900 */
1901 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1902         u_int32_t outbound_message;
1903
1904         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1905         outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1906         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1907                 arcmsr_dr_handle( acb );
1908 }
1909 /*
1910 **************************************************************************
1911 **************************************************************************
1912 */
1913 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1914 {
1915         u_int32_t doorbell_status;
1916
1917         /*
1918         *******************************************************************
1919         **  Maybe here we need to check wrqbuffer_lock is lock or not
1920         **  DOORBELL: din! don!
1921         **  check if there are any mail need to pack from firmware
1922         *******************************************************************
1923         */
1924         doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1925         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1926         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1927                 arcmsr_iop2drv_data_wrote_handle(acb);
1928         }
1929         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1930                 arcmsr_iop2drv_data_read_handle(acb);
1931         }
1932 }
1933 /*
1934 **************************************************************************
1935 **************************************************************************
1936 */
1937 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1938 {
1939         u_int32_t doorbell_status;
1940
1941         /*
1942         *******************************************************************
1943         **  Maybe here we need to check wrqbuffer_lock is lock or not
1944         **  DOORBELL: din! don!
1945         **  check if there are any mail need to pack from firmware
1946         *******************************************************************
1947         */
1948         doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1949         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1950         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1951                 arcmsr_iop2drv_data_wrote_handle(acb);
1952         }
1953         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1954                 arcmsr_iop2drv_data_read_handle(acb);
1955         }
1956         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1957                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1958         }
1959 }
1960 /*
1961 **************************************************************************
1962 **************************************************************************
1963 */
1964 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1965 {
1966         u_int32_t doorbell_status;
1967
1968         /*
1969         *******************************************************************
1970         **  Maybe here we need to check wrqbuffer_lock is lock or not
1971         **  DOORBELL: din! don!
1972         **  check if there are any mail need to pack from firmware
1973         *******************************************************************
1974         */
1975         doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1976         if(doorbell_status)
1977                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1978         while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1979                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1980                         arcmsr_iop2drv_data_wrote_handle(acb);
1981                 }
1982                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1983                         arcmsr_iop2drv_data_read_handle(acb);
1984                 }
1985                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1986                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1987                 }
1988                 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1989                 if(doorbell_status)
1990                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1991         }
1992 }
1993 /*
1994 **************************************************************************
1995 **************************************************************************
1996 */
1997 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
1998 {
1999         u_int32_t doorbell_status, in_doorbell;
2000
2001         /*
2002         *******************************************************************
2003         **  Maybe here we need to check wrqbuffer_lock is lock or not
2004         **  DOORBELL: din! don!
2005         **  check if there are any mail need to pack from firmware
2006         *******************************************************************
2007         */
2008         in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
2009         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
2010         doorbell_status = in_doorbell ^ acb->in_doorbell;
2011         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2012                 arcmsr_iop2drv_data_wrote_handle(acb);
2013         }
2014         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2015                 arcmsr_iop2drv_data_read_handle(acb);
2016         }
2017         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2018                 arcmsr_hbe_message_isr(acb);    /* messenger of "driver to iop commands" */
2019         }
2020         acb->in_doorbell = in_doorbell;
2021 }
2022 /*
2023 **************************************************************************
2024 **************************************************************************
2025 */
2026 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
2027 {
2028         u_int32_t flag_srb;
2029         u_int16_t error;
2030
2031         /*
2032         *****************************************************************************
2033         **               areca cdb command done
2034         *****************************************************************************
2035         */
2036         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2037                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2038         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2039                 0, outbound_queueport)) != 0xFFFFFFFF) {
2040                 /* check if command done with no error*/
2041                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2042                 arcmsr_drain_donequeue(acb, flag_srb, error);
2043         }       /*drain reply FIFO*/
2044 }
2045 /*
2046 **************************************************************************
2047 **************************************************************************
2048 */
2049 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2050 {
2051         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2052         u_int32_t flag_srb;
2053         int index;
2054         u_int16_t error;
2055
2056         /*
2057         *****************************************************************************
2058         **               areca cdb command done
2059         *****************************************************************************
2060         */
2061         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2062                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2063         index = phbbmu->doneq_index;
2064         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2065                 phbbmu->done_qbuffer[index] = 0;
2066                 index++;
2067                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
2068                 phbbmu->doneq_index = index;
2069                 /* check if command done with no error*/
2070                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2071                 arcmsr_drain_donequeue(acb, flag_srb, error);
2072         }       /*drain reply FIFO*/
2073 }
2074 /*
2075 **************************************************************************
2076 **************************************************************************
2077 */
2078 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2079 {
2080         u_int32_t flag_srb,throttling = 0;
2081         u_int16_t error;
2082
2083         /*
2084         *****************************************************************************
2085         **               areca cdb command done
2086         *****************************************************************************
2087         */
2088         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2089         do {
2090                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2091                 if (flag_srb == 0xFFFFFFFF)
2092                         break;
2093                 /* check if command done with no error*/
2094                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2095                 arcmsr_drain_donequeue(acb, flag_srb, error);
2096                 throttling++;
2097                 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2098                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2099                         throttling = 0;
2100                 }
2101         } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2102 }
2103 /*
2104 **********************************************************************
2105 **
2106 **********************************************************************
2107 */
2108 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2109 {
2110         uint16_t doneq_index, index_stripped;
2111
2112         doneq_index = phbdmu->doneq_index;
2113         if (doneq_index & 0x4000) {
2114                 index_stripped = doneq_index & 0xFF;
2115                 index_stripped += 1;
2116                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2117                 phbdmu->doneq_index = index_stripped ?
2118                     (index_stripped | 0x4000) : index_stripped;
2119         } else {
2120                 index_stripped = doneq_index;
2121                 index_stripped += 1;
2122                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2123                 phbdmu->doneq_index = index_stripped ?
2124                     index_stripped : (index_stripped | 0x4000);
2125         }
2126         return (phbdmu->doneq_index);
2127 }
2128 /*
2129 **************************************************************************
2130 **************************************************************************
2131 */
2132 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2133 {
2134         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2135         u_int32_t outbound_write_pointer;
2136         u_int32_t addressLow;
2137         uint16_t doneq_index;
2138         u_int16_t error;
2139         /*
2140         *****************************************************************************
2141         **               areca cdb command done
2142         *****************************************************************************
2143         */
2144         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2145                 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2146                 return;
2147         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2148                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2149         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2150         doneq_index = phbdmu->doneq_index;
2151         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2152                 doneq_index = arcmsr_get_doneq_index(phbdmu);
2153                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2154                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2155                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2156                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2157                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2158         }
2159         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2160         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2161 }
2162 /*
2163 **************************************************************************
2164 **************************************************************************
2165 */
2166 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2167 {
2168         u_int16_t error;
2169         uint32_t doneq_index;
2170         uint16_t cmdSMID;
2171
2172         /*
2173         *****************************************************************************
2174         **               areca cdb command done
2175         *****************************************************************************
2176         */
2177         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2178         doneq_index = acb->doneq_index;
2179         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2180                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2181                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2182                 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2183                 doneq_index++;
2184                 if (doneq_index >= acb->completionQ_entry)
2185                         doneq_index = 0;
2186         }
2187         acb->doneq_index = doneq_index;
2188         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2189 }
2190
2191 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
2192 {
2193         uint16_t error;
2194         uint32_t doneq_index;
2195         uint16_t cmdSMID;
2196
2197         /*
2198         *****************************************************************************
2199         **               areca cdb command done
2200         *****************************************************************************
2201         */
2202         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2203         doneq_index = acb->doneq_index;
2204         while (1) {
2205                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2206                 if (cmdSMID == 0xffff)
2207                         break;
2208                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2209                 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2210                 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
2211                 doneq_index++;
2212                 if (doneq_index >= acb->completionQ_entry)
2213                         doneq_index = 0;
2214         }
2215         acb->doneq_index = doneq_index;
2216         CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2217 }
2218
2219 /*
2220 **********************************************************************
2221 **********************************************************************
2222 */
2223 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2224 {
2225         u_int32_t outbound_intStatus;
2226         /*
2227         *********************************************
2228         **   check outbound intstatus
2229         *********************************************
2230         */
2231         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2232         if(!outbound_intStatus) {
2233                 /*it must be share irq*/
2234                 return;
2235         }
2236         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2237         /* MU doorbell interrupts*/
2238         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2239                 arcmsr_hba_doorbell_isr(acb);
2240         }
2241         /* MU post queue interrupts*/
2242         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2243                 arcmsr_hba_postqueue_isr(acb);
2244         }
2245         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2246                 arcmsr_hba_message_isr(acb);
2247         }
2248 }
2249 /*
2250 **********************************************************************
2251 **********************************************************************
2252 */
2253 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2254 {
2255         u_int32_t outbound_doorbell;
2256         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2257         /*
2258         *********************************************
2259         **   check outbound intstatus
2260         *********************************************
2261         */
2262         outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2263         if(!outbound_doorbell) {
2264                 /*it must be share irq*/
2265                 return;
2266         }
2267         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2268         READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2269         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2270         /* MU ioctl transfer doorbell interrupts*/
2271         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2272                 arcmsr_iop2drv_data_wrote_handle(acb);
2273         }
2274         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2275                 arcmsr_iop2drv_data_read_handle(acb);
2276         }
2277         /* MU post queue interrupts*/
2278         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2279                 arcmsr_hbb_postqueue_isr(acb);
2280         }
2281         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2282                 arcmsr_hbb_message_isr(acb);
2283         }
2284 }
2285 /*
2286 **********************************************************************
2287 **********************************************************************
2288 */
2289 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2290 {
2291         u_int32_t host_interrupt_status;
2292         /*
2293         *********************************************
2294         **   check outbound intstatus
2295         *********************************************
2296         */
2297         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2298                 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2299                 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2300         if(!host_interrupt_status) {
2301                 /*it must be share irq*/
2302                 return;
2303         }
2304         do {
2305                 /* MU doorbell interrupts*/
2306                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2307                         arcmsr_hbc_doorbell_isr(acb);
2308                 }
2309                 /* MU post queue interrupts*/
2310                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2311                         arcmsr_hbc_postqueue_isr(acb);
2312                 }
2313                 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2314         } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2315 }
2316 /*
2317 **********************************************************************
2318 **********************************************************************
2319 */
2320 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2321 {
2322         u_int32_t host_interrupt_status;
2323         u_int32_t intmask_org;
2324         /*
2325         *********************************************
2326         **   check outbound intstatus
2327         *********************************************
2328         */
2329         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2330         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2331                 /*it must be share irq*/
2332                 return;
2333         }
2334         /* disable outbound interrupt */
2335         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2336         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2337         /* MU doorbell interrupts*/
2338         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2339                 arcmsr_hbd_doorbell_isr(acb);
2340         }
2341         /* MU post queue interrupts*/
2342         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2343                 arcmsr_hbd_postqueue_isr(acb);
2344         }
2345         /* enable all outbound interrupt */
2346         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2347 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2348 }
2349 /*
2350 **********************************************************************
2351 **********************************************************************
2352 */
2353 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2354 {
2355         u_int32_t host_interrupt_status;
2356         /*
2357         *********************************************
2358         **   check outbound intstatus
2359         *********************************************
2360         */
2361         host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2362                 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2363                 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2364         if(!host_interrupt_status) {
2365                 /*it must be share irq*/
2366                 return;
2367         }
2368         do {
2369                 /* MU doorbell interrupts*/
2370                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2371                         arcmsr_hbe_doorbell_isr(acb);
2372                 }
2373                 /* MU post queue interrupts*/
2374                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2375                         arcmsr_hbe_postqueue_isr(acb);
2376                 }
2377                 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2378         } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2379 }
2380
2381 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
2382 {
2383         u_int32_t host_interrupt_status;
2384         /*
2385         *********************************************
2386         **   check outbound intstatus
2387         *********************************************
2388         */
2389         host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
2390                 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2391                 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2392         if(!host_interrupt_status) {
2393                 /*it must be share irq*/
2394                 return;
2395         }
2396         do {
2397                 /* MU doorbell interrupts*/
2398                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2399                         arcmsr_hbe_doorbell_isr(acb);
2400                 }
2401                 /* MU post queue interrupts*/
2402                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2403                         arcmsr_hbf_postqueue_isr(acb);
2404                 }
2405                 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
2406         } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2407 }
2408 /*
2409 ******************************************************************************
2410 ******************************************************************************
2411 */
2412 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2413 {
2414         switch (acb->adapter_type) {
2415         case ACB_ADAPTER_TYPE_A:
2416                 arcmsr_handle_hba_isr(acb);
2417                 break;
2418         case ACB_ADAPTER_TYPE_B:
2419                 arcmsr_handle_hbb_isr(acb);
2420                 break;
2421         case ACB_ADAPTER_TYPE_C:
2422                 arcmsr_handle_hbc_isr(acb);
2423                 break;
2424         case ACB_ADAPTER_TYPE_D:
2425                 arcmsr_handle_hbd_isr(acb);
2426                 break;
2427         case ACB_ADAPTER_TYPE_E:
2428                 arcmsr_handle_hbe_isr(acb);
2429                 break;
2430         case ACB_ADAPTER_TYPE_F:
2431                 arcmsr_handle_hbf_isr(acb);
2432                 break;
2433         default:
2434                 printf("arcmsr%d: interrupt service,"
2435                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2436                 break;
2437         }
2438 }
2439 /*
2440 **********************************************************************
2441 **********************************************************************
2442 */
2443 static void arcmsr_intr_handler(void *arg)
2444 {
2445         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2446
2447         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2448         arcmsr_interrupt(acb);
2449         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2450 }
2451 /*
2452 ******************************************************************************
2453 ******************************************************************************
2454 */
2455 static void     arcmsr_polling_devmap(void *arg)
2456 {
2457         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2458         switch (acb->adapter_type) {
2459         case ACB_ADAPTER_TYPE_A:
2460                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2461                 break;
2462
2463         case ACB_ADAPTER_TYPE_B: {
2464                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2465                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2466                 }
2467                 break;
2468
2469         case ACB_ADAPTER_TYPE_C:
2470                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2471                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2472                 break;
2473
2474         case ACB_ADAPTER_TYPE_D:
2475                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2476                 break;
2477
2478         case ACB_ADAPTER_TYPE_E:
2479                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2480                 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2481                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2482                 break;
2483
2484         case ACB_ADAPTER_TYPE_F: {
2485                 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
2486                 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
2487                         (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
2488                         goto nxt6s;
2489                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2490                 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2491                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2492                 break;
2493                 }
2494         }
2495 nxt6s:
2496         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2497         {
2498                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2499         }
2500 }
2501
2502 /*
2503 *******************************************************************************
2504 **
2505 *******************************************************************************
2506 */
2507 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2508 {
2509         u_int32_t intmask_org;
2510
2511         if(acb != NULL) {
2512                 /* stop adapter background rebuild */
2513                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2514                         intmask_org = arcmsr_disable_allintr(acb);
2515                         arcmsr_stop_adapter_bgrb(acb);
2516                         arcmsr_flush_adapter_cache(acb);
2517                         arcmsr_enable_allintr(acb, intmask_org);
2518                 }
2519         }
2520 }
2521 /*
2522 ***********************************************************************
2523 **
2524 ************************************************************************
2525 */
2526 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2527 {
2528         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2529         u_int32_t retvalue = EINVAL;
2530
2531         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2532         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2533                 return retvalue;
2534         }
2535         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2536         switch(ioctl_cmd) {
2537         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2538                         u_int8_t *pQbuffer;
2539                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2540                         u_int32_t allxfer_len=0;
2541
2542                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2543                                 && (allxfer_len < 1031)) {
2544                                 /*copy READ QBUFFER to srb*/
2545                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2546                                 *ptmpQbuffer = *pQbuffer;
2547                                 acb->rqbuf_firstindex++;
2548                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2549                                 /*if last index number set it to 0 */
2550                                 ptmpQbuffer++;
2551                                 allxfer_len++;
2552                         }
2553                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2554                                 struct QBUFFER *prbuffer;
2555
2556                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2557                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2558                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2559                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2560                         }
2561                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2562                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2563                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2564                 }
2565                 break;
2566         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2567                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2568                         u_int8_t *pQbuffer;
2569                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2570
2571                         user_len = pcmdmessagefld->cmdmessage.Length;
2572                         /*check if data xfer length of this request will overflow my array qbuffer */
2573                         wqbuf_lastindex = acb->wqbuf_lastindex;
2574                         wqbuf_firstindex = acb->wqbuf_firstindex;
2575                         if(wqbuf_lastindex != wqbuf_firstindex) {
2576                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2577                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2578                         } else {
2579                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2580                                         (ARCMSR_MAX_QBUFFER - 1);
2581                                 if(my_empty_len >= user_len) {
2582                                         while(user_len > 0) {
2583                                                 /*copy srb data to wqbuffer*/
2584                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2585                                                 *pQbuffer = *ptmpuserbuffer;
2586                                                 acb->wqbuf_lastindex++;
2587                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2588                                                 /*if last index number set it to 0 */
2589                                                 ptmpuserbuffer++;
2590                                                 user_len--;
2591                                         }
2592                                         /*post fist Qbuffer*/
2593                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2594                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2595                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2596                                         }
2597                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2598                                 } else {
2599                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2600                                 }
2601                         }
2602                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2603                 }
2604                 break;
2605         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2606                         u_int8_t *pQbuffer = acb->rqbuffer;
2607
2608                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2609                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2610                                 arcmsr_iop_message_read(acb);
2611                                 /*signature, let IOP know data has been readed */
2612                         }
2613                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2614                         acb->rqbuf_firstindex = 0;
2615                         acb->rqbuf_lastindex = 0;
2616                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2617                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2618                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2619                 }
2620                 break;
2621         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2622                 {
2623                         u_int8_t *pQbuffer = acb->wqbuffer;
2624
2625                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2626                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2627                                 arcmsr_iop_message_read(acb);
2628                                 /*signature, let IOP know data has been readed */
2629                         }
2630                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2631                         acb->wqbuf_firstindex = 0;
2632                         acb->wqbuf_lastindex = 0;
2633                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2634                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2635                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2636                 }
2637                 break;
2638         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2639                         u_int8_t *pQbuffer;
2640
2641                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2642                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2643                                 arcmsr_iop_message_read(acb);
2644                                 /*signature, let IOP know data has been readed */
2645                         }
2646                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2647                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2648                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2649                         acb->rqbuf_firstindex = 0;
2650                         acb->rqbuf_lastindex = 0;
2651                         acb->wqbuf_firstindex = 0;
2652                         acb->wqbuf_lastindex = 0;
2653                         pQbuffer = acb->rqbuffer;
2654                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2655                         pQbuffer = acb->wqbuffer;
2656                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2657                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2658                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2659                 }
2660                 break;
2661         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2662                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2663                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2664                 }
2665                 break;
2666         case ARCMSR_MESSAGE_SAY_HELLO: {
2667                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2668                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2669
2670                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2671                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2672                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2673                                 return ENOIOCTL;
2674                         }
2675                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2676                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2677                 }
2678                 break;
2679         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2680                         arcmsr_iop_parking(acb);
2681                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2682                 }
2683                 break;
2684         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2685                         arcmsr_flush_adapter_cache(acb);
2686                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2687                 }
2688                 break;
2689         }
2690         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2691         return (retvalue);
2692 }
2693 /*
2694 **************************************************************************
2695 **************************************************************************
2696 */
2697 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2698 {
2699         struct AdapterControlBlock      *acb;
2700
2701         acb = srb->acb;
2702         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2703         srb->srb_state = ARCMSR_SRB_DONE;
2704         srb->srb_flags = 0;
2705         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2706         acb->workingsrb_doneindex++;
2707         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2708         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2709 }
2710 /*
2711 **************************************************************************
2712 **************************************************************************
2713 */
2714 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2715 {
2716         struct CommandControlBlock *srb = NULL;
2717         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2718
2719         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2720         workingsrb_doneindex = acb->workingsrb_doneindex;
2721         workingsrb_startindex = acb->workingsrb_startindex;
2722         srb = acb->srbworkingQ[workingsrb_startindex];
2723         workingsrb_startindex++;
2724         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2725         if(workingsrb_doneindex != workingsrb_startindex) {
2726                 acb->workingsrb_startindex = workingsrb_startindex;
2727         } else {
2728                 srb = NULL;
2729         }
2730         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2731         return(srb);
2732 }
2733 /*
2734 **************************************************************************
2735 **************************************************************************
2736 */
2737 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2738 {
2739         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2740         int retvalue = 0, transfer_len = 0;
2741         char *buffer;
2742         uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2743         u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2744                                 (u_int32_t ) ptr[6] << 16 |
2745                                 (u_int32_t ) ptr[7] << 8  |
2746                                 (u_int32_t ) ptr[8];
2747                                         /* 4 bytes: Areca io control code */
2748         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2749                 buffer = pccb->csio.data_ptr;
2750                 transfer_len = pccb->csio.dxfer_len;
2751         } else {
2752                 retvalue = ARCMSR_MESSAGE_FAIL;
2753                 goto message_out;
2754         }
2755         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2756                 retvalue = ARCMSR_MESSAGE_FAIL;
2757                 goto message_out;
2758         }
2759         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2760         switch(controlcode) {
2761         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2762                         u_int8_t *pQbuffer;
2763                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2764                         int32_t allxfer_len = 0;
2765
2766                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2767                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2768                                 && (allxfer_len < 1031)) {
2769                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2770                                 *ptmpQbuffer = *pQbuffer;
2771                                 acb->rqbuf_firstindex++;
2772                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2773                                 ptmpQbuffer++;
2774                                 allxfer_len++;
2775                         }
2776                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2777                                 struct QBUFFER  *prbuffer;
2778
2779                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2780                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2781                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2782                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2783                         }
2784                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2785                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2786                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2787                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2788                 }
2789                 break;
2790         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2791                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2792                         u_int8_t *pQbuffer;
2793                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2794
2795                         user_len = pcmdmessagefld->cmdmessage.Length;
2796                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2797                         wqbuf_lastindex = acb->wqbuf_lastindex;
2798                         wqbuf_firstindex = acb->wqbuf_firstindex;
2799                         if (wqbuf_lastindex != wqbuf_firstindex) {
2800                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2801                                 /* has error report sensedata */
2802                                 if(pccb->csio.sense_len) {
2803                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2804                                 /* Valid,ErrorCode */
2805                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2806                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2807                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2808                                 /* AdditionalSenseLength */
2809                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2810                                 /* AdditionalSenseCode */
2811                                 }
2812                                 retvalue = ARCMSR_MESSAGE_FAIL;
2813                         } else {
2814                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2815                                                 &(ARCMSR_MAX_QBUFFER - 1);
2816                                 if (my_empty_len >= user_len) {
2817                                         while (user_len > 0) {
2818                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2819                                                 *pQbuffer = *ptmpuserbuffer;
2820                                                 acb->wqbuf_lastindex++;
2821                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2822                                                 ptmpuserbuffer++;
2823                                                 user_len--;
2824                                         }
2825                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2826                                                 acb->acb_flags &=
2827                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2828                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2829                                         }
2830                                 } else {
2831                                         /* has error report sensedata */
2832                                         if(pccb->csio.sense_len) {
2833                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2834                                         /* Valid,ErrorCode */
2835                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2836                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2837                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2838                                         /* AdditionalSenseLength */
2839                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2840                                         /* AdditionalSenseCode */
2841                                         }
2842                                         retvalue = ARCMSR_MESSAGE_FAIL;
2843                                 }
2844                         }
2845                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2846                 }
2847                 break;
2848         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2849                         u_int8_t *pQbuffer = acb->rqbuffer;
2850
2851                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2852                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2853                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2854                                 arcmsr_iop_message_read(acb);
2855                         }
2856                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2857                         acb->rqbuf_firstindex = 0;
2858                         acb->rqbuf_lastindex = 0;
2859                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2860                         pcmdmessagefld->cmdmessage.ReturnCode =
2861                             ARCMSR_MESSAGE_RETURNCODE_OK;
2862                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2863                 }
2864                 break;
2865         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2866                         u_int8_t *pQbuffer = acb->wqbuffer;
2867
2868                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2869                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2870                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2871                                 arcmsr_iop_message_read(acb);
2872                         }
2873                         acb->acb_flags |=
2874                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2875                                         ACB_F_MESSAGE_WQBUFFER_READ);
2876                         acb->wqbuf_firstindex = 0;
2877                         acb->wqbuf_lastindex = 0;
2878                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2879                         pcmdmessagefld->cmdmessage.ReturnCode =
2880                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2881                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2882                 }
2883                 break;
2884         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2885                         u_int8_t *pQbuffer;
2886
2887                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2888                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2889                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2890                                 arcmsr_iop_message_read(acb);
2891                         }
2892                         acb->acb_flags |=
2893                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2894                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2895                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2896                         acb->rqbuf_firstindex = 0;
2897                         acb->rqbuf_lastindex = 0;
2898                         acb->wqbuf_firstindex = 0;
2899                         acb->wqbuf_lastindex = 0;
2900                         pQbuffer = acb->rqbuffer;
2901                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2902                         pQbuffer = acb->wqbuffer;
2903                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2904                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2905                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2906                 }
2907                 break;
2908         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2909                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2910                 }
2911                 break;
2912         case ARCMSR_MESSAGE_SAY_HELLO: {
2913                         int8_t *hello_string = "Hello! I am ARCMSR";
2914
2915                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2916                                 , (int16_t)strlen(hello_string));
2917                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2918                 }
2919                 break;
2920         case ARCMSR_MESSAGE_SAY_GOODBYE:
2921                 arcmsr_iop_parking(acb);
2922                 break;
2923         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2924                 arcmsr_flush_adapter_cache(acb);
2925                 break;
2926         default:
2927                 retvalue = ARCMSR_MESSAGE_FAIL;
2928         }
2929 message_out:
2930         return (retvalue);
2931 }
2932 /*
2933 *********************************************************************
2934 *********************************************************************
2935 */
2936 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2937 {
2938         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2939         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2940         union ccb *pccb;
2941         int target, lun;
2942
2943         pccb = srb->pccb;
2944         target = pccb->ccb_h.target_id;
2945         lun = pccb->ccb_h.target_lun;
2946         acb->pktRequestCount++;
2947         if(error != 0) {
2948                 if(error != EFBIG) {
2949                         printf("arcmsr%d: unexpected error %x"
2950                                 " returned from 'bus_dmamap_load' \n"
2951                                 , acb->pci_unit, error);
2952                 }
2953                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2954                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2955                 }
2956                 arcmsr_srb_complete(srb, 0);
2957                 return;
2958         }
2959         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2960                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2961                 arcmsr_srb_complete(srb, 0);
2962                 return;
2963         }
2964         if(acb->acb_flags & ACB_F_BUS_RESET) {
2965                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2966                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2967                 arcmsr_srb_complete(srb, 0);
2968                 return;
2969         }
2970         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2971                 u_int8_t block_cmd, cmd;
2972
2973                 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
2974                 block_cmd = cmd & 0x0f;
2975                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2976                         printf("arcmsr%d:block 'read/write' command "
2977                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2978                                 , acb->pci_unit, cmd, target, lun);
2979                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2980                         arcmsr_srb_complete(srb, 0);
2981                         return;
2982                 }
2983         }
2984         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2985                 if(nseg != 0) {
2986                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2987                 }
2988                 arcmsr_srb_complete(srb, 0);
2989                 return;
2990         }
2991         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2992                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2993                 {
2994                         xpt_freeze_simq(acb->psim, 1);
2995                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2996                 }
2997                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2998                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2999                 arcmsr_srb_complete(srb, 0);
3000                 return;
3001         }
3002         pccb->ccb_h.status |= CAM_SIM_QUEUED;
3003         arcmsr_build_srb(srb, dm_segs, nseg);
3004         arcmsr_post_srb(acb, srb);
3005         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
3006         {
3007                 arcmsr_callout_init(&srb->ccb_callout);
3008                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
3009                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
3010                     arcmsr_srb_timeout, srb, 0);
3011                 srb->srb_flags |= SRB_FLAG_TIMER_START;
3012         }
3013 }
3014 /*
3015 *****************************************************************************************
3016 *****************************************************************************************
3017 */
3018 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
3019 {
3020         struct CommandControlBlock *srb;
3021         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
3022         u_int32_t intmask_org;
3023         int i = 0;
3024
3025         acb->num_aborts++;
3026         /*
3027         ***************************************************************************
3028         ** It is the upper layer do abort command this lock just prior to calling us.
3029         ** First determine if we currently own this command.
3030         ** Start by searching the device queue. If not found
3031         ** at all, and the system wanted us to just abort the
3032         ** command return success.
3033         ***************************************************************************
3034         */
3035         if(acb->srboutstandingcount != 0) {
3036                 /* disable all outbound interrupt */
3037                 intmask_org = arcmsr_disable_allintr(acb);
3038                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3039                         srb = acb->psrb_pool[i];
3040                         if(srb->srb_state == ARCMSR_SRB_START) {
3041                                 if(srb->pccb == abortccb) {
3042                                         srb->srb_state = ARCMSR_SRB_ABORTED;
3043                                         printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
3044                                                 "outstanding command \n"
3045                                                 , acb->pci_unit, abortccb->ccb_h.target_id
3046                                                 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
3047                                         arcmsr_polling_srbdone(acb, srb);
3048                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
3049                                         arcmsr_enable_allintr(acb, intmask_org);
3050                                         return (TRUE);
3051                                 }
3052                         }
3053                 }
3054                 /* enable outbound Post Queue, outbound doorbell Interrupt */
3055                 arcmsr_enable_allintr(acb, intmask_org);
3056         }
3057         return(FALSE);
3058 }
3059 /*
3060 ****************************************************************************
3061 ****************************************************************************
3062 */
3063 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
3064 {
3065         int retry = 0;
3066
3067         acb->num_resets++;
3068         acb->acb_flags |= ACB_F_BUS_RESET;
3069         while(acb->srboutstandingcount != 0 && retry < 400) {
3070                 arcmsr_interrupt(acb);
3071                 UDELAY(25000);
3072                 retry++;
3073         }
3074         arcmsr_iop_reset(acb);
3075         acb->acb_flags &= ~ACB_F_BUS_RESET;
3076 }
3077 /*
3078 **************************************************************************
3079 **************************************************************************
3080 */
3081 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3082                 union ccb *pccb)
3083 {
3084         if (pccb->ccb_h.target_lun) {
3085                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
3086                 xpt_done(pccb);
3087                 return;
3088         }
3089         pccb->ccb_h.status |= CAM_REQ_CMP;
3090         switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
3091         case INQUIRY: {
3092                 unsigned char inqdata[36];
3093                 char *buffer = pccb->csio.data_ptr;
3094
3095                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
3096                 inqdata[1] = 0;                 /* rem media bit & Dev Type Modifier */
3097                 inqdata[2] = 0;                 /* ISO, ECMA, & ANSI versions */
3098                 inqdata[3] = 0;
3099                 inqdata[4] = 31;                /* length of additional data */
3100                 inqdata[5] = 0;
3101                 inqdata[6] = 0;
3102                 inqdata[7] = 0;
3103                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
3104                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
3105                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3106                 memcpy(buffer, inqdata, sizeof(inqdata));
3107                 xpt_done(pccb);
3108         }
3109         break;
3110         case WRITE_BUFFER:
3111         case READ_BUFFER: {
3112                 if (arcmsr_iop_message_xfer(acb, pccb)) {
3113                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3114                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3115                 }
3116                 xpt_done(pccb);
3117         }
3118         break;
3119         default:
3120                 xpt_done(pccb);
3121         }
3122 }
3123 /*
3124 *********************************************************************
3125 *********************************************************************
3126 */
3127 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3128 {
3129         struct AdapterControlBlock *acb;
3130
3131         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3132         if(acb == NULL) {
3133                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3134                 xpt_done(pccb);
3135                 return;
3136         }
3137         switch (pccb->ccb_h.func_code) {
3138         case XPT_SCSI_IO: {
3139                         struct CommandControlBlock *srb;
3140                         int target = pccb->ccb_h.target_id;
3141                         int error;
3142
3143                         if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3144                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3145                                 xpt_done(pccb);
3146                                 return;
3147                         }
3148
3149                         if(target == 16) {
3150                                 /* virtual device for iop message transfer */
3151                                 arcmsr_handle_virtual_command(acb, pccb);
3152                                 return;
3153                         }
3154                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3155                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3156                                 xpt_done(pccb);
3157                                 return;
3158                         }
3159                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3160                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3161                         srb->pccb = pccb;
3162                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3163                                 , srb->dm_segs_dmamap
3164                                 , pccb
3165                                 , arcmsr_execute_srb, srb, /*flags*/0);
3166                         if(error == EINPROGRESS) {
3167                                 xpt_freeze_simq(acb->psim, 1);
3168                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3169                         }
3170                         break;
3171                 }
3172         case XPT_PATH_INQ: {
3173                         struct ccb_pathinq *cpi = &pccb->cpi;
3174
3175                         cpi->version_num = 1;
3176                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3177                         cpi->target_sprt = 0;
3178                         cpi->hba_misc = 0;
3179                         cpi->hba_eng_cnt = 0;
3180                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
3181                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
3182                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3183                         cpi->bus_id = cam_sim_bus(psim);
3184                         strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3185                         strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3186                         strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3187                         cpi->unit_number = cam_sim_unit(psim);
3188                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3189                                 cpi->base_transfer_speed = 1200000;
3190                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3191                                 cpi->base_transfer_speed = 600000;
3192                         else
3193                                 cpi->base_transfer_speed = 300000;
3194                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3195                            (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3196                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3197                            (acb->vendor_device_id == PCIDevVenIDARC1214))
3198                         {
3199                                 cpi->transport = XPORT_SAS;
3200                                 cpi->transport_version = 0;
3201                                 cpi->protocol_version = SCSI_REV_SPC2;
3202                         }
3203                         else
3204                         {
3205                                 cpi->transport = XPORT_SPI;
3206                                 cpi->transport_version = 2;
3207                                 cpi->protocol_version = SCSI_REV_2;
3208                         }
3209                         cpi->protocol = PROTO_SCSI;
3210                         cpi->ccb_h.status |= CAM_REQ_CMP;
3211                         xpt_done(pccb);
3212                         break;
3213                 }
3214         case XPT_ABORT: {
3215                         union ccb *pabort_ccb;
3216
3217                         pabort_ccb = pccb->cab.abort_ccb;
3218                         switch (pabort_ccb->ccb_h.func_code) {
3219                         case XPT_ACCEPT_TARGET_IO:
3220                         case XPT_CONT_TARGET_IO:
3221                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3222                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3223                                         xpt_done(pabort_ccb);
3224                                         pccb->ccb_h.status |= CAM_REQ_CMP;
3225                                 } else {
3226                                         xpt_print_path(pabort_ccb->ccb_h.path);
3227                                         printf("Not found\n");
3228                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
3229                                 }
3230                                 break;
3231                         case XPT_SCSI_IO:
3232                                 pccb->ccb_h.status |= CAM_UA_ABORT;
3233                                 break;
3234                         default:
3235                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3236                                 break;
3237                         }
3238                         xpt_done(pccb);
3239                         break;
3240                 }
3241         case XPT_RESET_BUS:
3242         case XPT_RESET_DEV: {
3243                         u_int32_t       i;
3244
3245                         arcmsr_bus_reset(acb);
3246                         for (i=0; i < 500; i++) {
3247                                 DELAY(1000);
3248                         }
3249                         pccb->ccb_h.status |= CAM_REQ_CMP;
3250                         xpt_done(pccb);
3251                         break;
3252                 }
3253         case XPT_TERM_IO: {
3254                         pccb->ccb_h.status |= CAM_REQ_INVALID;
3255                         xpt_done(pccb);
3256                         break;
3257                 }
3258         case XPT_GET_TRAN_SETTINGS: {
3259                         struct ccb_trans_settings *cts;
3260
3261                         if(pccb->ccb_h.target_id == 16) {
3262                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3263                                 xpt_done(pccb);
3264                                 break;
3265                         }
3266                         cts = &pccb->cts;
3267                         {
3268                                 struct ccb_trans_settings_scsi *scsi;
3269                                 struct ccb_trans_settings_spi *spi;
3270                                 struct ccb_trans_settings_sas *sas;
3271
3272                                 scsi = &cts->proto_specific.scsi;
3273                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3274                                 scsi->valid = CTS_SCSI_VALID_TQ;
3275                                 cts->protocol = PROTO_SCSI;
3276
3277                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3278                                    (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3279                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3280                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
3281                                 {
3282                                         cts->protocol_version = SCSI_REV_SPC2;
3283                                         cts->transport_version = 0;
3284                                         cts->transport = XPORT_SAS;
3285                                         sas = &cts->xport_specific.sas;
3286                                         sas->valid = CTS_SAS_VALID_SPEED;
3287                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3288                                                 sas->bitrate = 1200000;
3289                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3290                                                 sas->bitrate = 600000;
3291                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3292                                                 sas->bitrate = 300000;
3293                                 }
3294                                 else
3295                                 {
3296                                         cts->protocol_version = SCSI_REV_2;
3297                                         cts->transport_version = 2;
3298                                         cts->transport = XPORT_SPI;
3299                                         spi = &cts->xport_specific.spi;
3300                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3301                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3302                                                 spi->sync_period = 1;
3303                                         else
3304                                                 spi->sync_period = 2;
3305                                         spi->sync_offset = 32;
3306                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3307                                         spi->valid = CTS_SPI_VALID_DISC
3308                                                 | CTS_SPI_VALID_SYNC_RATE
3309                                                 | CTS_SPI_VALID_SYNC_OFFSET
3310                                                 | CTS_SPI_VALID_BUS_WIDTH;
3311                                 }
3312                         }
3313                         pccb->ccb_h.status |= CAM_REQ_CMP;
3314                         xpt_done(pccb);
3315                         break;
3316                 }
3317         case XPT_SET_TRAN_SETTINGS: {
3318                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3319                         xpt_done(pccb);
3320                         break;
3321                 }
3322         case XPT_CALC_GEOMETRY:
3323                         if(pccb->ccb_h.target_id == 16) {
3324                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3325                                 xpt_done(pccb);
3326                                 break;
3327                         }
3328                         cam_calc_geometry(&pccb->ccg, 1);
3329                         xpt_done(pccb);
3330                         break;
3331         default:
3332                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3333                 xpt_done(pccb);
3334                 break;
3335         }
3336 }
3337 /*
3338 **********************************************************************
3339 **********************************************************************
3340 */
3341 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3342 {
3343         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3344         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3345         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3346                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3347         }
3348 }
3349 /*
3350 **********************************************************************
3351 **********************************************************************
3352 */
3353 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3354 {
3355         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3356         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3357         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3358         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3359                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3360         }
3361 }
3362 /*
3363 **********************************************************************
3364 **********************************************************************
3365 */
3366 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3367 {
3368         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3369         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3370         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3371         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3372                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3373         }
3374 }
3375 /*
3376 **********************************************************************
3377 **********************************************************************
3378 */
3379 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3380 {
3381         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3382         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3383         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3384                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3385         }
3386 }
3387 /*
3388 **********************************************************************
3389 **********************************************************************
3390 */
3391 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3392 {
3393         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3394         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3395         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3396         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3397         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3398                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3399         }
3400 }
3401 /*
3402 **********************************************************************
3403 **********************************************************************
3404 */
3405 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3406 {
3407         switch (acb->adapter_type) {
3408         case ACB_ADAPTER_TYPE_A:
3409                 arcmsr_start_hba_bgrb(acb);
3410                 break;
3411         case ACB_ADAPTER_TYPE_B:
3412                 arcmsr_start_hbb_bgrb(acb);
3413                 break;
3414         case ACB_ADAPTER_TYPE_C:
3415                 arcmsr_start_hbc_bgrb(acb);
3416                 break;
3417         case ACB_ADAPTER_TYPE_D:
3418                 arcmsr_start_hbd_bgrb(acb);
3419                 break;
3420         case ACB_ADAPTER_TYPE_E:
3421         case ACB_ADAPTER_TYPE_F:
3422                 arcmsr_start_hbe_bgrb(acb);
3423                 break;
3424         }
3425 }
3426 /*
3427 **********************************************************************
3428 **
3429 **********************************************************************
3430 */
3431 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3432 {
3433         struct CommandControlBlock *srb;
3434         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3435         u_int16_t       error;
3436
3437 polling_ccb_retry:
3438         poll_count++;
3439         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3440         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3441         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3442         while(1) {
3443                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3444                         0, outbound_queueport)) == 0xFFFFFFFF) {
3445                         if(poll_srb_done) {
3446                                 break;/*chip FIFO no ccb for completion already*/
3447                         } else {
3448                                 UDELAY(25000);
3449                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3450                                         break;
3451                                 }
3452                                 goto polling_ccb_retry;
3453                         }
3454                 }
3455                 /* check if command done with no error*/
3456                 srb = (struct CommandControlBlock *)
3457                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3458                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3459                 poll_srb_done = (srb == poll_srb) ? 1:0;
3460                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3461                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3462                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3463                                         "poll command abort successfully \n"
3464                                         , acb->pci_unit
3465                                         , srb->pccb->ccb_h.target_id
3466                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3467                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3468                                 arcmsr_srb_complete(srb, 1);
3469                                 continue;
3470                         }
3471                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3472                                 "srboutstandingcount=%d \n"
3473                                 , acb->pci_unit
3474                                 , srb, acb->srboutstandingcount);
3475                         continue;
3476                 }
3477                 arcmsr_report_srb_state(acb, srb, error);
3478         }       /*drain reply FIFO*/
3479 }
3480 /*
3481 **********************************************************************
3482 **
3483 **********************************************************************
3484 */
3485 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3486 {
3487         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3488         struct CommandControlBlock *srb;
3489         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3490         int index;
3491         u_int16_t       error;
3492
3493 polling_ccb_retry:
3494         poll_count++;
3495         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3496         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3497         while(1) {
3498                 index = phbbmu->doneq_index;
3499                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3500                         if(poll_srb_done) {
3501                                 break;/*chip FIFO no ccb for completion already*/
3502                         } else {
3503                                 UDELAY(25000);
3504                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3505                                         break;
3506                                 }
3507                                 goto polling_ccb_retry;
3508                         }
3509                 }
3510                 phbbmu->done_qbuffer[index] = 0;
3511                 index++;
3512                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3513                 phbbmu->doneq_index = index;
3514                 /* check if command done with no error*/
3515                 srb = (struct CommandControlBlock *)
3516                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3517                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3518                 poll_srb_done = (srb == poll_srb) ? 1:0;
3519                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3520                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3521                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3522                                         "poll command abort successfully \n"
3523                                         , acb->pci_unit
3524                                         , srb->pccb->ccb_h.target_id
3525                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3526                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3527                                 arcmsr_srb_complete(srb, 1);
3528                                 continue;
3529                         }
3530                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3531                                 "srboutstandingcount=%d \n"
3532                                 , acb->pci_unit
3533                                 , srb, acb->srboutstandingcount);
3534                         continue;
3535                 }
3536                 arcmsr_report_srb_state(acb, srb, error);
3537         }       /*drain reply FIFO*/
3538 }
3539 /*
3540 **********************************************************************
3541 **
3542 **********************************************************************
3543 */
3544 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3545 {
3546         struct CommandControlBlock *srb;
3547         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3548         u_int16_t       error;
3549
3550 polling_ccb_retry:
3551         poll_count++;
3552         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3553         while(1) {
3554                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3555                         if(poll_srb_done) {
3556                                 break;/*chip FIFO no ccb for completion already*/
3557                         } else {
3558                                 UDELAY(25000);
3559                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3560                                         break;
3561                                 }
3562                                 if (acb->srboutstandingcount == 0) {
3563                                         break;
3564                                 }
3565                                 goto polling_ccb_retry;
3566                         }
3567                 }
3568                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3569                 /* check if command done with no error*/
3570                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3571                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3572                 if (poll_srb != NULL)
3573                         poll_srb_done = (srb == poll_srb) ? 1:0;
3574                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3575                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3576                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3577                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3578                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3579                                 arcmsr_srb_complete(srb, 1);
3580                                 continue;
3581                         }
3582                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3583                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3584                         continue;
3585                 }
3586                 arcmsr_report_srb_state(acb, srb, error);
3587         }       /*drain reply FIFO*/
3588 }
3589 /*
3590 **********************************************************************
3591 **
3592 **********************************************************************
3593 */
3594 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3595 {
3596         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3597         struct CommandControlBlock *srb;
3598         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3599         u_int32_t outbound_write_pointer;
3600         u_int16_t       error, doneq_index;
3601
3602 polling_ccb_retry:
3603         poll_count++;
3604         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3605         while(1) {
3606                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3607                 doneq_index = phbdmu->doneq_index;
3608                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3609                         if(poll_srb_done) {
3610                                 break;/*chip FIFO no ccb for completion already*/
3611                         } else {
3612                                 UDELAY(25000);
3613                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3614                                         break;
3615                                 }
3616                                 if (acb->srboutstandingcount == 0) {
3617                                         break;
3618                                 }
3619                                 goto polling_ccb_retry;
3620                         }
3621                 }
3622                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3623                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3624                 /* check if command done with no error*/
3625                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3626                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3627                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3628                 if (poll_srb != NULL)
3629                         poll_srb_done = (srb == poll_srb) ? 1:0;
3630                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3631                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3632                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3633                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3634                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3635                                 arcmsr_srb_complete(srb, 1);
3636                                 continue;
3637                         }
3638                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3639                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3640                         continue;
3641                 }
3642                 arcmsr_report_srb_state(acb, srb, error);
3643         }       /*drain reply FIFO*/
3644 }
3645 /*
3646 **********************************************************************
3647 **
3648 **********************************************************************
3649 */
3650 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3651 {
3652         struct CommandControlBlock *srb;
3653         u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3654         u_int16_t       error, cmdSMID;
3655
3656 polling_ccb_retry:
3657         poll_count++;
3658         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3659         while(1) {
3660                 doneq_index = acb->doneq_index;
3661                 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3662                         if(poll_srb_done) {
3663                                 break;/*chip FIFO no ccb for completion already*/
3664                         } else {
3665                                 UDELAY(25000);
3666                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3667                                         break;
3668                                 }
3669                                 if (acb->srboutstandingcount == 0) {
3670                                         break;
3671                                 }
3672                                 goto polling_ccb_retry;
3673                         }
3674                 }
3675                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3676                 doneq_index++;
3677                 if (doneq_index >= acb->completionQ_entry)
3678                         doneq_index = 0;
3679                 acb->doneq_index = doneq_index;
3680                 srb = acb->psrb_pool[cmdSMID];
3681                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3682                 if (poll_srb != NULL)
3683                         poll_srb_done = (srb == poll_srb) ? 1:0;
3684                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3685                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3686                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3687                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3688                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3689                                 arcmsr_srb_complete(srb, 1);
3690                                 continue;
3691                         }
3692                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3693                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3694                         continue;
3695                 }
3696                 arcmsr_report_srb_state(acb, srb, error);
3697         }       /*drain reply FIFO*/
3698         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3699 }
3700 /*
3701 **********************************************************************
3702 **********************************************************************
3703 */
3704 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3705 {
3706         switch (acb->adapter_type) {
3707         case ACB_ADAPTER_TYPE_A:
3708                 arcmsr_polling_hba_srbdone(acb, poll_srb);
3709                 break;
3710         case ACB_ADAPTER_TYPE_B:
3711                 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3712                 break;
3713         case ACB_ADAPTER_TYPE_C:
3714                 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3715                 break;
3716         case ACB_ADAPTER_TYPE_D:
3717                 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3718                 break;
3719         case ACB_ADAPTER_TYPE_E:
3720         case ACB_ADAPTER_TYPE_F:
3721                 arcmsr_polling_hbe_srbdone(acb, poll_srb);
3722                 break;
3723         }
3724 }
3725 /*
3726 **********************************************************************
3727 **********************************************************************
3728 */
3729 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3730 {
3731         char *acb_firm_model = acb->firm_model;
3732         char *acb_firm_version = acb->firm_version;
3733         char *acb_device_map = acb->device_map;
3734         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3735         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3736         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3737         int i;
3738
3739         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3740         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3741                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3742         }
3743         i = 0;
3744         while(i < 8) {
3745                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3746                 /* 8 bytes firm_model, 15, 60-67*/
3747                 acb_firm_model++;
3748                 i++;
3749         }
3750         i=0;
3751         while(i < 16) {
3752                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3753                 /* 16 bytes firm_version, 17, 68-83*/
3754                 acb_firm_version++;
3755                 i++;
3756         }
3757         i=0;
3758         while(i < 16) {
3759                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3760                 acb_device_map++;
3761                 i++;
3762         }
3763         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3764         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3765         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3766         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3767         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3768         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3769         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3770                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3771         else
3772                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3773 }
3774 /*
3775 **********************************************************************
3776 **********************************************************************
3777 */
3778 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3779 {
3780         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3781         char *acb_firm_model = acb->firm_model;
3782         char *acb_firm_version = acb->firm_version;
3783         char *acb_device_map = acb->device_map;
3784         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3785         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3786         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3787         int i;
3788
3789         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3790         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3791                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3792         }
3793         i = 0;
3794         while(i < 8) {
3795                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3796                 /* 8 bytes firm_model, 15, 60-67*/
3797                 acb_firm_model++;
3798                 i++;
3799         }
3800         i = 0;
3801         while(i < 16) {
3802                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3803                 /* 16 bytes firm_version, 17, 68-83*/
3804                 acb_firm_version++;
3805                 i++;
3806         }
3807         i = 0;
3808         while(i < 16) {
3809                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3810                 acb_device_map++;
3811                 i++;
3812         }
3813         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3814         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3815         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3816         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3817         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3818         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3819         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3820                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3821         else
3822                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3823 }
3824 /*
3825 **********************************************************************
3826 **********************************************************************
3827 */
3828 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3829 {
3830         char *acb_firm_model = acb->firm_model;
3831         char *acb_firm_version = acb->firm_version;
3832         char *acb_device_map = acb->device_map;
3833         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3834         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3835         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3836         int i;
3837
3838         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3839         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3840         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3841                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3842         }
3843         i = 0;
3844         while(i < 8) {
3845                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3846                 /* 8 bytes firm_model, 15, 60-67*/
3847                 acb_firm_model++;
3848                 i++;
3849         }
3850         i = 0;
3851         while(i < 16) {
3852                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3853                 /* 16 bytes firm_version, 17, 68-83*/
3854                 acb_firm_version++;
3855                 i++;
3856         }
3857         i = 0;
3858         while(i < 16) {
3859                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3860                 acb_device_map++;
3861                 i++;
3862         }
3863         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3864         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3865         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3866         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3867         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3868         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3869         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3870                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3871         else
3872                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3873 }
3874 /*
3875 **********************************************************************
3876 **********************************************************************
3877 */
3878 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3879 {
3880         char *acb_firm_model = acb->firm_model;
3881         char *acb_firm_version = acb->firm_version;
3882         char *acb_device_map = acb->device_map;
3883         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3884         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3885         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3886         int i;
3887
3888         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3889                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3890         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3891         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3892                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3893         }
3894         i = 0;
3895         while(i < 8) {
3896                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3897                 /* 8 bytes firm_model, 15, 60-67*/
3898                 acb_firm_model++;
3899                 i++;
3900         }
3901         i = 0;
3902         while(i < 16) {
3903                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3904                 /* 16 bytes firm_version, 17, 68-83*/
3905                 acb_firm_version++;
3906                 i++;
3907         }
3908         i = 0;
3909         while(i < 16) {
3910                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3911                 acb_device_map++;
3912                 i++;
3913         }
3914         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3915         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3916         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3917         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3918         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3919         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3920         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3921                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3922         else
3923                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3924 }
3925 /*
3926 **********************************************************************
3927 **********************************************************************
3928 */
3929 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3930 {
3931         char *acb_firm_model = acb->firm_model;
3932         char *acb_firm_version = acb->firm_version;
3933         char *acb_device_map = acb->device_map;
3934         size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3935         size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3936         size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3937         int i;
3938
3939         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3940         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3941         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3942         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3943                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3944         }
3945
3946         i = 0;
3947         while(i < 8) {
3948                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3949                 /* 8 bytes firm_model, 15, 60-67*/
3950                 acb_firm_model++;
3951                 i++;
3952         }
3953         i = 0;
3954         while(i < 16) {
3955                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3956                 /* 16 bytes firm_version, 17, 68-83*/
3957                 acb_firm_version++;
3958                 i++;
3959         }
3960         i = 0;
3961         while(i < 16) {
3962                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3963                 acb_device_map++;
3964                 i++;
3965         }
3966         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3967         acb->firm_request_len   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3968         acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3969         acb->firm_sdram_size    = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3970         acb->firm_ide_channels  = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3971         acb->firm_cfg_version   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3972         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3973                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3974         else
3975                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3976 }
3977 /*
3978 **********************************************************************
3979 **********************************************************************
3980 */
3981 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
3982 {
3983         u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
3984         u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
3985         u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
3986         size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET;   /*firm_model,15,60-67*/
3987         size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
3988         size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
3989         int i;
3990
3991         CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3992         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3993         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3994         if(!arcmsr_hbe_wait_msgint_ready(acb))
3995                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3996
3997         i = 0;
3998         while(i < 2) {
3999                 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
4000                 /* 8 bytes firm_model, 15, 60-67*/
4001                 acb_firm_model++;
4002                 iop_firm_model++;
4003                 i++;
4004         }
4005         i = 0;
4006         while(i < 4) {
4007                 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
4008                 /* 16 bytes firm_version, 17, 68-83*/
4009                 acb_firm_version++;
4010                 iop_firm_version++;
4011                 i++;
4012         }
4013         i = 0;
4014         while(i < 4) {
4015                 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
4016                 acb_device_map++;
4017                 iop_device_map++;
4018                 i++;
4019         }
4020         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
4021         acb->firm_request_len   = acb->msgcode_rwbuffer[1];     /*firm_request_len,   1, 04-07*/
4022         acb->firm_numbers_queue = acb->msgcode_rwbuffer[2];     /*firm_numbers_queue, 2, 08-11*/
4023         acb->firm_sdram_size    = acb->msgcode_rwbuffer[3];     /*firm_sdram_size,    3, 12-15*/
4024         acb->firm_ide_channels  = acb->msgcode_rwbuffer[4];     /*firm_ide_channels,  4, 16-19*/
4025         acb->firm_cfg_version   = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version,  25*/
4026         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
4027                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
4028         else
4029                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
4030 }
4031 /*
4032 **********************************************************************
4033 **********************************************************************
4034 */
4035 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
4036 {
4037         switch (acb->adapter_type) {
4038         case ACB_ADAPTER_TYPE_A:
4039                 arcmsr_get_hba_config(acb);
4040                 break;
4041         case ACB_ADAPTER_TYPE_B:
4042                 arcmsr_get_hbb_config(acb);
4043                 break;
4044         case ACB_ADAPTER_TYPE_C:
4045                 arcmsr_get_hbc_config(acb);
4046                 break;
4047         case ACB_ADAPTER_TYPE_D:
4048                 arcmsr_get_hbd_config(acb);
4049                 break;
4050         case ACB_ADAPTER_TYPE_E:
4051                 arcmsr_get_hbe_config(acb);
4052                 break;
4053         case ACB_ADAPTER_TYPE_F:
4054                 arcmsr_get_hbf_config(acb);
4055                 break;
4056         }
4057 }
4058 /*
4059 **********************************************************************
4060 **********************************************************************
4061 */
4062 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
4063 {
4064         int     timeout=0;
4065
4066         switch (acb->adapter_type) {
4067         case ACB_ADAPTER_TYPE_A: {
4068                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
4069                         {
4070                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4071                                 {
4072                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
4073                                         return;
4074                                 }
4075                                 UDELAY(15000); /* wait 15 milli-seconds */
4076                         }
4077                 }
4078                 break;
4079         case ACB_ADAPTER_TYPE_B: {
4080                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4081                         while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
4082                         {
4083                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4084                                 {
4085                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
4086                                         return;
4087                                 }
4088                                 UDELAY(15000); /* wait 15 milli-seconds */
4089                         }
4090                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
4091                 }
4092                 break;
4093         case ACB_ADAPTER_TYPE_C: {
4094                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
4095                         {
4096                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4097                                 {
4098                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4099                                         return;
4100                                 }
4101                                 UDELAY(15000); /* wait 15 milli-seconds */
4102                         }
4103                 }
4104                 break;
4105         case ACB_ADAPTER_TYPE_D: {
4106                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
4107                         {
4108                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
4109                                 {
4110                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4111                                         return;
4112                                 }
4113                                 UDELAY(15000); /* wait 15 milli-seconds */
4114                         }
4115                 }
4116                 break;
4117         case ACB_ADAPTER_TYPE_E:
4118         case ACB_ADAPTER_TYPE_F: {
4119                         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
4120                         {
4121                                 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
4122                                 {
4123                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
4124                                         return;
4125                                 }
4126                                 UDELAY(15000); /* wait 15 milli-seconds */
4127                         }
4128                 }
4129                 break;
4130         }
4131 }
4132 /*
4133 **********************************************************************
4134 **********************************************************************
4135 */
4136 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
4137 {
4138         u_int32_t outbound_doorbell;
4139
4140         switch (acb->adapter_type) {
4141         case ACB_ADAPTER_TYPE_A: {
4142                         /* empty doorbell Qbuffer if door bell ringed */
4143                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
4144                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
4145                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
4146                 }
4147                 break;
4148         case ACB_ADAPTER_TYPE_B: {
4149                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4150                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
4151                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
4152                         /* let IOP know data has been read */
4153                 }
4154                 break;
4155         case ACB_ADAPTER_TYPE_C: {
4156                         /* empty doorbell Qbuffer if door bell ringed */
4157                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4158                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
4159                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4160                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4161                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4162                 }
4163                 break;
4164         case ACB_ADAPTER_TYPE_D: {
4165                         /* empty doorbell Qbuffer if door bell ringed */
4166                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4167                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
4168                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4169                 }
4170                 break;
4171         case ACB_ADAPTER_TYPE_E:
4172         case ACB_ADAPTER_TYPE_F: {
4173                         /* empty doorbell Qbuffer if door bell ringed */
4174                         acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4175                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);       /*clear doorbell interrupt */
4176                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4177                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4178                 }
4179                 break;
4180         }
4181 }
4182 /*
4183 ************************************************************************
4184 ************************************************************************
4185 */
4186 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4187 {
4188         unsigned long srb_phyaddr;
4189         u_int32_t srb_phyaddr_hi32;
4190         u_int32_t srb_phyaddr_lo32;
4191
4192         /*
4193         ********************************************************************
4194         ** here we need to tell iop 331 our freesrb.HighPart
4195         ** if freesrb.HighPart is not zero
4196         ********************************************************************
4197         */
4198         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4199         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4200         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4201         switch (acb->adapter_type) {
4202         case ACB_ADAPTER_TYPE_A: {
4203                         if(srb_phyaddr_hi32 != 0) {
4204                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4205                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4206                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4207                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4208                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4209                                         return FALSE;
4210                                 }
4211                         }
4212                 }
4213                 break;
4214                 /*
4215                 ***********************************************************************
4216                 **    if adapter type B, set window of "post command Q"
4217                 ***********************************************************************
4218                 */
4219         case ACB_ADAPTER_TYPE_B: {
4220                         u_int32_t post_queue_phyaddr;
4221                         struct HBB_MessageUnit *phbbmu;
4222
4223                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4224                         phbbmu->postq_index = 0;
4225                         phbbmu->doneq_index = 0;
4226                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4227                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4228                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4229                                 return FALSE;
4230                         }
4231                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4232                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4233                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4234                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4235                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4236                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4237                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4238                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4239                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4240                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4241                                 return FALSE;
4242                         }
4243                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4244                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4245                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4246                                 return FALSE;
4247                         }
4248                 }
4249                 break;
4250         case ACB_ADAPTER_TYPE_C: {
4251                         if(srb_phyaddr_hi32 != 0) {
4252                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4253                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4254                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4255                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4256                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4257                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4258                                         return FALSE;
4259                                 }
4260                         }
4261                 }
4262                 break;
4263         case ACB_ADAPTER_TYPE_D: {
4264                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4265                         struct HBD_MessageUnit0 *phbdmu;
4266
4267                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4268                         phbdmu->postq_index = 0;
4269                         phbdmu->doneq_index = 0x40FF;
4270                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4271                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4272                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4273                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4274                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4275                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4276                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4277                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4278                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4279                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4280                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4281                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4282                                 return FALSE;
4283                         }
4284                 }
4285                 break;
4286         case ACB_ADAPTER_TYPE_E: {
4287                         u_int32_t cdb_phyaddr_lo32;
4288                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4289                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4290                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4291                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4292                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4293                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4294                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4295                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4296                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4297                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4298                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4299                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4300                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4301                         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4302                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4303                                 return FALSE;
4304                         }
4305                 }
4306                 break;
4307         case ACB_ADAPTER_TYPE_F: {
4308                         u_int32_t cdb_phyaddr_lo32;
4309                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4310                         acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
4311                         acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
4312                         acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
4313                         acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
4314                         acb->msgcode_rwbuffer[4] = SRB_SIZE;
4315                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4316                         acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
4317                         acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
4318                         acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
4319                         CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4320                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4321                         CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4322                         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4323                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4324                                 return FALSE;
4325                         }
4326                 }
4327                 break;
4328         }
4329         return (TRUE);
4330 }
4331 /*
4332 ************************************************************************
4333 ************************************************************************
4334 */
4335 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4336 {
4337         if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4338         {
4339                 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4340                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4341                 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4342                         printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4343                         return;
4344                 }
4345         }
4346 }
4347 /*
4348 **********************************************************************
4349 **********************************************************************
4350 */
4351 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4352 {
4353         u_int32_t intmask_org;
4354
4355         /* disable all outbound interrupt */
4356         intmask_org = arcmsr_disable_allintr(acb);
4357         arcmsr_wait_firmware_ready(acb);
4358         arcmsr_iop_confirm(acb);
4359         arcmsr_get_firmware_spec(acb);
4360         /*start background rebuild*/
4361         arcmsr_start_adapter_bgrb(acb);
4362         /* empty doorbell Qbuffer if door bell ringed */
4363         arcmsr_clear_doorbell_queue_buffer(acb);
4364         arcmsr_enable_eoi_mode(acb);
4365         /* enable outbound Post Queue, outbound doorbell Interrupt */
4366         arcmsr_enable_allintr(acb, intmask_org);
4367         acb->acb_flags |= ACB_F_IOP_INITED;
4368 }
4369 /*
4370 **********************************************************************
4371 **********************************************************************
4372 */
4373 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4374 {
4375         struct AdapterControlBlock *acb = arg;
4376         struct CommandControlBlock *srb_tmp;
4377         u_int32_t i;
4378         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4379
4380         acb->srb_phyaddr.phyaddr = srb_phyaddr;
4381         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4382         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4383                 if(bus_dmamap_create(acb->dm_segs_dmat,
4384                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4385                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4386                         printf("arcmsr%d:"
4387                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4388                         return;
4389                 }
4390                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4391                          || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
4392                 {
4393                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4394                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4395                 }
4396                 else
4397                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4398                 srb_tmp->acb = acb;
4399                 srb_tmp->smid = i << 16;
4400                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4401                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4402                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4403         }
4404         if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4405                 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4406         else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
4407                 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4408                 acb->completeQ_phys = srb_phyaddr;
4409                 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
4410                 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
4411                 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
4412                 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
4413                 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
4414         }
4415         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4416 }
4417 /*
4418 ************************************************************************
4419 ************************************************************************
4420 */
4421 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4422 {
4423         /* remove the control device */
4424         if(acb->ioctl_dev != NULL) {
4425                 destroy_dev(acb->ioctl_dev);
4426         }
4427         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4428         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4429         bus_dma_tag_destroy(acb->srb_dmat);
4430         bus_dma_tag_destroy(acb->dm_segs_dmat);
4431         bus_dma_tag_destroy(acb->parent_dmat);
4432 }
4433 /*
4434 ************************************************************************
4435 ************************************************************************
4436 */
4437 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4438 {
4439         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4440         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4441         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4442         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4443 }
4444 /*
4445 ************************************************************************
4446 ************************************************************************
4447 */
4448 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4449 {
4450         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4451         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4452         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4453         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4454 }
4455 /*
4456 ************************************************************************
4457 ************************************************************************
4458 */
4459 static u_int32_t arcmsr_initialize(device_t dev)
4460 {
4461         struct AdapterControlBlock *acb = device_get_softc(dev);
4462         u_int16_t pci_command;
4463         int i, j,max_coherent_size;
4464         u_int32_t vendor_dev_id;
4465
4466         vendor_dev_id = pci_get_devid(dev);
4467         acb->vendor_device_id = vendor_dev_id;
4468         acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4469         switch (vendor_dev_id) {
4470         case PCIDevVenIDARC1880:
4471         case PCIDevVenIDARC1882:
4472         case PCIDevVenIDARC1213:
4473         case PCIDevVenIDARC1223: {
4474                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
4475                         if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4476                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4477                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4478                                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4479                         else
4480                                 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4481                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4482                 }
4483                 break;
4484         case PCIDevVenIDARC1884:
4485                 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4486                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4487                 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4488                 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4489                 break;
4490         case PCIDevVenIDARC1886_:
4491         case PCIDevVenIDARC1886:
4492                 acb->adapter_type = ACB_ADAPTER_TYPE_F;
4493                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4494                 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
4495                 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4496                 break;
4497         case PCIDevVenIDARC1214: {
4498                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
4499                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4500                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4501                 }
4502                 break;
4503         case PCIDevVenIDARC1200:
4504         case PCIDevVenIDARC1201: {
4505                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4506                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4507                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4508                 }
4509                 break;
4510         case PCIDevVenIDARC1203: {
4511                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4512                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4513                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4514                 }
4515                 break;
4516         case PCIDevVenIDARC1110:
4517         case PCIDevVenIDARC1120:
4518         case PCIDevVenIDARC1130:
4519         case PCIDevVenIDARC1160:
4520         case PCIDevVenIDARC1170:
4521         case PCIDevVenIDARC1210:
4522         case PCIDevVenIDARC1220:
4523         case PCIDevVenIDARC1230:
4524         case PCIDevVenIDARC1231:
4525         case PCIDevVenIDARC1260:
4526         case PCIDevVenIDARC1261:
4527         case PCIDevVenIDARC1270:
4528         case PCIDevVenIDARC1280:
4529         case PCIDevVenIDARC1212:
4530         case PCIDevVenIDARC1222:
4531         case PCIDevVenIDARC1380:
4532         case PCIDevVenIDARC1381:
4533         case PCIDevVenIDARC1680:
4534         case PCIDevVenIDARC1681: {
4535                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4536                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4537                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4538                 }
4539                 break;
4540         default: {
4541                         printf("arcmsr%d:"
4542                         " unknown RAID adapter type \n", device_get_unit(dev));
4543                         return ENOMEM;
4544                 }
4545         }
4546         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4547                                 /*alignemnt*/           1,
4548                                 /*boundary*/            0,
4549                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4550                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4551                                 /*filter*/              NULL,
4552                                 /*filterarg*/           NULL,
4553                                 /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4554                                 /*nsegments*/           BUS_SPACE_UNRESTRICTED,
4555                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4556                                 /*flags*/               0,
4557                                 /*lockfunc*/            NULL,
4558                                 /*lockarg*/             NULL,
4559                                                         &acb->parent_dmat) != 0)
4560         {
4561                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4562                 return ENOMEM;
4563         }
4564
4565         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4566         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4567                                 /*alignment*/           1,
4568                                 /*boundary*/            0,
4569 #ifdef PAE
4570                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4571 #else
4572                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4573 #endif
4574                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4575                                 /*filter*/              NULL,
4576                                 /*filterarg*/           NULL,
4577                                 /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4578                                 /*nsegments*/           ARCMSR_MAX_SG_ENTRIES,
4579                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4580                                 /*flags*/               0,
4581                                 /*lockfunc*/            busdma_lock_mutex,
4582                                 /*lockarg*/             &acb->isr_lock,
4583                                                         &acb->dm_segs_dmat) != 0)
4584         {
4585                 bus_dma_tag_destroy(acb->parent_dmat);
4586                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4587                 return ENOMEM;
4588         }
4589
4590         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4591         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4592                                 /*alignment*/           0x20,
4593                                 /*boundary*/            0,
4594                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4595                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4596                                 /*filter*/              NULL,
4597                                 /*filterarg*/           NULL,
4598                                 /*maxsize*/             max_coherent_size,
4599                                 /*nsegments*/           1,
4600                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4601                                 /*flags*/               0,
4602                                 /*lockfunc*/            NULL,
4603                                 /*lockarg*/             NULL,
4604                                                         &acb->srb_dmat) != 0)
4605         {
4606                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4607                 bus_dma_tag_destroy(acb->parent_dmat);
4608                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4609                 return ENXIO;
4610         }
4611         /* Allocation for our srbs */
4612         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4613                 bus_dma_tag_destroy(acb->srb_dmat);
4614                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4615                 bus_dma_tag_destroy(acb->parent_dmat);
4616                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4617                 return ENXIO;
4618         }
4619         /* And permanently map them */
4620         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4621                 bus_dma_tag_destroy(acb->srb_dmat);
4622                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4623                 bus_dma_tag_destroy(acb->parent_dmat);
4624                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4625                 return ENXIO;
4626         }
4627         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4628         pci_command |= PCIM_CMD_BUSMASTEREN;
4629         pci_command |= PCIM_CMD_PERRESPEN;
4630         pci_command |= PCIM_CMD_MWRICEN;
4631         /* Enable Busmaster */
4632         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4633         switch(acb->adapter_type) {
4634         case ACB_ADAPTER_TYPE_A: {
4635                 u_int32_t rid0 = PCIR_BAR(0);
4636                 vm_offset_t     mem_base0;
4637
4638                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4639                 if(acb->sys_res_arcmsr[0] == NULL) {
4640                         arcmsr_free_resource(acb);
4641                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4642                         return ENOMEM;
4643                 }
4644                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4645                         arcmsr_free_resource(acb);
4646                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4647                         return ENXIO;
4648                 }
4649                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4650                 if(mem_base0 == 0) {
4651                         arcmsr_free_resource(acb);
4652                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4653                         return ENXIO;
4654                 }
4655                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4656                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4657                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4658                 acb->rid[0] = rid0;
4659                 }
4660                 break;
4661         case ACB_ADAPTER_TYPE_B: {
4662                 struct HBB_MessageUnit *phbbmu;
4663                 struct CommandControlBlock *freesrb;
4664                 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4665                 vm_offset_t     mem_base[]={0,0};
4666                 for(i=0; i < 2; i++) {
4667                         acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4668                         if(acb->sys_res_arcmsr[i] == NULL) {
4669                                 arcmsr_free_resource(acb);
4670                                 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4671                                 return ENOMEM;
4672                         }
4673                         if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4674                                 arcmsr_free_resource(acb);
4675                                 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4676                                 return ENXIO;
4677                         }
4678                         mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4679                         if(mem_base[i] == 0) {
4680                                 arcmsr_free_resource(acb);
4681                                 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4682                                 return ENXIO;
4683                         }
4684                         acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4685                         acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4686                 }
4687                 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4688                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4689                 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4690                 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4691                 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4692                 if (vendor_dev_id == PCIDevVenIDARC1203) {
4693                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4694                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4695                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4696                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4697                 } else {
4698                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4699                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4700                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4701                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4702                 }
4703                 acb->rid[0] = rid[0];
4704                 acb->rid[1] = rid[1];
4705                 }
4706                 break;
4707         case ACB_ADAPTER_TYPE_C: {
4708                 u_int32_t rid0 = PCIR_BAR(1);
4709                 vm_offset_t     mem_base0;
4710
4711                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4712                 if(acb->sys_res_arcmsr[0] == NULL) {
4713                         arcmsr_free_resource(acb);
4714                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4715                         return ENOMEM;
4716                 }
4717                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4718                         arcmsr_free_resource(acb);
4719                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4720                         return ENXIO;
4721                 }
4722                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4723                 if(mem_base0 == 0) {
4724                         arcmsr_free_resource(acb);
4725                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4726                         return ENXIO;
4727                 }
4728                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4729                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4730                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4731                 acb->rid[0] = rid0;
4732                 }
4733                 break;
4734         case ACB_ADAPTER_TYPE_D: {
4735                 struct HBD_MessageUnit0 *phbdmu;
4736                 u_int32_t rid0 = PCIR_BAR(0);
4737                 vm_offset_t     mem_base0;
4738
4739                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4740                 if(acb->sys_res_arcmsr[0] == NULL) {
4741                         arcmsr_free_resource(acb);
4742                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4743                         return ENOMEM;
4744                 }
4745                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4746                         arcmsr_free_resource(acb);
4747                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4748                         return ENXIO;
4749                 }
4750                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4751                 if(mem_base0 == 0) {
4752                         arcmsr_free_resource(acb);
4753                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4754                         return ENXIO;
4755                 }
4756                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4757                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4758                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4759                 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4760                 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4761                 acb->rid[0] = rid0;
4762                 }
4763                 break;
4764         case ACB_ADAPTER_TYPE_E: {
4765                 u_int32_t rid0 = PCIR_BAR(1);
4766                 vm_offset_t     mem_base0;
4767
4768                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4769                 if(acb->sys_res_arcmsr[0] == NULL) {
4770                         arcmsr_free_resource(acb);
4771                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4772                         return ENOMEM;
4773                 }
4774                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4775                         arcmsr_free_resource(acb);
4776                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4777                         return ENXIO;
4778                 }
4779                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4780                 if(mem_base0 == 0) {
4781                         arcmsr_free_resource(acb);
4782                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4783                         return ENXIO;
4784                 }
4785                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4786                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4787                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4788                 acb->doneq_index = 0;
4789                 acb->in_doorbell = 0;
4790                 acb->out_doorbell = 0;
4791                 acb->rid[0] = rid0;
4792                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4793                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4794                 }
4795                 break;
4796         case ACB_ADAPTER_TYPE_F: {
4797                 u_int32_t rid0 = PCIR_BAR(0);
4798                 vm_offset_t     mem_base0;
4799                 unsigned long   host_buffer_dma;
4800
4801                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4802                 if(acb->sys_res_arcmsr[0] == NULL) {
4803                         arcmsr_free_resource(acb);
4804                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4805                         return ENOMEM;
4806                 }
4807                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4808                         arcmsr_free_resource(acb);
4809                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4810                         return ENXIO;
4811                 }
4812                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4813                 if(mem_base0 == 0) {
4814                         arcmsr_free_resource(acb);
4815                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4816                         return ENXIO;
4817                 }
4818                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4819                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4820                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4821                 acb->doneq_index = 0;
4822                 acb->in_doorbell = 0;
4823                 acb->out_doorbell = 0;
4824                 acb->rid[0] = rid0;
4825                 arcmsr_wait_firmware_ready(acb);
4826                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4827                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4828                 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
4829                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1));  /* host buffer low addr, bit0:1 all buffer active */
4830                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
4831                 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1);       /* set host buffer physical address */
4832                 }
4833                 break;
4834         }
4835         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4836                 arcmsr_free_resource(acb);
4837                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4838                 return ENXIO;
4839         }
4840         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4841         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4842         /*
4843         ********************************************************************
4844         ** init raid volume state
4845         ********************************************************************
4846         */
4847         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4848                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4849                         acb->devstate[i][j] = ARECA_RAID_GONE;
4850                 }
4851         }
4852         arcmsr_iop_init(acb);
4853         return(0);
4854 }
4855
4856 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4857 {
4858         int i;
4859
4860         for (i = 0; i < acb->msix_vectors; i++) {
4861                 acb->irq_id[i] = 1 + i;
4862                 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4863                     SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4864                 if (acb->irqres[i] == NULL) {
4865                         printf("arcmsr: Can't allocate MSI-X resource\n");
4866                         goto irq_alloc_failed;
4867                 }
4868                 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4869                     INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4870                     acb, &acb->ih[i])) {
4871                         printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4872                         goto irq_alloc_failed;
4873                 }
4874         }
4875         printf("arcmsr: MSI-X INT enabled\n");
4876         acb->acb_flags |= ACB_F_MSIX_ENABLED;
4877         return TRUE;
4878
4879 irq_alloc_failed:
4880         arcmsr_teardown_intr(acb->pci_dev, acb);
4881         return FALSE;
4882 }
4883
4884 /*
4885 ************************************************************************
4886 ************************************************************************
4887 */
4888 static int arcmsr_attach(device_t dev)
4889 {
4890         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4891         u_int32_t unit=device_get_unit(dev);
4892         struct ccb_setasync csa;
4893         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4894         struct resource *irqres;
4895
4896         if(acb == NULL) {
4897                 printf("arcmsr%d: cannot allocate softc\n", unit);
4898                 return (ENOMEM);
4899         }
4900         arcmsr_mutex_init(acb);
4901         acb->pci_dev = dev;
4902         acb->pci_unit = unit;
4903         if(arcmsr_initialize(dev)) {
4904                 printf("arcmsr%d: initialize failure!\n", unit);
4905                 goto initialize_failed;
4906         }
4907         /* After setting up the adapter, map our interrupt */
4908         acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4909         if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4910                 if (arcmsr_setup_msix(acb) == TRUE)
4911                         goto irqx;
4912         }
4913         acb->irq_id[0] = 0;
4914         irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4915         if(irqres == NULL ||
4916                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4917                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4918                 goto setup_intr_failed;
4919         }
4920         acb->irqres[0] = irqres;
4921 irqx:
4922         /*
4923          * Now let the CAM generic SCSI layer find the SCSI devices on
4924          * the bus *  start queue to reset to the idle loop. *
4925          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4926          * max_sim_transactions
4927         */
4928         devq = cam_simq_alloc(acb->maxOutstanding);
4929         if(devq == NULL) {
4930                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4931                 goto simq_alloc_failed;
4932         }
4933         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4934         if(acb->psim == NULL) {
4935                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4936                 goto sim_alloc_failed;
4937         }
4938         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4939         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4940                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4941                 goto xpt_bus_failed;
4942         }
4943         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4944                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4945                 goto xpt_path_failed;
4946         }
4947         /*
4948         ****************************************************
4949         */
4950         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4951         csa.ccb_h.func_code = XPT_SASYNC_CB;
4952         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4953         csa.callback = arcmsr_async;
4954         csa.callback_arg = acb->psim;
4955         xpt_action((union ccb *)&csa);
4956         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4957         /* Create the control device.  */
4958         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4959
4960         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4961         arcmsr_callout_init(&acb->devmap_callout);
4962         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4963         return (0);
4964 xpt_path_failed:
4965         xpt_bus_deregister(cam_sim_path(acb->psim));
4966 xpt_bus_failed:
4967         cam_sim_free(acb->psim, /* free_simq */ TRUE);
4968 sim_alloc_failed:
4969         cam_simq_free(devq);
4970 simq_alloc_failed:
4971         arcmsr_teardown_intr(dev, acb);
4972 setup_intr_failed:
4973         arcmsr_free_resource(acb);
4974 initialize_failed:
4975         arcmsr_mutex_destroy(acb);
4976         return ENXIO;
4977 }
4978
4979 /*
4980 ************************************************************************
4981 ************************************************************************
4982 */
4983 static int arcmsr_probe(device_t dev)
4984 {
4985         u_int32_t id;
4986         u_int16_t sub_device_id;
4987         static char buf[256];
4988         char x_type[]={"unknown"};
4989         char *type;
4990         int raid6 = 1;
4991
4992         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4993                 return (ENXIO);
4994         }
4995         sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4996         switch(id = pci_get_devid(dev)) {
4997         case PCIDevVenIDARC1110:
4998         case PCIDevVenIDARC1200:
4999         case PCIDevVenIDARC1201:
5000         case PCIDevVenIDARC1210:
5001                 raid6 = 0;
5002                 /*FALLTHRU*/
5003         case PCIDevVenIDARC1120:
5004         case PCIDevVenIDARC1130:
5005         case PCIDevVenIDARC1160:
5006         case PCIDevVenIDARC1170:
5007         case PCIDevVenIDARC1220:
5008         case PCIDevVenIDARC1230:
5009         case PCIDevVenIDARC1231:
5010         case PCIDevVenIDARC1260:
5011         case PCIDevVenIDARC1261:
5012         case PCIDevVenIDARC1270:
5013         case PCIDevVenIDARC1280:
5014                 type = "SATA 3G";
5015                 break;
5016         case PCIDevVenIDARC1212:
5017         case PCIDevVenIDARC1222:
5018         case PCIDevVenIDARC1380:
5019         case PCIDevVenIDARC1381:
5020         case PCIDevVenIDARC1680:
5021         case PCIDevVenIDARC1681:
5022                 type = "SAS 3G";
5023                 break;
5024         case PCIDevVenIDARC1880:
5025         case PCIDevVenIDARC1882:
5026         case PCIDevVenIDARC1213:
5027         case PCIDevVenIDARC1223:
5028                 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
5029                     (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
5030                     (sub_device_id == ARECA_SUB_DEV_ID_1226))
5031                         type = "SAS 12G";
5032                 else
5033                         type = "SAS 6G";
5034                 break;
5035         case PCIDevVenIDARC1884:
5036                 type = "SAS 12G";
5037                 break;
5038         case PCIDevVenIDARC1886_:
5039         case PCIDevVenIDARC1886:
5040                 type = "NVME,SAS-12G,SATA-6G";
5041                 break;
5042         case PCIDevVenIDARC1214:
5043         case PCIDevVenIDARC1203:
5044                 type = "SATA 6G";
5045                 break;
5046         default:
5047                 type = x_type;
5048                 raid6 = 0;
5049                 break;
5050         }
5051         if(type == x_type)
5052                 return(ENXIO);
5053         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
5054                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
5055         device_set_desc_copy(dev, buf);
5056         return (BUS_PROBE_DEFAULT);
5057 }
5058 /*
5059 ************************************************************************
5060 ************************************************************************
5061 */
5062 static int arcmsr_shutdown(device_t dev)
5063 {
5064         u_int32_t  i;
5065         u_int32_t intmask_org;
5066         struct CommandControlBlock *srb;
5067         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5068
5069         /* stop adapter background rebuild */
5070         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5071         /* disable all outbound interrupt */
5072         intmask_org = arcmsr_disable_allintr(acb);
5073         arcmsr_stop_adapter_bgrb(acb);
5074         arcmsr_flush_adapter_cache(acb);
5075         /* abort all outstanding command */
5076         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
5077         acb->acb_flags &= ~ACB_F_IOP_INITED;
5078         if(acb->srboutstandingcount != 0) {
5079                 /*clear and abort all outbound posted Q*/
5080                 arcmsr_done4abort_postqueue(acb);
5081                 /* talk to iop 331 outstanding command aborted*/
5082                 arcmsr_abort_allcmd(acb);
5083                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
5084                         srb = acb->psrb_pool[i];
5085                         if(srb->srb_state == ARCMSR_SRB_START) {
5086                                 srb->srb_state = ARCMSR_SRB_ABORTED;
5087                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
5088                                 arcmsr_srb_complete(srb, 1);
5089                         }
5090                 }
5091         }
5092         acb->srboutstandingcount = 0;
5093         acb->workingsrb_doneindex = 0;
5094         acb->workingsrb_startindex = 0;
5095         acb->pktRequestCount = 0;
5096         acb->pktReturnCount = 0;
5097         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5098         return (0);
5099 }
5100 /*
5101 ************************************************************************
5102 ************************************************************************
5103 */
5104 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
5105 {
5106         int i;
5107
5108         if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
5109                 for (i = 0; i < acb->msix_vectors; i++) {
5110                         if (acb->ih[i])
5111                                 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
5112                         if (acb->irqres[i] != NULL)
5113                                 bus_release_resource(dev, SYS_RES_IRQ,
5114                                     acb->irq_id[i], acb->irqres[i]);
5115
5116                         acb->ih[i] = NULL;
5117                 }
5118                 pci_release_msi(dev);
5119         } else {
5120                 if (acb->ih[0])
5121                         bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
5122                 if (acb->irqres[0] != NULL)
5123                         bus_release_resource(dev, SYS_RES_IRQ,
5124                             acb->irq_id[0], acb->irqres[0]);
5125                 acb->ih[0] = NULL;
5126         }
5127
5128 }
5129 /*
5130 ************************************************************************
5131 ************************************************************************
5132 */
5133 static int arcmsr_detach(device_t dev)
5134 {
5135         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
5136         int i;
5137
5138         callout_stop(&acb->devmap_callout);
5139         arcmsr_teardown_intr(dev, acb);
5140         arcmsr_shutdown(dev);
5141         arcmsr_free_resource(acb);
5142         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
5143                 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
5144         }
5145         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
5146         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
5147         xpt_free_path(acb->ppath);
5148         xpt_bus_deregister(cam_sim_path(acb->psim));
5149         cam_sim_free(acb->psim, TRUE);
5150         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
5151         arcmsr_mutex_destroy(acb);
5152         return (0);
5153 }
5154
5155 #ifdef ARCMSR_DEBUG1
5156 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
5157 {
5158         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
5159                 return;
5160         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
5161         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
5162         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
5163         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
5164 }
5165 #endif