sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  13 **
  14 ** Redistribution and use in source and binary forms, with or without
  15 ** modification, are permitted provided that the following conditions
  16 ** are met:
  17 ** 1. Redistributions of source code must retain the above copyright
  18 **    notice, this list of conditions and the following disclaimer.
  19 ** 2. Redistributions in binary form must reproduce the above copyright
  20 **    notice, this list of conditions and the following disclaimer in the
  21 **    documentation and/or other materials provided with the distribution.
  22 ** 3. The name of the author may not be used to endorse or promote products
  23 **    derived from this software without specific prior written permission.
  24 **
  25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 ********************************************************************************
  36 ** History
  37 **
  38 **    REV#         DATE         NAME        DESCRIPTION
  39 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  40 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  41 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  42 **                                          clean unused function
  43 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  44 **                                          firmware version check
  45 **                                          and firmware update notify for hardware bug fix
  46 **                                          handling if none zero high part physical address
  47 **                                          of srb resource
  48 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  49 **                                          add iop message xfer
  50 **                                          with scsi pass-through command
  51 **                                          add new device id of sas raid adapters
  52 **                                          code fit for SPARC64 & PPC
  53 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  54 **                                          and cause g_vfs_done() read write error
  55 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  56 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  57 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  58 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  59 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  60 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  61 **                                          for any one LUN device failed
  62 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  63 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  64 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  65 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  66 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  67 **              02/14/2011  Ching Huang     Modified pktRequestCount
  68 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  69 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  70 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  71 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  72 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  73 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  74 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  75 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  76 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  77 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  78 ** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
  79 ******************************************************************************************
  80 */
  81
  82 #include <sys/cdefs.h>
  83 __FBSDID("$FreeBSD$");
  84
  85 #if 0
  86 #define ARCMSR_DEBUG1                   1
  87 #endif
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/malloc.h>
  91 #include <sys/kernel.h>
  92 #include <sys/bus.h>
  93 #include <sys/queue.h>
  94 #include <sys/stat.h>
  95 #include <sys/devicestat.h>
  96 #include <sys/kthread.h>
  97 #include <sys/module.h>
  98 #include <sys/proc.h>
  99 #include <sys/lock.h>
 100 #include <sys/sysctl.h>
 101 #include <sys/poll.h>
 102 #include <sys/ioccom.h>
 103 #include <vm/vm.h>
 104 #include <vm/vm_param.h>
 105 #include <vm/pmap.h>
 106
 107 #include <isa/rtc.h>
 108
 109 #include <machine/bus.h>
 110 #include <machine/resource.h>
 111 #include <machine/atomic.h>
 112 #include <sys/conf.h>
 113 #include <sys/rman.h>
 114
 115 #include <cam/cam.h>
 116 #include <cam/cam_ccb.h>
 117 #include <cam/cam_sim.h>
 118 #include <cam/cam_periph.h>
 119 #include <cam/cam_xpt_periph.h>
 120 #include <cam/cam_xpt_sim.h>
 121 #include <cam/cam_debug.h>
 122 #include <cam/scsi/scsi_all.h>
 123 #include <cam/scsi/scsi_message.h>
 124 /*
 125 **************************************************************************
 126 **************************************************************************
 127 */
 128 #if __FreeBSD_version >= 500005
 129     #include <sys/selinfo.h>
 130     #include <sys/mutex.h>
 131     #include <sys/endian.h>
 132     #include <dev/pci/pcivar.h>
 133     #include <dev/pci/pcireg.h>
 134 #else
 135     #include <sys/select.h>
 136     #include <pci/pcivar.h>
 137     #include <pci/pcireg.h>
 138 #endif
 139
 140 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
 141 #define CAM_NEW_TRAN_CODE       1
 142 #endif
 143
 144 #if __FreeBSD_version > 500000
 145 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 146 #else
 147 #define arcmsr_callout_init(a)  callout_init(a);
 148 #endif
 149
 150 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.20.00.29 2013-12-18"
 151 #include <dev/arcmsr/arcmsr.h>
 152 /*
 153 **************************************************************************
 154 **************************************************************************
 155 */
 156 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 157 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 158 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 159 static int arcmsr_probe(device_t dev);
 160 static int arcmsr_attach(device_t dev);
 161 static int arcmsr_detach(device_t dev);
 162 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 163 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 164 static int arcmsr_shutdown(device_t dev);
 165 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 166 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 167 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 168 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 169 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 170 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 171 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 172 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 173 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 174 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 175 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 176 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 177 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 178 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 179 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 180 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 181 static int arcmsr_resume(device_t dev);
 182 static int arcmsr_suspend(device_t dev);
 183 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 184 static void     arcmsr_polling_devmap(void *arg);
 185 static void     arcmsr_srb_timeout(void *arg);
 186 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 187 #ifdef ARCMSR_DEBUG1
 188 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 189 #endif
 190 /*
 191 **************************************************************************
 192 **************************************************************************
 193 */
 194 static void UDELAY(u_int32_t us) { DELAY(us); }
 195 /*
 196 **************************************************************************
 197 **************************************************************************
 198 */
 199 static bus_dmamap_callback_t arcmsr_map_free_srb;
 200 static bus_dmamap_callback_t arcmsr_execute_srb;
 201 /*
 202 **************************************************************************
 203 **************************************************************************
 204 */
 205 static d_open_t arcmsr_open;
 206 static d_close_t arcmsr_close;
 207 static d_ioctl_t arcmsr_ioctl;
 208
 209 static device_method_t arcmsr_methods[]={
 210         DEVMETHOD(device_probe,         arcmsr_probe),
 211         DEVMETHOD(device_attach,        arcmsr_attach),
 212         DEVMETHOD(device_detach,        arcmsr_detach),
 213         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 214         DEVMETHOD(device_suspend,       arcmsr_suspend),
 215         DEVMETHOD(device_resume,        arcmsr_resume),
 216
 217 #if __FreeBSD_version >= 803000
 218         DEVMETHOD_END
 219 #else
 220         { 0, 0 }
 221 #endif
 222 };
 223
 224 static driver_t arcmsr_driver={
 225         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 226 };
 227
 228 static devclass_t arcmsr_devclass;
 229 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 230 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 231 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 232 #ifndef BUS_DMA_COHERENT
 233         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 234 #endif
 235 #if __FreeBSD_version >= 501000
 236 static struct cdevsw arcmsr_cdevsw={
 237         #if __FreeBSD_version >= 503000
 238                 .d_version = D_VERSION,
 239         #endif
 240         #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
 241                 .d_flags   = D_NEEDGIANT,
 242         #endif
 243                 .d_open    = arcmsr_open,       /* open     */
 244                 .d_close   = arcmsr_close,      /* close    */
 245                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 246                 .d_name    = "arcmsr",          /* name     */
 247         };
 248 #else
 249         #define ARCMSR_CDEV_MAJOR       180
 250
 251 static struct cdevsw arcmsr_cdevsw = {
 252                 arcmsr_open,                            /* open     */
 253                 arcmsr_close,                           /* close    */
 254                 noread,                                         /* read     */
 255                 nowrite,                                        /* write    */
 256                 arcmsr_ioctl,                           /* ioctl    */
 257                 nopoll,                                         /* poll     */
 258                 nommap,                                         /* mmap     */
 259                 nostrategy,                                     /* strategy */
 260                 "arcmsr",                                       /* name     */
 261                 ARCMSR_CDEV_MAJOR,                      /* major    */
 262                 nodump,                                         /* dump     */
 263                 nopsize,                                        /* psize    */
 264                 0                                                       /* flags    */
 265         };
 266 #endif
 267 /*
 268 **************************************************************************
 269 **************************************************************************
 270 */
 271 #if __FreeBSD_version < 500005
 272         static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
 273 #else
 274         #if __FreeBSD_version < 503000
 275         static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
 276         #else
 277         static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 278         #endif
 279 #endif
 280 {
 281         #if __FreeBSD_version < 503000
 282                 struct AdapterControlBlock *acb = dev->si_drv1;
 283         #else
 284                 int     unit = dev2unit(dev);
 285                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 286         #endif
 287         if(acb == NULL) {
 288                 return ENXIO;
 289         }
 290         return (0);
 291 }
 292 /*
 293 **************************************************************************
 294 **************************************************************************
 295 */
 296 #if __FreeBSD_version < 500005
 297         static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
 298 #else
 299         #if __FreeBSD_version < 503000
 300         static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
 301         #else
 302         static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 303         #endif
 304 #endif
 305 {
 306         #if __FreeBSD_version < 503000
 307                 struct AdapterControlBlock *acb = dev->si_drv1;
 308         #else
 309                 int     unit = dev2unit(dev);
 310                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 311         #endif
 312         if(acb == NULL) {
 313                 return ENXIO;
 314         }
 315         return 0;
 316 }
 317 /*
 318 **************************************************************************
 319 **************************************************************************
 320 */
 321 #if __FreeBSD_version < 500005
 322         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
 323 #else
 324         #if __FreeBSD_version < 503000
 325         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 326         #else
 327         static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 328         #endif
 329 #endif
 330 {
 331         #if __FreeBSD_version < 503000
 332                 struct AdapterControlBlock *acb = dev->si_drv1;
 333         #else
 334                 int     unit = dev2unit(dev);
 335                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 336         #endif
 337
 338         if(acb == NULL) {
 339                 return ENXIO;
 340         }
 341         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 342 }
 343 /*
 344 **********************************************************************
 345 **********************************************************************
 346 */
 347 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 348 {
 349         u_int32_t intmask_org = 0;
 350
 351         switch (acb->adapter_type) {
 352         case ACB_ADAPTER_TYPE_A: {
 353                         /* disable all outbound interrupt */
 354                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 355                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 356                 }
 357                 break;
 358         case ACB_ADAPTER_TYPE_B: {
 359                         /* disable all outbound interrupt */
 360                         intmask_org = CHIP_REG_READ32(HBB_DOORBELL,
 361                                                 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 362                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
 363                 }
 364                 break;
 365         case ACB_ADAPTER_TYPE_C: {
 366                         /* disable all outbound interrupt */
 367                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 368                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 369                 }
 370                 break;
 371         case ACB_ADAPTER_TYPE_D: {
 372                         /* disable all outbound interrupt */
 373                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 374                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 375                 }
 376                 break;
 377         }
 378         return (intmask_org);
 379 }
 380 /*
 381 **********************************************************************
 382 **********************************************************************
 383 */
 384 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 385 {
 386         u_int32_t mask;
 387
 388         switch (acb->adapter_type) {
 389         case ACB_ADAPTER_TYPE_A: {
 390                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 391                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 392                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 393                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 394                 }
 395                 break;
 396         case ACB_ADAPTER_TYPE_B: {
 397                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 398                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 399                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 400                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 401                 }
 402                 break;
 403         case ACB_ADAPTER_TYPE_C: {
 404                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 405                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 406                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 407                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 408                 }
 409                 break;
 410         case ACB_ADAPTER_TYPE_D: {
 411                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 412                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 413                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 414                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 415                         acb->outbound_int_enable = mask;
 416                 }
 417                 break;
 418         }
 419 }
 420 /*
 421 **********************************************************************
 422 **********************************************************************
 423 */
 424 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 425 {
 426         u_int32_t Index;
 427         u_int8_t Retries = 0x00;
 428
 429         do {
 430                 for(Index=0; Index < 100; Index++) {
 431                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 432                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 433                                 return TRUE;
 434                         }
 435                         UDELAY(10000);
 436                 }/*max 1 seconds*/
 437         }while(Retries++ < 20);/*max 20 sec*/
 438         return (FALSE);
 439 }
 440 /*
 441 **********************************************************************
 442 **********************************************************************
 443 */
 444 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 445 {
 446         u_int32_t Index;
 447         u_int8_t Retries = 0x00;
 448
 449         do {
 450                 for(Index=0; Index < 100; Index++) {
 451                         if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 452                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 453                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 454                                 return TRUE;
 455                         }
 456                         UDELAY(10000);
 457                 }/*max 1 seconds*/
 458         }while(Retries++ < 20);/*max 20 sec*/
 459         return (FALSE);
 460 }
 461 /*
 462 **********************************************************************
 463 **********************************************************************
 464 */
 465 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 466 {
 467         u_int32_t Index;
 468         u_int8_t Retries = 0x00;
 469
 470         do {
 471                 for(Index=0; Index < 100; Index++) {
 472                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 473                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 474                                 return TRUE;
 475                         }
 476                         UDELAY(10000);
 477                 }/*max 1 seconds*/
 478         }while(Retries++ < 20);/*max 20 sec*/
 479         return (FALSE);
 480 }
 481 /*
 482 **********************************************************************
 483 **********************************************************************
 484 */
 485 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 486 {
 487         u_int32_t Index;
 488         u_int8_t Retries = 0x00;
 489
 490         do {
 491                 for(Index=0; Index < 100; Index++) {
 492                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 493                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 494                                 return TRUE;
 495                         }
 496                         UDELAY(10000);
 497                 }/*max 1 seconds*/
 498         }while(Retries++ < 20);/*max 20 sec*/
 499         return (FALSE);
 500 }
 501 /*
 502 ************************************************************************
 503 ************************************************************************
 504 */
 505 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 506 {
 507         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 508
 509         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 510         do {
 511                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 512                         break;
 513                 } else {
 514                         retry_count--;
 515                 }
 516         }while(retry_count != 0);
 517 }
 518 /*
 519 ************************************************************************
 520 ************************************************************************
 521 */
 522 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 523 {
 524         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 525
 526         CHIP_REG_WRITE32(HBB_DOORBELL,
 527         0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 528         do {
 529                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 530                         break;
 531                 } else {
 532                         retry_count--;
 533                 }
 534         }while(retry_count != 0);
 535 }
 536 /*
 537 ************************************************************************
 538 ************************************************************************
 539 */
 540 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 541 {
 542         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 543
 544         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 545         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 546         do {
 547                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 548                         break;
 549                 } else {
 550                         retry_count--;
 551                 }
 552         }while(retry_count != 0);
 553 }
 554 /*
 555 ************************************************************************
 556 ************************************************************************
 557 */
 558 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 559 {
 560         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 561
 562         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 563         do {
 564                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 565                         break;
 566                 } else {
 567                         retry_count--;
 568                 }
 569         }while(retry_count != 0);
 570 }
 571 /*
 572 ************************************************************************
 573 ************************************************************************
 574 */
 575 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 576 {
 577         switch (acb->adapter_type) {
 578         case ACB_ADAPTER_TYPE_A: {
 579                         arcmsr_flush_hba_cache(acb);
 580                 }
 581                 break;
 582         case ACB_ADAPTER_TYPE_B: {
 583                         arcmsr_flush_hbb_cache(acb);
 584                 }
 585                 break;
 586         case ACB_ADAPTER_TYPE_C: {
 587                         arcmsr_flush_hbc_cache(acb);
 588                 }
 589                 break;
 590         case ACB_ADAPTER_TYPE_D: {
 591                         arcmsr_flush_hbd_cache(acb);
 592                 }
 593                 break;
 594         }
 595 }
 596 /*
 597 *******************************************************************************
 598 *******************************************************************************
 599 */
 600 static int arcmsr_suspend(device_t dev)
 601 {
 602         struct AdapterControlBlock      *acb = device_get_softc(dev);
 603
 604         /* flush controller */
 605         arcmsr_iop_parking(acb);
 606         /* disable all outbound interrupt */
 607         arcmsr_disable_allintr(acb);
 608         return(0);
 609 }
 610 /*
 611 *******************************************************************************
 612 *******************************************************************************
 613 */
 614 static int arcmsr_resume(device_t dev)
 615 {
 616         struct AdapterControlBlock      *acb = device_get_softc(dev);
 617
 618         arcmsr_iop_init(acb);
 619         return(0);
 620 }
 621 /*
 622 *********************************************************************************
 623 *********************************************************************************
 624 */
 625 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 626 {
 627         struct AdapterControlBlock *acb;
 628         u_int8_t target_id, target_lun;
 629         struct cam_sim *sim;
 630
 631         sim = (struct cam_sim *) cb_arg;
 632         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 633         switch (code) {
 634         case AC_LOST_DEVICE:
 635                 target_id = xpt_path_target_id(path);
 636                 target_lun = xpt_path_lun_id(path);
 637                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 638                         break;
 639                 }
 640         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 641                 break;
 642         default:
 643                 break;
 644         }
 645 }
 646 /*
 647 **********************************************************************
 648 **********************************************************************
 649 */
 650 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 651 {
 652         union ccb *pccb = srb->pccb;
 653
 654         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 655         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 656         if(pccb->csio.sense_len) {
 657                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 658                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 659                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 660                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 661                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 662         }
 663 }
 664 /*
 665 *********************************************************************
 666 *********************************************************************
 667 */
 668 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 669 {
 670         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 671         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 672                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 673         }
 674 }
 675 /*
 676 *********************************************************************
 677 *********************************************************************
 678 */
 679 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 680 {
 681         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 682         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 683                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 684         }
 685 }
 686 /*
 687 *********************************************************************
 688 *********************************************************************
 689 */
 690 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 691 {
 692         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 693         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 694         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 695                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 696         }
 697 }
 698 /*
 699 *********************************************************************
 700 *********************************************************************
 701 */
 702 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 703 {
 704         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 705         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 706                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 707         }
 708 }
 709 /*
 710 *********************************************************************
 711 *********************************************************************
 712 */
 713 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 714 {
 715         switch (acb->adapter_type) {
 716         case ACB_ADAPTER_TYPE_A: {
 717                         arcmsr_abort_hba_allcmd(acb);
 718                 }
 719                 break;
 720         case ACB_ADAPTER_TYPE_B: {
 721                         arcmsr_abort_hbb_allcmd(acb);
 722                 }
 723                 break;
 724         case ACB_ADAPTER_TYPE_C: {
 725                         arcmsr_abort_hbc_allcmd(acb);
 726                 }
 727                 break;
 728         case ACB_ADAPTER_TYPE_D: {
 729                         arcmsr_abort_hbd_allcmd(acb);
 730                 }
 731                 break;
 732         }
 733 }
 734 /*
 735 **********************************************************************
 736 **********************************************************************
 737 */
 738 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 739 {
 740         struct AdapterControlBlock *acb = srb->acb;
 741         union ccb *pccb = srb->pccb;
 742
 743         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 744                 callout_stop(&srb->ccb_callout);
 745         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 746                 bus_dmasync_op_t op;
 747
 748                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 749                         op = BUS_DMASYNC_POSTREAD;
 750                 } else {
 751                         op = BUS_DMASYNC_POSTWRITE;
 752                 }
 753                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 754                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 755         }
 756         if(stand_flag == 1) {
 757                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 758                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 759                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 760                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 761                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 762                 }
 763         }
 764         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 765                 arcmsr_free_srb(srb);
 766         acb->pktReturnCount++;
 767         xpt_done(pccb);
 768 }
 769 /*
 770 **************************************************************************
 771 **************************************************************************
 772 */
 773 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 774 {
 775         int target, lun;
 776
 777         target = srb->pccb->ccb_h.target_id;
 778         lun = srb->pccb->ccb_h.target_lun;
 779         if(error == FALSE) {
 780                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 781                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 782                 }
 783                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 784                 arcmsr_srb_complete(srb, 1);
 785         } else {
 786                 switch(srb->arcmsr_cdb.DeviceStatus) {
 787                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 788                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 789                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 790                                 }
 791                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 792                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 793                                 arcmsr_srb_complete(srb, 1);
 794                         }
 795                         break;
 796                 case ARCMSR_DEV_ABORTED:
 797                 case ARCMSR_DEV_INIT_FAIL: {
 798                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 799                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 800                                 arcmsr_srb_complete(srb, 1);
 801                         }
 802                         break;
 803                 case SCSISTAT_CHECK_CONDITION: {
 804                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 805                                 arcmsr_report_sense_info(srb);
 806                                 arcmsr_srb_complete(srb, 1);
 807                         }
 808                         break;
 809                 default:
 810                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 811                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 812                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 813                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 814                         /*unknown error or crc error just for retry*/
 815                         arcmsr_srb_complete(srb, 1);
 816                         break;
 817                 }
 818         }
 819 }
 820 /*
 821 **************************************************************************
 822 **************************************************************************
 823 */
 824 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 825 {
 826         struct CommandControlBlock *srb;
 827
 828         /* check if command done with no error*/
 829         switch (acb->adapter_type) {
 830         case ACB_ADAPTER_TYPE_C:
 831         case ACB_ADAPTER_TYPE_D:
 832                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 833                 break;
 834         case ACB_ADAPTER_TYPE_A:
 835         case ACB_ADAPTER_TYPE_B:
 836         default:
 837                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 838                 break;
 839         }
 840         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 841                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 842                         arcmsr_free_srb(srb);
 843                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 844                         return;
 845                 }
 846                 printf("arcmsr%d: return srb has been completed\n"
 847                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 848                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 849                 return;
 850         }
 851         arcmsr_report_srb_state(acb, srb, error);
 852 }
 853 /*
 854 **************************************************************************
 855 **************************************************************************
 856 */
 857 static void     arcmsr_srb_timeout(void *arg)
 858 {
 859         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 860         struct AdapterControlBlock *acb;
 861         int target, lun;
 862         u_int8_t cmd;
 863
 864         target = srb->pccb->ccb_h.target_id;
 865         lun = srb->pccb->ccb_h.target_lun;
 866         acb = srb->acb;
 867         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 868         if(srb->srb_state == ARCMSR_SRB_START)
 869         {
 870                 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
 871                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 872                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 873                 arcmsr_srb_complete(srb, 1);
 874                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 875                                  acb->pci_unit, target, lun, cmd, srb);
 876         }
 877         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 878 #ifdef ARCMSR_DEBUG1
 879         arcmsr_dump_data(acb);
 880 #endif
 881 }
 882
 883 /*
 884 **********************************************************************
 885 **********************************************************************
 886 */
 887 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 888 {
 889         int i=0;
 890         u_int32_t flag_srb;
 891         u_int16_t error;
 892
 893         switch (acb->adapter_type) {
 894         case ACB_ADAPTER_TYPE_A: {
 895                         u_int32_t outbound_intstatus;
 896
 897                         /*clear and abort all outbound posted Q*/
 898                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 899                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 900                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 901                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 902                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 903                         }
 904                 }
 905                 break;
 906         case ACB_ADAPTER_TYPE_B: {
 907                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 908
 909                         /*clear all outbound posted Q*/
 910                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 911                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 912                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 913                                         phbbmu->done_qbuffer[i] = 0;
 914                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 915                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 916                                 }
 917                                 phbbmu->post_qbuffer[i] = 0;
 918                         }/*drain reply FIFO*/
 919                         phbbmu->doneq_index = 0;
 920                         phbbmu->postq_index = 0;
 921                 }
 922                 break;
 923         case ACB_ADAPTER_TYPE_C: {
 924
 925                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 926                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 927                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 928                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 929                         }
 930                 }
 931                 break;
 932         case ACB_ADAPTER_TYPE_D: {
 933                         arcmsr_hbd_postqueue_isr(acb);
 934                 }
 935                 break;
 936         }
 937 }
 938 /*
 939 ****************************************************************************
 940 ****************************************************************************
 941 */
 942 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 943 {
 944         struct CommandControlBlock *srb;
 945         u_int32_t intmask_org;
 946         u_int32_t i=0;
 947
 948         if(acb->srboutstandingcount>0) {
 949                 /* disable all outbound interrupt */
 950                 intmask_org = arcmsr_disable_allintr(acb);
 951                 /*clear and abort all outbound posted Q*/
 952                 arcmsr_done4abort_postqueue(acb);
 953                 /* talk to iop 331 outstanding command aborted*/
 954                 arcmsr_abort_allcmd(acb);
 955                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 956                         srb = acb->psrb_pool[i];
 957                         if(srb->srb_state == ARCMSR_SRB_START) {
 958                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 959                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 960                                 arcmsr_srb_complete(srb, 1);
 961                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
 962                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 963                                                 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 964                         }
 965                 }
 966                 /* enable all outbound interrupt */
 967                 arcmsr_enable_allintr(acb, intmask_org);
 968         }
 969         acb->srboutstandingcount = 0;
 970         acb->workingsrb_doneindex = 0;
 971         acb->workingsrb_startindex = 0;
 972         acb->pktRequestCount = 0;
 973         acb->pktReturnCount = 0;
 974 }
 975 /*
 976 **********************************************************************
 977 **********************************************************************
 978 */
 979 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 980                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 981 {
 982         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
 983         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
 984         u_int32_t address_lo, address_hi;
 985         union ccb *pccb = srb->pccb;
 986         struct ccb_scsiio *pcsio = &pccb->csio;
 987         u_int32_t arccdbsize = 0x30;
 988
 989         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
 990         arcmsr_cdb->Bus = 0;
 991         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
 992         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
 993         arcmsr_cdb->Function = 1;
 994         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
 995         bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
 996         if(nseg != 0) {
 997                 struct AdapterControlBlock *acb = srb->acb;
 998                 bus_dmasync_op_t op;
 999                 u_int32_t length, i, cdb_sgcount = 0;
1000
1001                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1002                         op = BUS_DMASYNC_PREREAD;
1003                 } else {
1004                         op = BUS_DMASYNC_PREWRITE;
1005                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1006                         srb->srb_flags |= SRB_FLAG_WRITE;
1007                 }
1008                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1009                 for(i=0; i < nseg; i++) {
1010                         /* Get the physical address of the current data pointer */
1011                         length = arcmsr_htole32(dm_segs[i].ds_len);
1012                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1013                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1014                         if(address_hi == 0) {
1015                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1016                                 pdma_sg->address = address_lo;
1017                                 pdma_sg->length = length;
1018                                 psge += sizeof(struct SG32ENTRY);
1019                                 arccdbsize += sizeof(struct SG32ENTRY);
1020                         } else {
1021                                 u_int32_t sg64s_size = 0, tmplength = length;
1022
1023                                 while(1) {
1024                                         u_int64_t span4G, length0;
1025                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1026
1027                                         span4G = (u_int64_t)address_lo + tmplength;
1028                                         pdma_sg->addresshigh = address_hi;
1029                                         pdma_sg->address = address_lo;
1030                                         if(span4G > 0x100000000) {
1031                                                 /*see if cross 4G boundary*/
1032                                                 length0 = 0x100000000-address_lo;
1033                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1034                                                 address_hi = address_hi+1;
1035                                                 address_lo = 0;
1036                                                 tmplength = tmplength - (u_int32_t)length0;
1037                                                 sg64s_size += sizeof(struct SG64ENTRY);
1038                                                 psge += sizeof(struct SG64ENTRY);
1039                                                 cdb_sgcount++;
1040                                         } else {
1041                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1042                                                 sg64s_size += sizeof(struct SG64ENTRY);
1043                                                 psge += sizeof(struct SG64ENTRY);
1044                                                 break;
1045                                         }
1046                                 }
1047                                 arccdbsize += sg64s_size;
1048                         }
1049                         cdb_sgcount++;
1050                 }
1051                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1052                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1053                 if( arccdbsize > 256) {
1054                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1055                 }
1056         } else {
1057                 arcmsr_cdb->DataLength = 0;
1058         }
1059     srb->arc_cdb_size = arccdbsize;
1060     arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1061 }
1062 /*
1063 **************************************************************************
1064 **************************************************************************
1065 */
1066 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1067 {
1068         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1069         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1070
1071         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1072         atomic_add_int(&acb->srboutstandingcount, 1);
1073         srb->srb_state = ARCMSR_SRB_START;
1074
1075         switch (acb->adapter_type) {
1076         case ACB_ADAPTER_TYPE_A: {
1077                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1078                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1079                         } else {
1080                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1081                         }
1082                 }
1083                 break;
1084         case ACB_ADAPTER_TYPE_B: {
1085                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1086                         int ending_index, index;
1087
1088                         index = phbbmu->postq_index;
1089                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1090                         phbbmu->post_qbuffer[ending_index] = 0;
1091                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1092                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1093                         } else {
1094                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1095                         }
1096                         index++;
1097                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1098                         phbbmu->postq_index = index;
1099                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1100                 }
1101                 break;
1102     case ACB_ADAPTER_TYPE_C: {
1103             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1104
1105             arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1106             ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1107                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1108             if(cdb_phyaddr_hi32)
1109             {
1110                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1111                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1112             }
1113             else
1114             {
1115                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1116             }
1117         }
1118         break;
1119         case ACB_ADAPTER_TYPE_D: {
1120                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1121                         u_int16_t index_stripped;
1122                         u_int16_t postq_index;
1123                         struct InBound_SRB *pinbound_srb;
1124
1125                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1126                         postq_index = phbdmu->postq_index;
1127                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1128                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1129                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1130                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1131                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1132                         if (postq_index & 0x4000) {
1133                                 index_stripped = postq_index & 0xFF;
1134                                 index_stripped += 1;
1135                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1136                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1137                         } else {
1138                                 index_stripped = postq_index;
1139                                 index_stripped += 1;
1140                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1141                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1142                         }
1143                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1144                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1145                 }
1146                 break;
1147         }
1148 }
1149 /*
1150 ************************************************************************
1151 ************************************************************************
1152 */
1153 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1154 {
1155         struct QBUFFER *qbuffer=NULL;
1156
1157         switch (acb->adapter_type) {
1158         case ACB_ADAPTER_TYPE_A: {
1159                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1160
1161                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1162                 }
1163                 break;
1164         case ACB_ADAPTER_TYPE_B: {
1165                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1166
1167                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1168                 }
1169                 break;
1170         case ACB_ADAPTER_TYPE_C: {
1171                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1172
1173                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1174                 }
1175                 break;
1176         case ACB_ADAPTER_TYPE_D: {
1177                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1178
1179                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1180                 }
1181                 break;
1182         }
1183         return(qbuffer);
1184 }
1185 /*
1186 ************************************************************************
1187 ************************************************************************
1188 */
1189 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1190 {
1191         struct QBUFFER *qbuffer = NULL;
1192
1193         switch (acb->adapter_type) {
1194         case ACB_ADAPTER_TYPE_A: {
1195                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1196
1197                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1198                 }
1199                 break;
1200         case ACB_ADAPTER_TYPE_B: {
1201                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1202
1203                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1204                 }
1205                 break;
1206         case ACB_ADAPTER_TYPE_C: {
1207                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1208
1209                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1210                 }
1211                 break;
1212         case ACB_ADAPTER_TYPE_D: {
1213                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1214
1215                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1216                 }
1217                 break;
1218         }
1219         return(qbuffer);
1220 }
1221 /*
1222 **************************************************************************
1223 **************************************************************************
1224 */
1225 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1226 {
1227         switch (acb->adapter_type) {
1228         case ACB_ADAPTER_TYPE_A: {
1229                         /* let IOP know data has been read */
1230                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1231                 }
1232                 break;
1233         case ACB_ADAPTER_TYPE_B: {
1234                         /* let IOP know data has been read */
1235                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1236                 }
1237                 break;
1238         case ACB_ADAPTER_TYPE_C: {
1239                         /* let IOP know data has been read */
1240                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1241                 }
1242                 break;
1243         case ACB_ADAPTER_TYPE_D: {
1244                         /* let IOP know data has been read */
1245                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1246                 }
1247                 break;
1248         }
1249 }
1250 /*
1251 **************************************************************************
1252 **************************************************************************
1253 */
1254 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1255 {
1256         switch (acb->adapter_type) {
1257         case ACB_ADAPTER_TYPE_A: {
1258                         /*
1259                         ** push inbound doorbell tell iop, driver data write ok
1260                         ** and wait reply on next hwinterrupt for next Qbuffer post
1261                         */
1262                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1263                 }
1264                 break;
1265         case ACB_ADAPTER_TYPE_B: {
1266                         /*
1267                         ** push inbound doorbell tell iop, driver data write ok
1268                         ** and wait reply on next hwinterrupt for next Qbuffer post
1269                         */
1270                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1271                 }
1272                 break;
1273         case ACB_ADAPTER_TYPE_C: {
1274                         /*
1275                         ** push inbound doorbell tell iop, driver data write ok
1276                         ** and wait reply on next hwinterrupt for next Qbuffer post
1277                         */
1278                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1279                 }
1280                 break;
1281         case ACB_ADAPTER_TYPE_D: {
1282                         /*
1283                         ** push inbound doorbell tell iop, driver data write ok
1284                         ** and wait reply on next hwinterrupt for next Qbuffer post
1285                         */
1286                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1287                 }
1288                 break;
1289         }
1290 }
1291 /*
1292 ************************************************************************
1293 ************************************************************************
1294 */
1295 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1296 {
1297         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1298         CHIP_REG_WRITE32(HBA_MessageUnit,
1299         0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1300         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1301                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1302                         , acb->pci_unit);
1303         }
1304 }
1305 /*
1306 ************************************************************************
1307 ************************************************************************
1308 */
1309 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1310 {
1311         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1312         CHIP_REG_WRITE32(HBB_DOORBELL,
1313         0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1314         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1315                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1316                         , acb->pci_unit);
1317         }
1318 }
1319 /*
1320 ************************************************************************
1321 ************************************************************************
1322 */
1323 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1324 {
1325         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1326         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1327         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1328         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1329                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1330         }
1331 }
1332 /*
1333 ************************************************************************
1334 ************************************************************************
1335 */
1336 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1337 {
1338         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1339         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1340         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1341                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1342         }
1343 }
1344 /*
1345 ************************************************************************
1346 ************************************************************************
1347 */
1348 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1349 {
1350         switch (acb->adapter_type) {
1351         case ACB_ADAPTER_TYPE_A: {
1352                         arcmsr_stop_hba_bgrb(acb);
1353                 }
1354                 break;
1355         case ACB_ADAPTER_TYPE_B: {
1356                         arcmsr_stop_hbb_bgrb(acb);
1357                 }
1358                 break;
1359         case ACB_ADAPTER_TYPE_C: {
1360                         arcmsr_stop_hbc_bgrb(acb);
1361                 }
1362                 break;
1363         case ACB_ADAPTER_TYPE_D: {
1364                         arcmsr_stop_hbd_bgrb(acb);
1365                 }
1366                 break;
1367         }
1368 }
1369 /*
1370 ************************************************************************
1371 ************************************************************************
1372 */
1373 static void arcmsr_poll(struct cam_sim *psim)
1374 {
1375         struct AdapterControlBlock *acb;
1376         int     mutex;
1377
1378         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1379         mutex = mtx_owned(&acb->isr_lock);
1380         if( mutex == 0 )
1381                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1382         arcmsr_interrupt(acb);
1383         if( mutex == 0 )
1384                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1385 }
1386 /*
1387 **************************************************************************
1388 **************************************************************************
1389 */
1390 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1391     struct QBUFFER *prbuffer) {
1392
1393         u_int8_t *pQbuffer;
1394         u_int8_t *buf1 = 0;
1395         u_int32_t *iop_data, *buf2 = 0;
1396         u_int32_t iop_len, data_len;
1397
1398         iop_data = (u_int32_t *)prbuffer->data;
1399         iop_len = (u_int32_t)prbuffer->data_len;
1400         if ( iop_len > 0 )
1401         {
1402                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1403                 buf2 = (u_int32_t *)buf1;
1404                 if( buf1 == NULL)
1405                         return (0);
1406                 data_len = iop_len;
1407                 while(data_len >= 4)
1408                 {
1409                         *buf2++ = *iop_data++;
1410                         data_len -= 4;
1411                 }
1412                 if(data_len)
1413                         *buf2 = *iop_data;
1414                 buf2 = (u_int32_t *)buf1;
1415         }
1416         while (iop_len > 0) {
1417                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1418                 *pQbuffer = *buf1;
1419                 acb->rqbuf_lastindex++;
1420                 /* if last, index number set it to 0 */
1421                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1422                 buf1++;
1423                 iop_len--;
1424         }
1425         if(buf2)
1426                 free( (u_int8_t *)buf2, M_DEVBUF);
1427         /* let IOP know data has been read */
1428         arcmsr_iop_message_read(acb);
1429         return (1);
1430 }
1431 /*
1432 **************************************************************************
1433 **************************************************************************
1434 */
1435 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1436     struct QBUFFER *prbuffer) {
1437
1438         u_int8_t *pQbuffer;
1439         u_int8_t *iop_data;
1440         u_int32_t iop_len;
1441
1442         if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1443                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1444         }
1445         iop_data = (u_int8_t *)prbuffer->data;
1446         iop_len = (u_int32_t)prbuffer->data_len;
1447         while (iop_len > 0) {
1448                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1449                 *pQbuffer = *iop_data;
1450                 acb->rqbuf_lastindex++;
1451                 /* if last, index number set it to 0 */
1452                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1453                 iop_data++;
1454                 iop_len--;
1455         }
1456         /* let IOP know data has been read */
1457         arcmsr_iop_message_read(acb);
1458         return (1);
1459 }
1460 /*
1461 **************************************************************************
1462 **************************************************************************
1463 */
1464 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1465 {
1466         struct QBUFFER *prbuffer;
1467         int my_empty_len;
1468
1469         /*check this iop data if overflow my rqbuffer*/
1470         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1471         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1472         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1473             (ARCMSR_MAX_QBUFFER-1);
1474         if(my_empty_len >= prbuffer->data_len) {
1475                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1476                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1477         } else {
1478                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1479         }
1480         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1481 }
1482 /*
1483 **********************************************************************
1484 **********************************************************************
1485 */
1486 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1487 {
1488         u_int8_t *pQbuffer;
1489         struct QBUFFER *pwbuffer;
1490         u_int8_t *buf1 = 0;
1491         u_int32_t *iop_data, *buf2 = 0;
1492         u_int32_t allxfer_len = 0, data_len;
1493
1494         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1495                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1496                 buf2 = (u_int32_t *)buf1;
1497                 if( buf1 == NULL)
1498                         return;
1499
1500                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1501                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1502                 iop_data = (u_int32_t *)pwbuffer->data;
1503                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1504                         && (allxfer_len < 124)) {
1505                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1506                         *buf1 = *pQbuffer;
1507                         acb->wqbuf_firstindex++;
1508                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1509                         buf1++;
1510                         allxfer_len++;
1511                 }
1512                 pwbuffer->data_len = allxfer_len;
1513                 data_len = allxfer_len;
1514                 buf1 = (u_int8_t *)buf2;
1515                 while(data_len >= 4)
1516                 {
1517                         *iop_data++ = *buf2++;
1518                         data_len -= 4;
1519                 }
1520                 if(data_len)
1521                         *iop_data = *buf2;
1522                 free( buf1, M_DEVBUF);
1523                 arcmsr_iop_message_wrote(acb);
1524         }
1525 }
1526 /*
1527 **********************************************************************
1528 **********************************************************************
1529 */
1530 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1531 {
1532         u_int8_t *pQbuffer;
1533         struct QBUFFER *pwbuffer;
1534         u_int8_t *iop_data;
1535         int32_t allxfer_len=0;
1536
1537         if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1538                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1539                 return;
1540         }
1541         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1542                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1543                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1544                 iop_data = (u_int8_t *)pwbuffer->data;
1545                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1546                         && (allxfer_len < 124)) {
1547                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1548                         *iop_data = *pQbuffer;
1549                         acb->wqbuf_firstindex++;
1550                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1551                         iop_data++;
1552                         allxfer_len++;
1553                 }
1554                 pwbuffer->data_len = allxfer_len;
1555                 arcmsr_iop_message_wrote(acb);
1556         }
1557 }
1558 /*
1559 **************************************************************************
1560 **************************************************************************
1561 */
1562 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1563 {
1564         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1565         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1566         /*
1567         *****************************************************************
1568         **   check if there are any mail packages from user space program
1569         **   in my post bag, now is the time to send them into Areca's firmware
1570         *****************************************************************
1571         */
1572         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1573                 arcmsr_Write_data_2iop_wqbuffer(acb);
1574         }
1575         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1576                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1577         }
1578         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1579 }
1580 /*
1581 **************************************************************************
1582 **************************************************************************
1583 */
1584 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1585 {
1586 /*
1587         if (ccb->ccb_h.status != CAM_REQ_CMP)
1588                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1589                     "failure status=%x\n", ccb->ccb_h.target_id,
1590                     ccb->ccb_h.target_lun, ccb->ccb_h.status);
1591         else
1592                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1593 */
1594         xpt_free_path(ccb->ccb_h.path);
1595         xpt_free_ccb(ccb);
1596 }
1597
1598 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1599 {
1600         struct cam_path     *path;
1601         union ccb           *ccb;
1602
1603         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1604                 return;
1605         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1606         {
1607                 xpt_free_ccb(ccb);
1608                 return;
1609         }
1610 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1611         bzero(ccb, sizeof(union ccb));
1612         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1613         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1614         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1615         ccb->crcn.flags = CAM_FLAG_NONE;
1616         xpt_action(ccb);
1617 }
1618
1619
1620 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1621 {
1622         struct CommandControlBlock *srb;
1623         u_int32_t intmask_org;
1624         int i;
1625
1626         /* disable all outbound interrupts */
1627         intmask_org = arcmsr_disable_allintr(acb);
1628         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1629         {
1630                 srb = acb->psrb_pool[i];
1631                 if (srb->srb_state == ARCMSR_SRB_START)
1632                 {
1633                 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1634             {
1635                         srb->srb_state = ARCMSR_SRB_ABORTED;
1636                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1637                         arcmsr_srb_complete(srb, 1);
1638                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1639                 }
1640                 }
1641         }
1642         /* enable outbound Post Queue, outbound doorbell Interrupt */
1643         arcmsr_enable_allintr(acb, intmask_org);
1644 }
1645 /*
1646 **************************************************************************
1647 **************************************************************************
1648 */
1649 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1650         u_int32_t       devicemap;
1651         u_int32_t       target, lun;
1652     u_int32_t   deviceMapCurrent[4]={0};
1653     u_int8_t    *pDevMap;
1654
1655         switch (acb->adapter_type) {
1656         case ACB_ADAPTER_TYPE_A:
1657                         devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1658                         for (target = 0; target < 4; target++)
1659                         {
1660                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1661                 devicemap += 4;
1662                         }
1663                         break;
1664
1665         case ACB_ADAPTER_TYPE_B:
1666                         devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1667                         for (target = 0; target < 4; target++)
1668                         {
1669                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1670                 devicemap += 4;
1671                         }
1672                         break;
1673
1674         case ACB_ADAPTER_TYPE_C:
1675                         devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1676                         for (target = 0; target < 4; target++)
1677                         {
1678                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1679                 devicemap += 4;
1680                         }
1681                         break;
1682         case ACB_ADAPTER_TYPE_D:
1683                         devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1684                         for (target = 0; target < 4; target++)
1685                         {
1686                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1687                 devicemap += 4;
1688                         }
1689                         break;
1690         }
1691
1692                 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1693                 {
1694                         acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1695                 }
1696                 /*
1697                 ** adapter posted CONFIG message
1698                 ** copy the new map, note if there are differences with the current map
1699                 */
1700                 pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1701                 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1702                 {
1703                         if (*pDevMap != acb->device_map[target])
1704                         {
1705                 u_int8_t difference, bit_check;
1706
1707                 difference = *pDevMap ^ acb->device_map[target];
1708                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1709                 {
1710                     bit_check = (1 << lun);                                             /*check bit from 0....31*/
1711                     if(difference & bit_check)
1712                     {
1713                         if(acb->device_map[target] & bit_check)
1714                         {/* unit departed */
1715                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1716                                                         arcmsr_abort_dr_ccbs(acb, target, lun);
1717                                 arcmsr_rescan_lun(acb, target, lun);
1718                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1719                         }
1720                         else
1721                         {/* unit arrived */
1722                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1723                                 arcmsr_rescan_lun(acb, target, lun);
1724                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1725                         }
1726                     }
1727                 }
1728 /*                              printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1729                                 acb->device_map[target] = *pDevMap;
1730                         }
1731                         pDevMap++;
1732                 }
1733 }
1734 /*
1735 **************************************************************************
1736 **************************************************************************
1737 */
1738 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1739         u_int32_t outbound_message;
1740
1741         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1742         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1743         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1744                 arcmsr_dr_handle( acb );
1745 }
1746 /*
1747 **************************************************************************
1748 **************************************************************************
1749 */
1750 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1751         u_int32_t outbound_message;
1752
1753         /* clear interrupts */
1754         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1755         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1756         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1757                 arcmsr_dr_handle( acb );
1758 }
1759 /*
1760 **************************************************************************
1761 **************************************************************************
1762 */
1763 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1764         u_int32_t outbound_message;
1765
1766         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1767         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1768         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1769                 arcmsr_dr_handle( acb );
1770 }
1771 /*
1772 **************************************************************************
1773 **************************************************************************
1774 */
1775 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1776         u_int32_t outbound_message;
1777
1778         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1779         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1780         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1781                 arcmsr_dr_handle( acb );
1782 }
1783 /*
1784 **************************************************************************
1785 **************************************************************************
1786 */
1787 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1788 {
1789         u_int32_t doorbell_status;
1790
1791         /*
1792         *******************************************************************
1793         **  Maybe here we need to check wrqbuffer_lock is lock or not
1794         **  DOORBELL: din! don!
1795         **  check if there are any mail need to pack from firmware
1796         *******************************************************************
1797         */
1798         doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1799         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1800         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1801                 arcmsr_iop2drv_data_wrote_handle(acb);
1802         }
1803         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1804                 arcmsr_iop2drv_data_read_handle(acb);
1805         }
1806 }
1807 /*
1808 **************************************************************************
1809 **************************************************************************
1810 */
1811 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1812 {
1813         u_int32_t doorbell_status;
1814
1815         /*
1816         *******************************************************************
1817         **  Maybe here we need to check wrqbuffer_lock is lock or not
1818         **  DOORBELL: din! don!
1819         **  check if there are any mail need to pack from firmware
1820         *******************************************************************
1821         */
1822         doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1823         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1824         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1825                 arcmsr_iop2drv_data_wrote_handle(acb);
1826         }
1827         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1828                 arcmsr_iop2drv_data_read_handle(acb);
1829         }
1830         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1831                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1832         }
1833 }
1834 /*
1835 **************************************************************************
1836 **************************************************************************
1837 */
1838 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1839 {
1840         u_int32_t doorbell_status;
1841
1842         /*
1843         *******************************************************************
1844         **  Maybe here we need to check wrqbuffer_lock is lock or not
1845         **  DOORBELL: din! don!
1846         **  check if there are any mail need to pack from firmware
1847         *******************************************************************
1848         */
1849         doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1850         if(doorbell_status)
1851                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1852         while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1853                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1854                         arcmsr_iop2drv_data_wrote_handle(acb);
1855                 }
1856                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1857                         arcmsr_iop2drv_data_read_handle(acb);
1858                 }
1859                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1860                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1861                 }
1862                 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1863                 if(doorbell_status)
1864                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1865         }
1866 }
1867 /*
1868 **************************************************************************
1869 **************************************************************************
1870 */
1871 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1872 {
1873         u_int32_t flag_srb;
1874         u_int16_t error;
1875
1876         /*
1877         *****************************************************************************
1878         **               areca cdb command done
1879         *****************************************************************************
1880         */
1881         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1882                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1883         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1884                 0, outbound_queueport)) != 0xFFFFFFFF) {
1885                 /* check if command done with no error*/
1886         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1887                 arcmsr_drain_donequeue(acb, flag_srb, error);
1888         }       /*drain reply FIFO*/
1889 }
1890 /*
1891 **************************************************************************
1892 **************************************************************************
1893 */
1894 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1895 {
1896         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1897         u_int32_t flag_srb;
1898         int index;
1899         u_int16_t error;
1900
1901         /*
1902         *****************************************************************************
1903         **               areca cdb command done
1904         *****************************************************************************
1905         */
1906         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1907                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1908         index = phbbmu->doneq_index;
1909         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1910                 phbbmu->done_qbuffer[index] = 0;
1911                 index++;
1912                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1913                 phbbmu->doneq_index = index;
1914                 /* check if command done with no error*/
1915         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1916                 arcmsr_drain_donequeue(acb, flag_srb, error);
1917         }       /*drain reply FIFO*/
1918 }
1919 /*
1920 **************************************************************************
1921 **************************************************************************
1922 */
1923 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1924 {
1925         u_int32_t flag_srb,throttling = 0;
1926         u_int16_t error;
1927
1928         /*
1929         *****************************************************************************
1930         **               areca cdb command done
1931         *****************************************************************************
1932         */
1933         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1934         do {
1935                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1936                 /* check if command done with no error*/
1937                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1938                 arcmsr_drain_donequeue(acb, flag_srb, error);
1939                 throttling++;
1940                 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1941                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1942                         throttling = 0;
1943                 }
1944         } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
1945 }
1946 /*
1947 **********************************************************************
1948 **
1949 **********************************************************************
1950 */
1951 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1952 {
1953         uint16_t doneq_index, index_stripped;
1954
1955         doneq_index = phbdmu->doneq_index;
1956         if (doneq_index & 0x4000) {
1957                 index_stripped = doneq_index & 0xFF;
1958                 index_stripped += 1;
1959                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1960                 phbdmu->doneq_index = index_stripped ?
1961                     (index_stripped | 0x4000) : index_stripped;
1962         } else {
1963                 index_stripped = doneq_index;
1964                 index_stripped += 1;
1965                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1966                 phbdmu->doneq_index = index_stripped ?
1967                     index_stripped : (index_stripped | 0x4000);
1968         }
1969         return (phbdmu->doneq_index);
1970 }
1971 /*
1972 **************************************************************************
1973 **************************************************************************
1974 */
1975 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1976 {
1977         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1978         u_int32_t outbound_write_pointer;
1979         u_int32_t addressLow;
1980         uint16_t doneq_index;
1981         u_int16_t error;
1982         /*
1983         *****************************************************************************
1984         **               areca cdb command done
1985         *****************************************************************************
1986         */
1987         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1988             ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
1989             return;
1990         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1991                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1992         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
1993         doneq_index = phbdmu->doneq_index;
1994         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
1995                 doneq_index = arcmsr_get_doneq_index(phbdmu);
1996                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
1997                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
1998                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
1999                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2000                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2001         }
2002         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2003         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2004 }
2005 /*
2006 **********************************************************************
2007 **********************************************************************
2008 */
2009 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2010 {
2011         u_int32_t outbound_intStatus;
2012         /*
2013         *********************************************
2014         **   check outbound intstatus
2015         *********************************************
2016         */
2017         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2018         if(!outbound_intStatus) {
2019                 /*it must be share irq*/
2020                 return;
2021         }
2022         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2023         /* MU doorbell interrupts*/
2024         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2025                 arcmsr_hba_doorbell_isr(acb);
2026         }
2027         /* MU post queue interrupts*/
2028         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2029                 arcmsr_hba_postqueue_isr(acb);
2030         }
2031         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2032                 arcmsr_hba_message_isr(acb);
2033         }
2034 }
2035 /*
2036 **********************************************************************
2037 **********************************************************************
2038 */
2039 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2040 {
2041         u_int32_t outbound_doorbell;
2042         /*
2043         *********************************************
2044         **   check outbound intstatus
2045         *********************************************
2046         */
2047         outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
2048         if(!outbound_doorbell) {
2049                 /*it must be share irq*/
2050                 return;
2051         }
2052         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2053         CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
2054         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2055         /* MU ioctl transfer doorbell interrupts*/
2056         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2057                 arcmsr_iop2drv_data_wrote_handle(acb);
2058         }
2059         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2060                 arcmsr_iop2drv_data_read_handle(acb);
2061         }
2062         /* MU post queue interrupts*/
2063         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2064                 arcmsr_hbb_postqueue_isr(acb);
2065         }
2066         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2067                 arcmsr_hbb_message_isr(acb);
2068         }
2069 }
2070 /*
2071 **********************************************************************
2072 **********************************************************************
2073 */
2074 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2075 {
2076         u_int32_t host_interrupt_status;
2077         /*
2078         *********************************************
2079         **   check outbound intstatus
2080         *********************************************
2081         */
2082         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2083                 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2084                 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2085         if(!host_interrupt_status) {
2086                 /*it must be share irq*/
2087                 return;
2088         }
2089         do {
2090                 /* MU doorbell interrupts*/
2091                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2092                         arcmsr_hbc_doorbell_isr(acb);
2093                 }
2094                 /* MU post queue interrupts*/
2095                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2096                         arcmsr_hbc_postqueue_isr(acb);
2097                 }
2098                 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2099         } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2100 }
2101 /*
2102 **********************************************************************
2103 **********************************************************************
2104 */
2105 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2106 {
2107         u_int32_t host_interrupt_status;
2108         u_int32_t intmask_org;
2109         /*
2110         *********************************************
2111         **   check outbound intstatus
2112         *********************************************
2113         */
2114         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2115         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2116                 /*it must be share irq*/
2117                 return;
2118         }
2119         /* disable outbound interrupt */
2120         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2121         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2122         /* MU doorbell interrupts*/
2123         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2124                 arcmsr_hbd_doorbell_isr(acb);
2125         }
2126         /* MU post queue interrupts*/
2127         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2128                 arcmsr_hbd_postqueue_isr(acb);
2129         }
2130         /* enable all outbound interrupt */
2131         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2132 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2133 }
2134 /*
2135 ******************************************************************************
2136 ******************************************************************************
2137 */
2138 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2139 {
2140         switch (acb->adapter_type) {
2141         case ACB_ADAPTER_TYPE_A:
2142                 arcmsr_handle_hba_isr(acb);
2143                 break;
2144         case ACB_ADAPTER_TYPE_B:
2145                 arcmsr_handle_hbb_isr(acb);
2146                 break;
2147         case ACB_ADAPTER_TYPE_C:
2148                 arcmsr_handle_hbc_isr(acb);
2149                 break;
2150         case ACB_ADAPTER_TYPE_D:
2151                 arcmsr_handle_hbd_isr(acb);
2152                 break;
2153         default:
2154                 printf("arcmsr%d: interrupt service,"
2155                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2156                 break;
2157         }
2158 }
2159 /*
2160 **********************************************************************
2161 **********************************************************************
2162 */
2163 static void arcmsr_intr_handler(void *arg)
2164 {
2165         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2166
2167         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2168         arcmsr_interrupt(acb);
2169         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2170 }
2171 /*
2172 ******************************************************************************
2173 ******************************************************************************
2174 */
2175 static void     arcmsr_polling_devmap(void *arg)
2176 {
2177         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2178         switch (acb->adapter_type) {
2179         case ACB_ADAPTER_TYPE_A:
2180                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2181                 break;
2182
2183         case ACB_ADAPTER_TYPE_B:
2184                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2185                 break;
2186
2187         case ACB_ADAPTER_TYPE_C:
2188                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2189                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2190                 break;
2191
2192         case ACB_ADAPTER_TYPE_D:
2193                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2194                 break;
2195         }
2196
2197         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2198         {
2199                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2200         }
2201 }
2202
2203 /*
2204 *******************************************************************************
2205 **
2206 *******************************************************************************
2207 */
2208 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2209 {
2210         u_int32_t intmask_org;
2211
2212         if(acb != NULL) {
2213                 /* stop adapter background rebuild */
2214                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2215                         intmask_org = arcmsr_disable_allintr(acb);
2216                         arcmsr_stop_adapter_bgrb(acb);
2217                         arcmsr_flush_adapter_cache(acb);
2218                         arcmsr_enable_allintr(acb, intmask_org);
2219                 }
2220         }
2221 }
2222 /*
2223 ***********************************************************************
2224 **
2225 ************************************************************************
2226 */
2227 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2228 {
2229         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2230         u_int32_t retvalue = EINVAL;
2231
2232         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2233         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2234                 return retvalue;
2235         }
2236         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2237         switch(ioctl_cmd) {
2238         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2239                         u_int8_t *pQbuffer;
2240                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2241                         u_int32_t allxfer_len=0;
2242
2243                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2244                                 && (allxfer_len < 1031)) {
2245                                 /*copy READ QBUFFER to srb*/
2246                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2247                                 *ptmpQbuffer = *pQbuffer;
2248                                 acb->rqbuf_firstindex++;
2249                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2250                                 /*if last index number set it to 0 */
2251                                 ptmpQbuffer++;
2252                                 allxfer_len++;
2253                         }
2254                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2255                                 struct QBUFFER *prbuffer;
2256
2257                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2258                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2259                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2260                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2261                         }
2262                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2263                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2264                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2265                 }
2266                 break;
2267         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2268                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2269                         u_int8_t *pQbuffer;
2270                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2271
2272                         user_len = pcmdmessagefld->cmdmessage.Length;
2273                         /*check if data xfer length of this request will overflow my array qbuffer */
2274                         wqbuf_lastindex = acb->wqbuf_lastindex;
2275                         wqbuf_firstindex = acb->wqbuf_firstindex;
2276                         if(wqbuf_lastindex != wqbuf_firstindex) {
2277                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2278                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2279                         } else {
2280                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2281                                     (ARCMSR_MAX_QBUFFER - 1);
2282                                 if(my_empty_len >= user_len) {
2283                                         while(user_len > 0) {
2284                                                 /*copy srb data to wqbuffer*/
2285                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2286                                                 *pQbuffer = *ptmpuserbuffer;
2287                                                 acb->wqbuf_lastindex++;
2288                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2289                                                 /*if last index number set it to 0 */
2290                                                 ptmpuserbuffer++;
2291                                                 user_len--;
2292                                         }
2293                                         /*post fist Qbuffer*/
2294                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2295                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2296                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2297                                         }
2298                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2299                                 } else {
2300                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2301                                 }
2302                         }
2303                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2304                 }
2305                 break;
2306         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2307                         u_int8_t *pQbuffer = acb->rqbuffer;
2308
2309                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2310                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2311                                 arcmsr_iop_message_read(acb);
2312                                 /*signature, let IOP know data has been readed */
2313                         }
2314                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2315                         acb->rqbuf_firstindex = 0;
2316                         acb->rqbuf_lastindex = 0;
2317                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2318                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2319                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2320                 }
2321                 break;
2322         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2323                 {
2324                         u_int8_t *pQbuffer = acb->wqbuffer;
2325
2326                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2327                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2328                 arcmsr_iop_message_read(acb);
2329                                 /*signature, let IOP know data has been readed */
2330                         }
2331                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2332                         acb->wqbuf_firstindex = 0;
2333                         acb->wqbuf_lastindex = 0;
2334                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2335                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2336                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2337                 }
2338                 break;
2339         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2340                         u_int8_t *pQbuffer;
2341
2342                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2343                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2344                 arcmsr_iop_message_read(acb);
2345                                 /*signature, let IOP know data has been readed */
2346                         }
2347                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2348                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2349                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2350                         acb->rqbuf_firstindex = 0;
2351                         acb->rqbuf_lastindex = 0;
2352                         acb->wqbuf_firstindex = 0;
2353                         acb->wqbuf_lastindex = 0;
2354                         pQbuffer = acb->rqbuffer;
2355                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2356                         pQbuffer = acb->wqbuffer;
2357                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2358                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2359                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2360                 }
2361                 break;
2362         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2363                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2364                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2365                 }
2366                 break;
2367         case ARCMSR_MESSAGE_SAY_HELLO: {
2368                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2369                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2370
2371                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2372                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2373                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2374                                 return ENOIOCTL;
2375                         }
2376                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2377                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2378                 }
2379                 break;
2380         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2381                         arcmsr_iop_parking(acb);
2382                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2383                 }
2384                 break;
2385         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2386                         arcmsr_flush_adapter_cache(acb);
2387                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2388                 }
2389                 break;
2390         }
2391         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2392         return (retvalue);
2393 }
2394 /*
2395 **************************************************************************
2396 **************************************************************************
2397 */
2398 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2399 {
2400         struct AdapterControlBlock      *acb;
2401
2402         acb = srb->acb;
2403         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2404         srb->srb_state = ARCMSR_SRB_DONE;
2405         srb->srb_flags = 0;
2406         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2407         acb->workingsrb_doneindex++;
2408         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2409         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2410 }
2411 /*
2412 **************************************************************************
2413 **************************************************************************
2414 */
2415 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2416 {
2417         struct CommandControlBlock *srb = NULL;
2418         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2419
2420         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2421         workingsrb_doneindex = acb->workingsrb_doneindex;
2422         workingsrb_startindex = acb->workingsrb_startindex;
2423         srb = acb->srbworkingQ[workingsrb_startindex];
2424         workingsrb_startindex++;
2425         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2426         if(workingsrb_doneindex != workingsrb_startindex) {
2427                 acb->workingsrb_startindex = workingsrb_startindex;
2428         } else {
2429                 srb = NULL;
2430         }
2431         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2432         return(srb);
2433 }
2434 /*
2435 **************************************************************************
2436 **************************************************************************
2437 */
2438 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2439 {
2440         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2441         int retvalue = 0, transfer_len = 0;
2442         char *buffer;
2443         u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
2444                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
2445                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
2446                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
2447                                         /* 4 bytes: Areca io control code */
2448         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2449                 buffer = pccb->csio.data_ptr;
2450                 transfer_len = pccb->csio.dxfer_len;
2451         } else {
2452                 retvalue = ARCMSR_MESSAGE_FAIL;
2453                 goto message_out;
2454         }
2455         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2456                 retvalue = ARCMSR_MESSAGE_FAIL;
2457                 goto message_out;
2458         }
2459         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2460         switch(controlcode) {
2461         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2462                         u_int8_t *pQbuffer;
2463                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2464                         int32_t allxfer_len = 0;
2465
2466                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2467                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2468                                 && (allxfer_len < 1031)) {
2469                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2470                                 *ptmpQbuffer = *pQbuffer;
2471                                 acb->rqbuf_firstindex++;
2472                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2473                                 ptmpQbuffer++;
2474                                 allxfer_len++;
2475                         }
2476                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2477                                 struct QBUFFER  *prbuffer;
2478
2479                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2480                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2481                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2482                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2483                         }
2484                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2485                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2486                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2487                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2488                 }
2489                 break;
2490         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2491                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2492                         u_int8_t *pQbuffer;
2493                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2494
2495                         user_len = pcmdmessagefld->cmdmessage.Length;
2496                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2497                         wqbuf_lastindex = acb->wqbuf_lastindex;
2498                         wqbuf_firstindex = acb->wqbuf_firstindex;
2499                         if (wqbuf_lastindex != wqbuf_firstindex) {
2500                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2501                                 /* has error report sensedata */
2502                             if(pccb->csio.sense_len) {
2503                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2504                                 /* Valid,ErrorCode */
2505                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2506                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2507                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2508                                 /* AdditionalSenseLength */
2509                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2510                                 /* AdditionalSenseCode */
2511                                 }
2512                                 retvalue = ARCMSR_MESSAGE_FAIL;
2513                         } else {
2514                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2515                                                 &(ARCMSR_MAX_QBUFFER - 1);
2516                                 if (my_empty_len >= user_len) {
2517                                         while (user_len > 0) {
2518                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2519                                                 *pQbuffer = *ptmpuserbuffer;
2520                                                 acb->wqbuf_lastindex++;
2521                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2522                                                 ptmpuserbuffer++;
2523                                                 user_len--;
2524                                         }
2525                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2526                                                 acb->acb_flags &=
2527                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2528                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2529                                         }
2530                                 } else {
2531                                         /* has error report sensedata */
2532                                         if(pccb->csio.sense_len) {
2533                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2534                                         /* Valid,ErrorCode */
2535                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2536                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2537                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2538                                         /* AdditionalSenseLength */
2539                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2540                                         /* AdditionalSenseCode */
2541                                         }
2542                                         retvalue = ARCMSR_MESSAGE_FAIL;
2543                                 }
2544                         }
2545                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2546                 }
2547                 break;
2548         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2549                         u_int8_t *pQbuffer = acb->rqbuffer;
2550
2551                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2552                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2553                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2554                                 arcmsr_iop_message_read(acb);
2555                         }
2556                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2557                         acb->rqbuf_firstindex = 0;
2558                         acb->rqbuf_lastindex = 0;
2559                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2560                         pcmdmessagefld->cmdmessage.ReturnCode =
2561                             ARCMSR_MESSAGE_RETURNCODE_OK;
2562                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2563                 }
2564                 break;
2565         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2566                         u_int8_t *pQbuffer = acb->wqbuffer;
2567
2568                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2569                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2570                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2571                                 arcmsr_iop_message_read(acb);
2572                         }
2573                         acb->acb_flags |=
2574                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2575                                         ACB_F_MESSAGE_WQBUFFER_READ);
2576                         acb->wqbuf_firstindex = 0;
2577                         acb->wqbuf_lastindex = 0;
2578                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2579                         pcmdmessagefld->cmdmessage.ReturnCode =
2580                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2581                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2582                 }
2583                 break;
2584         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2585                         u_int8_t *pQbuffer;
2586
2587                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2588                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2589                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2590                                 arcmsr_iop_message_read(acb);
2591                         }
2592                         acb->acb_flags |=
2593                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2594                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2595                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2596                         acb->rqbuf_firstindex = 0;
2597                         acb->rqbuf_lastindex = 0;
2598                         acb->wqbuf_firstindex = 0;
2599                         acb->wqbuf_lastindex = 0;
2600                         pQbuffer = acb->rqbuffer;
2601                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2602                         pQbuffer = acb->wqbuffer;
2603                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2604                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2605                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2606                 }
2607                 break;
2608         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2609                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2610                 }
2611                 break;
2612         case ARCMSR_MESSAGE_SAY_HELLO: {
2613                         int8_t *hello_string = "Hello! I am ARCMSR";
2614
2615                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2616                                 , (int16_t)strlen(hello_string));
2617                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2618                 }
2619                 break;
2620         case ARCMSR_MESSAGE_SAY_GOODBYE:
2621                 arcmsr_iop_parking(acb);
2622                 break;
2623         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2624                 arcmsr_flush_adapter_cache(acb);
2625                 break;
2626         default:
2627                 retvalue = ARCMSR_MESSAGE_FAIL;
2628         }
2629 message_out:
2630         return (retvalue);
2631 }
2632 /*
2633 *********************************************************************
2634 *********************************************************************
2635 */
2636 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2637 {
2638         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2639         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2640         union ccb *pccb;
2641         int target, lun;
2642
2643         pccb = srb->pccb;
2644         target = pccb->ccb_h.target_id;
2645         lun = pccb->ccb_h.target_lun;
2646         acb->pktRequestCount++;
2647         if(error != 0) {
2648                 if(error != EFBIG) {
2649                         printf("arcmsr%d: unexpected error %x"
2650                                 " returned from 'bus_dmamap_load' \n"
2651                                 , acb->pci_unit, error);
2652                 }
2653                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2654                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2655                 }
2656                 arcmsr_srb_complete(srb, 0);
2657                 return;
2658         }
2659         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2660                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2661                 arcmsr_srb_complete(srb, 0);
2662                 return;
2663         }
2664         if(acb->acb_flags & ACB_F_BUS_RESET) {
2665                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2666                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2667                 arcmsr_srb_complete(srb, 0);
2668                 return;
2669         }
2670         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2671                 u_int8_t block_cmd, cmd;
2672
2673                 cmd = pccb->csio.cdb_io.cdb_bytes[0];
2674                 block_cmd = cmd & 0x0f;
2675                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2676                         printf("arcmsr%d:block 'read/write' command "
2677                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2678                                 , acb->pci_unit, cmd, target, lun);
2679                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2680                         arcmsr_srb_complete(srb, 0);
2681                         return;
2682                 }
2683         }
2684         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2685                 if(nseg != 0) {
2686                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2687                 }
2688                 arcmsr_srb_complete(srb, 0);
2689                 return;
2690         }
2691         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2692                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2693                 {
2694                         xpt_freeze_simq(acb->psim, 1);
2695                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2696                 }
2697                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2698                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2699                 arcmsr_srb_complete(srb, 0);
2700                 return;
2701         }
2702         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2703         arcmsr_build_srb(srb, dm_segs, nseg);
2704         arcmsr_post_srb(acb, srb);
2705         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2706         {
2707                 arcmsr_callout_init(&srb->ccb_callout);
2708                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2709                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2710                     arcmsr_srb_timeout, srb, 0);
2711                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2712         }
2713 }
2714 /*
2715 *****************************************************************************************
2716 *****************************************************************************************
2717 */
2718 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2719 {
2720         struct CommandControlBlock *srb;
2721         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2722         u_int32_t intmask_org;
2723         int i = 0;
2724
2725         acb->num_aborts++;
2726         /*
2727         ***************************************************************************
2728         ** It is the upper layer do abort command this lock just prior to calling us.
2729         ** First determine if we currently own this command.
2730         ** Start by searching the device queue. If not found
2731         ** at all, and the system wanted us to just abort the
2732         ** command return success.
2733         ***************************************************************************
2734         */
2735         if(acb->srboutstandingcount != 0) {
2736                 /* disable all outbound interrupt */
2737                 intmask_org = arcmsr_disable_allintr(acb);
2738                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2739                         srb = acb->psrb_pool[i];
2740                         if(srb->srb_state == ARCMSR_SRB_START) {
2741                                 if(srb->pccb == abortccb) {
2742                                         srb->srb_state = ARCMSR_SRB_ABORTED;
2743                                         printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
2744                                                 "outstanding command \n"
2745                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2746                                                 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
2747                                         arcmsr_polling_srbdone(acb, srb);
2748                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
2749                                         arcmsr_enable_allintr(acb, intmask_org);
2750                                         return (TRUE);
2751                                 }
2752                         }
2753                 }
2754                 /* enable outbound Post Queue, outbound doorbell Interrupt */
2755                 arcmsr_enable_allintr(acb, intmask_org);
2756         }
2757         return(FALSE);
2758 }
2759 /*
2760 ****************************************************************************
2761 ****************************************************************************
2762 */
2763 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2764 {
2765         int retry = 0;
2766
2767         acb->num_resets++;
2768         acb->acb_flags |= ACB_F_BUS_RESET;
2769         while(acb->srboutstandingcount != 0 && retry < 400) {
2770                 arcmsr_interrupt(acb);
2771                 UDELAY(25000);
2772                 retry++;
2773         }
2774         arcmsr_iop_reset(acb);
2775         acb->acb_flags &= ~ACB_F_BUS_RESET;
2776 }
2777 /*
2778 **************************************************************************
2779 **************************************************************************
2780 */
2781 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2782                 union ccb *pccb)
2783 {
2784         if (pccb->ccb_h.target_lun) {
2785                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2786                 xpt_done(pccb);
2787                 return;
2788         }
2789         pccb->ccb_h.status |= CAM_REQ_CMP;
2790         switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2791         case INQUIRY: {
2792                 unsigned char inqdata[36];
2793                 char *buffer = pccb->csio.data_ptr;
2794
2795                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2796                 inqdata[1] = 0;                         /* rem media bit & Dev Type Modifier */
2797                 inqdata[2] = 0;                         /* ISO, ECMA, & ANSI versions */
2798                 inqdata[3] = 0;
2799                 inqdata[4] = 31;                        /* length of additional data */
2800                 inqdata[5] = 0;
2801                 inqdata[6] = 0;
2802                 inqdata[7] = 0;
2803                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
2804                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
2805                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2806                 memcpy(buffer, inqdata, sizeof(inqdata));
2807                 xpt_done(pccb);
2808         }
2809         break;
2810         case WRITE_BUFFER:
2811         case READ_BUFFER: {
2812                 if (arcmsr_iop_message_xfer(acb, pccb)) {
2813                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2814                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2815                 }
2816                 xpt_done(pccb);
2817         }
2818         break;
2819         default:
2820                 xpt_done(pccb);
2821         }
2822 }
2823 /*
2824 *********************************************************************
2825 *********************************************************************
2826 */
2827 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2828 {
2829         struct AdapterControlBlock *acb;
2830
2831         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2832         if(acb == NULL) {
2833                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2834                 xpt_done(pccb);
2835                 return;
2836         }
2837         switch (pccb->ccb_h.func_code) {
2838         case XPT_SCSI_IO: {
2839                         struct CommandControlBlock *srb;
2840                         int target = pccb->ccb_h.target_id;
2841                         int error;
2842
2843                         if(target == 16) {
2844                                 /* virtual device for iop message transfer */
2845                                 arcmsr_handle_virtual_command(acb, pccb);
2846                                 return;
2847                         }
2848                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2849                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2850                                 xpt_done(pccb);
2851                                 return;
2852                         }
2853                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2854                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2855                         srb->pccb = pccb;
2856                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
2857                                 , srb->dm_segs_dmamap
2858                                 , pccb
2859                                 , arcmsr_execute_srb, srb, /*flags*/0);
2860                         if(error == EINPROGRESS) {
2861                                 xpt_freeze_simq(acb->psim, 1);
2862                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2863                         }
2864                         break;
2865                 }
2866         case XPT_TARGET_IO: {
2867                         /* target mode not yet support vendor specific commands. */
2868                         pccb->ccb_h.status |= CAM_REQ_CMP;
2869                         xpt_done(pccb);
2870                         break;
2871                 }
2872         case XPT_PATH_INQ: {
2873                         struct ccb_pathinq *cpi = &pccb->cpi;
2874
2875                         cpi->version_num = 1;
2876                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2877                         cpi->target_sprt = 0;
2878                         cpi->hba_misc = 0;
2879                         cpi->hba_eng_cnt = 0;
2880                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
2881                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
2882                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2883                         cpi->bus_id = cam_sim_bus(psim);
2884                         strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2885                         strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2886                         strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2887                         cpi->unit_number = cam_sim_unit(psim);
2888                 #ifdef  CAM_NEW_TRAN_CODE
2889                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
2890                                 cpi->base_transfer_speed = 1200000;
2891                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2892                                 cpi->base_transfer_speed = 600000;
2893                         else
2894                                 cpi->base_transfer_speed = 300000;
2895                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2896                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2897                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2898                         {
2899                                 cpi->transport = XPORT_SAS;
2900                                 cpi->transport_version = 0;
2901                                 cpi->protocol_version = SCSI_REV_SPC2;
2902                         }
2903                         else
2904                         {
2905                                 cpi->transport = XPORT_SPI;
2906                                 cpi->transport_version = 2;
2907                                 cpi->protocol_version = SCSI_REV_2;
2908                         }
2909                         cpi->protocol = PROTO_SCSI;
2910                 #endif
2911                         cpi->ccb_h.status |= CAM_REQ_CMP;
2912                         xpt_done(pccb);
2913                         break;
2914                 }
2915         case XPT_ABORT: {
2916                         union ccb *pabort_ccb;
2917
2918                         pabort_ccb = pccb->cab.abort_ccb;
2919                         switch (pabort_ccb->ccb_h.func_code) {
2920                         case XPT_ACCEPT_TARGET_IO:
2921                         case XPT_IMMED_NOTIFY:
2922                         case XPT_CONT_TARGET_IO:
2923                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2924                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2925                                         xpt_done(pabort_ccb);
2926                                         pccb->ccb_h.status |= CAM_REQ_CMP;
2927                                 } else {
2928                                         xpt_print_path(pabort_ccb->ccb_h.path);
2929                                         printf("Not found\n");
2930                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
2931                                 }
2932                                 break;
2933                         case XPT_SCSI_IO:
2934                                 pccb->ccb_h.status |= CAM_UA_ABORT;
2935                                 break;
2936                         default:
2937                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2938                                 break;
2939                         }
2940                         xpt_done(pccb);
2941                         break;
2942                 }
2943         case XPT_RESET_BUS:
2944         case XPT_RESET_DEV: {
2945                         u_int32_t     i;
2946
2947                         arcmsr_bus_reset(acb);
2948                         for (i=0; i < 500; i++) {
2949                                 DELAY(1000);
2950                         }
2951                         pccb->ccb_h.status |= CAM_REQ_CMP;
2952                         xpt_done(pccb);
2953                         break;
2954                 }
2955         case XPT_TERM_IO: {
2956                         pccb->ccb_h.status |= CAM_REQ_INVALID;
2957                         xpt_done(pccb);
2958                         break;
2959                 }
2960         case XPT_GET_TRAN_SETTINGS: {
2961                         struct ccb_trans_settings *cts;
2962
2963                         if(pccb->ccb_h.target_id == 16) {
2964                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2965                                 xpt_done(pccb);
2966                                 break;
2967                         }
2968                         cts = &pccb->cts;
2969                 #ifdef  CAM_NEW_TRAN_CODE
2970                         {
2971                                 struct ccb_trans_settings_scsi *scsi;
2972                                 struct ccb_trans_settings_spi *spi;
2973                                 struct ccb_trans_settings_sas *sas;
2974
2975                                 scsi = &cts->proto_specific.scsi;
2976                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2977                                 scsi->valid = CTS_SCSI_VALID_TQ;
2978                                 cts->protocol = PROTO_SCSI;
2979
2980                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2981                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2982                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
2983                                 {
2984                                         cts->protocol_version = SCSI_REV_SPC2;
2985                                         cts->transport_version = 0;
2986                                         cts->transport = XPORT_SAS;
2987                                         sas = &cts->xport_specific.sas;
2988                                         sas->valid = CTS_SAS_VALID_SPEED;
2989                                         if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
2990                                                 sas->bitrate = 1200000;
2991                                         else if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2992                                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2993                                                 sas->bitrate = 600000;
2994                                         else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2995                                                 sas->bitrate = 300000;
2996                                 }
2997                                 else
2998                                 {
2999                                         cts->protocol_version = SCSI_REV_2;
3000                                         cts->transport_version = 2;
3001                                         cts->transport = XPORT_SPI;
3002                                         spi = &cts->xport_specific.spi;
3003                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3004                                         spi->sync_period = 2;
3005                                         spi->sync_offset = 32;
3006                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3007                                         spi->valid = CTS_SPI_VALID_DISC
3008                                                 | CTS_SPI_VALID_SYNC_RATE
3009                                                 | CTS_SPI_VALID_SYNC_OFFSET
3010                                                 | CTS_SPI_VALID_BUS_WIDTH;
3011                                 }
3012                         }
3013                 #else
3014                         {
3015                                 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3016                                 cts->sync_period = 2;
3017                                 cts->sync_offset = 32;
3018                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3019                                 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3020                                 CCB_TRANS_SYNC_OFFSET_VALID |
3021                                 CCB_TRANS_BUS_WIDTH_VALID |
3022                                 CCB_TRANS_DISC_VALID |
3023                                 CCB_TRANS_TQ_VALID;
3024                         }
3025                 #endif
3026                         pccb->ccb_h.status |= CAM_REQ_CMP;
3027                         xpt_done(pccb);
3028                         break;
3029                 }
3030         case XPT_SET_TRAN_SETTINGS: {
3031                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3032                         xpt_done(pccb);
3033                         break;
3034                 }
3035         case XPT_CALC_GEOMETRY:
3036                         if(pccb->ccb_h.target_id == 16) {
3037                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3038                                 xpt_done(pccb);
3039                                 break;
3040                         }
3041 #if __FreeBSD_version >= 500000
3042                         cam_calc_geometry(&pccb->ccg, 1);
3043 #else
3044                         {
3045                         struct ccb_calc_geometry *ccg;
3046                         u_int32_t size_mb;
3047                         u_int32_t secs_per_cylinder;
3048
3049                         ccg = &pccb->ccg;
3050                         if (ccg->block_size == 0) {
3051                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3052                                 xpt_done(pccb);
3053                                 break;
3054                         }
3055                         if(((1024L * 1024L)/ccg->block_size) < 0) {
3056                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3057                                 xpt_done(pccb);
3058                                 break;
3059                         }
3060                         size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3061                         if(size_mb > 1024 ) {
3062                                 ccg->heads = 255;
3063                                 ccg->secs_per_track = 63;
3064                         } else {
3065                                 ccg->heads = 64;
3066                                 ccg->secs_per_track = 32;
3067                         }
3068                         secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3069                         ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3070                         pccb->ccb_h.status |= CAM_REQ_CMP;
3071                         }
3072 #endif
3073                         xpt_done(pccb);
3074                         break;
3075         default:
3076                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3077                 xpt_done(pccb);
3078                 break;
3079         }
3080 }
3081 /*
3082 **********************************************************************
3083 **********************************************************************
3084 */
3085 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3086 {
3087         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3088         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3089         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3090                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3091         }
3092 }
3093 /*
3094 **********************************************************************
3095 **********************************************************************
3096 */
3097 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3098 {
3099         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3100         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,  ARCMSR_MESSAGE_START_BGRB);
3101         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3102                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3103         }
3104 }
3105 /*
3106 **********************************************************************
3107 **********************************************************************
3108 */
3109 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3110 {
3111         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3112         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3113         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3114         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3115                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3116         }
3117 }
3118 /*
3119 **********************************************************************
3120 **********************************************************************
3121 */
3122 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3123 {
3124         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3125         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3126         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3127                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3128         }
3129 }
3130 /*
3131 **********************************************************************
3132 **********************************************************************
3133 */
3134 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3135 {
3136         switch (acb->adapter_type) {
3137         case ACB_ADAPTER_TYPE_A:
3138                 arcmsr_start_hba_bgrb(acb);
3139                 break;
3140         case ACB_ADAPTER_TYPE_B:
3141                 arcmsr_start_hbb_bgrb(acb);
3142                 break;
3143         case ACB_ADAPTER_TYPE_C:
3144                 arcmsr_start_hbc_bgrb(acb);
3145                 break;
3146         case ACB_ADAPTER_TYPE_D:
3147                 arcmsr_start_hbd_bgrb(acb);
3148                 break;
3149         }
3150 }
3151 /*
3152 **********************************************************************
3153 **
3154 **********************************************************************
3155 */
3156 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3157 {
3158         struct CommandControlBlock *srb;
3159         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3160         u_int16_t       error;
3161
3162 polling_ccb_retry:
3163         poll_count++;
3164         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3165         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3166         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3167         while(1) {
3168                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3169                         0, outbound_queueport)) == 0xFFFFFFFF) {
3170                         if(poll_srb_done) {
3171                                 break;/*chip FIFO no ccb for completion already*/
3172                         } else {
3173                                 UDELAY(25000);
3174                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3175                                         break;
3176                                 }
3177                                 goto polling_ccb_retry;
3178                         }
3179                 }
3180                 /* check if command done with no error*/
3181                 srb = (struct CommandControlBlock *)
3182                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3183         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3184                 poll_srb_done = (srb == poll_srb) ? 1:0;
3185                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3186                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3187                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3188                                         "poll command abort successfully \n"
3189                                         , acb->pci_unit
3190                                         , srb->pccb->ccb_h.target_id
3191                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3192                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3193                                 arcmsr_srb_complete(srb, 1);
3194                                 continue;
3195                         }
3196                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3197                                 "srboutstandingcount=%d \n"
3198                                 , acb->pci_unit
3199                                 , srb, acb->srboutstandingcount);
3200                         continue;
3201                 }
3202                 arcmsr_report_srb_state(acb, srb, error);
3203         }       /*drain reply FIFO*/
3204 }
3205 /*
3206 **********************************************************************
3207 **
3208 **********************************************************************
3209 */
3210 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3211 {
3212         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3213         struct CommandControlBlock *srb;
3214         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3215         int index;
3216         u_int16_t       error;
3217
3218 polling_ccb_retry:
3219         poll_count++;
3220         CHIP_REG_WRITE32(HBB_DOORBELL,
3221         0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3222         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3223         while(1) {
3224                 index = phbbmu->doneq_index;
3225                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3226                         if(poll_srb_done) {
3227                                 break;/*chip FIFO no ccb for completion already*/
3228                         } else {
3229                                 UDELAY(25000);
3230                             if ((poll_count > 100) && (poll_srb != NULL)) {
3231                                         break;
3232                                 }
3233                                 goto polling_ccb_retry;
3234                         }
3235                 }
3236                 phbbmu->done_qbuffer[index] = 0;
3237                 index++;
3238                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3239                 phbbmu->doneq_index = index;
3240                 /* check if command done with no error*/
3241                 srb = (struct CommandControlBlock *)
3242                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3243         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3244                 poll_srb_done = (srb == poll_srb) ? 1:0;
3245                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3246                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3247                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3248                                         "poll command abort successfully \n"
3249                                         , acb->pci_unit
3250                                         , srb->pccb->ccb_h.target_id
3251                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3252                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3253                                 arcmsr_srb_complete(srb, 1);
3254                                 continue;
3255                         }
3256                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3257                                 "srboutstandingcount=%d \n"
3258                                 , acb->pci_unit
3259                                 , srb, acb->srboutstandingcount);
3260                         continue;
3261                 }
3262                 arcmsr_report_srb_state(acb, srb, error);
3263         }       /*drain reply FIFO*/
3264 }
3265 /*
3266 **********************************************************************
3267 **
3268 **********************************************************************
3269 */
3270 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3271 {
3272         struct CommandControlBlock *srb;
3273         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3274         u_int16_t       error;
3275
3276 polling_ccb_retry:
3277         poll_count++;
3278         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3279         while(1) {
3280                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3281                         if(poll_srb_done) {
3282                                 break;/*chip FIFO no ccb for completion already*/
3283                         } else {
3284                                 UDELAY(25000);
3285                             if ((poll_count > 100) && (poll_srb != NULL)) {
3286                                         break;
3287                                 }
3288                             if (acb->srboutstandingcount == 0) {
3289                                     break;
3290                             }
3291                                 goto polling_ccb_retry;
3292                         }
3293                 }
3294                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3295                 /* check if command done with no error*/
3296                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3297         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3298                 if (poll_srb != NULL)
3299                         poll_srb_done = (srb == poll_srb) ? 1:0;
3300                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3301                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3302                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3303                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3304                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3305                                 arcmsr_srb_complete(srb, 1);
3306                                 continue;
3307                         }
3308                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3309                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3310                         continue;
3311                 }
3312                 arcmsr_report_srb_state(acb, srb, error);
3313         }       /*drain reply FIFO*/
3314 }
3315 /*
3316 **********************************************************************
3317 **
3318 **********************************************************************
3319 */
3320 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3321 {
3322         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3323         struct CommandControlBlock *srb;
3324         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3325         u_int32_t outbound_write_pointer;
3326         u_int16_t       error, doneq_index;
3327
3328 polling_ccb_retry:
3329         poll_count++;
3330         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3331         while(1) {
3332                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3333                 doneq_index = phbdmu->doneq_index;
3334                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3335                         if(poll_srb_done) {
3336                                 break;/*chip FIFO no ccb for completion already*/
3337                         } else {
3338                                 UDELAY(25000);
3339                             if ((poll_count > 100) && (poll_srb != NULL)) {
3340                                         break;
3341                                 }
3342                             if (acb->srboutstandingcount == 0) {
3343                                     break;
3344                             }
3345                                 goto polling_ccb_retry;
3346                         }
3347                 }
3348                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3349                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3350                 /* check if command done with no error*/
3351                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3352         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3353                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3354                 if (poll_srb != NULL)
3355                         poll_srb_done = (srb == poll_srb) ? 1:0;
3356                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3357                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3358                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3359                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3360                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3361                                 arcmsr_srb_complete(srb, 1);
3362                                 continue;
3363                         }
3364                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3365                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3366                         continue;
3367                 }
3368                 arcmsr_report_srb_state(acb, srb, error);
3369         }       /*drain reply FIFO*/
3370 }
3371 /*
3372 **********************************************************************
3373 **********************************************************************
3374 */
3375 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3376 {
3377         switch (acb->adapter_type) {
3378         case ACB_ADAPTER_TYPE_A: {
3379                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3380                 }
3381                 break;
3382         case ACB_ADAPTER_TYPE_B: {
3383                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3384                 }
3385                 break;
3386         case ACB_ADAPTER_TYPE_C: {
3387                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3388                 }
3389                 break;
3390         case ACB_ADAPTER_TYPE_D: {
3391                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3392                 }
3393                 break;
3394         }
3395 }
3396 /*
3397 **********************************************************************
3398 **********************************************************************
3399 */
3400 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3401 {
3402         char *acb_firm_model = acb->firm_model;
3403         char *acb_firm_version = acb->firm_version;
3404         char *acb_device_map = acb->device_map;
3405         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3406         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3407         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3408         int i;
3409
3410         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3411         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3412                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3413         }
3414         i = 0;
3415         while(i < 8) {
3416                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3417                 /* 8 bytes firm_model, 15, 60-67*/
3418                 acb_firm_model++;
3419                 i++;
3420         }
3421         i=0;
3422         while(i < 16) {
3423                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3424                 /* 16 bytes firm_version, 17, 68-83*/
3425                 acb_firm_version++;
3426                 i++;
3427         }
3428         i=0;
3429         while(i < 16) {
3430                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3431                 acb_device_map++;
3432                 i++;
3433         }
3434         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3435         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3436         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3437         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3438         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3439         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3440         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3441                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3442         else
3443                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3444 }
3445 /*
3446 **********************************************************************
3447 **********************************************************************
3448 */
3449 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3450 {
3451         char *acb_firm_model = acb->firm_model;
3452         char *acb_firm_version = acb->firm_version;
3453         char *acb_device_map = acb->device_map;
3454         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3455         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3456         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3457         int i;
3458
3459         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3460         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3461                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3462         }
3463         i = 0;
3464         while(i < 8) {
3465                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3466                 /* 8 bytes firm_model, 15, 60-67*/
3467                 acb_firm_model++;
3468                 i++;
3469         }
3470         i = 0;
3471         while(i < 16) {
3472                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3473                 /* 16 bytes firm_version, 17, 68-83*/
3474                 acb_firm_version++;
3475                 i++;
3476         }
3477         i = 0;
3478         while(i < 16) {
3479                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3480                 acb_device_map++;
3481                 i++;
3482         }
3483         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3484         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3485         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3486         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3487         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3488         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3489         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3490                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3491         else
3492                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3493 }
3494 /*
3495 **********************************************************************
3496 **********************************************************************
3497 */
3498 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3499 {
3500         char *acb_firm_model = acb->firm_model;
3501         char *acb_firm_version = acb->firm_version;
3502         char *acb_device_map = acb->device_map;
3503         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3504         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3505         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3506         int i;
3507
3508         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3509         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3510         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3511                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3512         }
3513         i = 0;
3514         while(i < 8) {
3515                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3516                 /* 8 bytes firm_model, 15, 60-67*/
3517                 acb_firm_model++;
3518                 i++;
3519         }
3520         i = 0;
3521         while(i < 16) {
3522                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3523                 /* 16 bytes firm_version, 17, 68-83*/
3524                 acb_firm_version++;
3525                 i++;
3526         }
3527         i = 0;
3528         while(i < 16) {
3529                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3530                 acb_device_map++;
3531                 i++;
3532         }
3533         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3534         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3535         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3536         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3537         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3538         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3539         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3540                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3541         else
3542                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3543 }
3544 /*
3545 **********************************************************************
3546 **********************************************************************
3547 */
3548 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3549 {
3550         char *acb_firm_model = acb->firm_model;
3551         char *acb_firm_version = acb->firm_version;
3552         char *acb_device_map = acb->device_map;
3553         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3554         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3555         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3556         int i;
3557
3558         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3559                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3560         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3561         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3562                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3563         }
3564         i = 0;
3565         while(i < 8) {
3566                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3567                 /* 8 bytes firm_model, 15, 60-67*/
3568                 acb_firm_model++;
3569                 i++;
3570         }
3571         i = 0;
3572         while(i < 16) {
3573                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3574                 /* 16 bytes firm_version, 17, 68-83*/
3575                 acb_firm_version++;
3576                 i++;
3577         }
3578         i = 0;
3579         while(i < 16) {
3580                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3581                 acb_device_map++;
3582                 i++;
3583         }
3584         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3585         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_request_len,   1, 04-07*/
3586         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_numbers_queue, 2, 08-11*/
3587         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_sdram_size,    3, 12-15*/
3588         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]);     /*firm_ide_channels,  4, 16-19*/
3589         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3590         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3591                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3592         else
3593                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3594 }
3595 /*
3596 **********************************************************************
3597 **********************************************************************
3598 */
3599 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3600 {
3601         switch (acb->adapter_type) {
3602         case ACB_ADAPTER_TYPE_A: {
3603                         arcmsr_get_hba_config(acb);
3604                 }
3605                 break;
3606         case ACB_ADAPTER_TYPE_B: {
3607                         arcmsr_get_hbb_config(acb);
3608                 }
3609                 break;
3610         case ACB_ADAPTER_TYPE_C: {
3611                         arcmsr_get_hbc_config(acb);
3612                 }
3613                 break;
3614         case ACB_ADAPTER_TYPE_D: {
3615                         arcmsr_get_hbd_config(acb);
3616                 }
3617                 break;
3618         }
3619 }
3620 /*
3621 **********************************************************************
3622 **********************************************************************
3623 */
3624 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3625 {
3626         int     timeout=0;
3627
3628         switch (acb->adapter_type) {
3629         case ACB_ADAPTER_TYPE_A: {
3630                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3631                         {
3632                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3633                                 {
3634                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3635                                         return;
3636                                 }
3637                                 UDELAY(15000); /* wait 15 milli-seconds */
3638                         }
3639                 }
3640                 break;
3641         case ACB_ADAPTER_TYPE_B: {
3642                         while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3643                         {
3644                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3645                                 {
3646                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3647                                         return;
3648                                 }
3649                                 UDELAY(15000); /* wait 15 milli-seconds */
3650                         }
3651                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3652                 }
3653                 break;
3654         case ACB_ADAPTER_TYPE_C: {
3655                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3656                         {
3657                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3658                                 {
3659                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3660                                         return;
3661                                 }
3662                                 UDELAY(15000); /* wait 15 milli-seconds */
3663                         }
3664                 }
3665                 break;
3666         case ACB_ADAPTER_TYPE_D: {
3667                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3668                         {
3669                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3670                                 {
3671                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3672                                         return;
3673                                 }
3674                                 UDELAY(15000); /* wait 15 milli-seconds */
3675                         }
3676                 }
3677                 break;
3678         }
3679 }
3680 /*
3681 **********************************************************************
3682 **********************************************************************
3683 */
3684 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3685 {
3686         u_int32_t outbound_doorbell;
3687
3688         switch (acb->adapter_type) {
3689         case ACB_ADAPTER_TYPE_A: {
3690                         /* empty doorbell Qbuffer if door bell ringed */
3691                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3692                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3693                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3694
3695                 }
3696                 break;
3697         case ACB_ADAPTER_TYPE_B: {
3698                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3699                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3700                         /* let IOP know data has been read */
3701                 }
3702                 break;
3703         case ACB_ADAPTER_TYPE_C: {
3704                         /* empty doorbell Qbuffer if door bell ringed */
3705                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3706                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
3707                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3708                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3709                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3710                 }
3711                 break;
3712         case ACB_ADAPTER_TYPE_D: {
3713                         /* empty doorbell Qbuffer if door bell ringed */
3714                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3715                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3716                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3717
3718                 }
3719                 break;
3720         }
3721 }
3722 /*
3723 ************************************************************************
3724 ************************************************************************
3725 */
3726 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3727 {
3728         unsigned long srb_phyaddr;
3729         u_int32_t srb_phyaddr_hi32;
3730         u_int32_t srb_phyaddr_lo32;
3731
3732         /*
3733         ********************************************************************
3734         ** here we need to tell iop 331 our freesrb.HighPart
3735         ** if freesrb.HighPart is not zero
3736         ********************************************************************
3737         */
3738         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3739         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3740         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3741         switch (acb->adapter_type) {
3742         case ACB_ADAPTER_TYPE_A: {
3743                         if(srb_phyaddr_hi32 != 0) {
3744                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3745                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3746                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3747                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3748                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3749                                         return FALSE;
3750                                 }
3751                         }
3752                 }
3753                 break;
3754                 /*
3755                 ***********************************************************************
3756                 **    if adapter type B, set window of "post command Q"
3757                 ***********************************************************************
3758                 */
3759         case ACB_ADAPTER_TYPE_B: {
3760                         u_int32_t post_queue_phyaddr;
3761                         struct HBB_MessageUnit *phbbmu;
3762
3763                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3764                         phbbmu->postq_index = 0;
3765                         phbbmu->doneq_index = 0;
3766                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3767                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3768                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3769                                 return FALSE;
3770                         }
3771                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3772                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
3773                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3774                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3775                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3776                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3777                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3778                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3779                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3780                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3781                                 return FALSE;
3782                         }
3783                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3784                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3785                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3786                                 return FALSE;
3787                         }
3788                 }
3789                 break;
3790         case ACB_ADAPTER_TYPE_C: {
3791                         if(srb_phyaddr_hi32 != 0) {
3792                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3793                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3794                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3795                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3796                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3797                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3798                                         return FALSE;
3799                                 }
3800                         }
3801                 }
3802                 break;
3803         case ACB_ADAPTER_TYPE_D: {
3804                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3805                         struct HBD_MessageUnit0 *phbdmu;
3806
3807                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3808                         phbdmu->postq_index = 0;
3809                         phbdmu->doneq_index = 0x40FF;
3810                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3811                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
3812                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3813                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
3814                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3815                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3816                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3817                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3818                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3819                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3820                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3821                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3822                                 return FALSE;
3823                         }
3824                 }
3825                 break;
3826         }
3827         return (TRUE);
3828 }
3829 /*
3830 ************************************************************************
3831 ************************************************************************
3832 */
3833 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3834 {
3835         switch (acb->adapter_type)
3836         {
3837         case ACB_ADAPTER_TYPE_A:
3838         case ACB_ADAPTER_TYPE_C:
3839         case ACB_ADAPTER_TYPE_D:
3840                 break;
3841         case ACB_ADAPTER_TYPE_B: {
3842                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3843                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3844                                 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3845                                 return;
3846                         }
3847                 }
3848                 break;
3849         }
3850 }
3851 /*
3852 **********************************************************************
3853 **********************************************************************
3854 */
3855 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3856 {
3857         u_int32_t intmask_org;
3858
3859         /* disable all outbound interrupt */
3860         intmask_org = arcmsr_disable_allintr(acb);
3861         arcmsr_wait_firmware_ready(acb);
3862         arcmsr_iop_confirm(acb);
3863         arcmsr_get_firmware_spec(acb);
3864         /*start background rebuild*/
3865         arcmsr_start_adapter_bgrb(acb);
3866         /* empty doorbell Qbuffer if door bell ringed */
3867         arcmsr_clear_doorbell_queue_buffer(acb);
3868         arcmsr_enable_eoi_mode(acb);
3869         /* enable outbound Post Queue, outbound doorbell Interrupt */
3870         arcmsr_enable_allintr(acb, intmask_org);
3871         acb->acb_flags |= ACB_F_IOP_INITED;
3872 }
3873 /*
3874 **********************************************************************
3875 **********************************************************************
3876 */
3877 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3878 {
3879         struct AdapterControlBlock *acb = arg;
3880         struct CommandControlBlock *srb_tmp;
3881         u_int32_t i;
3882         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3883
3884         acb->srb_phyaddr.phyaddr = srb_phyaddr;
3885         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3886         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3887                 if(bus_dmamap_create(acb->dm_segs_dmat,
3888                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3889                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3890                         printf("arcmsr%d:"
3891                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3892                         return;
3893                 }
3894                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3895                 {
3896                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3897                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3898                 }
3899                 else
3900                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3901                 srb_tmp->acb = acb;
3902                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3903                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
3904                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3905         }
3906         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3907 }
3908 /*
3909 ************************************************************************
3910 ************************************************************************
3911 */
3912 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3913 {
3914         /* remove the control device */
3915         if(acb->ioctl_dev != NULL) {
3916                 destroy_dev(acb->ioctl_dev);
3917         }
3918         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3919         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3920         bus_dma_tag_destroy(acb->srb_dmat);
3921         bus_dma_tag_destroy(acb->dm_segs_dmat);
3922         bus_dma_tag_destroy(acb->parent_dmat);
3923 }
3924 /*
3925 ************************************************************************
3926 ************************************************************************
3927 */
3928 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3929 {
3930         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3931         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3932         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3933         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3934 }
3935 /*
3936 ************************************************************************
3937 ************************************************************************
3938 */
3939 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3940 {
3941         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3942         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3943         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3944         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3945 }
3946 /*
3947 ************************************************************************
3948 ************************************************************************
3949 */
3950 static u_int32_t arcmsr_initialize(device_t dev)
3951 {
3952         struct AdapterControlBlock *acb = device_get_softc(dev);
3953         u_int16_t pci_command;
3954         int i, j,max_coherent_size;
3955         u_int32_t vendor_dev_id;
3956
3957         vendor_dev_id = pci_get_devid(dev);
3958         acb->vendor_device_id = vendor_dev_id;
3959         acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3960         switch (vendor_dev_id) {
3961         case PCIDevVenIDARC1880:
3962         case PCIDevVenIDARC1882:
3963         case PCIDevVenIDARC1213:
3964         case PCIDevVenIDARC1223: {
3965                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
3966                         if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
3967                                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
3968                         else
3969                                 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3970                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3971                 }
3972                 break;
3973         case PCIDevVenIDARC1214: {
3974                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
3975                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3976                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
3977                 }
3978                 break;
3979         case PCIDevVenIDARC1200:
3980         case PCIDevVenIDARC1201: {
3981                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
3982                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3983                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
3984                 }
3985                 break;
3986         case PCIDevVenIDARC1110:
3987         case PCIDevVenIDARC1120:
3988         case PCIDevVenIDARC1130:
3989         case PCIDevVenIDARC1160:
3990         case PCIDevVenIDARC1170:
3991         case PCIDevVenIDARC1210:
3992         case PCIDevVenIDARC1220:
3993         case PCIDevVenIDARC1230:
3994         case PCIDevVenIDARC1231:
3995         case PCIDevVenIDARC1260:
3996         case PCIDevVenIDARC1261:
3997         case PCIDevVenIDARC1270:
3998         case PCIDevVenIDARC1280:
3999         case PCIDevVenIDARC1212:
4000         case PCIDevVenIDARC1222:
4001         case PCIDevVenIDARC1380:
4002         case PCIDevVenIDARC1381:
4003         case PCIDevVenIDARC1680:
4004         case PCIDevVenIDARC1681: {
4005                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4006                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4007                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4008                 }
4009                 break;
4010         default: {
4011                         printf("arcmsr%d:"
4012                         " unknown RAID adapter type \n", device_get_unit(dev));
4013                         return ENOMEM;
4014                 }
4015         }
4016 #if __FreeBSD_version >= 700000
4017         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4018 #else
4019         if(bus_dma_tag_create(  /*PCI parent*/          NULL,
4020 #endif
4021                                                         /*alignemnt*/   1,
4022                                                         /*boundary*/    0,
4023                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4024                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4025                                                         /*filter*/              NULL,
4026                                                         /*filterarg*/   NULL,
4027                                                         /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4028                                                         /*nsegments*/   BUS_SPACE_UNRESTRICTED,
4029                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4030                                                         /*flags*/               0,
4031 #if __FreeBSD_version >= 501102
4032                                                         /*lockfunc*/    NULL,
4033                                                         /*lockarg*/             NULL,
4034 #endif
4035                                                 &acb->parent_dmat) != 0)
4036         {
4037                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4038                 return ENOMEM;
4039         }
4040
4041         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4042         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4043                                                         /*alignment*/   1,
4044                                                         /*boundary*/    0,
4045 #ifdef PAE
4046                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4047 #else
4048                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4049 #endif
4050                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4051                                                         /*filter*/              NULL,
4052                                                         /*filterarg*/   NULL,
4053                                                         /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4054                                                         /*nsegments*/   ARCMSR_MAX_SG_ENTRIES,
4055                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4056                                                         /*flags*/               0,
4057 #if __FreeBSD_version >= 501102
4058                                                         /*lockfunc*/    busdma_lock_mutex,
4059                                                         /*lockarg*/             &acb->isr_lock,
4060 #endif
4061                                                 &acb->dm_segs_dmat) != 0)
4062         {
4063                 bus_dma_tag_destroy(acb->parent_dmat);
4064                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4065                 return ENOMEM;
4066         }
4067
4068         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4069         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4070                                                         /*alignment*/   0x20,
4071                                                         /*boundary*/    0,
4072                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4073                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4074                                                         /*filter*/              NULL,
4075                                                         /*filterarg*/   NULL,
4076                                                         /*maxsize*/             max_coherent_size,
4077                                                         /*nsegments*/   1,
4078                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4079                                                         /*flags*/               0,
4080 #if __FreeBSD_version >= 501102
4081                                                         /*lockfunc*/    NULL,
4082                                                         /*lockarg*/             NULL,
4083 #endif
4084                                                 &acb->srb_dmat) != 0)
4085         {
4086                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4087                 bus_dma_tag_destroy(acb->parent_dmat);
4088                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4089                 return ENXIO;
4090         }
4091         /* Allocation for our srbs */
4092         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4093                 bus_dma_tag_destroy(acb->srb_dmat);
4094                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4095                 bus_dma_tag_destroy(acb->parent_dmat);
4096                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4097                 return ENXIO;
4098         }
4099         /* And permanently map them */
4100         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4101                 bus_dma_tag_destroy(acb->srb_dmat);
4102                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4103                 bus_dma_tag_destroy(acb->parent_dmat);
4104                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4105                 return ENXIO;
4106         }
4107         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4108         pci_command |= PCIM_CMD_BUSMASTEREN;
4109         pci_command |= PCIM_CMD_PERRESPEN;
4110         pci_command |= PCIM_CMD_MWRICEN;
4111         /* Enable Busmaster */
4112         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4113         switch(acb->adapter_type) {
4114         case ACB_ADAPTER_TYPE_A: {
4115                         u_int32_t rid0 = PCIR_BAR(0);
4116                         vm_offset_t     mem_base0;
4117
4118                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
4119                         if(acb->sys_res_arcmsr[0] == NULL) {
4120                                 arcmsr_free_resource(acb);
4121                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4122                                 return ENOMEM;
4123                         }
4124                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4125                                 arcmsr_free_resource(acb);
4126                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4127                                 return ENXIO;
4128                         }
4129                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4130                         if(mem_base0 == 0) {
4131                                 arcmsr_free_resource(acb);
4132                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4133                                 return ENXIO;
4134                         }
4135                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4136                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4137                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4138                 }
4139                 break;
4140         case ACB_ADAPTER_TYPE_B: {
4141                         struct HBB_MessageUnit *phbbmu;
4142                         struct CommandControlBlock *freesrb;
4143                         u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4144                         vm_offset_t     mem_base[]={0,0};
4145                         for(i=0; i < 2; i++) {
4146                                 if(i == 0) {
4147                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
4148                                                                                         0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
4149                                 } else {
4150                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
4151                                                                                         0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
4152                                 }
4153                                 if(acb->sys_res_arcmsr[i] == NULL) {
4154                                         arcmsr_free_resource(acb);
4155                                         printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4156                                         return ENOMEM;
4157                                 }
4158                                 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4159                                         arcmsr_free_resource(acb);
4160                                         printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4161                                         return ENXIO;
4162                                 }
4163                                 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4164                                 if(mem_base[i] == 0) {
4165                                         arcmsr_free_resource(acb);
4166                                         printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4167                                         return ENXIO;
4168                                 }
4169                                 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4170                                 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4171                         }
4172                         freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4173                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4174                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4175                         phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4176                         phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4177                 }
4178                 break;
4179         case ACB_ADAPTER_TYPE_C: {
4180                         u_int32_t rid0 = PCIR_BAR(1);
4181                         vm_offset_t     mem_base0;
4182
4183                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
4184                         if(acb->sys_res_arcmsr[0] == NULL) {
4185                                 arcmsr_free_resource(acb);
4186                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4187                                 return ENOMEM;
4188                         }
4189                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4190                                 arcmsr_free_resource(acb);
4191                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4192                                 return ENXIO;
4193                         }
4194                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4195                         if(mem_base0 == 0) {
4196                                 arcmsr_free_resource(acb);
4197                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4198                                 return ENXIO;
4199                         }
4200                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4201                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4202                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4203                 }
4204                 break;
4205         case ACB_ADAPTER_TYPE_D: {
4206                         struct HBD_MessageUnit0 *phbdmu;
4207                         u_int32_t rid0 = PCIR_BAR(0);
4208                         vm_offset_t     mem_base0;
4209
4210                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
4211                         if(acb->sys_res_arcmsr[0] == NULL) {
4212                                 arcmsr_free_resource(acb);
4213                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4214                                 return ENOMEM;
4215                         }
4216                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4217                                 arcmsr_free_resource(acb);
4218                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4219                                 return ENXIO;
4220                         }
4221                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4222                         if(mem_base0 == 0) {
4223                                 arcmsr_free_resource(acb);
4224                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4225                                 return ENXIO;
4226                         }
4227                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4228                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4229                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4230                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4231                         phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4232                 }
4233                 break;
4234         }
4235         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4236                 arcmsr_free_resource(acb);
4237                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4238                 return ENXIO;
4239         }
4240         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4241         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4242         /*
4243         ********************************************************************
4244         ** init raid volume state
4245         ********************************************************************
4246         */
4247         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4248                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4249                         acb->devstate[i][j] = ARECA_RAID_GONE;
4250                 }
4251         }
4252         arcmsr_iop_init(acb);
4253         return(0);
4254 }
4255 /*
4256 ************************************************************************
4257 ************************************************************************
4258 */
4259 static int arcmsr_attach(device_t dev)
4260 {
4261         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4262         u_int32_t unit=device_get_unit(dev);
4263         struct ccb_setasync csa;
4264         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4265         struct resource *irqres;
4266         int     rid;
4267
4268         if(acb == NULL) {
4269                 printf("arcmsr%d: cannot allocate softc\n", unit);
4270                 return (ENOMEM);
4271         }
4272         arcmsr_mutex_init(acb);
4273         acb->pci_dev = dev;
4274         acb->pci_unit = unit;
4275         if(arcmsr_initialize(dev)) {
4276                 printf("arcmsr%d: initialize failure!\n", unit);
4277                 arcmsr_mutex_destroy(acb);
4278                 return ENXIO;
4279         }
4280         /* After setting up the adapter, map our interrupt */
4281         rid = 0;
4282         irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
4283         if(irqres == NULL ||
4284 #if __FreeBSD_version >= 700025
4285                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4286 #else
4287                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4288 #endif
4289                 arcmsr_free_resource(acb);
4290                 arcmsr_mutex_destroy(acb);
4291                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4292                 return ENXIO;
4293         }
4294         acb->irqres = irqres;
4295         /*
4296          * Now let the CAM generic SCSI layer find the SCSI devices on
4297          * the bus *  start queue to reset to the idle loop. *
4298          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4299          * max_sim_transactions
4300         */
4301         devq = cam_simq_alloc(acb->maxOutstanding);
4302         if(devq == NULL) {
4303             arcmsr_free_resource(acb);
4304                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4305                 arcmsr_mutex_destroy(acb);
4306                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4307                 return ENXIO;
4308         }
4309 #if __FreeBSD_version >= 700025
4310         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4311 #else
4312         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4313 #endif
4314         if(acb->psim == NULL) {
4315                 arcmsr_free_resource(acb);
4316                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4317                 cam_simq_free(devq);
4318                 arcmsr_mutex_destroy(acb);
4319                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4320                 return ENXIO;
4321         }
4322         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4323 #if __FreeBSD_version >= 700044
4324         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4325 #else
4326         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4327 #endif
4328                 arcmsr_free_resource(acb);
4329                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4330                 cam_sim_free(acb->psim, /*free_devq*/TRUE);
4331                 arcmsr_mutex_destroy(acb);
4332                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4333                 return ENXIO;
4334         }
4335         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4336                 arcmsr_free_resource(acb);
4337                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4338                 xpt_bus_deregister(cam_sim_path(acb->psim));
4339                 cam_sim_free(acb->psim, /* free_simq */ TRUE);
4340                 arcmsr_mutex_destroy(acb);
4341                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4342                 return ENXIO;
4343         }
4344         /*
4345         ****************************************************
4346         */
4347         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4348         csa.ccb_h.func_code = XPT_SASYNC_CB;
4349         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4350         csa.callback = arcmsr_async;
4351         csa.callback_arg = acb->psim;
4352         xpt_action((union ccb *)&csa);
4353         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4354         /* Create the control device.  */
4355         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4356
4357 #if __FreeBSD_version < 503000
4358         acb->ioctl_dev->si_drv1 = acb;
4359 #endif
4360 #if __FreeBSD_version > 500005
4361         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4362 #endif
4363         arcmsr_callout_init(&acb->devmap_callout);
4364         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4365         return (0);
4366 }
4367
4368 /*
4369 ************************************************************************
4370 ************************************************************************
4371 */
4372 static int arcmsr_probe(device_t dev)
4373 {
4374         u_int32_t id;
4375         u_int16_t sub_device_id;
4376         static char buf[256];
4377         char x_type[]={"unknown"};
4378         char *type;
4379         int raid6 = 1;
4380
4381         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4382                 return (ENXIO);
4383         }
4384         sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4385         switch(id = pci_get_devid(dev)) {
4386         case PCIDevVenIDARC1110:
4387         case PCIDevVenIDARC1200:
4388         case PCIDevVenIDARC1201:
4389         case PCIDevVenIDARC1210:
4390                 raid6 = 0;
4391                 /*FALLTHRU*/
4392         case PCIDevVenIDARC1120:
4393         case PCIDevVenIDARC1130:
4394         case PCIDevVenIDARC1160:
4395         case PCIDevVenIDARC1170:
4396         case PCIDevVenIDARC1220:
4397         case PCIDevVenIDARC1230:
4398         case PCIDevVenIDARC1231:
4399         case PCIDevVenIDARC1260:
4400         case PCIDevVenIDARC1261:
4401         case PCIDevVenIDARC1270:
4402         case PCIDevVenIDARC1280:
4403                 type = "SATA 3G";
4404                 break;
4405         case PCIDevVenIDARC1212:
4406         case PCIDevVenIDARC1222:
4407         case PCIDevVenIDARC1380:
4408         case PCIDevVenIDARC1381:
4409         case PCIDevVenIDARC1680:
4410         case PCIDevVenIDARC1681:
4411                 type = "SAS 3G";
4412                 break;
4413         case PCIDevVenIDARC1880:
4414         case PCIDevVenIDARC1882:
4415         case PCIDevVenIDARC1213:
4416         case PCIDevVenIDARC1223:
4417                 if (sub_device_id == ARECA_SUB_DEV_ID_1883)
4418                         type = "SAS 12G";
4419                 else
4420                         type = "SAS 6G";
4421                 break;
4422         case PCIDevVenIDARC1214:
4423                 type = "SATA 6G";
4424                 break;
4425         default:
4426                 type = x_type;
4427                 raid6 = 0;
4428                 break;
4429         }
4430         if(type == x_type)
4431                 return(ENXIO);
4432         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4433                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4434         device_set_desc_copy(dev, buf);
4435         return (BUS_PROBE_DEFAULT);
4436 }
4437 /*
4438 ************************************************************************
4439 ************************************************************************
4440 */
4441 static int arcmsr_shutdown(device_t dev)
4442 {
4443         u_int32_t  i;
4444         u_int32_t intmask_org;
4445         struct CommandControlBlock *srb;
4446         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4447
4448         /* stop adapter background rebuild */
4449         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4450         /* disable all outbound interrupt */
4451         intmask_org = arcmsr_disable_allintr(acb);
4452         arcmsr_stop_adapter_bgrb(acb);
4453         arcmsr_flush_adapter_cache(acb);
4454         /* abort all outstanding command */
4455         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4456         acb->acb_flags &= ~ACB_F_IOP_INITED;
4457         if(acb->srboutstandingcount != 0) {
4458                 /*clear and abort all outbound posted Q*/
4459                 arcmsr_done4abort_postqueue(acb);
4460                 /* talk to iop 331 outstanding command aborted*/
4461                 arcmsr_abort_allcmd(acb);
4462                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4463                         srb = acb->psrb_pool[i];
4464                         if(srb->srb_state == ARCMSR_SRB_START) {
4465                                 srb->srb_state = ARCMSR_SRB_ABORTED;
4466                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4467                                 arcmsr_srb_complete(srb, 1);
4468                         }
4469                 }
4470         }
4471         acb->srboutstandingcount = 0;
4472         acb->workingsrb_doneindex = 0;
4473         acb->workingsrb_startindex = 0;
4474         acb->pktRequestCount = 0;
4475         acb->pktReturnCount = 0;
4476         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4477         return (0);
4478 }
4479 /*
4480 ************************************************************************
4481 ************************************************************************
4482 */
4483 static int arcmsr_detach(device_t dev)
4484 {
4485         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4486         int i;
4487
4488         callout_stop(&acb->devmap_callout);
4489         bus_teardown_intr(dev, acb->irqres, acb->ih);
4490         arcmsr_shutdown(dev);
4491         arcmsr_free_resource(acb);
4492         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4493                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4494         }
4495         bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4496         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4497         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4498         xpt_free_path(acb->ppath);
4499         xpt_bus_deregister(cam_sim_path(acb->psim));
4500         cam_sim_free(acb->psim, TRUE);
4501         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4502         arcmsr_mutex_destroy(acb);
4503         return (0);
4504 }
4505
4506 #ifdef ARCMSR_DEBUG1
4507 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4508 {
4509         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4510                 return;
4511         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4512         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4513         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4514         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4515 }
4516 #endif
4517