sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** SPDX-License-Identifier: BSD-3-Clause
  13 **
  14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  15 **
  16 ** Redistribution and use in source and binary forms, with or without
  17 ** modification, are permitted provided that the following conditions
  18 ** are met:
  19 ** 1. Redistributions of source code must retain the above copyright
  20 **    notice, this list of conditions and the following disclaimer.
  21 ** 2. Redistributions in binary form must reproduce the above copyright
  22 **    notice, this list of conditions and the following disclaimer in the
  23 **    documentation and/or other materials provided with the distribution.
  24 ** 3. The name of the author may not be used to endorse or promote products
  25 **    derived from this software without specific prior written permission.
  26 **
  27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 ********************************************************************************
  38 ** History
  39 **
  40 **    REV#         DATE         NAME        DESCRIPTION
  41 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  42 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  43 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  44 **                                          clean unused function
  45 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  46 **                                          firmware version check
  47 **                                          and firmware update notify for hardware bug fix
  48 **                                          handling if none zero high part physical address
  49 **                                          of srb resource
  50 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  51 **                                          add iop message xfer
  52 **                                          with scsi pass-through command
  53 **                                          add new device id of sas raid adapters
  54 **                                          code fit for SPARC64 & PPC
  55 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  56 **                                          and cause g_vfs_done() read write error
  57 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  58 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  59 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  60 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  61 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  62 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  63 **                                          for any one LUN device failed
  64 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  65 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  66 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  67 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  68 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  69 **              02/14/2011  Ching Huang     Modified pktRequestCount
  70 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  71 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  72 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  73 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  74 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  75 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  76 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  77 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  78 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  79 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  80 ** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
  81 ** 1.30.00.00   11/30/2015  Ching Huang     Added support ARC1203
  82 ** 1.40.00.00   07/11/2017  Ching Huang     Added support ARC1884
  83 ** 1.40.00.01   10/30/2017  Ching Huang     Fixed release memory resource
  84 ******************************************************************************************
  85 */
  86
  87 #include <sys/cdefs.h>
  88 __FBSDID("$FreeBSD$");
  89
  90 #if 0
  91 #define ARCMSR_DEBUG1                   1
  92 #endif
  93 #include <sys/param.h>
  94 #include <sys/systm.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/bus.h>
  98 #include <sys/queue.h>
  99 #include <sys/stat.h>
 100 #include <sys/devicestat.h>
 101 #include <sys/kthread.h>
 102 #include <sys/module.h>
 103 #include <sys/proc.h>
 104 #include <sys/lock.h>
 105 #include <sys/sysctl.h>
 106 #include <sys/poll.h>
 107 #include <sys/ioccom.h>
 108 #include <vm/vm.h>
 109 #include <vm/vm_param.h>
 110 #include <vm/pmap.h>
 111
 112 #include <isa/rtc.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <machine/atomic.h>
 117 #include <sys/conf.h>
 118 #include <sys/rman.h>
 119
 120 #include <cam/cam.h>
 121 #include <cam/cam_ccb.h>
 122 #include <cam/cam_sim.h>
 123 #include <cam/cam_periph.h>
 124 #include <cam/cam_xpt_periph.h>
 125 #include <cam/cam_xpt_sim.h>
 126 #include <cam/cam_debug.h>
 127 #include <cam/scsi/scsi_all.h>
 128 #include <cam/scsi/scsi_message.h>
 129 /*
 130 **************************************************************************
 131 **************************************************************************
 132 */
 133 #include <sys/selinfo.h>
 134 #include <sys/mutex.h>
 135 #include <sys/endian.h>
 136 #include <dev/pci/pcivar.h>
 137 #include <dev/pci/pcireg.h>
 138
 139 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 140
 141 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.40.00.01 2017-10-30"
 142 #include <dev/arcmsr/arcmsr.h>
 143 /*
 144 **************************************************************************
 145 **************************************************************************
 146 */
 147 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 148 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 149 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 150 static int arcmsr_probe(device_t dev);
 151 static int arcmsr_attach(device_t dev);
 152 static int arcmsr_detach(device_t dev);
 153 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 154 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 155 static int arcmsr_shutdown(device_t dev);
 156 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 157 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 158 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 159 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 160 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 161 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 162 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 163 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 164 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 165 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 166 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 167 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 168 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 169 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 170 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 171 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 172 static int arcmsr_resume(device_t dev);
 173 static int arcmsr_suspend(device_t dev);
 174 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 175 static void arcmsr_polling_devmap(void *arg);
 176 static void arcmsr_srb_timeout(void *arg);
 177 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 178 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
 179 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
 180 #ifdef ARCMSR_DEBUG1
 181 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 182 #endif
 183 /*
 184 **************************************************************************
 185 **************************************************************************
 186 */
 187 static void UDELAY(u_int32_t us) { DELAY(us); }
 188 /*
 189 **************************************************************************
 190 **************************************************************************
 191 */
 192 static bus_dmamap_callback_t arcmsr_map_free_srb;
 193 static bus_dmamap_callback_t arcmsr_execute_srb;
 194 /*
 195 **************************************************************************
 196 **************************************************************************
 197 */
 198 static d_open_t arcmsr_open;
 199 static d_close_t arcmsr_close;
 200 static d_ioctl_t arcmsr_ioctl;
 201
 202 static device_method_t arcmsr_methods[]={
 203         DEVMETHOD(device_probe,         arcmsr_probe),
 204         DEVMETHOD(device_attach,        arcmsr_attach),
 205         DEVMETHOD(device_detach,        arcmsr_detach),
 206         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 207         DEVMETHOD(device_suspend,       arcmsr_suspend),
 208         DEVMETHOD(device_resume,        arcmsr_resume),
 209         DEVMETHOD_END
 210 };
 211
 212 static driver_t arcmsr_driver={
 213         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 214 };
 215
 216 static devclass_t arcmsr_devclass;
 217 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 218 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 219 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 220 #ifndef BUS_DMA_COHERENT
 221         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 222 #endif
 223 static struct cdevsw arcmsr_cdevsw={
 224                 .d_version = D_VERSION,
 225                 .d_open    = arcmsr_open,       /* open     */
 226                 .d_close   = arcmsr_close,      /* close    */
 227                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 228                 .d_name    = "arcmsr",          /* name     */
 229         };
 230 /*
 231 **************************************************************************
 232 **************************************************************************
 233 */
 234 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 235 {
 236         int     unit = dev2unit(dev);
 237         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 238
 239         if (acb == NULL) {
 240                 return ENXIO;
 241         }
 242         return (0);
 243 }
 244 /*
 245 **************************************************************************
 246 **************************************************************************
 247 */
 248 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 249 {
 250         int     unit = dev2unit(dev);
 251         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 252
 253         if (acb == NULL) {
 254                 return ENXIO;
 255         }
 256         return 0;
 257 }
 258 /*
 259 **************************************************************************
 260 **************************************************************************
 261 */
 262 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 263 {
 264         int     unit = dev2unit(dev);
 265         struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 266
 267         if (acb == NULL) {
 268                 return ENXIO;
 269         }
 270         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 271 }
 272 /*
 273 **********************************************************************
 274 **********************************************************************
 275 */
 276 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 277 {
 278         u_int32_t intmask_org = 0;
 279
 280         switch (acb->adapter_type) {
 281         case ACB_ADAPTER_TYPE_A: {
 282                         /* disable all outbound interrupt */
 283                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 284                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 285                 }
 286                 break;
 287         case ACB_ADAPTER_TYPE_B: {
 288                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 289                         /* disable all outbound interrupt */
 290                         intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
 291                                                 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 292                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
 293                 }
 294                 break;
 295         case ACB_ADAPTER_TYPE_C: {
 296                         /* disable all outbound interrupt */
 297                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 298                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 299                 }
 300                 break;
 301         case ACB_ADAPTER_TYPE_D: {
 302                         /* disable all outbound interrupt */
 303                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 304                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 305                 }
 306                 break;
 307         case ACB_ADAPTER_TYPE_E: {
 308                         /* disable all outbound interrupt */
 309                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 310                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
 311                 }
 312                 break;
 313         }
 314         return (intmask_org);
 315 }
 316 /*
 317 **********************************************************************
 318 **********************************************************************
 319 */
 320 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 321 {
 322         u_int32_t mask;
 323
 324         switch (acb->adapter_type) {
 325         case ACB_ADAPTER_TYPE_A: {
 326                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 327                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 328                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 329                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 330                 }
 331                 break;
 332         case ACB_ADAPTER_TYPE_B: {
 333                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 334                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 335                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 336                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 337                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 338                 }
 339                 break;
 340         case ACB_ADAPTER_TYPE_C: {
 341                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 342                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 343                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 344                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 345                 }
 346                 break;
 347         case ACB_ADAPTER_TYPE_D: {
 348                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 349                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 350                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 351                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 352                         acb->outbound_int_enable = mask;
 353                 }
 354                 break;
 355         case ACB_ADAPTER_TYPE_E: {
 356                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 357                         mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
 358                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
 359                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 360                 }
 361                 break;
 362         }
 363 }
 364 /*
 365 **********************************************************************
 366 **********************************************************************
 367 */
 368 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 369 {
 370         u_int32_t Index;
 371         u_int8_t Retries = 0x00;
 372
 373         do {
 374                 for(Index=0; Index < 100; Index++) {
 375                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 376                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 377                                 return TRUE;
 378                         }
 379                         UDELAY(10000);
 380                 }/*max 1 seconds*/
 381         }while(Retries++ < 20);/*max 20 sec*/
 382         return (FALSE);
 383 }
 384 /*
 385 **********************************************************************
 386 **********************************************************************
 387 */
 388 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 389 {
 390         u_int32_t Index;
 391         u_int8_t Retries = 0x00;
 392         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 393
 394         do {
 395                 for(Index=0; Index < 100; Index++) {
 396                         if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 397                                 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 398                                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 399                                 return TRUE;
 400                         }
 401                         UDELAY(10000);
 402                 }/*max 1 seconds*/
 403         }while(Retries++ < 20);/*max 20 sec*/
 404         return (FALSE);
 405 }
 406 /*
 407 **********************************************************************
 408 **********************************************************************
 409 */
 410 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 411 {
 412         u_int32_t Index;
 413         u_int8_t Retries = 0x00;
 414
 415         do {
 416                 for(Index=0; Index < 100; Index++) {
 417                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 418                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 419                                 return TRUE;
 420                         }
 421                         UDELAY(10000);
 422                 }/*max 1 seconds*/
 423         }while(Retries++ < 20);/*max 20 sec*/
 424         return (FALSE);
 425 }
 426 /*
 427 **********************************************************************
 428 **********************************************************************
 429 */
 430 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 431 {
 432         u_int32_t Index;
 433         u_int8_t Retries = 0x00;
 434
 435         do {
 436                 for(Index=0; Index < 100; Index++) {
 437                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 438                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 439                                 return TRUE;
 440                         }
 441                         UDELAY(10000);
 442                 }/*max 1 seconds*/
 443         }while(Retries++ < 20);/*max 20 sec*/
 444         return (FALSE);
 445 }
 446 /*
 447 **********************************************************************
 448 **********************************************************************
 449 */
 450 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb)
 451 {
 452         u_int32_t Index, read_doorbell;
 453         u_int8_t Retries = 0x00;
 454
 455         do {
 456                 for(Index=0; Index < 100; Index++) {
 457                         read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
 458                         if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
 459                                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/
 460                                 acb->in_doorbell = read_doorbell;
 461                                 return TRUE;
 462                         }
 463                         UDELAY(10000);
 464                 }/*max 1 seconds*/
 465         }while(Retries++ < 20);/*max 20 sec*/
 466         return (FALSE);
 467 }
 468 /*
 469 ************************************************************************
 470 ************************************************************************
 471 */
 472 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 473 {
 474         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 475
 476         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 477         do {
 478                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 479                         break;
 480                 } else {
 481                         retry_count--;
 482                 }
 483         }while(retry_count != 0);
 484 }
 485 /*
 486 ************************************************************************
 487 ************************************************************************
 488 */
 489 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 490 {
 491         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 492         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 493
 494         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 495         do {
 496                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 497                         break;
 498                 } else {
 499                         retry_count--;
 500                 }
 501         }while(retry_count != 0);
 502 }
 503 /*
 504 ************************************************************************
 505 ************************************************************************
 506 */
 507 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 508 {
 509         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 510
 511         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 512         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 513         do {
 514                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 515                         break;
 516                 } else {
 517                         retry_count--;
 518                 }
 519         }while(retry_count != 0);
 520 }
 521 /*
 522 ************************************************************************
 523 ************************************************************************
 524 */
 525 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 526 {
 527         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 528
 529         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 530         do {
 531                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 532                         break;
 533                 } else {
 534                         retry_count--;
 535                 }
 536         }while(retry_count != 0);
 537 }
 538 /*
 539 ************************************************************************
 540 ************************************************************************
 541 */
 542 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb)
 543 {
 544         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 545
 546         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 547         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 548         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 549         do {
 550                 if(arcmsr_hbe_wait_msgint_ready(acb)) {
 551                         break;
 552                 } else {
 553                         retry_count--;
 554                 }
 555         }while(retry_count != 0);
 556 }
 557 /*
 558 ************************************************************************
 559 ************************************************************************
 560 */
 561 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 562 {
 563         switch (acb->adapter_type) {
 564         case ACB_ADAPTER_TYPE_A: {
 565                         arcmsr_flush_hba_cache(acb);
 566                 }
 567                 break;
 568         case ACB_ADAPTER_TYPE_B: {
 569                         arcmsr_flush_hbb_cache(acb);
 570                 }
 571                 break;
 572         case ACB_ADAPTER_TYPE_C: {
 573                         arcmsr_flush_hbc_cache(acb);
 574                 }
 575                 break;
 576         case ACB_ADAPTER_TYPE_D: {
 577                         arcmsr_flush_hbd_cache(acb);
 578                 }
 579                 break;
 580         case ACB_ADAPTER_TYPE_E: {
 581                         arcmsr_flush_hbe_cache(acb);
 582                 }
 583                 break;
 584         }
 585 }
 586 /*
 587 *******************************************************************************
 588 *******************************************************************************
 589 */
 590 static int arcmsr_suspend(device_t dev)
 591 {
 592         struct AdapterControlBlock      *acb = device_get_softc(dev);
 593
 594         /* flush controller */
 595         arcmsr_iop_parking(acb);
 596         /* disable all outbound interrupt */
 597         arcmsr_disable_allintr(acb);
 598         return(0);
 599 }
 600 /*
 601 *******************************************************************************
 602 *******************************************************************************
 603 */
 604 static int arcmsr_resume(device_t dev)
 605 {
 606         struct AdapterControlBlock      *acb = device_get_softc(dev);
 607
 608         arcmsr_iop_init(acb);
 609         return(0);
 610 }
 611 /*
 612 *********************************************************************************
 613 *********************************************************************************
 614 */
 615 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 616 {
 617         struct AdapterControlBlock *acb;
 618         u_int8_t target_id, target_lun;
 619         struct cam_sim *sim;
 620
 621         sim = (struct cam_sim *) cb_arg;
 622         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 623         switch (code) {
 624         case AC_LOST_DEVICE:
 625                 target_id = xpt_path_target_id(path);
 626                 target_lun = xpt_path_lun_id(path);
 627                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 628                         break;
 629                 }
 630         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 631                 break;
 632         default:
 633                 break;
 634         }
 635 }
 636 /*
 637 **********************************************************************
 638 **********************************************************************
 639 */
 640 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 641 {
 642         union ccb *pccb = srb->pccb;
 643
 644         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 645         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 646         if(pccb->csio.sense_len) {
 647                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 648                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 649                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 650                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 651                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 652         }
 653 }
 654 /*
 655 *********************************************************************
 656 *********************************************************************
 657 */
 658 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 659 {
 660         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 661         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 662                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 663         }
 664 }
 665 /*
 666 *********************************************************************
 667 *********************************************************************
 668 */
 669 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 670 {
 671         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 672         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 673         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 674                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 675         }
 676 }
 677 /*
 678 *********************************************************************
 679 *********************************************************************
 680 */
 681 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 682 {
 683         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 684         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 685         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 686                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 687         }
 688 }
 689 /*
 690 *********************************************************************
 691 *********************************************************************
 692 */
 693 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 694 {
 695         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 696         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 697                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 698         }
 699 }
 700 /*
 701 *********************************************************************
 702 *********************************************************************
 703 */
 704 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb)
 705 {
 706         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 707         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
 708         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
 709         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
 710                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 711         }
 712 }
 713 /*
 714 *********************************************************************
 715 *********************************************************************
 716 */
 717 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 718 {
 719         switch (acb->adapter_type) {
 720         case ACB_ADAPTER_TYPE_A: {
 721                         arcmsr_abort_hba_allcmd(acb);
 722                 }
 723                 break;
 724         case ACB_ADAPTER_TYPE_B: {
 725                         arcmsr_abort_hbb_allcmd(acb);
 726                 }
 727                 break;
 728         case ACB_ADAPTER_TYPE_C: {
 729                         arcmsr_abort_hbc_allcmd(acb);
 730                 }
 731                 break;
 732         case ACB_ADAPTER_TYPE_D: {
 733                         arcmsr_abort_hbd_allcmd(acb);
 734                 }
 735                 break;
 736         case ACB_ADAPTER_TYPE_E: {
 737                         arcmsr_abort_hbe_allcmd(acb);
 738                 }
 739                 break;
 740         }
 741 }
 742 /*
 743 **********************************************************************
 744 **********************************************************************
 745 */
 746 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 747 {
 748         struct AdapterControlBlock *acb = srb->acb;
 749         union ccb *pccb = srb->pccb;
 750
 751         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 752                 callout_stop(&srb->ccb_callout);
 753         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 754                 bus_dmasync_op_t op;
 755
 756                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 757                         op = BUS_DMASYNC_POSTREAD;
 758                 } else {
 759                         op = BUS_DMASYNC_POSTWRITE;
 760                 }
 761                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 762                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 763         }
 764         if(stand_flag == 1) {
 765                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 766                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 767                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 768                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 769                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 770                 }
 771         }
 772         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 773                 arcmsr_free_srb(srb);
 774         acb->pktReturnCount++;
 775         xpt_done(pccb);
 776 }
 777 /*
 778 **************************************************************************
 779 **************************************************************************
 780 */
 781 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 782 {
 783         int target, lun;
 784
 785         target = srb->pccb->ccb_h.target_id;
 786         lun = srb->pccb->ccb_h.target_lun;
 787         if(error == FALSE) {
 788                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 789                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 790                 }
 791                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 792                 arcmsr_srb_complete(srb, 1);
 793         } else {
 794                 switch(srb->arcmsr_cdb.DeviceStatus) {
 795                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 796                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 797                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 798                                 }
 799                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 800                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 801                                 arcmsr_srb_complete(srb, 1);
 802                         }
 803                         break;
 804                 case ARCMSR_DEV_ABORTED:
 805                 case ARCMSR_DEV_INIT_FAIL: {
 806                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 807                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 808                                 arcmsr_srb_complete(srb, 1);
 809                         }
 810                         break;
 811                 case SCSISTAT_CHECK_CONDITION: {
 812                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 813                                 arcmsr_report_sense_info(srb);
 814                                 arcmsr_srb_complete(srb, 1);
 815                         }
 816                         break;
 817                 default:
 818                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 819                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 820                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 821                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 822                         /*unknown error or crc error just for retry*/
 823                         arcmsr_srb_complete(srb, 1);
 824                         break;
 825                 }
 826         }
 827 }
 828 /*
 829 **************************************************************************
 830 **************************************************************************
 831 */
 832 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 833 {
 834         struct CommandControlBlock *srb;
 835
 836         /* check if command done with no error*/
 837         switch (acb->adapter_type) {
 838         case ACB_ADAPTER_TYPE_A:
 839         case ACB_ADAPTER_TYPE_B:
 840                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 841                 break;
 842         case ACB_ADAPTER_TYPE_C:
 843         case ACB_ADAPTER_TYPE_D:
 844                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 845                 break;
 846         case ACB_ADAPTER_TYPE_E:
 847                 srb = acb->psrb_pool[flag_srb];
 848                 break;
 849         default:
 850                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 851                 break;
 852         }
 853         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 854                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 855                         arcmsr_free_srb(srb);
 856                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 857                         return;
 858                 }
 859                 printf("arcmsr%d: return srb has been completed\n"
 860                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 861                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 862                 return;
 863         }
 864         arcmsr_report_srb_state(acb, srb, error);
 865 }
 866 /*
 867 **************************************************************************
 868 **************************************************************************
 869 */
 870 static void     arcmsr_srb_timeout(void *arg)
 871 {
 872         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 873         struct AdapterControlBlock *acb;
 874         int target, lun;
 875         u_int8_t cmd;
 876
 877         target = srb->pccb->ccb_h.target_id;
 878         lun = srb->pccb->ccb_h.target_lun;
 879         acb = srb->acb;
 880         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 881         if(srb->srb_state == ARCMSR_SRB_START)
 882         {
 883                 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
 884                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 885                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 886                 arcmsr_srb_complete(srb, 1);
 887                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 888                                  acb->pci_unit, target, lun, cmd, srb);
 889         }
 890         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 891 #ifdef ARCMSR_DEBUG1
 892         arcmsr_dump_data(acb);
 893 #endif
 894 }
 895
 896 /*
 897 **********************************************************************
 898 **********************************************************************
 899 */
 900 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 901 {
 902         int i=0;
 903         u_int32_t flag_srb;
 904         u_int16_t error;
 905
 906         switch (acb->adapter_type) {
 907         case ACB_ADAPTER_TYPE_A: {
 908                         u_int32_t outbound_intstatus;
 909
 910                         /*clear and abort all outbound posted Q*/
 911                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 912                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 913                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 914                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 915                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 916                         }
 917                 }
 918                 break;
 919         case ACB_ADAPTER_TYPE_B: {
 920                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 921
 922                         /*clear all outbound posted Q*/
 923                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 924                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 925                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 926                                         phbbmu->done_qbuffer[i] = 0;
 927                                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 928                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 929                                 }
 930                                 phbbmu->post_qbuffer[i] = 0;
 931                         }/*drain reply FIFO*/
 932                         phbbmu->doneq_index = 0;
 933                         phbbmu->postq_index = 0;
 934                 }
 935                 break;
 936         case ACB_ADAPTER_TYPE_C: {
 937
 938                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 939                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 940                                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 941                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 942                         }
 943                 }
 944                 break;
 945         case ACB_ADAPTER_TYPE_D: {
 946                         arcmsr_hbd_postqueue_isr(acb);
 947                 }
 948                 break;
 949         case ACB_ADAPTER_TYPE_E: {
 950                         arcmsr_hbe_postqueue_isr(acb);
 951                 }
 952                 break;
 953         }
 954 }
 955 /*
 956 ****************************************************************************
 957 ****************************************************************************
 958 */
 959 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 960 {
 961         struct CommandControlBlock *srb;
 962         u_int32_t intmask_org;
 963         u_int32_t i=0;
 964
 965         if(acb->srboutstandingcount>0) {
 966                 /* disable all outbound interrupt */
 967                 intmask_org = arcmsr_disable_allintr(acb);
 968                 /*clear and abort all outbound posted Q*/
 969                 arcmsr_done4abort_postqueue(acb);
 970                 /* talk to iop 331 outstanding command aborted*/
 971                 arcmsr_abort_allcmd(acb);
 972                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 973                         srb = acb->psrb_pool[i];
 974                         if(srb->srb_state == ARCMSR_SRB_START) {
 975                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 976                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 977                                 arcmsr_srb_complete(srb, 1);
 978                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
 979                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 980                                                 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 981                         }
 982                 }
 983                 /* enable all outbound interrupt */
 984                 arcmsr_enable_allintr(acb, intmask_org);
 985         }
 986         acb->srboutstandingcount = 0;
 987         acb->workingsrb_doneindex = 0;
 988         acb->workingsrb_startindex = 0;
 989         acb->pktRequestCount = 0;
 990         acb->pktReturnCount = 0;
 991 }
 992 /*
 993 **********************************************************************
 994 **********************************************************************
 995 */
 996 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 997                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 998 {
 999         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
1000         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
1001         u_int32_t address_lo, address_hi;
1002         union ccb *pccb = srb->pccb;
1003         struct ccb_scsiio *pcsio = &pccb->csio;
1004         u_int32_t arccdbsize = 0x30;
1005
1006         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1007         arcmsr_cdb->Bus = 0;
1008         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
1009         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
1010         arcmsr_cdb->Function = 1;
1011         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1012         bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1013         if(nseg != 0) {
1014                 struct AdapterControlBlock *acb = srb->acb;
1015                 bus_dmasync_op_t op;
1016                 u_int32_t length, i, cdb_sgcount = 0;
1017
1018                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1019                         op = BUS_DMASYNC_PREREAD;
1020                 } else {
1021                         op = BUS_DMASYNC_PREWRITE;
1022                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1023                         srb->srb_flags |= SRB_FLAG_WRITE;
1024                 }
1025                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1026                 for(i=0; i < nseg; i++) {
1027                         /* Get the physical address of the current data pointer */
1028                         length = arcmsr_htole32(dm_segs[i].ds_len);
1029                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1030                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1031                         if(address_hi == 0) {
1032                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1033                                 pdma_sg->address = address_lo;
1034                                 pdma_sg->length = length;
1035                                 psge += sizeof(struct SG32ENTRY);
1036                                 arccdbsize += sizeof(struct SG32ENTRY);
1037                         } else {
1038                                 u_int32_t sg64s_size = 0, tmplength = length;
1039
1040                                 while(1) {
1041                                         u_int64_t span4G, length0;
1042                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1043
1044                                         span4G = (u_int64_t)address_lo + tmplength;
1045                                         pdma_sg->addresshigh = address_hi;
1046                                         pdma_sg->address = address_lo;
1047                                         if(span4G > 0x100000000) {
1048                                                 /*see if cross 4G boundary*/
1049                                                 length0 = 0x100000000-address_lo;
1050                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1051                                                 address_hi = address_hi+1;
1052                                                 address_lo = 0;
1053                                                 tmplength = tmplength - (u_int32_t)length0;
1054                                                 sg64s_size += sizeof(struct SG64ENTRY);
1055                                                 psge += sizeof(struct SG64ENTRY);
1056                                                 cdb_sgcount++;
1057                                         } else {
1058                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1059                                                 sg64s_size += sizeof(struct SG64ENTRY);
1060                                                 psge += sizeof(struct SG64ENTRY);
1061                                                 break;
1062                                         }
1063                                 }
1064                                 arccdbsize += sg64s_size;
1065                         }
1066                         cdb_sgcount++;
1067                 }
1068                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1069                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1070                 if( arccdbsize > 256) {
1071                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1072                 }
1073         } else {
1074                 arcmsr_cdb->DataLength = 0;
1075         }
1076         srb->arc_cdb_size = arccdbsize;
1077         arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1078 }
1079 /*
1080 **************************************************************************
1081 **************************************************************************
1082 */
1083 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1084 {
1085         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1086         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1087
1088         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1089         atomic_add_int(&acb->srboutstandingcount, 1);
1090         srb->srb_state = ARCMSR_SRB_START;
1091
1092         switch (acb->adapter_type) {
1093         case ACB_ADAPTER_TYPE_A: {
1094                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1095                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1096                         } else {
1097                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1098                         }
1099                 }
1100                 break;
1101         case ACB_ADAPTER_TYPE_B: {
1102                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1103                         int ending_index, index;
1104
1105                         index = phbbmu->postq_index;
1106                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1107                         phbbmu->post_qbuffer[ending_index] = 0;
1108                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1109                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1110                         } else {
1111                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1112                         }
1113                         index++;
1114                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1115                         phbbmu->postq_index = index;
1116                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1117                 }
1118                 break;
1119         case ACB_ADAPTER_TYPE_C: {
1120                         u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1121
1122                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1123                         ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1124                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1125                         if(cdb_phyaddr_hi32)
1126                         {
1127                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1128                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1129                         }
1130                         else
1131                         {
1132                                 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1133                         }
1134                 }
1135                 break;
1136         case ACB_ADAPTER_TYPE_D: {
1137                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1138                         u_int16_t index_stripped;
1139                         u_int16_t postq_index;
1140                         struct InBound_SRB *pinbound_srb;
1141
1142                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1143                         postq_index = phbdmu->postq_index;
1144                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1145                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1146                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1147                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1148                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1149                         if (postq_index & 0x4000) {
1150                                 index_stripped = postq_index & 0xFF;
1151                                 index_stripped += 1;
1152                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1153                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1154                         } else {
1155                                 index_stripped = postq_index;
1156                                 index_stripped += 1;
1157                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1158                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1159                         }
1160                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1161                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1162                 }
1163                 break;
1164         case ACB_ADAPTER_TYPE_E: {
1165                         u_int32_t ccb_post_stamp, arc_cdb_size;
1166
1167                         arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1168                         ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
1169                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
1170                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
1171                 }
1172                 break;
1173         }
1174 }
1175 /*
1176 ************************************************************************
1177 ************************************************************************
1178 */
1179 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1180 {
1181         struct QBUFFER *qbuffer=NULL;
1182
1183         switch (acb->adapter_type) {
1184         case ACB_ADAPTER_TYPE_A: {
1185                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1186
1187                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1188                 }
1189                 break;
1190         case ACB_ADAPTER_TYPE_B: {
1191                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1192
1193                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1194                 }
1195                 break;
1196         case ACB_ADAPTER_TYPE_C: {
1197                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1198
1199                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1200                 }
1201                 break;
1202         case ACB_ADAPTER_TYPE_D: {
1203                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1204
1205                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1206                 }
1207                 break;
1208         case ACB_ADAPTER_TYPE_E: {
1209                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1210
1211                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1212                 }
1213                 break;
1214         }
1215         return(qbuffer);
1216 }
1217 /*
1218 ************************************************************************
1219 ************************************************************************
1220 */
1221 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1222 {
1223         struct QBUFFER *qbuffer = NULL;
1224
1225         switch (acb->adapter_type) {
1226         case ACB_ADAPTER_TYPE_A: {
1227                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1228
1229                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1230                 }
1231                 break;
1232         case ACB_ADAPTER_TYPE_B: {
1233                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1234
1235                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1236                 }
1237                 break;
1238         case ACB_ADAPTER_TYPE_C: {
1239                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1240
1241                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1242                 }
1243                 break;
1244         case ACB_ADAPTER_TYPE_D: {
1245                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1246
1247                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1248                 }
1249                 break;
1250         case ACB_ADAPTER_TYPE_E: {
1251                         struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
1252
1253                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1254                 }
1255                 break;
1256         }
1257         return(qbuffer);
1258 }
1259 /*
1260 **************************************************************************
1261 **************************************************************************
1262 */
1263 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1264 {
1265         switch (acb->adapter_type) {
1266         case ACB_ADAPTER_TYPE_A: {
1267                         /* let IOP know data has been read */
1268                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1269                 }
1270                 break;
1271         case ACB_ADAPTER_TYPE_B: {
1272                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1273                         /* let IOP know data has been read */
1274                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1275                 }
1276                 break;
1277         case ACB_ADAPTER_TYPE_C: {
1278                         /* let IOP know data has been read */
1279                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1280                 }
1281                 break;
1282         case ACB_ADAPTER_TYPE_D: {
1283                         /* let IOP know data has been read */
1284                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1285                 }
1286                 break;
1287         case ACB_ADAPTER_TYPE_E: {
1288                         /* let IOP know data has been read */
1289                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1290                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1291                 }
1292                 break;
1293         }
1294 }
1295 /*
1296 **************************************************************************
1297 **************************************************************************
1298 */
1299 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1300 {
1301         switch (acb->adapter_type) {
1302         case ACB_ADAPTER_TYPE_A: {
1303                         /*
1304                         ** push inbound doorbell tell iop, driver data write ok
1305                         ** and wait reply on next hwinterrupt for next Qbuffer post
1306                         */
1307                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1308                 }
1309                 break;
1310         case ACB_ADAPTER_TYPE_B: {
1311                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1312                         /*
1313                         ** push inbound doorbell tell iop, driver data write ok
1314                         ** and wait reply on next hwinterrupt for next Qbuffer post
1315                         */
1316                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1317                 }
1318                 break;
1319         case ACB_ADAPTER_TYPE_C: {
1320                         /*
1321                         ** push inbound doorbell tell iop, driver data write ok
1322                         ** and wait reply on next hwinterrupt for next Qbuffer post
1323                         */
1324                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1325                 }
1326                 break;
1327         case ACB_ADAPTER_TYPE_D: {
1328                         /*
1329                         ** push inbound doorbell tell iop, driver data write ok
1330                         ** and wait reply on next hwinterrupt for next Qbuffer post
1331                         */
1332                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1333                 }
1334                 break;
1335         case ACB_ADAPTER_TYPE_E: {
1336                         /*
1337                         ** push inbound doorbell tell iop, driver data write ok
1338                         ** and wait reply on next hwinterrupt for next Qbuffer post
1339                         */
1340                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
1341                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1342                 }
1343                 break;
1344         }
1345 }
1346 /*
1347 ************************************************************************
1348 ************************************************************************
1349 */
1350 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1351 {
1352         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1353         CHIP_REG_WRITE32(HBA_MessageUnit,
1354                 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1355         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1356                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1357                         , acb->pci_unit);
1358         }
1359 }
1360 /*
1361 ************************************************************************
1362 ************************************************************************
1363 */
1364 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1365 {
1366         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1367         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1368         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1369         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1370                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1371                         , acb->pci_unit);
1372         }
1373 }
1374 /*
1375 ************************************************************************
1376 ************************************************************************
1377 */
1378 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1379 {
1380         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1381         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1382         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1383         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1384                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1385         }
1386 }
1387 /*
1388 ************************************************************************
1389 ************************************************************************
1390 */
1391 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1392 {
1393         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1394         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1395         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1396                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1397         }
1398 }
1399 /*
1400 ************************************************************************
1401 ************************************************************************
1402 */
1403 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb)
1404 {
1405         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1406         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1407         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1408         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
1409         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
1410                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1411         }
1412 }
1413 /*
1414 ************************************************************************
1415 ************************************************************************
1416 */
1417 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1418 {
1419         switch (acb->adapter_type) {
1420         case ACB_ADAPTER_TYPE_A: {
1421                         arcmsr_stop_hba_bgrb(acb);
1422                 }
1423                 break;
1424         case ACB_ADAPTER_TYPE_B: {
1425                         arcmsr_stop_hbb_bgrb(acb);
1426                 }
1427                 break;
1428         case ACB_ADAPTER_TYPE_C: {
1429                         arcmsr_stop_hbc_bgrb(acb);
1430                 }
1431                 break;
1432         case ACB_ADAPTER_TYPE_D: {
1433                         arcmsr_stop_hbd_bgrb(acb);
1434                 }
1435                 break;
1436         case ACB_ADAPTER_TYPE_E: {
1437                         arcmsr_stop_hbe_bgrb(acb);
1438                 }
1439                 break;
1440         }
1441 }
1442 /*
1443 ************************************************************************
1444 ************************************************************************
1445 */
1446 static void arcmsr_poll(struct cam_sim *psim)
1447 {
1448         struct AdapterControlBlock *acb;
1449         int     mutex;
1450
1451         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1452         mutex = mtx_owned(&acb->isr_lock);
1453         if( mutex == 0 )
1454                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1455         arcmsr_interrupt(acb);
1456         if( mutex == 0 )
1457                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1458 }
1459 /*
1460 **************************************************************************
1461 **************************************************************************
1462 */
1463 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1464         struct QBUFFER *prbuffer) {
1465
1466         u_int8_t *pQbuffer;
1467         u_int8_t *buf1 = NULL;
1468         u_int32_t *iop_data, *buf2 = NULL;
1469         u_int32_t iop_len, data_len;
1470
1471         iop_data = (u_int32_t *)prbuffer->data;
1472         iop_len = (u_int32_t)prbuffer->data_len;
1473         if ( iop_len > 0 )
1474         {
1475                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1476                 buf2 = (u_int32_t *)buf1;
1477                 if( buf1 == NULL)
1478                         return (0);
1479                 data_len = iop_len;
1480                 while(data_len >= 4)
1481                 {
1482                         *buf2++ = *iop_data++;
1483                         data_len -= 4;
1484                 }
1485                 if(data_len)
1486                         *buf2 = *iop_data;
1487                 buf2 = (u_int32_t *)buf1;
1488         }
1489         while (iop_len > 0) {
1490                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1491                 *pQbuffer = *buf1;
1492                 acb->rqbuf_lastindex++;
1493                 /* if last, index number set it to 0 */
1494                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1495                 buf1++;
1496                 iop_len--;
1497         }
1498         if(buf2)
1499                 free( (u_int8_t *)buf2, M_DEVBUF);
1500         /* let IOP know data has been read */
1501         arcmsr_iop_message_read(acb);
1502         return (1);
1503 }
1504 /*
1505 **************************************************************************
1506 **************************************************************************
1507 */
1508 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1509         struct QBUFFER *prbuffer) {
1510
1511         u_int8_t *pQbuffer;
1512         u_int8_t *iop_data;
1513         u_int32_t iop_len;
1514
1515         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1516                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1517         }
1518         iop_data = (u_int8_t *)prbuffer->data;
1519         iop_len = (u_int32_t)prbuffer->data_len;
1520         while (iop_len > 0) {
1521                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1522                 *pQbuffer = *iop_data;
1523                 acb->rqbuf_lastindex++;
1524                 /* if last, index number set it to 0 */
1525                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1526                 iop_data++;
1527                 iop_len--;
1528         }
1529         /* let IOP know data has been read */
1530         arcmsr_iop_message_read(acb);
1531         return (1);
1532 }
1533 /*
1534 **************************************************************************
1535 **************************************************************************
1536 */
1537 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1538 {
1539         struct QBUFFER *prbuffer;
1540         int my_empty_len;
1541
1542         /*check this iop data if overflow my rqbuffer*/
1543         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1544         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1545         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1546                 (ARCMSR_MAX_QBUFFER-1);
1547         if(my_empty_len >= prbuffer->data_len) {
1548                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1549                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1550         } else {
1551                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1552         }
1553         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1554 }
1555 /*
1556 **********************************************************************
1557 **********************************************************************
1558 */
1559 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1560 {
1561         u_int8_t *pQbuffer;
1562         struct QBUFFER *pwbuffer;
1563         u_int8_t *buf1 = NULL;
1564         u_int32_t *iop_data, *buf2 = NULL;
1565         u_int32_t allxfer_len = 0, data_len;
1566
1567         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1568                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1569                 buf2 = (u_int32_t *)buf1;
1570                 if( buf1 == NULL)
1571                         return;
1572
1573                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1574                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1575                 iop_data = (u_int32_t *)pwbuffer->data;
1576                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1577                         && (allxfer_len < 124)) {
1578                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1579                         *buf1 = *pQbuffer;
1580                         acb->wqbuf_firstindex++;
1581                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1582                         buf1++;
1583                         allxfer_len++;
1584                 }
1585                 pwbuffer->data_len = allxfer_len;
1586                 data_len = allxfer_len;
1587                 buf1 = (u_int8_t *)buf2;
1588                 while(data_len >= 4)
1589                 {
1590                         *iop_data++ = *buf2++;
1591                         data_len -= 4;
1592                 }
1593                 if(data_len)
1594                         *iop_data = *buf2;
1595                 free( buf1, M_DEVBUF);
1596                 arcmsr_iop_message_wrote(acb);
1597         }
1598 }
1599 /*
1600 **********************************************************************
1601 **********************************************************************
1602 */
1603 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1604 {
1605         u_int8_t *pQbuffer;
1606         struct QBUFFER *pwbuffer;
1607         u_int8_t *iop_data;
1608         int32_t allxfer_len=0;
1609
1610         if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) {
1611                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1612                 return;
1613         }
1614         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1615                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1616                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1617                 iop_data = (u_int8_t *)pwbuffer->data;
1618                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1619                         && (allxfer_len < 124)) {
1620                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1621                         *iop_data = *pQbuffer;
1622                         acb->wqbuf_firstindex++;
1623                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1624                         iop_data++;
1625                         allxfer_len++;
1626                 }
1627                 pwbuffer->data_len = allxfer_len;
1628                 arcmsr_iop_message_wrote(acb);
1629         }
1630 }
1631 /*
1632 **************************************************************************
1633 **************************************************************************
1634 */
1635 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1636 {
1637         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1638         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1639         /*
1640         *****************************************************************
1641         **   check if there are any mail packages from user space program
1642         **   in my post bag, now is the time to send them into Areca's firmware
1643         *****************************************************************
1644         */
1645         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1646                 arcmsr_Write_data_2iop_wqbuffer(acb);
1647         }
1648         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1649                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1650         }
1651         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1652 }
1653 /*
1654 **************************************************************************
1655 **************************************************************************
1656 */
1657 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1658 {
1659 /*
1660         if (ccb->ccb_h.status != CAM_REQ_CMP)
1661                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1662                         "failure status=%x\n", ccb->ccb_h.target_id,
1663                         ccb->ccb_h.target_lun, ccb->ccb_h.status);
1664         else
1665                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1666 */
1667         xpt_free_path(ccb->ccb_h.path);
1668         xpt_free_ccb(ccb);
1669 }
1670
1671 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1672 {
1673         struct cam_path     *path;
1674         union ccb           *ccb;
1675
1676         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1677                         return;
1678         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1679         {
1680                 xpt_free_ccb(ccb);
1681                 return;
1682         }
1683 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1684         bzero(ccb, sizeof(union ccb));
1685         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1686         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1687         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1688         ccb->crcn.flags = CAM_FLAG_NONE;
1689         xpt_action(ccb);
1690 }
1691
1692
1693 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1694 {
1695         struct CommandControlBlock *srb;
1696         u_int32_t intmask_org;
1697         int i;
1698
1699         /* disable all outbound interrupts */
1700         intmask_org = arcmsr_disable_allintr(acb);
1701         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1702         {
1703                 srb = acb->psrb_pool[i];
1704                 if (srb->srb_state == ARCMSR_SRB_START)
1705                 {
1706                         if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1707                         {
1708                                 srb->srb_state = ARCMSR_SRB_ABORTED;
1709                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1710                                 arcmsr_srb_complete(srb, 1);
1711                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1712                         }
1713                 }
1714         }
1715         /* enable outbound Post Queue, outbound doorbell Interrupt */
1716         arcmsr_enable_allintr(acb, intmask_org);
1717 }
1718 /*
1719 **************************************************************************
1720 **************************************************************************
1721 */
1722 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1723         u_int32_t       devicemap;
1724         u_int32_t       target, lun;
1725         u_int32_t       deviceMapCurrent[4]={0};
1726         u_int8_t        *pDevMap;
1727
1728         switch (acb->adapter_type) {
1729         case ACB_ADAPTER_TYPE_A:
1730                 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1731                 for (target = 0; target < 4; target++)
1732                 {
1733                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1734                         devicemap += 4;
1735                 }
1736                 break;
1737
1738         case ACB_ADAPTER_TYPE_B:
1739                 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1740                 for (target = 0; target < 4; target++)
1741                 {
1742                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1743                         devicemap += 4;
1744                 }
1745                 break;
1746
1747         case ACB_ADAPTER_TYPE_C:
1748                 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1749                 for (target = 0; target < 4; target++)
1750                 {
1751                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1752                         devicemap += 4;
1753                 }
1754                 break;
1755         case ACB_ADAPTER_TYPE_D:
1756                 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1757                 for (target = 0; target < 4; target++)
1758                 {
1759                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1760                         devicemap += 4;
1761                 }
1762                 break;
1763         case ACB_ADAPTER_TYPE_E:
1764                 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1765                 for (target = 0; target < 4; target++)
1766                 {
1767                         deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1768                         devicemap += 4;
1769                 }
1770                 break;
1771         }
1772
1773         if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1774         {
1775                 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1776         }
1777         /*
1778         ** adapter posted CONFIG message
1779         ** copy the new map, note if there are differences with the current map
1780         */
1781         pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1782         for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1783         {
1784                 if (*pDevMap != acb->device_map[target])
1785                 {
1786                         u_int8_t difference, bit_check;
1787
1788                         difference = *pDevMap ^ acb->device_map[target];
1789                         for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1790                         {
1791                                 bit_check = (1 << lun);         /*check bit from 0....31*/
1792                                 if(difference & bit_check)
1793                                 {
1794                                         if(acb->device_map[target] & bit_check)
1795                                         {/* unit departed */
1796                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1797                                                 arcmsr_abort_dr_ccbs(acb, target, lun);
1798                                                 arcmsr_rescan_lun(acb, target, lun);
1799                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1800                                         }
1801                                         else
1802                                         {/* unit arrived */
1803                                                 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1804                                                 arcmsr_rescan_lun(acb, target, lun);
1805                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1806                                         }
1807                                 }
1808                         }
1809 /*                      printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1810                         acb->device_map[target] = *pDevMap;
1811                 }
1812                 pDevMap++;
1813         }
1814 }
1815 /*
1816 **************************************************************************
1817 **************************************************************************
1818 */
1819 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1820         u_int32_t outbound_message;
1821
1822         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1823         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1824         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1825                 arcmsr_dr_handle( acb );
1826 }
1827 /*
1828 **************************************************************************
1829 **************************************************************************
1830 */
1831 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1832         u_int32_t outbound_message;
1833         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1834
1835         /* clear interrupts */
1836         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1837         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1838         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1839                 arcmsr_dr_handle( acb );
1840 }
1841 /*
1842 **************************************************************************
1843 **************************************************************************
1844 */
1845 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1846         u_int32_t outbound_message;
1847
1848         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1849         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1850         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1851                 arcmsr_dr_handle( acb );
1852 }
1853 /*
1854 **************************************************************************
1855 **************************************************************************
1856 */
1857 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1858         u_int32_t outbound_message;
1859
1860         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1861         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1862         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1863                 arcmsr_dr_handle( acb );
1864 }
1865 /*
1866 **************************************************************************
1867 **************************************************************************
1868 */
1869 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) {
1870         u_int32_t outbound_message;
1871
1872         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);
1873         outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]);
1874         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1875                 arcmsr_dr_handle( acb );
1876 }
1877 /*
1878 **************************************************************************
1879 **************************************************************************
1880 */
1881 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1882 {
1883         u_int32_t doorbell_status;
1884
1885         /*
1886         *******************************************************************
1887         **  Maybe here we need to check wrqbuffer_lock is lock or not
1888         **  DOORBELL: din! don!
1889         **  check if there are any mail need to pack from firmware
1890         *******************************************************************
1891         */
1892         doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1893         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1894         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1895                 arcmsr_iop2drv_data_wrote_handle(acb);
1896         }
1897         if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1898                 arcmsr_iop2drv_data_read_handle(acb);
1899         }
1900 }
1901 /*
1902 **************************************************************************
1903 **************************************************************************
1904 */
1905 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1906 {
1907         u_int32_t doorbell_status;
1908
1909         /*
1910         *******************************************************************
1911         **  Maybe here we need to check wrqbuffer_lock is lock or not
1912         **  DOORBELL: din! don!
1913         **  check if there are any mail need to pack from firmware
1914         *******************************************************************
1915         */
1916         doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1917         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1918         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1919                 arcmsr_iop2drv_data_wrote_handle(acb);
1920         }
1921         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1922                 arcmsr_iop2drv_data_read_handle(acb);
1923         }
1924         if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1925                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1926         }
1927 }
1928 /*
1929 **************************************************************************
1930 **************************************************************************
1931 */
1932 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1933 {
1934         u_int32_t doorbell_status;
1935
1936         /*
1937         *******************************************************************
1938         **  Maybe here we need to check wrqbuffer_lock is lock or not
1939         **  DOORBELL: din! don!
1940         **  check if there are any mail need to pack from firmware
1941         *******************************************************************
1942         */
1943         doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1944         if(doorbell_status)
1945                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1946         while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1947                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1948                         arcmsr_iop2drv_data_wrote_handle(acb);
1949                 }
1950                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1951                         arcmsr_iop2drv_data_read_handle(acb);
1952                 }
1953                 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1954                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1955                 }
1956                 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1957                 if(doorbell_status)
1958                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1959         }
1960 }
1961 /*
1962 **************************************************************************
1963 **************************************************************************
1964 */
1965 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb)
1966 {
1967         u_int32_t doorbell_status, in_doorbell;
1968
1969         /*
1970         *******************************************************************
1971         **  Maybe here we need to check wrqbuffer_lock is lock or not
1972         **  DOORBELL: din! don!
1973         **  check if there are any mail need to pack from firmware
1974         *******************************************************************
1975         */
1976         in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
1977         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */
1978         doorbell_status = in_doorbell ^ acb->in_doorbell;
1979         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
1980                 arcmsr_iop2drv_data_wrote_handle(acb);
1981         }
1982         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
1983                 arcmsr_iop2drv_data_read_handle(acb);
1984         }
1985         if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
1986                 arcmsr_hbe_message_isr(acb);    /* messenger of "driver to iop commands" */
1987         }
1988         acb->in_doorbell = in_doorbell;
1989 }
1990 /*
1991 **************************************************************************
1992 **************************************************************************
1993 */
1994 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1995 {
1996         u_int32_t flag_srb;
1997         u_int16_t error;
1998
1999         /*
2000         *****************************************************************************
2001         **               areca cdb command done
2002         *****************************************************************************
2003         */
2004         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2005                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2006         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
2007                 0, outbound_queueport)) != 0xFFFFFFFF) {
2008                 /* check if command done with no error*/
2009         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
2010                 arcmsr_drain_donequeue(acb, flag_srb, error);
2011         }       /*drain reply FIFO*/
2012 }
2013 /*
2014 **************************************************************************
2015 **************************************************************************
2016 */
2017 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
2018 {
2019         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2020         u_int32_t flag_srb;
2021         int index;
2022         u_int16_t error;
2023
2024         /*
2025         *****************************************************************************
2026         **               areca cdb command done
2027         *****************************************************************************
2028         */
2029         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2030                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2031         index = phbbmu->doneq_index;
2032         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
2033                 phbbmu->done_qbuffer[index] = 0;
2034                 index++;
2035                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
2036                 phbbmu->doneq_index = index;
2037                 /* check if command done with no error*/
2038         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
2039                 arcmsr_drain_donequeue(acb, flag_srb, error);
2040         }       /*drain reply FIFO*/
2041 }
2042 /*
2043 **************************************************************************
2044 **************************************************************************
2045 */
2046 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
2047 {
2048         u_int32_t flag_srb,throttling = 0;
2049         u_int16_t error;
2050
2051         /*
2052         *****************************************************************************
2053         **               areca cdb command done
2054         *****************************************************************************
2055         */
2056         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2057         do {
2058                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
2059                 if (flag_srb == 0xFFFFFFFF)
2060                         break;
2061                 /* check if command done with no error*/
2062                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
2063                 arcmsr_drain_donequeue(acb, flag_srb, error);
2064                 throttling++;
2065                 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2066                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
2067                         throttling = 0;
2068                 }
2069         } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
2070 }
2071 /*
2072 **********************************************************************
2073 **
2074 **********************************************************************
2075 */
2076 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
2077 {
2078         uint16_t doneq_index, index_stripped;
2079
2080         doneq_index = phbdmu->doneq_index;
2081         if (doneq_index & 0x4000) {
2082                 index_stripped = doneq_index & 0xFF;
2083                 index_stripped += 1;
2084                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2085                 phbdmu->doneq_index = index_stripped ?
2086                     (index_stripped | 0x4000) : index_stripped;
2087         } else {
2088                 index_stripped = doneq_index;
2089                 index_stripped += 1;
2090                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
2091                 phbdmu->doneq_index = index_stripped ?
2092                     index_stripped : (index_stripped | 0x4000);
2093         }
2094         return (phbdmu->doneq_index);
2095 }
2096 /*
2097 **************************************************************************
2098 **************************************************************************
2099 */
2100 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
2101 {
2102         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
2103         u_int32_t outbound_write_pointer;
2104         u_int32_t addressLow;
2105         uint16_t doneq_index;
2106         u_int16_t error;
2107         /*
2108         *****************************************************************************
2109         **               areca cdb command done
2110         *****************************************************************************
2111         */
2112         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
2113                 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2114                 return;
2115         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2116                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2117         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2118         doneq_index = phbdmu->doneq_index;
2119         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2120                 doneq_index = arcmsr_get_doneq_index(phbdmu);
2121                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2122                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2123                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2124                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2125                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2126         }
2127         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2128         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2129 }
2130 /*
2131 **************************************************************************
2132 **************************************************************************
2133 */
2134 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
2135 {
2136         u_int16_t error;
2137         uint32_t doneq_index;
2138         uint16_t cmdSMID;
2139
2140         /*
2141         *****************************************************************************
2142         **               areca cdb command done
2143         *****************************************************************************
2144         */
2145         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2146         doneq_index = acb->doneq_index;
2147         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) {
2148                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2149                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2150                 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
2151                 doneq_index++;
2152                 if (doneq_index >= acb->completionQ_entry)
2153                         doneq_index = 0;
2154         }
2155         acb->doneq_index = doneq_index;
2156         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
2157 }
2158 /*
2159 **********************************************************************
2160 **********************************************************************
2161 */
2162 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2163 {
2164         u_int32_t outbound_intStatus;
2165         /*
2166         *********************************************
2167         **   check outbound intstatus
2168         *********************************************
2169         */
2170         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2171         if(!outbound_intStatus) {
2172                 /*it must be share irq*/
2173                 return;
2174         }
2175         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2176         /* MU doorbell interrupts*/
2177         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2178                 arcmsr_hba_doorbell_isr(acb);
2179         }
2180         /* MU post queue interrupts*/
2181         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2182                 arcmsr_hba_postqueue_isr(acb);
2183         }
2184         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2185                 arcmsr_hba_message_isr(acb);
2186         }
2187 }
2188 /*
2189 **********************************************************************
2190 **********************************************************************
2191 */
2192 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2193 {
2194         u_int32_t outbound_doorbell;
2195         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2196         /*
2197         *********************************************
2198         **   check outbound intstatus
2199         *********************************************
2200         */
2201         outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2202         if(!outbound_doorbell) {
2203                 /*it must be share irq*/
2204                 return;
2205         }
2206         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2207         READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2208         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2209         /* MU ioctl transfer doorbell interrupts*/
2210         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2211                 arcmsr_iop2drv_data_wrote_handle(acb);
2212         }
2213         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2214                 arcmsr_iop2drv_data_read_handle(acb);
2215         }
2216         /* MU post queue interrupts*/
2217         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2218                 arcmsr_hbb_postqueue_isr(acb);
2219         }
2220         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2221                 arcmsr_hbb_message_isr(acb);
2222         }
2223 }
2224 /*
2225 **********************************************************************
2226 **********************************************************************
2227 */
2228 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2229 {
2230         u_int32_t host_interrupt_status;
2231         /*
2232         *********************************************
2233         **   check outbound intstatus
2234         *********************************************
2235         */
2236         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2237                 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2238                 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2239         if(!host_interrupt_status) {
2240                 /*it must be share irq*/
2241                 return;
2242         }
2243         do {
2244                 /* MU doorbell interrupts*/
2245                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2246                         arcmsr_hbc_doorbell_isr(acb);
2247                 }
2248                 /* MU post queue interrupts*/
2249                 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2250                         arcmsr_hbc_postqueue_isr(acb);
2251                 }
2252                 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2253         } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2254 }
2255 /*
2256 **********************************************************************
2257 **********************************************************************
2258 */
2259 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2260 {
2261         u_int32_t host_interrupt_status;
2262         u_int32_t intmask_org;
2263         /*
2264         *********************************************
2265         **   check outbound intstatus
2266         *********************************************
2267         */
2268         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2269         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2270                 /*it must be share irq*/
2271                 return;
2272         }
2273         /* disable outbound interrupt */
2274         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2275         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2276         /* MU doorbell interrupts*/
2277         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2278                 arcmsr_hbd_doorbell_isr(acb);
2279         }
2280         /* MU post queue interrupts*/
2281         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2282                 arcmsr_hbd_postqueue_isr(acb);
2283         }
2284         /* enable all outbound interrupt */
2285         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2286 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2287 }
2288 /*
2289 **********************************************************************
2290 **********************************************************************
2291 */
2292 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
2293 {
2294         u_int32_t host_interrupt_status;
2295         /*
2296         *********************************************
2297         **   check outbound intstatus
2298         *********************************************
2299         */
2300         host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) &
2301                 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2302                 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2303         if(!host_interrupt_status) {
2304                 /*it must be share irq*/
2305                 return;
2306         }
2307         do {
2308                 /* MU doorbell interrupts*/
2309                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2310                         arcmsr_hbe_doorbell_isr(acb);
2311                 }
2312                 /* MU post queue interrupts*/
2313                 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2314                         arcmsr_hbe_postqueue_isr(acb);
2315                 }
2316                 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
2317         } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2318 }
2319 /*
2320 ******************************************************************************
2321 ******************************************************************************
2322 */
2323 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2324 {
2325         switch (acb->adapter_type) {
2326         case ACB_ADAPTER_TYPE_A:
2327                 arcmsr_handle_hba_isr(acb);
2328                 break;
2329         case ACB_ADAPTER_TYPE_B:
2330                 arcmsr_handle_hbb_isr(acb);
2331                 break;
2332         case ACB_ADAPTER_TYPE_C:
2333                 arcmsr_handle_hbc_isr(acb);
2334                 break;
2335         case ACB_ADAPTER_TYPE_D:
2336                 arcmsr_handle_hbd_isr(acb);
2337                 break;
2338         case ACB_ADAPTER_TYPE_E:
2339                 arcmsr_handle_hbe_isr(acb);
2340                 break;
2341         default:
2342                 printf("arcmsr%d: interrupt service,"
2343                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2344                 break;
2345         }
2346 }
2347 /*
2348 **********************************************************************
2349 **********************************************************************
2350 */
2351 static void arcmsr_intr_handler(void *arg)
2352 {
2353         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2354
2355         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2356         arcmsr_interrupt(acb);
2357         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2358 }
2359 /*
2360 ******************************************************************************
2361 ******************************************************************************
2362 */
2363 static void     arcmsr_polling_devmap(void *arg)
2364 {
2365         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2366         switch (acb->adapter_type) {
2367         case ACB_ADAPTER_TYPE_A:
2368                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2369                 break;
2370
2371         case ACB_ADAPTER_TYPE_B: {
2372                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2373                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2374                 }
2375                 break;
2376
2377         case ACB_ADAPTER_TYPE_C:
2378                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2379                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2380                 break;
2381
2382         case ACB_ADAPTER_TYPE_D:
2383                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2384                 break;
2385
2386         case ACB_ADAPTER_TYPE_E:
2387                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2388                 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
2389                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
2390                 break;
2391         }
2392
2393         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2394         {
2395                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2396         }
2397 }
2398
2399 /*
2400 *******************************************************************************
2401 **
2402 *******************************************************************************
2403 */
2404 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2405 {
2406         u_int32_t intmask_org;
2407
2408         if(acb != NULL) {
2409                 /* stop adapter background rebuild */
2410                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2411                         intmask_org = arcmsr_disable_allintr(acb);
2412                         arcmsr_stop_adapter_bgrb(acb);
2413                         arcmsr_flush_adapter_cache(acb);
2414                         arcmsr_enable_allintr(acb, intmask_org);
2415                 }
2416         }
2417 }
2418 /*
2419 ***********************************************************************
2420 **
2421 ************************************************************************
2422 */
2423 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2424 {
2425         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2426         u_int32_t retvalue = EINVAL;
2427
2428         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2429         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2430                 return retvalue;
2431         }
2432         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2433         switch(ioctl_cmd) {
2434         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2435                         u_int8_t *pQbuffer;
2436                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2437                         u_int32_t allxfer_len=0;
2438
2439                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2440                                 && (allxfer_len < 1031)) {
2441                                 /*copy READ QBUFFER to srb*/
2442                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2443                                 *ptmpQbuffer = *pQbuffer;
2444                                 acb->rqbuf_firstindex++;
2445                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2446                                 /*if last index number set it to 0 */
2447                                 ptmpQbuffer++;
2448                                 allxfer_len++;
2449                         }
2450                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2451                                 struct QBUFFER *prbuffer;
2452
2453                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2454                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2455                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2456                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2457                         }
2458                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2459                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2460                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2461                 }
2462                 break;
2463         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2464                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2465                         u_int8_t *pQbuffer;
2466                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2467
2468                         user_len = pcmdmessagefld->cmdmessage.Length;
2469                         /*check if data xfer length of this request will overflow my array qbuffer */
2470                         wqbuf_lastindex = acb->wqbuf_lastindex;
2471                         wqbuf_firstindex = acb->wqbuf_firstindex;
2472                         if(wqbuf_lastindex != wqbuf_firstindex) {
2473                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2474                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2475                         } else {
2476                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2477                                         (ARCMSR_MAX_QBUFFER - 1);
2478                                 if(my_empty_len >= user_len) {
2479                                         while(user_len > 0) {
2480                                                 /*copy srb data to wqbuffer*/
2481                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2482                                                 *pQbuffer = *ptmpuserbuffer;
2483                                                 acb->wqbuf_lastindex++;
2484                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2485                                                 /*if last index number set it to 0 */
2486                                                 ptmpuserbuffer++;
2487                                                 user_len--;
2488                                         }
2489                                         /*post fist Qbuffer*/
2490                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2491                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2492                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2493                                         }
2494                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2495                                 } else {
2496                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2497                                 }
2498                         }
2499                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2500                 }
2501                 break;
2502         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2503                         u_int8_t *pQbuffer = acb->rqbuffer;
2504
2505                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2506                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2507                                 arcmsr_iop_message_read(acb);
2508                                 /*signature, let IOP know data has been readed */
2509                         }
2510                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2511                         acb->rqbuf_firstindex = 0;
2512                         acb->rqbuf_lastindex = 0;
2513                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2514                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2515                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2516                 }
2517                 break;
2518         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2519                 {
2520                         u_int8_t *pQbuffer = acb->wqbuffer;
2521
2522                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2523                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2524                                 arcmsr_iop_message_read(acb);
2525                                 /*signature, let IOP know data has been readed */
2526                         }
2527                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2528                         acb->wqbuf_firstindex = 0;
2529                         acb->wqbuf_lastindex = 0;
2530                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2531                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2532                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2533                 }
2534                 break;
2535         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2536                         u_int8_t *pQbuffer;
2537
2538                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2539                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2540                                 arcmsr_iop_message_read(acb);
2541                                 /*signature, let IOP know data has been readed */
2542                         }
2543                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2544                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2545                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2546                         acb->rqbuf_firstindex = 0;
2547                         acb->rqbuf_lastindex = 0;
2548                         acb->wqbuf_firstindex = 0;
2549                         acb->wqbuf_lastindex = 0;
2550                         pQbuffer = acb->rqbuffer;
2551                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2552                         pQbuffer = acb->wqbuffer;
2553                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2554                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2555                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2556                 }
2557                 break;
2558         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2559                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2560                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2561                 }
2562                 break;
2563         case ARCMSR_MESSAGE_SAY_HELLO: {
2564                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2565                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2566
2567                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2568                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2569                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2570                                 return ENOIOCTL;
2571                         }
2572                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2573                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2574                 }
2575                 break;
2576         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2577                         arcmsr_iop_parking(acb);
2578                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2579                 }
2580                 break;
2581         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2582                         arcmsr_flush_adapter_cache(acb);
2583                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2584                 }
2585                 break;
2586         }
2587         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2588         return (retvalue);
2589 }
2590 /*
2591 **************************************************************************
2592 **************************************************************************
2593 */
2594 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2595 {
2596         struct AdapterControlBlock      *acb;
2597
2598         acb = srb->acb;
2599         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2600         srb->srb_state = ARCMSR_SRB_DONE;
2601         srb->srb_flags = 0;
2602         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2603         acb->workingsrb_doneindex++;
2604         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2605         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2606 }
2607 /*
2608 **************************************************************************
2609 **************************************************************************
2610 */
2611 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2612 {
2613         struct CommandControlBlock *srb = NULL;
2614         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2615
2616         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2617         workingsrb_doneindex = acb->workingsrb_doneindex;
2618         workingsrb_startindex = acb->workingsrb_startindex;
2619         srb = acb->srbworkingQ[workingsrb_startindex];
2620         workingsrb_startindex++;
2621         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2622         if(workingsrb_doneindex != workingsrb_startindex) {
2623                 acb->workingsrb_startindex = workingsrb_startindex;
2624         } else {
2625                 srb = NULL;
2626         }
2627         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2628         return(srb);
2629 }
2630 /*
2631 **************************************************************************
2632 **************************************************************************
2633 */
2634 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2635 {
2636         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2637         int retvalue = 0, transfer_len = 0;
2638         char *buffer;
2639         uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2640         u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2641                                 (u_int32_t ) ptr[6] << 16 |
2642                                 (u_int32_t ) ptr[7] << 8  |
2643                                 (u_int32_t ) ptr[8];
2644                                         /* 4 bytes: Areca io control code */
2645         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2646                 buffer = pccb->csio.data_ptr;
2647                 transfer_len = pccb->csio.dxfer_len;
2648         } else {
2649                 retvalue = ARCMSR_MESSAGE_FAIL;
2650                 goto message_out;
2651         }
2652         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2653                 retvalue = ARCMSR_MESSAGE_FAIL;
2654                 goto message_out;
2655         }
2656         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2657         switch(controlcode) {
2658         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2659                         u_int8_t *pQbuffer;
2660                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2661                         int32_t allxfer_len = 0;
2662
2663                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2664                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2665                                 && (allxfer_len < 1031)) {
2666                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2667                                 *ptmpQbuffer = *pQbuffer;
2668                                 acb->rqbuf_firstindex++;
2669                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2670                                 ptmpQbuffer++;
2671                                 allxfer_len++;
2672                         }
2673                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2674                                 struct QBUFFER  *prbuffer;
2675
2676                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2677                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2678                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2679                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2680                         }
2681                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2682                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2683                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2684                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2685                 }
2686                 break;
2687         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2688                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2689                         u_int8_t *pQbuffer;
2690                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2691
2692                         user_len = pcmdmessagefld->cmdmessage.Length;
2693                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2694                         wqbuf_lastindex = acb->wqbuf_lastindex;
2695                         wqbuf_firstindex = acb->wqbuf_firstindex;
2696                         if (wqbuf_lastindex != wqbuf_firstindex) {
2697                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2698                                 /* has error report sensedata */
2699                                 if(pccb->csio.sense_len) {
2700                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2701                                 /* Valid,ErrorCode */
2702                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2703                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2704                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2705                                 /* AdditionalSenseLength */
2706                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2707                                 /* AdditionalSenseCode */
2708                                 }
2709                                 retvalue = ARCMSR_MESSAGE_FAIL;
2710                         } else {
2711                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2712                                                 &(ARCMSR_MAX_QBUFFER - 1);
2713                                 if (my_empty_len >= user_len) {
2714                                         while (user_len > 0) {
2715                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2716                                                 *pQbuffer = *ptmpuserbuffer;
2717                                                 acb->wqbuf_lastindex++;
2718                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2719                                                 ptmpuserbuffer++;
2720                                                 user_len--;
2721                                         }
2722                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2723                                                 acb->acb_flags &=
2724                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2725                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2726                                         }
2727                                 } else {
2728                                         /* has error report sensedata */
2729                                         if(pccb->csio.sense_len) {
2730                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2731                                         /* Valid,ErrorCode */
2732                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2733                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2734                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2735                                         /* AdditionalSenseLength */
2736                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2737                                         /* AdditionalSenseCode */
2738                                         }
2739                                         retvalue = ARCMSR_MESSAGE_FAIL;
2740                                 }
2741                         }
2742                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2743                 }
2744                 break;
2745         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2746                         u_int8_t *pQbuffer = acb->rqbuffer;
2747
2748                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2749                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2750                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2751                                 arcmsr_iop_message_read(acb);
2752                         }
2753                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2754                         acb->rqbuf_firstindex = 0;
2755                         acb->rqbuf_lastindex = 0;
2756                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2757                         pcmdmessagefld->cmdmessage.ReturnCode =
2758                             ARCMSR_MESSAGE_RETURNCODE_OK;
2759                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2760                 }
2761                 break;
2762         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2763                         u_int8_t *pQbuffer = acb->wqbuffer;
2764
2765                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2766                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2767                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2768                                 arcmsr_iop_message_read(acb);
2769                         }
2770                         acb->acb_flags |=
2771                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2772                                         ACB_F_MESSAGE_WQBUFFER_READ);
2773                         acb->wqbuf_firstindex = 0;
2774                         acb->wqbuf_lastindex = 0;
2775                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2776                         pcmdmessagefld->cmdmessage.ReturnCode =
2777                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2778                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2779                 }
2780                 break;
2781         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2782                         u_int8_t *pQbuffer;
2783
2784                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2785                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2786                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2787                                 arcmsr_iop_message_read(acb);
2788                         }
2789                         acb->acb_flags |=
2790                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2791                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2792                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2793                         acb->rqbuf_firstindex = 0;
2794                         acb->rqbuf_lastindex = 0;
2795                         acb->wqbuf_firstindex = 0;
2796                         acb->wqbuf_lastindex = 0;
2797                         pQbuffer = acb->rqbuffer;
2798                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2799                         pQbuffer = acb->wqbuffer;
2800                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2801                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2802                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2803                 }
2804                 break;
2805         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2806                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2807                 }
2808                 break;
2809         case ARCMSR_MESSAGE_SAY_HELLO: {
2810                         int8_t *hello_string = "Hello! I am ARCMSR";
2811
2812                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2813                                 , (int16_t)strlen(hello_string));
2814                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2815                 }
2816                 break;
2817         case ARCMSR_MESSAGE_SAY_GOODBYE:
2818                 arcmsr_iop_parking(acb);
2819                 break;
2820         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2821                 arcmsr_flush_adapter_cache(acb);
2822                 break;
2823         default:
2824                 retvalue = ARCMSR_MESSAGE_FAIL;
2825         }
2826 message_out:
2827         return (retvalue);
2828 }
2829 /*
2830 *********************************************************************
2831 *********************************************************************
2832 */
2833 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2834 {
2835         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2836         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2837         union ccb *pccb;
2838         int target, lun;
2839
2840         pccb = srb->pccb;
2841         target = pccb->ccb_h.target_id;
2842         lun = pccb->ccb_h.target_lun;
2843         acb->pktRequestCount++;
2844         if(error != 0) {
2845                 if(error != EFBIG) {
2846                         printf("arcmsr%d: unexpected error %x"
2847                                 " returned from 'bus_dmamap_load' \n"
2848                                 , acb->pci_unit, error);
2849                 }
2850                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2851                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2852                 }
2853                 arcmsr_srb_complete(srb, 0);
2854                 return;
2855         }
2856         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2857                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2858                 arcmsr_srb_complete(srb, 0);
2859                 return;
2860         }
2861         if(acb->acb_flags & ACB_F_BUS_RESET) {
2862                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2863                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2864                 arcmsr_srb_complete(srb, 0);
2865                 return;
2866         }
2867         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2868                 u_int8_t block_cmd, cmd;
2869
2870                 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
2871                 block_cmd = cmd & 0x0f;
2872                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2873                         printf("arcmsr%d:block 'read/write' command "
2874                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2875                                 , acb->pci_unit, cmd, target, lun);
2876                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2877                         arcmsr_srb_complete(srb, 0);
2878                         return;
2879                 }
2880         }
2881         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2882                 if(nseg != 0) {
2883                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2884                 }
2885                 arcmsr_srb_complete(srb, 0);
2886                 return;
2887         }
2888         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2889                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2890                 {
2891                         xpt_freeze_simq(acb->psim, 1);
2892                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2893                 }
2894                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2895                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2896                 arcmsr_srb_complete(srb, 0);
2897                 return;
2898         }
2899         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2900         arcmsr_build_srb(srb, dm_segs, nseg);
2901         arcmsr_post_srb(acb, srb);
2902         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2903         {
2904                 arcmsr_callout_init(&srb->ccb_callout);
2905                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2906                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2907                     arcmsr_srb_timeout, srb, 0);
2908                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2909         }
2910 }
2911 /*
2912 *****************************************************************************************
2913 *****************************************************************************************
2914 */
2915 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2916 {
2917         struct CommandControlBlock *srb;
2918         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2919         u_int32_t intmask_org;
2920         int i = 0;
2921
2922         acb->num_aborts++;
2923         /*
2924         ***************************************************************************
2925         ** It is the upper layer do abort command this lock just prior to calling us.
2926         ** First determine if we currently own this command.
2927         ** Start by searching the device queue. If not found
2928         ** at all, and the system wanted us to just abort the
2929         ** command return success.
2930         ***************************************************************************
2931         */
2932         if(acb->srboutstandingcount != 0) {
2933                 /* disable all outbound interrupt */
2934                 intmask_org = arcmsr_disable_allintr(acb);
2935                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2936                         srb = acb->psrb_pool[i];
2937                         if(srb->srb_state == ARCMSR_SRB_START) {
2938                                 if(srb->pccb == abortccb) {
2939                                         srb->srb_state = ARCMSR_SRB_ABORTED;
2940                                         printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
2941                                                 "outstanding command \n"
2942                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2943                                                 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
2944                                         arcmsr_polling_srbdone(acb, srb);
2945                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
2946                                         arcmsr_enable_allintr(acb, intmask_org);
2947                                         return (TRUE);
2948                                 }
2949                         }
2950                 }
2951                 /* enable outbound Post Queue, outbound doorbell Interrupt */
2952                 arcmsr_enable_allintr(acb, intmask_org);
2953         }
2954         return(FALSE);
2955 }
2956 /*
2957 ****************************************************************************
2958 ****************************************************************************
2959 */
2960 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2961 {
2962         int retry = 0;
2963
2964         acb->num_resets++;
2965         acb->acb_flags |= ACB_F_BUS_RESET;
2966         while(acb->srboutstandingcount != 0 && retry < 400) {
2967                 arcmsr_interrupt(acb);
2968                 UDELAY(25000);
2969                 retry++;
2970         }
2971         arcmsr_iop_reset(acb);
2972         acb->acb_flags &= ~ACB_F_BUS_RESET;
2973 }
2974 /*
2975 **************************************************************************
2976 **************************************************************************
2977 */
2978 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2979                 union ccb *pccb)
2980 {
2981         if (pccb->ccb_h.target_lun) {
2982                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2983                 xpt_done(pccb);
2984                 return;
2985         }
2986         pccb->ccb_h.status |= CAM_REQ_CMP;
2987         switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
2988         case INQUIRY: {
2989                 unsigned char inqdata[36];
2990                 char *buffer = pccb->csio.data_ptr;
2991
2992                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2993                 inqdata[1] = 0;                 /* rem media bit & Dev Type Modifier */
2994                 inqdata[2] = 0;                 /* ISO, ECMA, & ANSI versions */
2995                 inqdata[3] = 0;
2996                 inqdata[4] = 31;                /* length of additional data */
2997                 inqdata[5] = 0;
2998                 inqdata[6] = 0;
2999                 inqdata[7] = 0;
3000                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
3001                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
3002                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
3003                 memcpy(buffer, inqdata, sizeof(inqdata));
3004                 xpt_done(pccb);
3005         }
3006         break;
3007         case WRITE_BUFFER:
3008         case READ_BUFFER: {
3009                 if (arcmsr_iop_message_xfer(acb, pccb)) {
3010                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
3011                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
3012                 }
3013                 xpt_done(pccb);
3014         }
3015         break;
3016         default:
3017                 xpt_done(pccb);
3018         }
3019 }
3020 /*
3021 *********************************************************************
3022 *********************************************************************
3023 */
3024 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
3025 {
3026         struct AdapterControlBlock *acb;
3027
3028         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
3029         if(acb == NULL) {
3030                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3031                 xpt_done(pccb);
3032                 return;
3033         }
3034         switch (pccb->ccb_h.func_code) {
3035         case XPT_SCSI_IO: {
3036                         struct CommandControlBlock *srb;
3037                         int target = pccb->ccb_h.target_id;
3038                         int error;
3039
3040                         if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
3041                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3042                                 xpt_done(pccb);
3043                                 return;
3044                         }
3045
3046                         if(target == 16) {
3047                                 /* virtual device for iop message transfer */
3048                                 arcmsr_handle_virtual_command(acb, pccb);
3049                                 return;
3050                         }
3051                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
3052                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
3053                                 xpt_done(pccb);
3054                                 return;
3055                         }
3056                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
3057                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
3058                         srb->pccb = pccb;
3059                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
3060                                 , srb->dm_segs_dmamap
3061                                 , pccb
3062                                 , arcmsr_execute_srb, srb, /*flags*/0);
3063                         if(error == EINPROGRESS) {
3064                                 xpt_freeze_simq(acb->psim, 1);
3065                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
3066                         }
3067                         break;
3068                 }
3069         case XPT_PATH_INQ: {
3070                         struct ccb_pathinq *cpi = &pccb->cpi;
3071
3072                         cpi->version_num = 1;
3073                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
3074                         cpi->target_sprt = 0;
3075                         cpi->hba_misc = 0;
3076                         cpi->hba_eng_cnt = 0;
3077                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
3078                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
3079                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
3080                         cpi->bus_id = cam_sim_bus(psim);
3081                         strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
3082                         strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
3083                         strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
3084                         cpi->unit_number = cam_sim_unit(psim);
3085                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3086                                 cpi->base_transfer_speed = 1200000;
3087                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3088                                 cpi->base_transfer_speed = 600000;
3089                         else
3090                                 cpi->base_transfer_speed = 300000;
3091                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3092                            (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3093                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3094                            (acb->vendor_device_id == PCIDevVenIDARC1214))
3095                         {
3096                                 cpi->transport = XPORT_SAS;
3097                                 cpi->transport_version = 0;
3098                                 cpi->protocol_version = SCSI_REV_SPC2;
3099                         }
3100                         else
3101                         {
3102                                 cpi->transport = XPORT_SPI;
3103                                 cpi->transport_version = 2;
3104                                 cpi->protocol_version = SCSI_REV_2;
3105                         }
3106                         cpi->protocol = PROTO_SCSI;
3107                         cpi->ccb_h.status |= CAM_REQ_CMP;
3108                         xpt_done(pccb);
3109                         break;
3110                 }
3111         case XPT_ABORT: {
3112                         union ccb *pabort_ccb;
3113
3114                         pabort_ccb = pccb->cab.abort_ccb;
3115                         switch (pabort_ccb->ccb_h.func_code) {
3116                         case XPT_ACCEPT_TARGET_IO:
3117                         case XPT_CONT_TARGET_IO:
3118                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
3119                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
3120                                         xpt_done(pabort_ccb);
3121                                         pccb->ccb_h.status |= CAM_REQ_CMP;
3122                                 } else {
3123                                         xpt_print_path(pabort_ccb->ccb_h.path);
3124                                         printf("Not found\n");
3125                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
3126                                 }
3127                                 break;
3128                         case XPT_SCSI_IO:
3129                                 pccb->ccb_h.status |= CAM_UA_ABORT;
3130                                 break;
3131                         default:
3132                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3133                                 break;
3134                         }
3135                         xpt_done(pccb);
3136                         break;
3137                 }
3138         case XPT_RESET_BUS:
3139         case XPT_RESET_DEV: {
3140                         u_int32_t       i;
3141
3142                         arcmsr_bus_reset(acb);
3143                         for (i=0; i < 500; i++) {
3144                                 DELAY(1000);
3145                         }
3146                         pccb->ccb_h.status |= CAM_REQ_CMP;
3147                         xpt_done(pccb);
3148                         break;
3149                 }
3150         case XPT_TERM_IO: {
3151                         pccb->ccb_h.status |= CAM_REQ_INVALID;
3152                         xpt_done(pccb);
3153                         break;
3154                 }
3155         case XPT_GET_TRAN_SETTINGS: {
3156                         struct ccb_trans_settings *cts;
3157
3158                         if(pccb->ccb_h.target_id == 16) {
3159                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3160                                 xpt_done(pccb);
3161                                 break;
3162                         }
3163                         cts = &pccb->cts;
3164                         {
3165                                 struct ccb_trans_settings_scsi *scsi;
3166                                 struct ccb_trans_settings_spi *spi;
3167                                 struct ccb_trans_settings_sas *sas;
3168
3169                                 scsi = &cts->proto_specific.scsi;
3170                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
3171                                 scsi->valid = CTS_SCSI_VALID_TQ;
3172                                 cts->protocol = PROTO_SCSI;
3173
3174                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
3175                                    (acb->vendor_device_id == PCIDevVenIDARC1884) ||
3176                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
3177                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
3178                                 {
3179                                         cts->protocol_version = SCSI_REV_SPC2;
3180                                         cts->transport_version = 0;
3181                                         cts->transport = XPORT_SAS;
3182                                         sas = &cts->xport_specific.sas;
3183                                         sas->valid = CTS_SAS_VALID_SPEED;
3184                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3185                                                 sas->bitrate = 1200000;
3186                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3187                                                 sas->bitrate = 600000;
3188                                         else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3189                                                 sas->bitrate = 300000;
3190                                 }
3191                                 else
3192                                 {
3193                                         cts->protocol_version = SCSI_REV_2;
3194                                         cts->transport_version = 2;
3195                                         cts->transport = XPORT_SPI;
3196                                         spi = &cts->xport_specific.spi;
3197                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3198                                         if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3199                                                 spi->sync_period = 1;
3200                                         else
3201                                                 spi->sync_period = 2;
3202                                         spi->sync_offset = 32;
3203                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3204                                         spi->valid = CTS_SPI_VALID_DISC
3205                                                 | CTS_SPI_VALID_SYNC_RATE
3206                                                 | CTS_SPI_VALID_SYNC_OFFSET
3207                                                 | CTS_SPI_VALID_BUS_WIDTH;
3208                                 }
3209                         }
3210                         pccb->ccb_h.status |= CAM_REQ_CMP;
3211                         xpt_done(pccb);
3212                         break;
3213                 }
3214         case XPT_SET_TRAN_SETTINGS: {
3215                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3216                         xpt_done(pccb);
3217                         break;
3218                 }
3219         case XPT_CALC_GEOMETRY:
3220                         if(pccb->ccb_h.target_id == 16) {
3221                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3222                                 xpt_done(pccb);
3223                                 break;
3224                         }
3225                         cam_calc_geometry(&pccb->ccg, 1);
3226                         xpt_done(pccb);
3227                         break;
3228         default:
3229                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3230                 xpt_done(pccb);
3231                 break;
3232         }
3233 }
3234 /*
3235 **********************************************************************
3236 **********************************************************************
3237 */
3238 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3239 {
3240         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3241         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3242         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3243                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3244         }
3245 }
3246 /*
3247 **********************************************************************
3248 **********************************************************************
3249 */
3250 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3251 {
3252         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3253         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3254         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3255         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3256                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3257         }
3258 }
3259 /*
3260 **********************************************************************
3261 **********************************************************************
3262 */
3263 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3264 {
3265         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3266         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3267         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3268         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3269                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3270         }
3271 }
3272 /*
3273 **********************************************************************
3274 **********************************************************************
3275 */
3276 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3277 {
3278         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3279         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3280         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3281                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3282         }
3283 }
3284 /*
3285 **********************************************************************
3286 **********************************************************************
3287 */
3288 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb)
3289 {
3290         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3291         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3292         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3293         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3294         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3295                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3296         }
3297 }
3298 /*
3299 **********************************************************************
3300 **********************************************************************
3301 */
3302 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3303 {
3304         switch (acb->adapter_type) {
3305         case ACB_ADAPTER_TYPE_A:
3306                 arcmsr_start_hba_bgrb(acb);
3307                 break;
3308         case ACB_ADAPTER_TYPE_B:
3309                 arcmsr_start_hbb_bgrb(acb);
3310                 break;
3311         case ACB_ADAPTER_TYPE_C:
3312                 arcmsr_start_hbc_bgrb(acb);
3313                 break;
3314         case ACB_ADAPTER_TYPE_D:
3315                 arcmsr_start_hbd_bgrb(acb);
3316                 break;
3317         case ACB_ADAPTER_TYPE_E:
3318                 arcmsr_start_hbe_bgrb(acb);
3319                 break;
3320         }
3321 }
3322 /*
3323 **********************************************************************
3324 **
3325 **********************************************************************
3326 */
3327 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3328 {
3329         struct CommandControlBlock *srb;
3330         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3331         u_int16_t       error;
3332
3333 polling_ccb_retry:
3334         poll_count++;
3335         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3336         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3337         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3338         while(1) {
3339                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3340                         0, outbound_queueport)) == 0xFFFFFFFF) {
3341                         if(poll_srb_done) {
3342                                 break;/*chip FIFO no ccb for completion already*/
3343                         } else {
3344                                 UDELAY(25000);
3345                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3346                                         break;
3347                                 }
3348                                 goto polling_ccb_retry;
3349                         }
3350                 }
3351                 /* check if command done with no error*/
3352                 srb = (struct CommandControlBlock *)
3353                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3354                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3355                 poll_srb_done = (srb == poll_srb) ? 1:0;
3356                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3357                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3358                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3359                                         "poll command abort successfully \n"
3360                                         , acb->pci_unit
3361                                         , srb->pccb->ccb_h.target_id
3362                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3363                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3364                                 arcmsr_srb_complete(srb, 1);
3365                                 continue;
3366                         }
3367                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3368                                 "srboutstandingcount=%d \n"
3369                                 , acb->pci_unit
3370                                 , srb, acb->srboutstandingcount);
3371                         continue;
3372                 }
3373                 arcmsr_report_srb_state(acb, srb, error);
3374         }       /*drain reply FIFO*/
3375 }
3376 /*
3377 **********************************************************************
3378 **
3379 **********************************************************************
3380 */
3381 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3382 {
3383         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3384         struct CommandControlBlock *srb;
3385         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3386         int index;
3387         u_int16_t       error;
3388
3389 polling_ccb_retry:
3390         poll_count++;
3391         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3392         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3393         while(1) {
3394                 index = phbbmu->doneq_index;
3395                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3396                         if(poll_srb_done) {
3397                                 break;/*chip FIFO no ccb for completion already*/
3398                         } else {
3399                                 UDELAY(25000);
3400                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3401                                         break;
3402                                 }
3403                                 goto polling_ccb_retry;
3404                         }
3405                 }
3406                 phbbmu->done_qbuffer[index] = 0;
3407                 index++;
3408                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3409                 phbbmu->doneq_index = index;
3410                 /* check if command done with no error*/
3411                 srb = (struct CommandControlBlock *)
3412                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3413                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3414                 poll_srb_done = (srb == poll_srb) ? 1:0;
3415                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3416                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3417                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3418                                         "poll command abort successfully \n"
3419                                         , acb->pci_unit
3420                                         , srb->pccb->ccb_h.target_id
3421                                         , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3422                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3423                                 arcmsr_srb_complete(srb, 1);
3424                                 continue;
3425                         }
3426                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3427                                 "srboutstandingcount=%d \n"
3428                                 , acb->pci_unit
3429                                 , srb, acb->srboutstandingcount);
3430                         continue;
3431                 }
3432                 arcmsr_report_srb_state(acb, srb, error);
3433         }       /*drain reply FIFO*/
3434 }
3435 /*
3436 **********************************************************************
3437 **
3438 **********************************************************************
3439 */
3440 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3441 {
3442         struct CommandControlBlock *srb;
3443         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3444         u_int16_t       error;
3445
3446 polling_ccb_retry:
3447         poll_count++;
3448         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3449         while(1) {
3450                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3451                         if(poll_srb_done) {
3452                                 break;/*chip FIFO no ccb for completion already*/
3453                         } else {
3454                                 UDELAY(25000);
3455                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3456                                         break;
3457                                 }
3458                                 if (acb->srboutstandingcount == 0) {
3459                                     break;
3460                                 }
3461                                 goto polling_ccb_retry;
3462                         }
3463                 }
3464                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3465                 /* check if command done with no error*/
3466                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3467                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3468                 if (poll_srb != NULL)
3469                         poll_srb_done = (srb == poll_srb) ? 1:0;
3470                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3471                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3472                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3473                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3474                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3475                                 arcmsr_srb_complete(srb, 1);
3476                                 continue;
3477                         }
3478                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3479                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3480                         continue;
3481                 }
3482                 arcmsr_report_srb_state(acb, srb, error);
3483         }       /*drain reply FIFO*/
3484 }
3485 /*
3486 **********************************************************************
3487 **
3488 **********************************************************************
3489 */
3490 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3491 {
3492         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3493         struct CommandControlBlock *srb;
3494         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3495         u_int32_t outbound_write_pointer;
3496         u_int16_t       error, doneq_index;
3497
3498 polling_ccb_retry:
3499         poll_count++;
3500         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3501         while(1) {
3502                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3503                 doneq_index = phbdmu->doneq_index;
3504                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3505                         if(poll_srb_done) {
3506                                 break;/*chip FIFO no ccb for completion already*/
3507                         } else {
3508                                 UDELAY(25000);
3509                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3510                                         break;
3511                                 }
3512                                 if (acb->srboutstandingcount == 0) {
3513                                         break;
3514                                 }
3515                                 goto polling_ccb_retry;
3516                         }
3517                 }
3518                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3519                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3520                 /* check if command done with no error*/
3521                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3522                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3523                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3524                 if (poll_srb != NULL)
3525                         poll_srb_done = (srb == poll_srb) ? 1:0;
3526                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3527                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3528                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3529                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3530                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3531                                 arcmsr_srb_complete(srb, 1);
3532                                 continue;
3533                         }
3534                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3535                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3536                         continue;
3537                 }
3538                 arcmsr_report_srb_state(acb, srb, error);
3539         }       /*drain reply FIFO*/
3540 }
3541 /*
3542 **********************************************************************
3543 **
3544 **********************************************************************
3545 */
3546 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3547 {
3548         struct CommandControlBlock *srb;
3549         u_int32_t poll_srb_done=0, poll_count=0, doneq_index;
3550         u_int16_t       error, cmdSMID;
3551
3552 polling_ccb_retry:
3553         poll_count++;
3554         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3555         while(1) {
3556                 doneq_index = acb->doneq_index;
3557                 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) {
3558                         if(poll_srb_done) {
3559                                 break;/*chip FIFO no ccb for completion already*/
3560                         } else {
3561                                 UDELAY(25000);
3562                             if ((poll_count > 100) && (poll_srb != NULL)) {
3563                                         break;
3564                                 }
3565                             if (acb->srboutstandingcount == 0) {
3566                                     break;
3567                             }
3568                                 goto polling_ccb_retry;
3569                         }
3570                 }
3571                 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3572                 doneq_index++;
3573                 if (doneq_index >= acb->completionQ_entry)
3574                         doneq_index = 0;
3575                 acb->doneq_index = doneq_index;
3576                 srb = acb->psrb_pool[cmdSMID];
3577                 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3578                 if (poll_srb != NULL)
3579                         poll_srb_done = (srb == poll_srb) ? 1:0;
3580                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3581                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3582                                 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3583                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3584                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3585                                 arcmsr_srb_complete(srb, 1);
3586                                 continue;
3587                         }
3588                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3589                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3590                         continue;
3591                 }
3592                 arcmsr_report_srb_state(acb, srb, error);
3593         }       /*drain reply FIFO*/
3594         CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index);
3595 }
3596 /*
3597 **********************************************************************
3598 **********************************************************************
3599 */
3600 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3601 {
3602         switch (acb->adapter_type) {
3603         case ACB_ADAPTER_TYPE_A: {
3604                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3605                 }
3606                 break;
3607         case ACB_ADAPTER_TYPE_B: {
3608                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3609                 }
3610                 break;
3611         case ACB_ADAPTER_TYPE_C: {
3612                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3613                 }
3614                 break;
3615         case ACB_ADAPTER_TYPE_D: {
3616                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3617                 }
3618                 break;
3619         case ACB_ADAPTER_TYPE_E: {
3620                         arcmsr_polling_hbe_srbdone(acb, poll_srb);
3621                 }
3622                 break;
3623         }
3624 }
3625 /*
3626 **********************************************************************
3627 **********************************************************************
3628 */
3629 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3630 {
3631         char *acb_firm_model = acb->firm_model;
3632         char *acb_firm_version = acb->firm_version;
3633         char *acb_device_map = acb->device_map;
3634         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3635         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3636         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3637         int i;
3638
3639         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3640         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3641                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3642         }
3643         i = 0;
3644         while(i < 8) {
3645                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3646                 /* 8 bytes firm_model, 15, 60-67*/
3647                 acb_firm_model++;
3648                 i++;
3649         }
3650         i=0;
3651         while(i < 16) {
3652                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3653                 /* 16 bytes firm_version, 17, 68-83*/
3654                 acb_firm_version++;
3655                 i++;
3656         }
3657         i=0;
3658         while(i < 16) {
3659                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3660                 acb_device_map++;
3661                 i++;
3662         }
3663         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3664         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3665         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3666         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3667         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3668         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3669         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3670                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3671         else
3672                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3673 }
3674 /*
3675 **********************************************************************
3676 **********************************************************************
3677 */
3678 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3679 {
3680         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3681         char *acb_firm_model = acb->firm_model;
3682         char *acb_firm_version = acb->firm_version;
3683         char *acb_device_map = acb->device_map;
3684         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3685         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3686         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3687         int i;
3688
3689         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3690         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3691                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3692         }
3693         i = 0;
3694         while(i < 8) {
3695                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3696                 /* 8 bytes firm_model, 15, 60-67*/
3697                 acb_firm_model++;
3698                 i++;
3699         }
3700         i = 0;
3701         while(i < 16) {
3702                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3703                 /* 16 bytes firm_version, 17, 68-83*/
3704                 acb_firm_version++;
3705                 i++;
3706         }
3707         i = 0;
3708         while(i < 16) {
3709                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3710                 acb_device_map++;
3711                 i++;
3712         }
3713         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3714         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3715         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3716         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3717         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3718         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3719         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3720                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3721         else
3722                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3723 }
3724 /*
3725 **********************************************************************
3726 **********************************************************************
3727 */
3728 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3729 {
3730         char *acb_firm_model = acb->firm_model;
3731         char *acb_firm_version = acb->firm_version;
3732         char *acb_device_map = acb->device_map;
3733         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3734         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3735         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3736         int i;
3737
3738         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3739         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3740         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3741                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3742         }
3743         i = 0;
3744         while(i < 8) {
3745                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3746                 /* 8 bytes firm_model, 15, 60-67*/
3747                 acb_firm_model++;
3748                 i++;
3749         }
3750         i = 0;
3751         while(i < 16) {
3752                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3753                 /* 16 bytes firm_version, 17, 68-83*/
3754                 acb_firm_version++;
3755                 i++;
3756         }
3757         i = 0;
3758         while(i < 16) {
3759                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3760                 acb_device_map++;
3761                 i++;
3762         }
3763         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3764         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3765         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3766         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3767         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3768         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3769         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3770                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3771         else
3772                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3773 }
3774 /*
3775 **********************************************************************
3776 **********************************************************************
3777 */
3778 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3779 {
3780         char *acb_firm_model = acb->firm_model;
3781         char *acb_firm_version = acb->firm_version;
3782         char *acb_device_map = acb->device_map;
3783         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3784         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3785         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3786         int i;
3787
3788         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3789                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3790         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3791         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3792                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3793         }
3794         i = 0;
3795         while(i < 8) {
3796                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3797                 /* 8 bytes firm_model, 15, 60-67*/
3798                 acb_firm_model++;
3799                 i++;
3800         }
3801         i = 0;
3802         while(i < 16) {
3803                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3804                 /* 16 bytes firm_version, 17, 68-83*/
3805                 acb_firm_version++;
3806                 i++;
3807         }
3808         i = 0;
3809         while(i < 16) {
3810                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3811                 acb_device_map++;
3812                 i++;
3813         }
3814         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3815         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3816         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3817         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3818         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3819         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3820         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3821                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3822         else
3823                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3824 }
3825 /*
3826 **********************************************************************
3827 **********************************************************************
3828 */
3829 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
3830 {
3831         char *acb_firm_model = acb->firm_model;
3832         char *acb_firm_version = acb->firm_version;
3833         char *acb_device_map = acb->device_map;
3834         size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3835         size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3836         size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3837         int i;
3838
3839         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3840         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3841         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
3842         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
3843                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3844         }
3845
3846         i = 0;
3847         while(i < 8) {
3848                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3849                 /* 8 bytes firm_model, 15, 60-67*/
3850                 acb_firm_model++;
3851                 i++;
3852         }
3853         i = 0;
3854         while(i < 16) {
3855                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3856                 /* 16 bytes firm_version, 17, 68-83*/
3857                 acb_firm_version++;
3858                 i++;
3859         }
3860         i = 0;
3861         while(i < 16) {
3862                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3863                 acb_device_map++;
3864                 i++;
3865         }
3866         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3867         acb->firm_request_len   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3868         acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3869         acb->firm_sdram_size    = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3870         acb->firm_ide_channels  = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3871         acb->firm_cfg_version   = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3872         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3873                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3874         else
3875                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3876 }
3877 /*
3878 **********************************************************************
3879 **********************************************************************
3880 */
3881 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3882 {
3883         switch (acb->adapter_type) {
3884         case ACB_ADAPTER_TYPE_A: {
3885                         arcmsr_get_hba_config(acb);
3886                 }
3887                 break;
3888         case ACB_ADAPTER_TYPE_B: {
3889                         arcmsr_get_hbb_config(acb);
3890                 }
3891                 break;
3892         case ACB_ADAPTER_TYPE_C: {
3893                         arcmsr_get_hbc_config(acb);
3894                 }
3895                 break;
3896         case ACB_ADAPTER_TYPE_D: {
3897                         arcmsr_get_hbd_config(acb);
3898                 }
3899                 break;
3900         case ACB_ADAPTER_TYPE_E: {
3901                         arcmsr_get_hbe_config(acb);
3902                 }
3903                 break;
3904         }
3905 }
3906 /*
3907 **********************************************************************
3908 **********************************************************************
3909 */
3910 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3911 {
3912         int     timeout=0;
3913
3914         switch (acb->adapter_type) {
3915         case ACB_ADAPTER_TYPE_A: {
3916                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3917                         {
3918                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3919                                 {
3920                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3921                                         return;
3922                                 }
3923                                 UDELAY(15000); /* wait 15 milli-seconds */
3924                         }
3925                 }
3926                 break;
3927         case ACB_ADAPTER_TYPE_B: {
3928                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3929                         while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3930                         {
3931                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3932                                 {
3933                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3934                                         return;
3935                                 }
3936                                 UDELAY(15000); /* wait 15 milli-seconds */
3937                         }
3938                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3939                 }
3940                 break;
3941         case ACB_ADAPTER_TYPE_C: {
3942                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3943                         {
3944                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3945                                 {
3946                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3947                                         return;
3948                                 }
3949                                 UDELAY(15000); /* wait 15 milli-seconds */
3950                         }
3951                 }
3952                 break;
3953         case ACB_ADAPTER_TYPE_D: {
3954                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3955                         {
3956                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3957                                 {
3958                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3959                                         return;
3960                                 }
3961                                 UDELAY(15000); /* wait 15 milli-seconds */
3962                         }
3963                 }
3964                 break;
3965         case ACB_ADAPTER_TYPE_E: {
3966                         while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
3967                         {
3968                                 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
3969                                 {
3970                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3971                                         return;
3972                                 }
3973                                 UDELAY(15000); /* wait 15 milli-seconds */
3974                         }
3975                 }
3976                 break;
3977         }
3978 }
3979 /*
3980 **********************************************************************
3981 **********************************************************************
3982 */
3983 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3984 {
3985         u_int32_t outbound_doorbell;
3986
3987         switch (acb->adapter_type) {
3988         case ACB_ADAPTER_TYPE_A: {
3989                         /* empty doorbell Qbuffer if door bell ringed */
3990                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3991                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3992                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3993                 }
3994                 break;
3995         case ACB_ADAPTER_TYPE_B: {
3996                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3997                         WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3998                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3999                         /* let IOP know data has been read */
4000                 }
4001                 break;
4002         case ACB_ADAPTER_TYPE_C: {
4003                         /* empty doorbell Qbuffer if door bell ringed */
4004                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
4005                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
4006                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
4007                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
4008                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
4009                 }
4010                 break;
4011         case ACB_ADAPTER_TYPE_D: {
4012                         /* empty doorbell Qbuffer if door bell ringed */
4013                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
4014                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
4015                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
4016                 }
4017                 break;
4018         case ACB_ADAPTER_TYPE_E: {
4019                         /* empty doorbell Qbuffer if door bell ringed */
4020                         acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
4021                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);       /*clear doorbell interrupt */
4022                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4023                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4024                 }
4025                 break;
4026         }
4027 }
4028 /*
4029 ************************************************************************
4030 ************************************************************************
4031 */
4032 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
4033 {
4034         unsigned long srb_phyaddr;
4035         u_int32_t srb_phyaddr_hi32;
4036         u_int32_t srb_phyaddr_lo32;
4037
4038         /*
4039         ********************************************************************
4040         ** here we need to tell iop 331 our freesrb.HighPart
4041         ** if freesrb.HighPart is not zero
4042         ********************************************************************
4043         */
4044         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
4045         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
4046         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
4047         switch (acb->adapter_type) {
4048         case ACB_ADAPTER_TYPE_A: {
4049                         if(srb_phyaddr_hi32 != 0) {
4050                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4051                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4052                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4053                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
4054                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4055                                         return FALSE;
4056                                 }
4057                         }
4058                 }
4059                 break;
4060                 /*
4061                 ***********************************************************************
4062                 **    if adapter type B, set window of "post command Q"
4063                 ***********************************************************************
4064                 */
4065         case ACB_ADAPTER_TYPE_B: {
4066                         u_int32_t post_queue_phyaddr;
4067                         struct HBB_MessageUnit *phbbmu;
4068
4069                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4070                         phbbmu->postq_index = 0;
4071                         phbbmu->doneq_index = 0;
4072                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
4073                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4074                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
4075                                 return FALSE;
4076                         }
4077                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
4078                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
4079                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4080                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
4081                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
4082                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
4083                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
4084                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
4085                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4086                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
4087                                 return FALSE;
4088                         }
4089                         WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
4090                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4091                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
4092                                 return FALSE;
4093                         }
4094                 }
4095                 break;
4096         case ACB_ADAPTER_TYPE_C: {
4097                         if(srb_phyaddr_hi32 != 0) {
4098                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4099                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4100                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4101                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
4102                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
4103                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4104                                         return FALSE;
4105                                 }
4106                         }
4107                 }
4108                 break;
4109         case ACB_ADAPTER_TYPE_D: {
4110                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
4111                         struct HBD_MessageUnit0 *phbdmu;
4112
4113                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4114                         phbdmu->postq_index = 0;
4115                         phbdmu->doneq_index = 0x40FF;
4116                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4117                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
4118                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
4119                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
4120                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
4121                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
4122                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
4123                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
4124                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
4125                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4126                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
4127                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4128                                 return FALSE;
4129                         }
4130                 }
4131                 break;
4132         case ACB_ADAPTER_TYPE_E: {
4133                         u_int32_t cdb_phyaddr_lo32;
4134                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
4135                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
4136                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884);
4137                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32);
4138                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32);
4139                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE);
4140                         cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
4141                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32);
4142                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32);
4143                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE);
4144                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
4145                         acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4146                         CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
4147                         if(!arcmsr_hbe_wait_msgint_ready(acb)) {
4148                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
4149                                 return FALSE;
4150                         }
4151                 }
4152                 break;
4153         }
4154         return (TRUE);
4155 }
4156 /*
4157 ************************************************************************
4158 ************************************************************************
4159 */
4160 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4161 {
4162         if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
4163         {
4164                 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4165                 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
4166                 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
4167                         printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
4168                         return;
4169                 }
4170         }
4171 }
4172 /*
4173 **********************************************************************
4174 **********************************************************************
4175 */
4176 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4177 {
4178         u_int32_t intmask_org;
4179
4180         /* disable all outbound interrupt */
4181         intmask_org = arcmsr_disable_allintr(acb);
4182         arcmsr_wait_firmware_ready(acb);
4183         arcmsr_iop_confirm(acb);
4184         arcmsr_get_firmware_spec(acb);
4185         /*start background rebuild*/
4186         arcmsr_start_adapter_bgrb(acb);
4187         /* empty doorbell Qbuffer if door bell ringed */
4188         arcmsr_clear_doorbell_queue_buffer(acb);
4189         arcmsr_enable_eoi_mode(acb);
4190         /* enable outbound Post Queue, outbound doorbell Interrupt */
4191         arcmsr_enable_allintr(acb, intmask_org);
4192         acb->acb_flags |= ACB_F_IOP_INITED;
4193 }
4194 /*
4195 **********************************************************************
4196 **********************************************************************
4197 */
4198 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4199 {
4200         struct AdapterControlBlock *acb = arg;
4201         struct CommandControlBlock *srb_tmp;
4202         u_int32_t i;
4203         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
4204
4205         acb->srb_phyaddr.phyaddr = srb_phyaddr;
4206         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
4207         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4208                 if(bus_dmamap_create(acb->dm_segs_dmat,
4209                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
4210                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
4211                         printf("arcmsr%d:"
4212                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
4213                         return;
4214                 }
4215                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
4216                          || (acb->adapter_type == ACB_ADAPTER_TYPE_E))
4217                 {
4218                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
4219                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
4220                 }
4221                 else
4222                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
4223                 srb_tmp->acb = acb;
4224                 srb_tmp->smid = i << 16;
4225                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
4226                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
4227                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
4228         }
4229         if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
4230                 acb->pCompletionQ = (pCompletion_Q)srb_tmp;
4231         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
4232 }
4233 /*
4234 ************************************************************************
4235 ************************************************************************
4236 */
4237 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
4238 {
4239         /* remove the control device */
4240         if(acb->ioctl_dev != NULL) {
4241                 destroy_dev(acb->ioctl_dev);
4242         }
4243         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
4244         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
4245         bus_dma_tag_destroy(acb->srb_dmat);
4246         bus_dma_tag_destroy(acb->dm_segs_dmat);
4247         bus_dma_tag_destroy(acb->parent_dmat);
4248 }
4249 /*
4250 ************************************************************************
4251 ************************************************************************
4252 */
4253 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
4254 {
4255         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
4256         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
4257         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
4258         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
4259 }
4260 /*
4261 ************************************************************************
4262 ************************************************************************
4263 */
4264 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
4265 {
4266         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
4267         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
4268         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
4269         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
4270 }
4271 /*
4272 ************************************************************************
4273 ************************************************************************
4274 */
4275 static u_int32_t arcmsr_initialize(device_t dev)
4276 {
4277         struct AdapterControlBlock *acb = device_get_softc(dev);
4278         u_int16_t pci_command;
4279         int i, j,max_coherent_size;
4280         u_int32_t vendor_dev_id;
4281
4282         vendor_dev_id = pci_get_devid(dev);
4283         acb->vendor_device_id = vendor_dev_id;
4284         acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4285         switch (vendor_dev_id) {
4286         case PCIDevVenIDARC1880:
4287         case PCIDevVenIDARC1882:
4288         case PCIDevVenIDARC1213:
4289         case PCIDevVenIDARC1223: {
4290                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
4291                         if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4292                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4293                             (acb->sub_device_id == ARECA_SUB_DEV_ID_1226))
4294                                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4295                         else
4296                                 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4297                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4298                 }
4299                 break;
4300         case PCIDevVenIDARC1884:
4301                 acb->adapter_type = ACB_ADAPTER_TYPE_E;
4302                 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
4303                 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
4304                 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
4305                 break;
4306         case PCIDevVenIDARC1214: {
4307                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
4308                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4309                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4310                 }
4311                 break;
4312         case PCIDevVenIDARC1200:
4313         case PCIDevVenIDARC1201: {
4314                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4315                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4316                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4317                 }
4318                 break;
4319         case PCIDevVenIDARC1203: {
4320                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
4321                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4322                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4323                 }
4324                 break;
4325         case PCIDevVenIDARC1110:
4326         case PCIDevVenIDARC1120:
4327         case PCIDevVenIDARC1130:
4328         case PCIDevVenIDARC1160:
4329         case PCIDevVenIDARC1170:
4330         case PCIDevVenIDARC1210:
4331         case PCIDevVenIDARC1220:
4332         case PCIDevVenIDARC1230:
4333         case PCIDevVenIDARC1231:
4334         case PCIDevVenIDARC1260:
4335         case PCIDevVenIDARC1261:
4336         case PCIDevVenIDARC1270:
4337         case PCIDevVenIDARC1280:
4338         case PCIDevVenIDARC1212:
4339         case PCIDevVenIDARC1222:
4340         case PCIDevVenIDARC1380:
4341         case PCIDevVenIDARC1381:
4342         case PCIDevVenIDARC1680:
4343         case PCIDevVenIDARC1681: {
4344                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
4345                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4346                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4347                 }
4348                 break;
4349         default: {
4350                         printf("arcmsr%d:"
4351                         " unknown RAID adapter type \n", device_get_unit(dev));
4352                         return ENOMEM;
4353                 }
4354         }
4355         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4356                                 /*alignemnt*/           1,
4357                                 /*boundary*/            0,
4358                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4359                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4360                                 /*filter*/              NULL,
4361                                 /*filterarg*/           NULL,
4362                                 /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4363                                 /*nsegments*/           BUS_SPACE_UNRESTRICTED,
4364                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4365                                 /*flags*/               0,
4366                                 /*lockfunc*/            NULL,
4367                                 /*lockarg*/             NULL,
4368                                                         &acb->parent_dmat) != 0)
4369         {
4370                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4371                 return ENOMEM;
4372         }
4373
4374         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4375         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4376                                 /*alignment*/           1,
4377                                 /*boundary*/            0,
4378 #ifdef PAE
4379                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4380 #else
4381                                 /*lowaddr*/             BUS_SPACE_MAXADDR,
4382 #endif
4383                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4384                                 /*filter*/              NULL,
4385                                 /*filterarg*/           NULL,
4386                                 /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4387                                 /*nsegments*/           ARCMSR_MAX_SG_ENTRIES,
4388                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4389                                 /*flags*/               0,
4390                                 /*lockfunc*/            busdma_lock_mutex,
4391                                 /*lockarg*/             &acb->isr_lock,
4392                                                         &acb->dm_segs_dmat) != 0)
4393         {
4394                 bus_dma_tag_destroy(acb->parent_dmat);
4395                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4396                 return ENOMEM;
4397         }
4398
4399         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4400         if(bus_dma_tag_create(  /*parent_dmat*/         acb->parent_dmat,
4401                                 /*alignment*/           0x20,
4402                                 /*boundary*/            0,
4403                                 /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4404                                 /*highaddr*/            BUS_SPACE_MAXADDR,
4405                                 /*filter*/              NULL,
4406                                 /*filterarg*/           NULL,
4407                                 /*maxsize*/             max_coherent_size,
4408                                 /*nsegments*/           1,
4409                                 /*maxsegsz*/            BUS_SPACE_MAXSIZE_32BIT,
4410                                 /*flags*/               0,
4411                                 /*lockfunc*/            NULL,
4412                                 /*lockarg*/             NULL,
4413                                                         &acb->srb_dmat) != 0)
4414         {
4415                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4416                 bus_dma_tag_destroy(acb->parent_dmat);
4417                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4418                 return ENXIO;
4419         }
4420         /* Allocation for our srbs */
4421         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4422                 bus_dma_tag_destroy(acb->srb_dmat);
4423                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4424                 bus_dma_tag_destroy(acb->parent_dmat);
4425                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4426                 return ENXIO;
4427         }
4428         /* And permanently map them */
4429         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4430                 bus_dma_tag_destroy(acb->srb_dmat);
4431                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4432                 bus_dma_tag_destroy(acb->parent_dmat);
4433                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4434                 return ENXIO;
4435         }
4436         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4437         pci_command |= PCIM_CMD_BUSMASTEREN;
4438         pci_command |= PCIM_CMD_PERRESPEN;
4439         pci_command |= PCIM_CMD_MWRICEN;
4440         /* Enable Busmaster */
4441         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4442         switch(acb->adapter_type) {
4443         case ACB_ADAPTER_TYPE_A: {
4444                 u_int32_t rid0 = PCIR_BAR(0);
4445                 vm_offset_t     mem_base0;
4446
4447                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4448                 if(acb->sys_res_arcmsr[0] == NULL) {
4449                         arcmsr_free_resource(acb);
4450                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4451                         return ENOMEM;
4452                 }
4453                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4454                         arcmsr_free_resource(acb);
4455                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4456                         return ENXIO;
4457                 }
4458                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4459                 if(mem_base0 == 0) {
4460                         arcmsr_free_resource(acb);
4461                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4462                         return ENXIO;
4463                 }
4464                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4465                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4466                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4467                 acb->rid[0] = rid0;
4468                 }
4469                 break;
4470         case ACB_ADAPTER_TYPE_B: {
4471                 struct HBB_MessageUnit *phbbmu;
4472                 struct CommandControlBlock *freesrb;
4473                 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4474                 vm_offset_t     mem_base[]={0,0};
4475                 for(i=0; i < 2; i++) {
4476                         acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE);
4477                         if(acb->sys_res_arcmsr[i] == NULL) {
4478                                 arcmsr_free_resource(acb);
4479                                 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4480                                 return ENOMEM;
4481                         }
4482                         if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4483                                 arcmsr_free_resource(acb);
4484                                 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4485                                 return ENXIO;
4486                         }
4487                         mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4488                         if(mem_base[i] == 0) {
4489                                 arcmsr_free_resource(acb);
4490                                 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4491                                 return ENXIO;
4492                         }
4493                         acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4494                         acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4495                 }
4496                 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4497                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4498                 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4499                 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4500                 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4501                 if (vendor_dev_id == PCIDevVenIDARC1203) {
4502                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4503                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4504                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4505                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4506                 } else {
4507                         phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4508                         phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4509                         phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4510                         phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4511                 }
4512                 acb->rid[0] = rid[0];
4513                 acb->rid[1] = rid[1];
4514                 }
4515                 break;
4516         case ACB_ADAPTER_TYPE_C: {
4517                 u_int32_t rid0 = PCIR_BAR(1);
4518                 vm_offset_t     mem_base0;
4519
4520                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4521                 if(acb->sys_res_arcmsr[0] == NULL) {
4522                         arcmsr_free_resource(acb);
4523                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4524                         return ENOMEM;
4525                 }
4526                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4527                         arcmsr_free_resource(acb);
4528                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4529                         return ENXIO;
4530                 }
4531                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4532                 if(mem_base0 == 0) {
4533                         arcmsr_free_resource(acb);
4534                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4535                         return ENXIO;
4536                 }
4537                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4538                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4539                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4540                 acb->rid[0] = rid0;
4541                 }
4542                 break;
4543         case ACB_ADAPTER_TYPE_D: {
4544                 struct HBD_MessageUnit0 *phbdmu;
4545                 u_int32_t rid0 = PCIR_BAR(0);
4546                 vm_offset_t     mem_base0;
4547
4548                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4549                 if(acb->sys_res_arcmsr[0] == NULL) {
4550                         arcmsr_free_resource(acb);
4551                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4552                         return ENOMEM;
4553                 }
4554                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4555                         arcmsr_free_resource(acb);
4556                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4557                         return ENXIO;
4558                 }
4559                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4560                 if(mem_base0 == 0) {
4561                         arcmsr_free_resource(acb);
4562                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4563                         return ENXIO;
4564                 }
4565                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4566                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4567                 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4568                 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4569                 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4570                 acb->rid[0] = rid0;
4571                 }
4572                 break;
4573         case ACB_ADAPTER_TYPE_E: {
4574                 u_int32_t rid0 = PCIR_BAR(1);
4575                 vm_offset_t     mem_base0;
4576
4577                 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4578                 if(acb->sys_res_arcmsr[0] == NULL) {
4579                         arcmsr_free_resource(acb);
4580                         printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4581                         return ENOMEM;
4582                 }
4583                 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4584                         arcmsr_free_resource(acb);
4585                         printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4586                         return ENXIO;
4587                 }
4588                 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4589                 if(mem_base0 == 0) {
4590                         arcmsr_free_resource(acb);
4591                         printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4592                         return ENXIO;
4593                 }
4594                 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4595                 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4596                 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4597                 acb->doneq_index = 0;
4598                 acb->in_doorbell = 0;
4599                 acb->out_doorbell = 0;
4600                 acb->rid[0] = rid0;
4601                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
4602                 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
4603                 }
4604                 break;
4605         }
4606         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4607                 arcmsr_free_resource(acb);
4608                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4609                 return ENXIO;
4610         }
4611         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4612         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4613         /*
4614         ********************************************************************
4615         ** init raid volume state
4616         ********************************************************************
4617         */
4618         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4619                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4620                         acb->devstate[i][j] = ARECA_RAID_GONE;
4621                 }
4622         }
4623         arcmsr_iop_init(acb);
4624         return(0);
4625 }
4626
4627 static int arcmsr_setup_msix(struct AdapterControlBlock *acb)
4628 {
4629         int i;
4630
4631         for (i = 0; i < acb->msix_vectors; i++) {
4632                 acb->irq_id[i] = 1 + i;
4633                 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev,
4634                     SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE);
4635                 if (acb->irqres[i] == NULL) {
4636                         printf("arcmsr: Can't allocate MSI-X resource\n");
4637                         goto irq_alloc_failed;
4638                 }
4639                 if (bus_setup_intr(acb->pci_dev, acb->irqres[i],
4640                     INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler,
4641                     acb, &acb->ih[i])) {
4642                         printf("arcmsr: Cannot set up MSI-X interrupt handler\n");
4643                         goto irq_alloc_failed;
4644                 }
4645         }
4646         printf("arcmsr: MSI-X INT enabled\n");
4647         acb->acb_flags |= ACB_F_MSIX_ENABLED;
4648         return TRUE;
4649
4650 irq_alloc_failed:
4651         arcmsr_teardown_intr(acb->pci_dev, acb);
4652         return FALSE;
4653 }
4654
4655 /*
4656 ************************************************************************
4657 ************************************************************************
4658 */
4659 static int arcmsr_attach(device_t dev)
4660 {
4661         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4662         u_int32_t unit=device_get_unit(dev);
4663         struct ccb_setasync csa;
4664         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4665         struct resource *irqres;
4666
4667         if(acb == NULL) {
4668                 printf("arcmsr%d: cannot allocate softc\n", unit);
4669                 return (ENOMEM);
4670         }
4671         arcmsr_mutex_init(acb);
4672         acb->pci_dev = dev;
4673         acb->pci_unit = unit;
4674         if(arcmsr_initialize(dev)) {
4675                 printf("arcmsr%d: initialize failure!\n", unit);
4676                 goto initialize_failed;
4677         }
4678         /* After setting up the adapter, map our interrupt */
4679         acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS;
4680         if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) {
4681                 if (arcmsr_setup_msix(acb) == TRUE)
4682                         goto irqx;
4683         }
4684         acb->irq_id[0] = 0;
4685         irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
4686         if(irqres == NULL ||
4687                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) {
4688                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4689                 goto setup_intr_failed;
4690         }
4691         acb->irqres[0] = irqres;
4692 irqx:
4693         /*
4694          * Now let the CAM generic SCSI layer find the SCSI devices on
4695          * the bus *  start queue to reset to the idle loop. *
4696          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4697          * max_sim_transactions
4698         */
4699         devq = cam_simq_alloc(acb->maxOutstanding);
4700         if(devq == NULL) {
4701                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4702                 goto simq_alloc_failed;
4703         }
4704         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4705         if(acb->psim == NULL) {
4706                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4707                 goto sim_alloc_failed;
4708         }
4709         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4710         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4711                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4712                 goto xpt_bus_failed;
4713         }
4714         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4715                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4716                 goto xpt_path_failed;
4717         }
4718         /*
4719         ****************************************************
4720         */
4721         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4722         csa.ccb_h.func_code = XPT_SASYNC_CB;
4723         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4724         csa.callback = arcmsr_async;
4725         csa.callback_arg = acb->psim;
4726         xpt_action((union ccb *)&csa);
4727         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4728         /* Create the control device.  */
4729         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4730
4731         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4732         arcmsr_callout_init(&acb->devmap_callout);
4733         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4734         return (0);
4735 xpt_path_failed:
4736         xpt_bus_deregister(cam_sim_path(acb->psim));
4737 xpt_bus_failed:
4738         cam_sim_free(acb->psim, /* free_simq */ TRUE);
4739 sim_alloc_failed:
4740         cam_simq_free(devq);
4741 simq_alloc_failed:
4742         arcmsr_teardown_intr(dev, acb);
4743 setup_intr_failed:
4744         arcmsr_free_resource(acb);
4745 initialize_failed:
4746         arcmsr_mutex_destroy(acb);
4747         return ENXIO;
4748 }
4749
4750 /*
4751 ************************************************************************
4752 ************************************************************************
4753 */
4754 static int arcmsr_probe(device_t dev)
4755 {
4756         u_int32_t id;
4757         u_int16_t sub_device_id;
4758         static char buf[256];
4759         char x_type[]={"unknown"};
4760         char *type;
4761         int raid6 = 1;
4762
4763         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4764                 return (ENXIO);
4765         }
4766         sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4767         switch(id = pci_get_devid(dev)) {
4768         case PCIDevVenIDARC1110:
4769         case PCIDevVenIDARC1200:
4770         case PCIDevVenIDARC1201:
4771         case PCIDevVenIDARC1210:
4772                 raid6 = 0;
4773                 /*FALLTHRU*/
4774         case PCIDevVenIDARC1120:
4775         case PCIDevVenIDARC1130:
4776         case PCIDevVenIDARC1160:
4777         case PCIDevVenIDARC1170:
4778         case PCIDevVenIDARC1220:
4779         case PCIDevVenIDARC1230:
4780         case PCIDevVenIDARC1231:
4781         case PCIDevVenIDARC1260:
4782         case PCIDevVenIDARC1261:
4783         case PCIDevVenIDARC1270:
4784         case PCIDevVenIDARC1280:
4785                 type = "SATA 3G";
4786                 break;
4787         case PCIDevVenIDARC1212:
4788         case PCIDevVenIDARC1222:
4789         case PCIDevVenIDARC1380:
4790         case PCIDevVenIDARC1381:
4791         case PCIDevVenIDARC1680:
4792         case PCIDevVenIDARC1681:
4793                 type = "SAS 3G";
4794                 break;
4795         case PCIDevVenIDARC1880:
4796         case PCIDevVenIDARC1882:
4797         case PCIDevVenIDARC1213:
4798         case PCIDevVenIDARC1223:
4799                 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) ||
4800                     (sub_device_id == ARECA_SUB_DEV_ID_1216) ||
4801                     (sub_device_id == ARECA_SUB_DEV_ID_1226))
4802                         type = "SAS 12G";
4803                 else
4804                         type = "SAS 6G";
4805                 break;
4806         case PCIDevVenIDARC1884:
4807                 type = "SAS 12G";
4808                 break;
4809         case PCIDevVenIDARC1214:
4810         case PCIDevVenIDARC1203:
4811                 type = "SATA 6G";
4812                 break;
4813         default:
4814                 type = x_type;
4815                 raid6 = 0;
4816                 break;
4817         }
4818         if(type == x_type)
4819                 return(ENXIO);
4820         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4821                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4822         device_set_desc_copy(dev, buf);
4823         return (BUS_PROBE_DEFAULT);
4824 }
4825 /*
4826 ************************************************************************
4827 ************************************************************************
4828 */
4829 static int arcmsr_shutdown(device_t dev)
4830 {
4831         u_int32_t  i;
4832         u_int32_t intmask_org;
4833         struct CommandControlBlock *srb;
4834         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4835
4836         /* stop adapter background rebuild */
4837         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4838         /* disable all outbound interrupt */
4839         intmask_org = arcmsr_disable_allintr(acb);
4840         arcmsr_stop_adapter_bgrb(acb);
4841         arcmsr_flush_adapter_cache(acb);
4842         /* abort all outstanding command */
4843         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4844         acb->acb_flags &= ~ACB_F_IOP_INITED;
4845         if(acb->srboutstandingcount != 0) {
4846                 /*clear and abort all outbound posted Q*/
4847                 arcmsr_done4abort_postqueue(acb);
4848                 /* talk to iop 331 outstanding command aborted*/
4849                 arcmsr_abort_allcmd(acb);
4850                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4851                         srb = acb->psrb_pool[i];
4852                         if(srb->srb_state == ARCMSR_SRB_START) {
4853                                 srb->srb_state = ARCMSR_SRB_ABORTED;
4854                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4855                                 arcmsr_srb_complete(srb, 1);
4856                         }
4857                 }
4858         }
4859         acb->srboutstandingcount = 0;
4860         acb->workingsrb_doneindex = 0;
4861         acb->workingsrb_startindex = 0;
4862         acb->pktRequestCount = 0;
4863         acb->pktReturnCount = 0;
4864         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4865         return (0);
4866 }
4867 /*
4868 ************************************************************************
4869 ************************************************************************
4870 */
4871 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb)
4872 {
4873         int i;
4874
4875         if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
4876                 for (i = 0; i < acb->msix_vectors; i++) {
4877                         if (acb->ih[i])
4878                                 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]);
4879                         if (acb->irqres[i] != NULL)
4880                                 bus_release_resource(dev, SYS_RES_IRQ,
4881                                     acb->irq_id[i], acb->irqres[i]);
4882
4883                         acb->ih[i] = NULL;
4884                 }
4885                 pci_release_msi(dev);
4886         } else {
4887                 if (acb->ih[0])
4888                         bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]);
4889                 if (acb->irqres[0] != NULL)
4890                         bus_release_resource(dev, SYS_RES_IRQ,
4891                             acb->irq_id[0], acb->irqres[0]);
4892                 acb->ih[0] = NULL;
4893         }
4894
4895 }
4896 /*
4897 ************************************************************************
4898 ************************************************************************
4899 */
4900 static int arcmsr_detach(device_t dev)
4901 {
4902         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4903         int i;
4904
4905         callout_stop(&acb->devmap_callout);
4906         arcmsr_teardown_intr(dev, acb);
4907         arcmsr_shutdown(dev);
4908         arcmsr_free_resource(acb);
4909         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4910                 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]);
4911         }
4912         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4913         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4914         xpt_free_path(acb->ppath);
4915         xpt_bus_deregister(cam_sim_path(acb->psim));
4916         cam_sim_free(acb->psim, TRUE);
4917         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4918         arcmsr_mutex_destroy(acb);
4919         return (0);
4920 }
4921
4922 #ifdef ARCMSR_DEBUG1
4923 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4924 {
4925         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4926                 return;
4927         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4928         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4929         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4930         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4931 }
4932 #endif