2 ********************************************************************************
4 ** FILE NAME : arcmsr.c
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
14 ** Redistribution and use in source and binary forms, with or without
15 ** modification, are permitted provided that the following conditions
17 ** 1. Redistributions of source code must retain the above copyright
18 ** notice, this list of conditions and the following disclaimer.
19 ** 2. Redistributions in binary form must reproduce the above copyright
20 ** notice, this list of conditions and the following disclaimer in the
21 ** documentation and/or other materials provided with the distribution.
22 ** 3. The name of the author may not be used to endorse or promote products
23 ** derived from this software without specific prior written permission.
25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ********************************************************************************
38 ** REV# DATE NAME DESCRIPTION
39 ** 1.00.00.00 03/31/2004 Erich Chen First release
40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error
41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support
42 ** clean unused function
43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling,
44 ** firmware version check
45 ** and firmware update notify for hardware bug fix
46 ** handling if none zero high part physical address
48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy
49 ** add iop message xfer
50 ** with scsi pass-through command
51 ** add new device id of sas raid adapters
52 ** code fit for SPARC64 & PPC
53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report
54 ** and cause g_vfs_done() read write error
55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x
56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x
57 ** bus_dmamem_alloc() with BUS_DMA_ZERO
58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880
59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
60 ** prevent cam_periph_error removing all LUN devices of one Target id
61 ** for any one LUN device failed
62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step"
63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function
66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout
67 ** 02/14/2011 Ching Huang Modified pktRequestCount
68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it
69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic
70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start
71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed
72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command
73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition
74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter
75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284
76 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4
77 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs
78 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883
79 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
80 ******************************************************************************************
83 #include <sys/cdefs.h>
84 __FBSDID("$FreeBSD$");
87 #define ARCMSR_DEBUG1 1
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/malloc.h>
92 #include <sys/kernel.h>
94 #include <sys/queue.h>
96 #include <sys/devicestat.h>
97 #include <sys/kthread.h>
98 #include <sys/module.h>
100 #include <sys/lock.h>
101 #include <sys/sysctl.h>
102 #include <sys/poll.h>
103 #include <sys/ioccom.h>
105 #include <vm/vm_param.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
112 #include <machine/atomic.h>
113 #include <sys/conf.h>
114 #include <sys/rman.h>
117 #include <cam/cam_ccb.h>
118 #include <cam/cam_sim.h>
119 #include <cam/cam_periph.h>
120 #include <cam/cam_xpt_periph.h>
121 #include <cam/cam_xpt_sim.h>
122 #include <cam/cam_debug.h>
123 #include <cam/scsi/scsi_all.h>
124 #include <cam/scsi/scsi_message.h>
126 **************************************************************************
127 **************************************************************************
129 #if __FreeBSD_version >= 500005
130 #include <sys/selinfo.h>
131 #include <sys/mutex.h>
132 #include <sys/endian.h>
133 #include <dev/pci/pcivar.h>
134 #include <dev/pci/pcireg.h>
136 #include <sys/select.h>
137 #include <pci/pcivar.h>
138 #include <pci/pcireg.h>
141 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
142 #define CAM_NEW_TRAN_CODE 1
145 #if __FreeBSD_version > 500000
146 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
148 #define arcmsr_callout_init(a) callout_init(a);
151 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.30.00.00 2015-11-30"
152 #include <dev/arcmsr/arcmsr.h>
154 **************************************************************************
155 **************************************************************************
157 static void arcmsr_free_srb(struct CommandControlBlock *srb);
158 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
159 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
160 static int arcmsr_probe(device_t dev);
161 static int arcmsr_attach(device_t dev);
162 static int arcmsr_detach(device_t dev);
163 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
164 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
165 static int arcmsr_shutdown(device_t dev);
166 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
167 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
168 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
169 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
170 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
171 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
172 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
173 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
174 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
175 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
176 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
177 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
178 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
179 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
180 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
181 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
182 static int arcmsr_resume(device_t dev);
183 static int arcmsr_suspend(device_t dev);
184 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
185 static void arcmsr_polling_devmap(void *arg);
186 static void arcmsr_srb_timeout(void *arg);
187 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
189 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
192 **************************************************************************
193 **************************************************************************
195 static void UDELAY(u_int32_t us) { DELAY(us); }
197 **************************************************************************
198 **************************************************************************
200 static bus_dmamap_callback_t arcmsr_map_free_srb;
201 static bus_dmamap_callback_t arcmsr_execute_srb;
203 **************************************************************************
204 **************************************************************************
206 static d_open_t arcmsr_open;
207 static d_close_t arcmsr_close;
208 static d_ioctl_t arcmsr_ioctl;
210 static device_method_t arcmsr_methods[]={
211 DEVMETHOD(device_probe, arcmsr_probe),
212 DEVMETHOD(device_attach, arcmsr_attach),
213 DEVMETHOD(device_detach, arcmsr_detach),
214 DEVMETHOD(device_shutdown, arcmsr_shutdown),
215 DEVMETHOD(device_suspend, arcmsr_suspend),
216 DEVMETHOD(device_resume, arcmsr_resume),
218 #if __FreeBSD_version >= 803000
225 static driver_t arcmsr_driver={
226 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
229 static devclass_t arcmsr_devclass;
230 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
231 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
232 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
233 #ifndef BUS_DMA_COHERENT
234 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */
236 #if __FreeBSD_version >= 501000
237 static struct cdevsw arcmsr_cdevsw={
238 #if __FreeBSD_version >= 503000
239 .d_version = D_VERSION,
241 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
242 .d_flags = D_NEEDGIANT,
244 .d_open = arcmsr_open, /* open */
245 .d_close = arcmsr_close, /* close */
246 .d_ioctl = arcmsr_ioctl, /* ioctl */
247 .d_name = "arcmsr", /* name */
250 #define ARCMSR_CDEV_MAJOR 180
252 static struct cdevsw arcmsr_cdevsw = {
253 arcmsr_open, /* open */
254 arcmsr_close, /* close */
257 arcmsr_ioctl, /* ioctl */
260 nostrategy, /* strategy */
262 ARCMSR_CDEV_MAJOR, /* major */
269 **************************************************************************
270 **************************************************************************
272 #if __FreeBSD_version < 500005
273 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
275 #if __FreeBSD_version < 503000
276 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
278 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
282 #if __FreeBSD_version < 503000
283 struct AdapterControlBlock *acb = dev->si_drv1;
285 int unit = dev2unit(dev);
286 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
294 **************************************************************************
295 **************************************************************************
297 #if __FreeBSD_version < 500005
298 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
300 #if __FreeBSD_version < 503000
301 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
303 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
307 #if __FreeBSD_version < 503000
308 struct AdapterControlBlock *acb = dev->si_drv1;
310 int unit = dev2unit(dev);
311 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
319 **************************************************************************
320 **************************************************************************
322 #if __FreeBSD_version < 500005
323 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
325 #if __FreeBSD_version < 503000
326 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
328 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
332 #if __FreeBSD_version < 503000
333 struct AdapterControlBlock *acb = dev->si_drv1;
335 int unit = dev2unit(dev);
336 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
342 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
345 **********************************************************************
346 **********************************************************************
348 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
350 u_int32_t intmask_org = 0;
352 switch (acb->adapter_type) {
353 case ACB_ADAPTER_TYPE_A: {
354 /* disable all outbound interrupt */
355 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
356 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
359 case ACB_ADAPTER_TYPE_B: {
360 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
361 /* disable all outbound interrupt */
362 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask)
363 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
364 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */
367 case ACB_ADAPTER_TYPE_C: {
368 /* disable all outbound interrupt */
369 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
370 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
373 case ACB_ADAPTER_TYPE_D: {
374 /* disable all outbound interrupt */
375 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
376 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
380 return (intmask_org);
383 **********************************************************************
384 **********************************************************************
386 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
390 switch (acb->adapter_type) {
391 case ACB_ADAPTER_TYPE_A: {
392 /* enable outbound Post Queue, outbound doorbell Interrupt */
393 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
394 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
395 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
398 case ACB_ADAPTER_TYPE_B: {
399 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
400 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
401 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
402 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
403 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
406 case ACB_ADAPTER_TYPE_C: {
407 /* enable outbound Post Queue, outbound doorbell Interrupt */
408 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
410 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
413 case ACB_ADAPTER_TYPE_D: {
414 /* enable outbound Post Queue, outbound doorbell Interrupt */
415 mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
416 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
417 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
418 acb->outbound_int_enable = mask;
424 **********************************************************************
425 **********************************************************************
427 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
430 u_int8_t Retries = 0x00;
433 for(Index=0; Index < 100; Index++) {
434 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
435 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
440 }while(Retries++ < 20);/*max 20 sec*/
444 **********************************************************************
445 **********************************************************************
447 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
450 u_int8_t Retries = 0x00;
451 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
454 for(Index=0; Index < 100; Index++) {
455 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
456 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
457 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
462 }while(Retries++ < 20);/*max 20 sec*/
466 **********************************************************************
467 **********************************************************************
469 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
472 u_int8_t Retries = 0x00;
475 for(Index=0; Index < 100; Index++) {
476 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
477 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
482 }while(Retries++ < 20);/*max 20 sec*/
486 **********************************************************************
487 **********************************************************************
489 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
492 u_int8_t Retries = 0x00;
495 for(Index=0; Index < 100; Index++) {
496 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
497 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
502 }while(Retries++ < 20);/*max 20 sec*/
506 ************************************************************************
507 ************************************************************************
509 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
511 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
513 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
515 if(arcmsr_hba_wait_msgint_ready(acb)) {
520 }while(retry_count != 0);
523 ************************************************************************
524 ************************************************************************
526 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
528 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
529 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
531 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
533 if(arcmsr_hbb_wait_msgint_ready(acb)) {
538 }while(retry_count != 0);
541 ************************************************************************
542 ************************************************************************
544 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
546 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
548 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
549 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
551 if(arcmsr_hbc_wait_msgint_ready(acb)) {
556 }while(retry_count != 0);
559 ************************************************************************
560 ************************************************************************
562 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
564 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
566 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
568 if(arcmsr_hbd_wait_msgint_ready(acb)) {
573 }while(retry_count != 0);
576 ************************************************************************
577 ************************************************************************
579 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
581 switch (acb->adapter_type) {
582 case ACB_ADAPTER_TYPE_A: {
583 arcmsr_flush_hba_cache(acb);
586 case ACB_ADAPTER_TYPE_B: {
587 arcmsr_flush_hbb_cache(acb);
590 case ACB_ADAPTER_TYPE_C: {
591 arcmsr_flush_hbc_cache(acb);
594 case ACB_ADAPTER_TYPE_D: {
595 arcmsr_flush_hbd_cache(acb);
601 *******************************************************************************
602 *******************************************************************************
604 static int arcmsr_suspend(device_t dev)
606 struct AdapterControlBlock *acb = device_get_softc(dev);
608 /* flush controller */
609 arcmsr_iop_parking(acb);
610 /* disable all outbound interrupt */
611 arcmsr_disable_allintr(acb);
615 *******************************************************************************
616 *******************************************************************************
618 static int arcmsr_resume(device_t dev)
620 struct AdapterControlBlock *acb = device_get_softc(dev);
622 arcmsr_iop_init(acb);
626 *********************************************************************************
627 *********************************************************************************
629 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
631 struct AdapterControlBlock *acb;
632 u_int8_t target_id, target_lun;
635 sim = (struct cam_sim *) cb_arg;
636 acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
639 target_id = xpt_path_target_id(path);
640 target_lun = xpt_path_lun_id(path);
641 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
644 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
651 **********************************************************************
652 **********************************************************************
654 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
656 union ccb *pccb = srb->pccb;
658 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
659 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
660 if(pccb->csio.sense_len) {
661 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
662 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
663 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
664 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
665 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
669 *********************************************************************
670 *********************************************************************
672 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
674 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
675 if(!arcmsr_hba_wait_msgint_ready(acb)) {
676 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
680 *********************************************************************
681 *********************************************************************
683 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
685 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
686 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
687 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
688 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
692 *********************************************************************
693 *********************************************************************
695 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
697 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
698 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
699 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
700 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
704 *********************************************************************
705 *********************************************************************
707 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
709 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
710 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
711 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
715 *********************************************************************
716 *********************************************************************
718 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
720 switch (acb->adapter_type) {
721 case ACB_ADAPTER_TYPE_A: {
722 arcmsr_abort_hba_allcmd(acb);
725 case ACB_ADAPTER_TYPE_B: {
726 arcmsr_abort_hbb_allcmd(acb);
729 case ACB_ADAPTER_TYPE_C: {
730 arcmsr_abort_hbc_allcmd(acb);
733 case ACB_ADAPTER_TYPE_D: {
734 arcmsr_abort_hbd_allcmd(acb);
740 **********************************************************************
741 **********************************************************************
743 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
745 struct AdapterControlBlock *acb = srb->acb;
746 union ccb *pccb = srb->pccb;
748 if(srb->srb_flags & SRB_FLAG_TIMER_START)
749 callout_stop(&srb->ccb_callout);
750 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
753 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
754 op = BUS_DMASYNC_POSTREAD;
756 op = BUS_DMASYNC_POSTWRITE;
758 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
759 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
761 if(stand_flag == 1) {
762 atomic_subtract_int(&acb->srboutstandingcount, 1);
763 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
764 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
765 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
766 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
769 if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
770 arcmsr_free_srb(srb);
771 acb->pktReturnCount++;
775 **************************************************************************
776 **************************************************************************
778 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
782 target = srb->pccb->ccb_h.target_id;
783 lun = srb->pccb->ccb_h.target_lun;
785 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
786 acb->devstate[target][lun] = ARECA_RAID_GOOD;
788 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
789 arcmsr_srb_complete(srb, 1);
791 switch(srb->arcmsr_cdb.DeviceStatus) {
792 case ARCMSR_DEV_SELECT_TIMEOUT: {
793 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
794 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
796 acb->devstate[target][lun] = ARECA_RAID_GONE;
797 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
798 arcmsr_srb_complete(srb, 1);
801 case ARCMSR_DEV_ABORTED:
802 case ARCMSR_DEV_INIT_FAIL: {
803 acb->devstate[target][lun] = ARECA_RAID_GONE;
804 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
805 arcmsr_srb_complete(srb, 1);
808 case SCSISTAT_CHECK_CONDITION: {
809 acb->devstate[target][lun] = ARECA_RAID_GOOD;
810 arcmsr_report_sense_info(srb);
811 arcmsr_srb_complete(srb, 1);
815 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
816 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
817 acb->devstate[target][lun] = ARECA_RAID_GONE;
818 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
819 /*unknown error or crc error just for retry*/
820 arcmsr_srb_complete(srb, 1);
826 **************************************************************************
827 **************************************************************************
829 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
831 struct CommandControlBlock *srb;
833 /* check if command done with no error*/
834 switch (acb->adapter_type) {
835 case ACB_ADAPTER_TYPE_C:
836 case ACB_ADAPTER_TYPE_D:
837 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
839 case ACB_ADAPTER_TYPE_A:
840 case ACB_ADAPTER_TYPE_B:
842 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
845 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
846 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
847 arcmsr_free_srb(srb);
848 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
851 printf("arcmsr%d: return srb has been completed\n"
852 "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
853 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
856 arcmsr_report_srb_state(acb, srb, error);
859 **************************************************************************
860 **************************************************************************
862 static void arcmsr_srb_timeout(void *arg)
864 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
865 struct AdapterControlBlock *acb;
869 target = srb->pccb->ccb_h.target_id;
870 lun = srb->pccb->ccb_h.target_lun;
872 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
873 if(srb->srb_state == ARCMSR_SRB_START)
875 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0];
876 srb->srb_state = ARCMSR_SRB_TIMEOUT;
877 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
878 arcmsr_srb_complete(srb, 1);
879 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
880 acb->pci_unit, target, lun, cmd, srb);
882 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
884 arcmsr_dump_data(acb);
889 **********************************************************************
890 **********************************************************************
892 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
898 switch (acb->adapter_type) {
899 case ACB_ADAPTER_TYPE_A: {
900 u_int32_t outbound_intstatus;
902 /*clear and abort all outbound posted Q*/
903 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
904 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
905 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
906 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
907 arcmsr_drain_donequeue(acb, flag_srb, error);
911 case ACB_ADAPTER_TYPE_B: {
912 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
914 /*clear all outbound posted Q*/
915 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
916 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
917 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
918 phbbmu->done_qbuffer[i] = 0;
919 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
920 arcmsr_drain_donequeue(acb, flag_srb, error);
922 phbbmu->post_qbuffer[i] = 0;
923 }/*drain reply FIFO*/
924 phbbmu->doneq_index = 0;
925 phbbmu->postq_index = 0;
928 case ACB_ADAPTER_TYPE_C: {
930 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
931 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
932 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
933 arcmsr_drain_donequeue(acb, flag_srb, error);
937 case ACB_ADAPTER_TYPE_D: {
938 arcmsr_hbd_postqueue_isr(acb);
944 ****************************************************************************
945 ****************************************************************************
947 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
949 struct CommandControlBlock *srb;
950 u_int32_t intmask_org;
953 if(acb->srboutstandingcount>0) {
954 /* disable all outbound interrupt */
955 intmask_org = arcmsr_disable_allintr(acb);
956 /*clear and abort all outbound posted Q*/
957 arcmsr_done4abort_postqueue(acb);
958 /* talk to iop 331 outstanding command aborted*/
959 arcmsr_abort_allcmd(acb);
960 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
961 srb = acb->psrb_pool[i];
962 if(srb->srb_state == ARCMSR_SRB_START) {
963 srb->srb_state = ARCMSR_SRB_ABORTED;
964 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
965 arcmsr_srb_complete(srb, 1);
966 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
967 , acb->pci_unit, srb->pccb->ccb_h.target_id
968 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
971 /* enable all outbound interrupt */
972 arcmsr_enable_allintr(acb, intmask_org);
974 acb->srboutstandingcount = 0;
975 acb->workingsrb_doneindex = 0;
976 acb->workingsrb_startindex = 0;
977 acb->pktRequestCount = 0;
978 acb->pktReturnCount = 0;
981 **********************************************************************
982 **********************************************************************
984 static void arcmsr_build_srb(struct CommandControlBlock *srb,
985 bus_dma_segment_t *dm_segs, u_int32_t nseg)
987 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
988 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
989 u_int32_t address_lo, address_hi;
990 union ccb *pccb = srb->pccb;
991 struct ccb_scsiio *pcsio = &pccb->csio;
992 u_int32_t arccdbsize = 0x30;
994 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
996 arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
997 arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
998 arcmsr_cdb->Function = 1;
999 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
1000 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len);
1002 struct AdapterControlBlock *acb = srb->acb;
1003 bus_dmasync_op_t op;
1004 u_int32_t length, i, cdb_sgcount = 0;
1006 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1007 op = BUS_DMASYNC_PREREAD;
1009 op = BUS_DMASYNC_PREWRITE;
1010 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1011 srb->srb_flags |= SRB_FLAG_WRITE;
1013 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1014 for(i=0; i < nseg; i++) {
1015 /* Get the physical address of the current data pointer */
1016 length = arcmsr_htole32(dm_segs[i].ds_len);
1017 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1018 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1019 if(address_hi == 0) {
1020 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1021 pdma_sg->address = address_lo;
1022 pdma_sg->length = length;
1023 psge += sizeof(struct SG32ENTRY);
1024 arccdbsize += sizeof(struct SG32ENTRY);
1026 u_int32_t sg64s_size = 0, tmplength = length;
1029 u_int64_t span4G, length0;
1030 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1032 span4G = (u_int64_t)address_lo + tmplength;
1033 pdma_sg->addresshigh = address_hi;
1034 pdma_sg->address = address_lo;
1035 if(span4G > 0x100000000) {
1036 /*see if cross 4G boundary*/
1037 length0 = 0x100000000-address_lo;
1038 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1039 address_hi = address_hi+1;
1041 tmplength = tmplength - (u_int32_t)length0;
1042 sg64s_size += sizeof(struct SG64ENTRY);
1043 psge += sizeof(struct SG64ENTRY);
1046 pdma_sg->length = tmplength | IS_SG64_ADDR;
1047 sg64s_size += sizeof(struct SG64ENTRY);
1048 psge += sizeof(struct SG64ENTRY);
1052 arccdbsize += sg64s_size;
1056 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1057 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1058 if( arccdbsize > 256) {
1059 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1062 arcmsr_cdb->DataLength = 0;
1064 srb->arc_cdb_size = arccdbsize;
1065 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1068 **************************************************************************
1069 **************************************************************************
1071 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1073 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1074 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1076 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1077 atomic_add_int(&acb->srboutstandingcount, 1);
1078 srb->srb_state = ARCMSR_SRB_START;
1080 switch (acb->adapter_type) {
1081 case ACB_ADAPTER_TYPE_A: {
1082 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1083 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1085 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1089 case ACB_ADAPTER_TYPE_B: {
1090 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1091 int ending_index, index;
1093 index = phbbmu->postq_index;
1094 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1095 phbbmu->post_qbuffer[ending_index] = 0;
1096 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1097 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1099 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1102 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
1103 phbbmu->postq_index = index;
1104 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1107 case ACB_ADAPTER_TYPE_C: {
1108 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1110 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1111 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1112 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1113 if(cdb_phyaddr_hi32)
1115 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1116 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1120 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1124 case ACB_ADAPTER_TYPE_D: {
1125 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1126 u_int16_t index_stripped;
1127 u_int16_t postq_index;
1128 struct InBound_SRB *pinbound_srb;
1130 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1131 postq_index = phbdmu->postq_index;
1132 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1133 pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1134 pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1135 pinbound_srb->length = srb->arc_cdb_size >> 2;
1136 arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1137 if (postq_index & 0x4000) {
1138 index_stripped = postq_index & 0xFF;
1139 index_stripped += 1;
1140 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1141 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1143 index_stripped = postq_index;
1144 index_stripped += 1;
1145 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1146 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1148 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1149 ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1155 ************************************************************************
1156 ************************************************************************
1158 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1160 struct QBUFFER *qbuffer=NULL;
1162 switch (acb->adapter_type) {
1163 case ACB_ADAPTER_TYPE_A: {
1164 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1166 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1169 case ACB_ADAPTER_TYPE_B: {
1170 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1172 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1175 case ACB_ADAPTER_TYPE_C: {
1176 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1178 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1181 case ACB_ADAPTER_TYPE_D: {
1182 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1184 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1191 ************************************************************************
1192 ************************************************************************
1194 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1196 struct QBUFFER *qbuffer = NULL;
1198 switch (acb->adapter_type) {
1199 case ACB_ADAPTER_TYPE_A: {
1200 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1202 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1205 case ACB_ADAPTER_TYPE_B: {
1206 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1208 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1211 case ACB_ADAPTER_TYPE_C: {
1212 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1214 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1217 case ACB_ADAPTER_TYPE_D: {
1218 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1220 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1227 **************************************************************************
1228 **************************************************************************
1230 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1232 switch (acb->adapter_type) {
1233 case ACB_ADAPTER_TYPE_A: {
1234 /* let IOP know data has been read */
1235 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1238 case ACB_ADAPTER_TYPE_B: {
1239 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1240 /* let IOP know data has been read */
1241 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1244 case ACB_ADAPTER_TYPE_C: {
1245 /* let IOP know data has been read */
1246 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1249 case ACB_ADAPTER_TYPE_D: {
1250 /* let IOP know data has been read */
1251 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1257 **************************************************************************
1258 **************************************************************************
1260 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1262 switch (acb->adapter_type) {
1263 case ACB_ADAPTER_TYPE_A: {
1265 ** push inbound doorbell tell iop, driver data write ok
1266 ** and wait reply on next hwinterrupt for next Qbuffer post
1268 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1271 case ACB_ADAPTER_TYPE_B: {
1272 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1274 ** push inbound doorbell tell iop, driver data write ok
1275 ** and wait reply on next hwinterrupt for next Qbuffer post
1277 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1280 case ACB_ADAPTER_TYPE_C: {
1282 ** push inbound doorbell tell iop, driver data write ok
1283 ** and wait reply on next hwinterrupt for next Qbuffer post
1285 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1288 case ACB_ADAPTER_TYPE_D: {
1290 ** push inbound doorbell tell iop, driver data write ok
1291 ** and wait reply on next hwinterrupt for next Qbuffer post
1293 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1299 ************************************************************************
1300 ************************************************************************
1302 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1304 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1305 CHIP_REG_WRITE32(HBA_MessageUnit,
1306 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1307 if(!arcmsr_hba_wait_msgint_ready(acb)) {
1308 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1313 ************************************************************************
1314 ************************************************************************
1316 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1318 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1319 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1320 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1321 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1322 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1327 ************************************************************************
1328 ************************************************************************
1330 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1332 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1333 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1334 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1335 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1336 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1340 ************************************************************************
1341 ************************************************************************
1343 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1345 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1347 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1348 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1352 ************************************************************************
1353 ************************************************************************
1355 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1357 switch (acb->adapter_type) {
1358 case ACB_ADAPTER_TYPE_A: {
1359 arcmsr_stop_hba_bgrb(acb);
1362 case ACB_ADAPTER_TYPE_B: {
1363 arcmsr_stop_hbb_bgrb(acb);
1366 case ACB_ADAPTER_TYPE_C: {
1367 arcmsr_stop_hbc_bgrb(acb);
1370 case ACB_ADAPTER_TYPE_D: {
1371 arcmsr_stop_hbd_bgrb(acb);
1377 ************************************************************************
1378 ************************************************************************
1380 static void arcmsr_poll(struct cam_sim *psim)
1382 struct AdapterControlBlock *acb;
1385 acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1386 mutex = mtx_owned(&acb->isr_lock);
1388 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1389 arcmsr_interrupt(acb);
1391 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1394 **************************************************************************
1395 **************************************************************************
1397 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1398 struct QBUFFER *prbuffer) {
1401 u_int8_t *buf1 = NULL;
1402 u_int32_t *iop_data, *buf2 = NULL;
1403 u_int32_t iop_len, data_len;
1405 iop_data = (u_int32_t *)prbuffer->data;
1406 iop_len = (u_int32_t)prbuffer->data_len;
1409 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1410 buf2 = (u_int32_t *)buf1;
1414 while(data_len >= 4)
1416 *buf2++ = *iop_data++;
1421 buf2 = (u_int32_t *)buf1;
1423 while (iop_len > 0) {
1424 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1426 acb->rqbuf_lastindex++;
1427 /* if last, index number set it to 0 */
1428 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1433 free( (u_int8_t *)buf2, M_DEVBUF);
1434 /* let IOP know data has been read */
1435 arcmsr_iop_message_read(acb);
1439 **************************************************************************
1440 **************************************************************************
1442 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1443 struct QBUFFER *prbuffer) {
1449 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1450 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1452 iop_data = (u_int8_t *)prbuffer->data;
1453 iop_len = (u_int32_t)prbuffer->data_len;
1454 while (iop_len > 0) {
1455 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1456 *pQbuffer = *iop_data;
1457 acb->rqbuf_lastindex++;
1458 /* if last, index number set it to 0 */
1459 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1463 /* let IOP know data has been read */
1464 arcmsr_iop_message_read(acb);
1468 **************************************************************************
1469 **************************************************************************
1471 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1473 struct QBUFFER *prbuffer;
1476 /*check this iop data if overflow my rqbuffer*/
1477 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1478 prbuffer = arcmsr_get_iop_rqbuffer(acb);
1479 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1480 (ARCMSR_MAX_QBUFFER-1);
1481 if(my_empty_len >= prbuffer->data_len) {
1482 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1483 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1485 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1487 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1490 **********************************************************************
1491 **********************************************************************
1493 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1496 struct QBUFFER *pwbuffer;
1497 u_int8_t *buf1 = NULL;
1498 u_int32_t *iop_data, *buf2 = NULL;
1499 u_int32_t allxfer_len = 0, data_len;
1501 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1502 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1503 buf2 = (u_int32_t *)buf1;
1507 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1508 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1509 iop_data = (u_int32_t *)pwbuffer->data;
1510 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1511 && (allxfer_len < 124)) {
1512 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1514 acb->wqbuf_firstindex++;
1515 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1519 pwbuffer->data_len = allxfer_len;
1520 data_len = allxfer_len;
1521 buf1 = (u_int8_t *)buf2;
1522 while(data_len >= 4)
1524 *iop_data++ = *buf2++;
1529 free( buf1, M_DEVBUF);
1530 arcmsr_iop_message_wrote(acb);
1534 **********************************************************************
1535 **********************************************************************
1537 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1540 struct QBUFFER *pwbuffer;
1542 int32_t allxfer_len=0;
1544 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
1545 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1548 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1549 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1550 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1551 iop_data = (u_int8_t *)pwbuffer->data;
1552 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1553 && (allxfer_len < 124)) {
1554 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1555 *iop_data = *pQbuffer;
1556 acb->wqbuf_firstindex++;
1557 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1561 pwbuffer->data_len = allxfer_len;
1562 arcmsr_iop_message_wrote(acb);
1566 **************************************************************************
1567 **************************************************************************
1569 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1571 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1572 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1574 *****************************************************************
1575 ** check if there are any mail packages from user space program
1576 ** in my post bag, now is the time to send them into Areca's firmware
1577 *****************************************************************
1579 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1580 arcmsr_Write_data_2iop_wqbuffer(acb);
1582 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1583 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1585 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1588 **************************************************************************
1589 **************************************************************************
1591 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1594 if (ccb->ccb_h.status != CAM_REQ_CMP)
1595 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1596 "failure status=%x\n", ccb->ccb_h.target_id,
1597 ccb->ccb_h.target_lun, ccb->ccb_h.status);
1599 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1601 xpt_free_path(ccb->ccb_h.path);
1605 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1607 struct cam_path *path;
1610 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1612 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1617 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1618 bzero(ccb, sizeof(union ccb));
1619 xpt_setup_ccb(&ccb->ccb_h, path, 5);
1620 ccb->ccb_h.func_code = XPT_SCAN_LUN;
1621 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1622 ccb->crcn.flags = CAM_FLAG_NONE;
1627 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1629 struct CommandControlBlock *srb;
1630 u_int32_t intmask_org;
1633 /* disable all outbound interrupts */
1634 intmask_org = arcmsr_disable_allintr(acb);
1635 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1637 srb = acb->psrb_pool[i];
1638 if (srb->srb_state == ARCMSR_SRB_START)
1640 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1642 srb->srb_state = ARCMSR_SRB_ABORTED;
1643 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1644 arcmsr_srb_complete(srb, 1);
1645 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1649 /* enable outbound Post Queue, outbound doorbell Interrupt */
1650 arcmsr_enable_allintr(acb, intmask_org);
1653 **************************************************************************
1654 **************************************************************************
1656 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1657 u_int32_t devicemap;
1658 u_int32_t target, lun;
1659 u_int32_t deviceMapCurrent[4]={0};
1662 switch (acb->adapter_type) {
1663 case ACB_ADAPTER_TYPE_A:
1664 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1665 for (target = 0; target < 4; target++)
1667 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1672 case ACB_ADAPTER_TYPE_B:
1673 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1674 for (target = 0; target < 4; target++)
1676 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap);
1681 case ACB_ADAPTER_TYPE_C:
1682 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1683 for (target = 0; target < 4; target++)
1685 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1689 case ACB_ADAPTER_TYPE_D:
1690 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1691 for (target = 0; target < 4; target++)
1693 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
1699 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1701 acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1704 ** adapter posted CONFIG message
1705 ** copy the new map, note if there are differences with the current map
1707 pDevMap = (u_int8_t *)&deviceMapCurrent[0];
1708 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1710 if (*pDevMap != acb->device_map[target])
1712 u_int8_t difference, bit_check;
1714 difference = *pDevMap ^ acb->device_map[target];
1715 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1717 bit_check = (1 << lun); /*check bit from 0....31*/
1718 if(difference & bit_check)
1720 if(acb->device_map[target] & bit_check)
1721 {/* unit departed */
1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1723 arcmsr_abort_dr_ccbs(acb, target, lun);
1724 arcmsr_rescan_lun(acb, target, lun);
1725 acb->devstate[target][lun] = ARECA_RAID_GONE;
1729 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1730 arcmsr_rescan_lun(acb, target, lun);
1731 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1735 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1736 acb->device_map[target] = *pDevMap;
1742 **************************************************************************
1743 **************************************************************************
1745 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1746 u_int32_t outbound_message;
1748 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1749 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1750 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1751 arcmsr_dr_handle( acb );
1754 **************************************************************************
1755 **************************************************************************
1757 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1758 u_int32_t outbound_message;
1759 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1761 /* clear interrupts */
1762 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1763 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1764 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1765 arcmsr_dr_handle( acb );
1768 **************************************************************************
1769 **************************************************************************
1771 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1772 u_int32_t outbound_message;
1774 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1775 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1776 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1777 arcmsr_dr_handle( acb );
1780 **************************************************************************
1781 **************************************************************************
1783 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1784 u_int32_t outbound_message;
1786 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1787 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1788 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1789 arcmsr_dr_handle( acb );
1792 **************************************************************************
1793 **************************************************************************
1795 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1797 u_int32_t doorbell_status;
1800 *******************************************************************
1801 ** Maybe here we need to check wrqbuffer_lock is lock or not
1802 ** DOORBELL: din! don!
1803 ** check if there are any mail need to pack from firmware
1804 *******************************************************************
1806 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
1807 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1808 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1809 arcmsr_iop2drv_data_wrote_handle(acb);
1811 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1812 arcmsr_iop2drv_data_read_handle(acb);
1816 **************************************************************************
1817 **************************************************************************
1819 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1821 u_int32_t doorbell_status;
1824 *******************************************************************
1825 ** Maybe here we need to check wrqbuffer_lock is lock or not
1826 ** DOORBELL: din! don!
1827 ** check if there are any mail need to pack from firmware
1828 *******************************************************************
1830 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1831 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
1832 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1833 arcmsr_iop2drv_data_wrote_handle(acb);
1835 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1836 arcmsr_iop2drv_data_read_handle(acb);
1838 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1839 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */
1843 **************************************************************************
1844 **************************************************************************
1846 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1848 u_int32_t doorbell_status;
1851 *******************************************************************
1852 ** Maybe here we need to check wrqbuffer_lock is lock or not
1853 ** DOORBELL: din! don!
1854 ** check if there are any mail need to pack from firmware
1855 *******************************************************************
1857 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1859 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1860 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1861 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1862 arcmsr_iop2drv_data_wrote_handle(acb);
1864 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1865 arcmsr_iop2drv_data_read_handle(acb);
1867 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1868 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */
1870 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1872 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
1876 **************************************************************************
1877 **************************************************************************
1879 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1885 *****************************************************************************
1886 ** areca cdb command done
1887 *****************************************************************************
1889 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1890 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1891 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1892 0, outbound_queueport)) != 0xFFFFFFFF) {
1893 /* check if command done with no error*/
1894 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1895 arcmsr_drain_donequeue(acb, flag_srb, error);
1896 } /*drain reply FIFO*/
1899 **************************************************************************
1900 **************************************************************************
1902 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1904 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1910 *****************************************************************************
1911 ** areca cdb command done
1912 *****************************************************************************
1914 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1915 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1916 index = phbbmu->doneq_index;
1917 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1918 phbbmu->done_qbuffer[index] = 0;
1920 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
1921 phbbmu->doneq_index = index;
1922 /* check if command done with no error*/
1923 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1924 arcmsr_drain_donequeue(acb, flag_srb, error);
1925 } /*drain reply FIFO*/
1928 **************************************************************************
1929 **************************************************************************
1931 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1933 u_int32_t flag_srb,throttling = 0;
1937 *****************************************************************************
1938 ** areca cdb command done
1939 *****************************************************************************
1941 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1943 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1944 if (flag_srb == 0xFFFFFFFF)
1946 /* check if command done with no error*/
1947 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1948 arcmsr_drain_donequeue(acb, flag_srb, error);
1950 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1951 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1954 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
1957 **********************************************************************
1959 **********************************************************************
1961 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1963 uint16_t doneq_index, index_stripped;
1965 doneq_index = phbdmu->doneq_index;
1966 if (doneq_index & 0x4000) {
1967 index_stripped = doneq_index & 0xFF;
1968 index_stripped += 1;
1969 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1970 phbdmu->doneq_index = index_stripped ?
1971 (index_stripped | 0x4000) : index_stripped;
1973 index_stripped = doneq_index;
1974 index_stripped += 1;
1975 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1976 phbdmu->doneq_index = index_stripped ?
1977 index_stripped : (index_stripped | 0x4000);
1979 return (phbdmu->doneq_index);
1982 **************************************************************************
1983 **************************************************************************
1985 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1987 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1988 u_int32_t outbound_write_pointer;
1989 u_int32_t addressLow;
1990 uint16_t doneq_index;
1993 *****************************************************************************
1994 ** areca cdb command done
1995 *****************************************************************************
1997 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1998 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
2000 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
2001 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2002 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2003 doneq_index = phbdmu->doneq_index;
2004 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
2005 doneq_index = arcmsr_get_doneq_index(phbdmu);
2006 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2007 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2008 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2009 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2010 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2012 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2013 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2016 **********************************************************************
2017 **********************************************************************
2019 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2021 u_int32_t outbound_intStatus;
2023 *********************************************
2024 ** check outbound intstatus
2025 *********************************************
2027 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2028 if(!outbound_intStatus) {
2029 /*it must be share irq*/
2032 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2033 /* MU doorbell interrupts*/
2034 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2035 arcmsr_hba_doorbell_isr(acb);
2037 /* MU post queue interrupts*/
2038 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2039 arcmsr_hba_postqueue_isr(acb);
2041 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2042 arcmsr_hba_message_isr(acb);
2046 **********************************************************************
2047 **********************************************************************
2049 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2051 u_int32_t outbound_doorbell;
2052 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2054 *********************************************
2055 ** check outbound intstatus
2056 *********************************************
2058 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable;
2059 if(!outbound_doorbell) {
2060 /*it must be share irq*/
2063 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2064 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell);
2065 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2066 /* MU ioctl transfer doorbell interrupts*/
2067 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2068 arcmsr_iop2drv_data_wrote_handle(acb);
2070 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2071 arcmsr_iop2drv_data_read_handle(acb);
2073 /* MU post queue interrupts*/
2074 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2075 arcmsr_hbb_postqueue_isr(acb);
2077 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2078 arcmsr_hbb_message_isr(acb);
2082 **********************************************************************
2083 **********************************************************************
2085 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2087 u_int32_t host_interrupt_status;
2089 *********************************************
2090 ** check outbound intstatus
2091 *********************************************
2093 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
2094 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2095 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2096 if(!host_interrupt_status) {
2097 /*it must be share irq*/
2101 /* MU doorbell interrupts*/
2102 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2103 arcmsr_hbc_doorbell_isr(acb);
2105 /* MU post queue interrupts*/
2106 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2107 arcmsr_hbc_postqueue_isr(acb);
2109 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2110 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2113 **********************************************************************
2114 **********************************************************************
2116 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2118 u_int32_t host_interrupt_status;
2119 u_int32_t intmask_org;
2121 *********************************************
2122 ** check outbound intstatus
2123 *********************************************
2125 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2126 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2127 /*it must be share irq*/
2130 /* disable outbound interrupt */
2131 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
2132 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2133 /* MU doorbell interrupts*/
2134 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2135 arcmsr_hbd_doorbell_isr(acb);
2137 /* MU post queue interrupts*/
2138 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2139 arcmsr_hbd_postqueue_isr(acb);
2141 /* enable all outbound interrupt */
2142 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2143 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2146 ******************************************************************************
2147 ******************************************************************************
2149 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2151 switch (acb->adapter_type) {
2152 case ACB_ADAPTER_TYPE_A:
2153 arcmsr_handle_hba_isr(acb);
2155 case ACB_ADAPTER_TYPE_B:
2156 arcmsr_handle_hbb_isr(acb);
2158 case ACB_ADAPTER_TYPE_C:
2159 arcmsr_handle_hbc_isr(acb);
2161 case ACB_ADAPTER_TYPE_D:
2162 arcmsr_handle_hbd_isr(acb);
2165 printf("arcmsr%d: interrupt service,"
2166 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2171 **********************************************************************
2172 **********************************************************************
2174 static void arcmsr_intr_handler(void *arg)
2176 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2178 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2179 arcmsr_interrupt(acb);
2180 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2183 ******************************************************************************
2184 ******************************************************************************
2186 static void arcmsr_polling_devmap(void *arg)
2188 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2189 switch (acb->adapter_type) {
2190 case ACB_ADAPTER_TYPE_A:
2191 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2194 case ACB_ADAPTER_TYPE_B: {
2195 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
2196 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2200 case ACB_ADAPTER_TYPE_C:
2201 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2202 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2205 case ACB_ADAPTER_TYPE_D:
2206 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2210 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2212 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
2217 *******************************************************************************
2219 *******************************************************************************
2221 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2223 u_int32_t intmask_org;
2226 /* stop adapter background rebuild */
2227 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2228 intmask_org = arcmsr_disable_allintr(acb);
2229 arcmsr_stop_adapter_bgrb(acb);
2230 arcmsr_flush_adapter_cache(acb);
2231 arcmsr_enable_allintr(acb, intmask_org);
2236 ***********************************************************************
2238 ************************************************************************
2240 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2242 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2243 u_int32_t retvalue = EINVAL;
2245 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2246 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2249 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2251 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2253 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2254 u_int32_t allxfer_len=0;
2256 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2257 && (allxfer_len < 1031)) {
2258 /*copy READ QBUFFER to srb*/
2259 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2260 *ptmpQbuffer = *pQbuffer;
2261 acb->rqbuf_firstindex++;
2262 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2263 /*if last index number set it to 0 */
2267 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2268 struct QBUFFER *prbuffer;
2270 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2271 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2272 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2273 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2275 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2276 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2277 retvalue = ARCMSR_MESSAGE_SUCCESS;
2280 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2281 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2283 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2285 user_len = pcmdmessagefld->cmdmessage.Length;
2286 /*check if data xfer length of this request will overflow my array qbuffer */
2287 wqbuf_lastindex = acb->wqbuf_lastindex;
2288 wqbuf_firstindex = acb->wqbuf_firstindex;
2289 if(wqbuf_lastindex != wqbuf_firstindex) {
2290 arcmsr_Write_data_2iop_wqbuffer(acb);
2291 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2293 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2294 (ARCMSR_MAX_QBUFFER - 1);
2295 if(my_empty_len >= user_len) {
2296 while(user_len > 0) {
2297 /*copy srb data to wqbuffer*/
2298 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2299 *pQbuffer = *ptmpuserbuffer;
2300 acb->wqbuf_lastindex++;
2301 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2302 /*if last index number set it to 0 */
2306 /*post fist Qbuffer*/
2307 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2308 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2309 arcmsr_Write_data_2iop_wqbuffer(acb);
2311 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2313 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2316 retvalue = ARCMSR_MESSAGE_SUCCESS;
2319 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2320 u_int8_t *pQbuffer = acb->rqbuffer;
2322 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2323 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2324 arcmsr_iop_message_read(acb);
2325 /*signature, let IOP know data has been readed */
2327 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2328 acb->rqbuf_firstindex = 0;
2329 acb->rqbuf_lastindex = 0;
2330 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2331 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2332 retvalue = ARCMSR_MESSAGE_SUCCESS;
2335 case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2337 u_int8_t *pQbuffer = acb->wqbuffer;
2339 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2340 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2341 arcmsr_iop_message_read(acb);
2342 /*signature, let IOP know data has been readed */
2344 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2345 acb->wqbuf_firstindex = 0;
2346 acb->wqbuf_lastindex = 0;
2347 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2348 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2349 retvalue = ARCMSR_MESSAGE_SUCCESS;
2352 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2355 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2356 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2357 arcmsr_iop_message_read(acb);
2358 /*signature, let IOP know data has been readed */
2360 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2361 |ACB_F_MESSAGE_RQBUFFER_CLEARED
2362 |ACB_F_MESSAGE_WQBUFFER_READ);
2363 acb->rqbuf_firstindex = 0;
2364 acb->rqbuf_lastindex = 0;
2365 acb->wqbuf_firstindex = 0;
2366 acb->wqbuf_lastindex = 0;
2367 pQbuffer = acb->rqbuffer;
2368 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2369 pQbuffer = acb->wqbuffer;
2370 memset(pQbuffer, 0, sizeof(struct QBUFFER));
2371 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2372 retvalue = ARCMSR_MESSAGE_SUCCESS;
2375 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2376 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2377 retvalue = ARCMSR_MESSAGE_SUCCESS;
2380 case ARCMSR_MESSAGE_SAY_HELLO: {
2381 u_int8_t *hello_string = "Hello! I am ARCMSR";
2382 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2384 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2385 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2386 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2389 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2390 retvalue = ARCMSR_MESSAGE_SUCCESS;
2393 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2394 arcmsr_iop_parking(acb);
2395 retvalue = ARCMSR_MESSAGE_SUCCESS;
2398 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2399 arcmsr_flush_adapter_cache(acb);
2400 retvalue = ARCMSR_MESSAGE_SUCCESS;
2404 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2408 **************************************************************************
2409 **************************************************************************
2411 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2413 struct AdapterControlBlock *acb;
2416 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2417 srb->srb_state = ARCMSR_SRB_DONE;
2419 acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2420 acb->workingsrb_doneindex++;
2421 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2422 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2425 **************************************************************************
2426 **************************************************************************
2428 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2430 struct CommandControlBlock *srb = NULL;
2431 u_int32_t workingsrb_startindex, workingsrb_doneindex;
2433 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2434 workingsrb_doneindex = acb->workingsrb_doneindex;
2435 workingsrb_startindex = acb->workingsrb_startindex;
2436 srb = acb->srbworkingQ[workingsrb_startindex];
2437 workingsrb_startindex++;
2438 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2439 if(workingsrb_doneindex != workingsrb_startindex) {
2440 acb->workingsrb_startindex = workingsrb_startindex;
2444 ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2448 **************************************************************************
2449 **************************************************************************
2451 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2453 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2454 int retvalue = 0, transfer_len = 0;
2456 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio);
2457 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 |
2458 (u_int32_t ) ptr[6] << 16 |
2459 (u_int32_t ) ptr[7] << 8 |
2460 (u_int32_t ) ptr[8];
2461 /* 4 bytes: Areca io control code */
2462 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2463 buffer = pccb->csio.data_ptr;
2464 transfer_len = pccb->csio.dxfer_len;
2466 retvalue = ARCMSR_MESSAGE_FAIL;
2469 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2470 retvalue = ARCMSR_MESSAGE_FAIL;
2473 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2474 switch(controlcode) {
2475 case ARCMSR_MESSAGE_READ_RQBUFFER: {
2477 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2478 int32_t allxfer_len = 0;
2480 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2481 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2482 && (allxfer_len < 1031)) {
2483 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2484 *ptmpQbuffer = *pQbuffer;
2485 acb->rqbuf_firstindex++;
2486 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2490 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2491 struct QBUFFER *prbuffer;
2493 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2494 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2495 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2496 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2498 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2499 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2500 retvalue = ARCMSR_MESSAGE_SUCCESS;
2501 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2504 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2505 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2507 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2509 user_len = pcmdmessagefld->cmdmessage.Length;
2510 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2511 wqbuf_lastindex = acb->wqbuf_lastindex;
2512 wqbuf_firstindex = acb->wqbuf_firstindex;
2513 if (wqbuf_lastindex != wqbuf_firstindex) {
2514 arcmsr_Write_data_2iop_wqbuffer(acb);
2515 /* has error report sensedata */
2516 if(pccb->csio.sense_len) {
2517 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2518 /* Valid,ErrorCode */
2519 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2520 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2521 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2522 /* AdditionalSenseLength */
2523 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2524 /* AdditionalSenseCode */
2526 retvalue = ARCMSR_MESSAGE_FAIL;
2528 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2529 &(ARCMSR_MAX_QBUFFER - 1);
2530 if (my_empty_len >= user_len) {
2531 while (user_len > 0) {
2532 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2533 *pQbuffer = *ptmpuserbuffer;
2534 acb->wqbuf_lastindex++;
2535 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2539 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2541 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2542 arcmsr_Write_data_2iop_wqbuffer(acb);
2545 /* has error report sensedata */
2546 if(pccb->csio.sense_len) {
2547 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2548 /* Valid,ErrorCode */
2549 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2550 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2551 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2552 /* AdditionalSenseLength */
2553 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2554 /* AdditionalSenseCode */
2556 retvalue = ARCMSR_MESSAGE_FAIL;
2559 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2562 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2563 u_int8_t *pQbuffer = acb->rqbuffer;
2565 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2566 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2567 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2568 arcmsr_iop_message_read(acb);
2570 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2571 acb->rqbuf_firstindex = 0;
2572 acb->rqbuf_lastindex = 0;
2573 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2574 pcmdmessagefld->cmdmessage.ReturnCode =
2575 ARCMSR_MESSAGE_RETURNCODE_OK;
2576 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2579 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2580 u_int8_t *pQbuffer = acb->wqbuffer;
2582 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2583 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2584 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2585 arcmsr_iop_message_read(acb);
2588 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2589 ACB_F_MESSAGE_WQBUFFER_READ);
2590 acb->wqbuf_firstindex = 0;
2591 acb->wqbuf_lastindex = 0;
2592 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2593 pcmdmessagefld->cmdmessage.ReturnCode =
2594 ARCMSR_MESSAGE_RETURNCODE_OK;
2595 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2598 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2601 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2602 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2603 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2604 arcmsr_iop_message_read(acb);
2607 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2608 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2609 | ACB_F_MESSAGE_WQBUFFER_READ);
2610 acb->rqbuf_firstindex = 0;
2611 acb->rqbuf_lastindex = 0;
2612 acb->wqbuf_firstindex = 0;
2613 acb->wqbuf_lastindex = 0;
2614 pQbuffer = acb->rqbuffer;
2615 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2616 pQbuffer = acb->wqbuffer;
2617 memset(pQbuffer, 0, sizeof (struct QBUFFER));
2618 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2619 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2622 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2623 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2626 case ARCMSR_MESSAGE_SAY_HELLO: {
2627 int8_t *hello_string = "Hello! I am ARCMSR";
2629 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2630 , (int16_t)strlen(hello_string));
2631 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2634 case ARCMSR_MESSAGE_SAY_GOODBYE:
2635 arcmsr_iop_parking(acb);
2637 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2638 arcmsr_flush_adapter_cache(acb);
2641 retvalue = ARCMSR_MESSAGE_FAIL;
2647 *********************************************************************
2648 *********************************************************************
2650 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2652 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2653 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2658 target = pccb->ccb_h.target_id;
2659 lun = pccb->ccb_h.target_lun;
2660 acb->pktRequestCount++;
2662 if(error != EFBIG) {
2663 printf("arcmsr%d: unexpected error %x"
2664 " returned from 'bus_dmamap_load' \n"
2665 , acb->pci_unit, error);
2667 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2668 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2670 arcmsr_srb_complete(srb, 0);
2673 if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2674 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2675 arcmsr_srb_complete(srb, 0);
2678 if(acb->acb_flags & ACB_F_BUS_RESET) {
2679 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2680 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2681 arcmsr_srb_complete(srb, 0);
2684 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2685 u_int8_t block_cmd, cmd;
2687 cmd = scsiio_cdb_ptr(&pccb->csio)[0];
2688 block_cmd = cmd & 0x0f;
2689 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2690 printf("arcmsr%d:block 'read/write' command "
2691 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2692 , acb->pci_unit, cmd, target, lun);
2693 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2694 arcmsr_srb_complete(srb, 0);
2698 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2700 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2702 arcmsr_srb_complete(srb, 0);
2705 if(acb->srboutstandingcount >= acb->maxOutstanding) {
2706 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2708 xpt_freeze_simq(acb->psim, 1);
2709 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2711 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2712 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2713 arcmsr_srb_complete(srb, 0);
2716 pccb->ccb_h.status |= CAM_SIM_QUEUED;
2717 arcmsr_build_srb(srb, dm_segs, nseg);
2718 arcmsr_post_srb(acb, srb);
2719 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2721 arcmsr_callout_init(&srb->ccb_callout);
2722 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2723 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2724 arcmsr_srb_timeout, srb, 0);
2725 srb->srb_flags |= SRB_FLAG_TIMER_START;
2729 *****************************************************************************************
2730 *****************************************************************************************
2732 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2734 struct CommandControlBlock *srb;
2735 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2736 u_int32_t intmask_org;
2741 ***************************************************************************
2742 ** It is the upper layer do abort command this lock just prior to calling us.
2743 ** First determine if we currently own this command.
2744 ** Start by searching the device queue. If not found
2745 ** at all, and the system wanted us to just abort the
2746 ** command return success.
2747 ***************************************************************************
2749 if(acb->srboutstandingcount != 0) {
2750 /* disable all outbound interrupt */
2751 intmask_org = arcmsr_disable_allintr(acb);
2752 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2753 srb = acb->psrb_pool[i];
2754 if(srb->srb_state == ARCMSR_SRB_START) {
2755 if(srb->pccb == abortccb) {
2756 srb->srb_state = ARCMSR_SRB_ABORTED;
2757 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
2758 "outstanding command \n"
2759 , acb->pci_unit, abortccb->ccb_h.target_id
2760 , (uintmax_t)abortccb->ccb_h.target_lun, srb);
2761 arcmsr_polling_srbdone(acb, srb);
2762 /* enable outbound Post Queue, outbound doorbell Interrupt */
2763 arcmsr_enable_allintr(acb, intmask_org);
2768 /* enable outbound Post Queue, outbound doorbell Interrupt */
2769 arcmsr_enable_allintr(acb, intmask_org);
2774 ****************************************************************************
2775 ****************************************************************************
2777 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2782 acb->acb_flags |= ACB_F_BUS_RESET;
2783 while(acb->srboutstandingcount != 0 && retry < 400) {
2784 arcmsr_interrupt(acb);
2788 arcmsr_iop_reset(acb);
2789 acb->acb_flags &= ~ACB_F_BUS_RESET;
2792 **************************************************************************
2793 **************************************************************************
2795 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2798 if (pccb->ccb_h.target_lun) {
2799 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2803 pccb->ccb_h.status |= CAM_REQ_CMP;
2804 switch (scsiio_cdb_ptr(&pccb->csio)[0]) {
2806 unsigned char inqdata[36];
2807 char *buffer = pccb->csio.data_ptr;
2809 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */
2810 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */
2811 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */
2813 inqdata[4] = 31; /* length of additional data */
2817 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */
2818 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */
2819 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2820 memcpy(buffer, inqdata, sizeof(inqdata));
2826 if (arcmsr_iop_message_xfer(acb, pccb)) {
2827 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2828 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2838 *********************************************************************
2839 *********************************************************************
2841 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2843 struct AdapterControlBlock *acb;
2845 acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2847 pccb->ccb_h.status |= CAM_REQ_INVALID;
2851 switch (pccb->ccb_h.func_code) {
2853 struct CommandControlBlock *srb;
2854 int target = pccb->ccb_h.target_id;
2857 if (pccb->ccb_h.flags & CAM_CDB_PHYS) {
2858 pccb->ccb_h.status = CAM_REQ_INVALID;
2864 /* virtual device for iop message transfer */
2865 arcmsr_handle_virtual_command(acb, pccb);
2868 if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2869 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2873 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2874 pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2876 error = bus_dmamap_load_ccb(acb->dm_segs_dmat
2877 , srb->dm_segs_dmamap
2879 , arcmsr_execute_srb, srb, /*flags*/0);
2880 if(error == EINPROGRESS) {
2881 xpt_freeze_simq(acb->psim, 1);
2882 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2886 case XPT_PATH_INQ: {
2887 struct ccb_pathinq *cpi = &pccb->cpi;
2889 cpi->version_num = 1;
2890 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2891 cpi->target_sprt = 0;
2893 cpi->hba_eng_cnt = 0;
2894 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */
2895 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */
2896 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2897 cpi->bus_id = cam_sim_bus(psim);
2898 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2899 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2900 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2901 cpi->unit_number = cam_sim_unit(psim);
2902 #ifdef CAM_NEW_TRAN_CODE
2903 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
2904 cpi->base_transfer_speed = 1200000;
2905 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2906 cpi->base_transfer_speed = 600000;
2908 cpi->base_transfer_speed = 300000;
2909 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2910 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2911 (acb->vendor_device_id == PCIDevVenIDARC1214))
2913 cpi->transport = XPORT_SAS;
2914 cpi->transport_version = 0;
2915 cpi->protocol_version = SCSI_REV_SPC2;
2919 cpi->transport = XPORT_SPI;
2920 cpi->transport_version = 2;
2921 cpi->protocol_version = SCSI_REV_2;
2923 cpi->protocol = PROTO_SCSI;
2925 cpi->ccb_h.status |= CAM_REQ_CMP;
2930 union ccb *pabort_ccb;
2932 pabort_ccb = pccb->cab.abort_ccb;
2933 switch (pabort_ccb->ccb_h.func_code) {
2934 case XPT_ACCEPT_TARGET_IO:
2935 case XPT_CONT_TARGET_IO:
2936 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2937 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2938 xpt_done(pabort_ccb);
2939 pccb->ccb_h.status |= CAM_REQ_CMP;
2941 xpt_print_path(pabort_ccb->ccb_h.path);
2942 printf("Not found\n");
2943 pccb->ccb_h.status |= CAM_PATH_INVALID;
2947 pccb->ccb_h.status |= CAM_UA_ABORT;
2950 pccb->ccb_h.status |= CAM_REQ_INVALID;
2957 case XPT_RESET_DEV: {
2960 arcmsr_bus_reset(acb);
2961 for (i=0; i < 500; i++) {
2964 pccb->ccb_h.status |= CAM_REQ_CMP;
2969 pccb->ccb_h.status |= CAM_REQ_INVALID;
2973 case XPT_GET_TRAN_SETTINGS: {
2974 struct ccb_trans_settings *cts;
2976 if(pccb->ccb_h.target_id == 16) {
2977 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2982 #ifdef CAM_NEW_TRAN_CODE
2984 struct ccb_trans_settings_scsi *scsi;
2985 struct ccb_trans_settings_spi *spi;
2986 struct ccb_trans_settings_sas *sas;
2988 scsi = &cts->proto_specific.scsi;
2989 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2990 scsi->valid = CTS_SCSI_VALID_TQ;
2991 cts->protocol = PROTO_SCSI;
2993 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2994 (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2995 (acb->vendor_device_id == PCIDevVenIDARC1214))
2997 cts->protocol_version = SCSI_REV_SPC2;
2998 cts->transport_version = 0;
2999 cts->transport = XPORT_SAS;
3000 sas = &cts->xport_specific.sas;
3001 sas->valid = CTS_SAS_VALID_SPEED;
3002 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
3003 sas->bitrate = 1200000;
3004 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3005 sas->bitrate = 600000;
3006 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G)
3007 sas->bitrate = 300000;
3011 cts->protocol_version = SCSI_REV_2;
3012 cts->transport_version = 2;
3013 cts->transport = XPORT_SPI;
3014 spi = &cts->xport_specific.spi;
3015 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
3016 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3017 spi->sync_period = 1;
3019 spi->sync_period = 2;
3020 spi->sync_offset = 32;
3021 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3022 spi->valid = CTS_SPI_VALID_DISC
3023 | CTS_SPI_VALID_SYNC_RATE
3024 | CTS_SPI_VALID_SYNC_OFFSET
3025 | CTS_SPI_VALID_BUS_WIDTH;
3030 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3031 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
3032 cts->sync_period = 1;
3034 cts->sync_period = 2;
3035 cts->sync_offset = 32;
3036 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3037 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3038 CCB_TRANS_SYNC_OFFSET_VALID |
3039 CCB_TRANS_BUS_WIDTH_VALID |
3040 CCB_TRANS_DISC_VALID |
3044 pccb->ccb_h.status |= CAM_REQ_CMP;
3048 case XPT_SET_TRAN_SETTINGS: {
3049 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3053 case XPT_CALC_GEOMETRY:
3054 if(pccb->ccb_h.target_id == 16) {
3055 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3059 #if __FreeBSD_version >= 500000
3060 cam_calc_geometry(&pccb->ccg, 1);
3063 struct ccb_calc_geometry *ccg;
3065 u_int32_t secs_per_cylinder;
3068 if (ccg->block_size == 0) {
3069 pccb->ccb_h.status = CAM_REQ_INVALID;
3073 if(((1024L * 1024L)/ccg->block_size) < 0) {
3074 pccb->ccb_h.status = CAM_REQ_INVALID;
3078 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3079 if(size_mb > 1024 ) {
3081 ccg->secs_per_track = 63;
3084 ccg->secs_per_track = 32;
3086 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3087 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3088 pccb->ccb_h.status |= CAM_REQ_CMP;
3094 pccb->ccb_h.status |= CAM_REQ_INVALID;
3100 **********************************************************************
3101 **********************************************************************
3103 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3105 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3106 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3107 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3108 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3112 **********************************************************************
3113 **********************************************************************
3115 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3117 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3118 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3119 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB);
3120 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3121 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3125 **********************************************************************
3126 **********************************************************************
3128 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3130 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3131 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3132 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3133 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3134 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3138 **********************************************************************
3139 **********************************************************************
3141 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3143 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3144 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3145 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3146 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3150 **********************************************************************
3151 **********************************************************************
3153 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3155 switch (acb->adapter_type) {
3156 case ACB_ADAPTER_TYPE_A:
3157 arcmsr_start_hba_bgrb(acb);
3159 case ACB_ADAPTER_TYPE_B:
3160 arcmsr_start_hbb_bgrb(acb);
3162 case ACB_ADAPTER_TYPE_C:
3163 arcmsr_start_hbc_bgrb(acb);
3165 case ACB_ADAPTER_TYPE_D:
3166 arcmsr_start_hbd_bgrb(acb);
3171 **********************************************************************
3173 **********************************************************************
3175 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3177 struct CommandControlBlock *srb;
3178 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3183 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3184 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/
3185 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3187 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3188 0, outbound_queueport)) == 0xFFFFFFFF) {
3190 break;/*chip FIFO no ccb for completion already*/
3193 if ((poll_count > 100) && (poll_srb != NULL)) {
3196 goto polling_ccb_retry;
3199 /* check if command done with no error*/
3200 srb = (struct CommandControlBlock *)
3201 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3202 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3203 poll_srb_done = (srb == poll_srb) ? 1:0;
3204 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3205 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3206 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3207 "poll command abort successfully \n"
3209 , srb->pccb->ccb_h.target_id
3210 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3211 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3212 arcmsr_srb_complete(srb, 1);
3215 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3216 "srboutstandingcount=%d \n"
3218 , srb, acb->srboutstandingcount);
3221 arcmsr_report_srb_state(acb, srb, error);
3222 } /*drain reply FIFO*/
3225 **********************************************************************
3227 **********************************************************************
3229 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3231 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3232 struct CommandControlBlock *srb;
3233 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3239 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3240 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3242 index = phbbmu->doneq_index;
3243 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3245 break;/*chip FIFO no ccb for completion already*/
3248 if ((poll_count > 100) && (poll_srb != NULL)) {
3251 goto polling_ccb_retry;
3254 phbbmu->done_qbuffer[index] = 0;
3256 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
3257 phbbmu->doneq_index = index;
3258 /* check if command done with no error*/
3259 srb = (struct CommandControlBlock *)
3260 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3261 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3262 poll_srb_done = (srb == poll_srb) ? 1:0;
3263 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3264 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3265 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
3266 "poll command abort successfully \n"
3268 , srb->pccb->ccb_h.target_id
3269 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3270 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3271 arcmsr_srb_complete(srb, 1);
3274 printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3275 "srboutstandingcount=%d \n"
3277 , srb, acb->srboutstandingcount);
3280 arcmsr_report_srb_state(acb, srb, error);
3281 } /*drain reply FIFO*/
3284 **********************************************************************
3286 **********************************************************************
3288 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3290 struct CommandControlBlock *srb;
3291 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3296 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3298 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3300 break;/*chip FIFO no ccb for completion already*/
3303 if ((poll_count > 100) && (poll_srb != NULL)) {
3306 if (acb->srboutstandingcount == 0) {
3309 goto polling_ccb_retry;
3312 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3313 /* check if command done with no error*/
3314 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3315 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3316 if (poll_srb != NULL)
3317 poll_srb_done = (srb == poll_srb) ? 1:0;
3318 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3319 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3320 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3321 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3322 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3323 arcmsr_srb_complete(srb, 1);
3326 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3327 , acb->pci_unit, srb, acb->srboutstandingcount);
3330 arcmsr_report_srb_state(acb, srb, error);
3331 } /*drain reply FIFO*/
3334 **********************************************************************
3336 **********************************************************************
3338 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3340 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3341 struct CommandControlBlock *srb;
3342 u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3343 u_int32_t outbound_write_pointer;
3344 u_int16_t error, doneq_index;
3348 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3350 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3351 doneq_index = phbdmu->doneq_index;
3352 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3354 break;/*chip FIFO no ccb for completion already*/
3357 if ((poll_count > 100) && (poll_srb != NULL)) {
3360 if (acb->srboutstandingcount == 0) {
3363 goto polling_ccb_retry;
3366 doneq_index = arcmsr_get_doneq_index(phbdmu);
3367 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3368 /* check if command done with no error*/
3369 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3370 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3371 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3372 if (poll_srb != NULL)
3373 poll_srb_done = (srb == poll_srb) ? 1:0;
3374 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3375 if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3376 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
3377 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
3378 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3379 arcmsr_srb_complete(srb, 1);
3382 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3383 , acb->pci_unit, srb, acb->srboutstandingcount);
3386 arcmsr_report_srb_state(acb, srb, error);
3387 } /*drain reply FIFO*/
3390 **********************************************************************
3391 **********************************************************************
3393 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3395 switch (acb->adapter_type) {
3396 case ACB_ADAPTER_TYPE_A: {
3397 arcmsr_polling_hba_srbdone(acb, poll_srb);
3400 case ACB_ADAPTER_TYPE_B: {
3401 arcmsr_polling_hbb_srbdone(acb, poll_srb);
3404 case ACB_ADAPTER_TYPE_C: {
3405 arcmsr_polling_hbc_srbdone(acb, poll_srb);
3408 case ACB_ADAPTER_TYPE_D: {
3409 arcmsr_polling_hbd_srbdone(acb, poll_srb);
3415 **********************************************************************
3416 **********************************************************************
3418 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3420 char *acb_firm_model = acb->firm_model;
3421 char *acb_firm_version = acb->firm_version;
3422 char *acb_device_map = acb->device_map;
3423 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3424 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3425 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3428 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3429 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3430 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3434 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3435 /* 8 bytes firm_model, 15, 60-67*/
3441 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3442 /* 16 bytes firm_version, 17, 68-83*/
3448 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3452 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3453 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3454 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3455 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3456 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3457 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3458 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3459 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3461 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3464 **********************************************************************
3465 **********************************************************************
3467 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3469 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3470 char *acb_firm_model = acb->firm_model;
3471 char *acb_firm_version = acb->firm_version;
3472 char *acb_device_map = acb->device_map;
3473 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3474 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3475 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3478 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3479 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3480 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3484 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3485 /* 8 bytes firm_model, 15, 60-67*/
3491 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3492 /* 16 bytes firm_version, 17, 68-83*/
3498 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3502 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3503 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3504 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3505 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3506 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3507 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3508 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3509 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3511 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3514 **********************************************************************
3515 **********************************************************************
3517 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3519 char *acb_firm_model = acb->firm_model;
3520 char *acb_firm_version = acb->firm_version;
3521 char *acb_device_map = acb->device_map;
3522 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3523 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3524 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3527 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3528 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3529 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3530 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3534 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3535 /* 8 bytes firm_model, 15, 60-67*/
3541 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3542 /* 16 bytes firm_version, 17, 68-83*/
3548 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3552 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3553 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3554 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3555 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3556 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3557 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3558 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3559 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3561 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3564 **********************************************************************
3565 **********************************************************************
3567 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3569 char *acb_firm_model = acb->firm_model;
3570 char *acb_firm_version = acb->firm_version;
3571 char *acb_device_map = acb->device_map;
3572 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/
3573 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3574 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3577 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3578 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3579 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3580 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3581 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3585 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3586 /* 8 bytes firm_model, 15, 60-67*/
3592 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3593 /* 16 bytes firm_version, 17, 68-83*/
3599 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3603 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3604 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/
3605 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3606 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/
3607 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/
3608 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */
3609 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3610 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3612 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3615 **********************************************************************
3616 **********************************************************************
3618 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3620 switch (acb->adapter_type) {
3621 case ACB_ADAPTER_TYPE_A: {
3622 arcmsr_get_hba_config(acb);
3625 case ACB_ADAPTER_TYPE_B: {
3626 arcmsr_get_hbb_config(acb);
3629 case ACB_ADAPTER_TYPE_C: {
3630 arcmsr_get_hbc_config(acb);
3633 case ACB_ADAPTER_TYPE_D: {
3634 arcmsr_get_hbd_config(acb);
3640 **********************************************************************
3641 **********************************************************************
3643 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3647 switch (acb->adapter_type) {
3648 case ACB_ADAPTER_TYPE_A: {
3649 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3651 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3653 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3656 UDELAY(15000); /* wait 15 milli-seconds */
3660 case ACB_ADAPTER_TYPE_B: {
3661 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3662 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3664 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3666 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3669 UDELAY(15000); /* wait 15 milli-seconds */
3671 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3674 case ACB_ADAPTER_TYPE_C: {
3675 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3677 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3679 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3682 UDELAY(15000); /* wait 15 milli-seconds */
3686 case ACB_ADAPTER_TYPE_D: {
3687 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3689 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3691 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3694 UDELAY(15000); /* wait 15 milli-seconds */
3701 **********************************************************************
3702 **********************************************************************
3704 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3706 u_int32_t outbound_doorbell;
3708 switch (acb->adapter_type) {
3709 case ACB_ADAPTER_TYPE_A: {
3710 /* empty doorbell Qbuffer if door bell ringed */
3711 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3712 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
3713 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3717 case ACB_ADAPTER_TYPE_B: {
3718 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3719 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3720 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3721 /* let IOP know data has been read */
3724 case ACB_ADAPTER_TYPE_C: {
3725 /* empty doorbell Qbuffer if door bell ringed */
3726 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3727 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */
3728 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3729 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3730 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3733 case ACB_ADAPTER_TYPE_D: {
3734 /* empty doorbell Qbuffer if door bell ringed */
3735 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3736 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */
3737 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3744 ************************************************************************
3745 ************************************************************************
3747 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3749 unsigned long srb_phyaddr;
3750 u_int32_t srb_phyaddr_hi32;
3751 u_int32_t srb_phyaddr_lo32;
3754 ********************************************************************
3755 ** here we need to tell iop 331 our freesrb.HighPart
3756 ** if freesrb.HighPart is not zero
3757 ********************************************************************
3759 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3760 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3761 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3762 switch (acb->adapter_type) {
3763 case ACB_ADAPTER_TYPE_A: {
3764 if(srb_phyaddr_hi32 != 0) {
3765 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3766 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3767 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3768 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3769 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3776 ***********************************************************************
3777 ** if adapter type B, set window of "post command Q"
3778 ***********************************************************************
3780 case ACB_ADAPTER_TYPE_B: {
3781 u_int32_t post_queue_phyaddr;
3782 struct HBB_MessageUnit *phbbmu;
3784 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3785 phbbmu->postq_index = 0;
3786 phbbmu->doneq_index = 0;
3787 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3788 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3789 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3792 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3793 + offsetof(struct HBB_MessageUnit, post_qbuffer);
3794 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3795 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3796 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3797 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3798 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3799 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3800 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3801 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3804 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3805 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3806 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3811 case ACB_ADAPTER_TYPE_C: {
3812 if(srb_phyaddr_hi32 != 0) {
3813 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3814 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3815 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3816 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3817 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3818 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3824 case ACB_ADAPTER_TYPE_D: {
3825 u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3826 struct HBD_MessageUnit0 *phbdmu;
3828 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3829 phbdmu->postq_index = 0;
3830 phbdmu->doneq_index = 0x40FF;
3831 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3832 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
3833 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3834 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
3835 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3836 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3837 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3838 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3839 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3840 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3841 if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3842 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3851 ************************************************************************
3852 ************************************************************************
3854 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3856 switch (acb->adapter_type)
3858 case ACB_ADAPTER_TYPE_A:
3859 case ACB_ADAPTER_TYPE_C:
3860 case ACB_ADAPTER_TYPE_D:
3862 case ACB_ADAPTER_TYPE_B: {
3863 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3864 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3865 if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3866 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3874 **********************************************************************
3875 **********************************************************************
3877 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3879 u_int32_t intmask_org;
3881 /* disable all outbound interrupt */
3882 intmask_org = arcmsr_disable_allintr(acb);
3883 arcmsr_wait_firmware_ready(acb);
3884 arcmsr_iop_confirm(acb);
3885 arcmsr_get_firmware_spec(acb);
3886 /*start background rebuild*/
3887 arcmsr_start_adapter_bgrb(acb);
3888 /* empty doorbell Qbuffer if door bell ringed */
3889 arcmsr_clear_doorbell_queue_buffer(acb);
3890 arcmsr_enable_eoi_mode(acb);
3891 /* enable outbound Post Queue, outbound doorbell Interrupt */
3892 arcmsr_enable_allintr(acb, intmask_org);
3893 acb->acb_flags |= ACB_F_IOP_INITED;
3896 **********************************************************************
3897 **********************************************************************
3899 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3901 struct AdapterControlBlock *acb = arg;
3902 struct CommandControlBlock *srb_tmp;
3904 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3906 acb->srb_phyaddr.phyaddr = srb_phyaddr;
3907 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3908 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3909 if(bus_dmamap_create(acb->dm_segs_dmat,
3910 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3911 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3913 " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3916 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3918 srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3919 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3922 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3924 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3925 srb_phyaddr = srb_phyaddr + SRB_SIZE;
3926 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3928 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3931 ************************************************************************
3932 ************************************************************************
3934 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3936 /* remove the control device */
3937 if(acb->ioctl_dev != NULL) {
3938 destroy_dev(acb->ioctl_dev);
3940 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3941 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3942 bus_dma_tag_destroy(acb->srb_dmat);
3943 bus_dma_tag_destroy(acb->dm_segs_dmat);
3944 bus_dma_tag_destroy(acb->parent_dmat);
3947 ************************************************************************
3948 ************************************************************************
3950 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3952 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3953 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3954 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3955 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3958 ************************************************************************
3959 ************************************************************************
3961 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3963 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3964 ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3965 ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3966 ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3969 ************************************************************************
3970 ************************************************************************
3972 static u_int32_t arcmsr_initialize(device_t dev)
3974 struct AdapterControlBlock *acb = device_get_softc(dev);
3975 u_int16_t pci_command;
3976 int i, j,max_coherent_size;
3977 u_int32_t vendor_dev_id;
3979 vendor_dev_id = pci_get_devid(dev);
3980 acb->vendor_device_id = vendor_dev_id;
3981 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3982 switch (vendor_dev_id) {
3983 case PCIDevVenIDARC1880:
3984 case PCIDevVenIDARC1882:
3985 case PCIDevVenIDARC1213:
3986 case PCIDevVenIDARC1223: {
3987 acb->adapter_type = ACB_ADAPTER_TYPE_C;
3988 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
3989 acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
3991 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3992 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3995 case PCIDevVenIDARC1214: {
3996 acb->adapter_type = ACB_ADAPTER_TYPE_D;
3997 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3998 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
4001 case PCIDevVenIDARC1200:
4002 case PCIDevVenIDARC1201: {
4003 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4004 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4005 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4008 case PCIDevVenIDARC1203: {
4009 acb->adapter_type = ACB_ADAPTER_TYPE_B;
4010 acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
4011 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
4014 case PCIDevVenIDARC1110:
4015 case PCIDevVenIDARC1120:
4016 case PCIDevVenIDARC1130:
4017 case PCIDevVenIDARC1160:
4018 case PCIDevVenIDARC1170:
4019 case PCIDevVenIDARC1210:
4020 case PCIDevVenIDARC1220:
4021 case PCIDevVenIDARC1230:
4022 case PCIDevVenIDARC1231:
4023 case PCIDevVenIDARC1260:
4024 case PCIDevVenIDARC1261:
4025 case PCIDevVenIDARC1270:
4026 case PCIDevVenIDARC1280:
4027 case PCIDevVenIDARC1212:
4028 case PCIDevVenIDARC1222:
4029 case PCIDevVenIDARC1380:
4030 case PCIDevVenIDARC1381:
4031 case PCIDevVenIDARC1680:
4032 case PCIDevVenIDARC1681: {
4033 acb->adapter_type = ACB_ADAPTER_TYPE_A;
4034 acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
4035 max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
4040 " unknown RAID adapter type \n", device_get_unit(dev));
4044 #if __FreeBSD_version >= 700000
4045 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev),
4047 if(bus_dma_tag_create( /*PCI parent*/ NULL,
4051 /*lowaddr*/ BUS_SPACE_MAXADDR,
4052 /*highaddr*/ BUS_SPACE_MAXADDR,
4055 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
4056 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
4057 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4059 #if __FreeBSD_version >= 501102
4063 &acb->parent_dmat) != 0)
4065 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4069 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4070 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4074 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4076 /*lowaddr*/ BUS_SPACE_MAXADDR,
4078 /*highaddr*/ BUS_SPACE_MAXADDR,
4081 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4082 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES,
4083 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4085 #if __FreeBSD_version >= 501102
4086 /*lockfunc*/ busdma_lock_mutex,
4087 /*lockarg*/ &acb->isr_lock,
4089 &acb->dm_segs_dmat) != 0)
4091 bus_dma_tag_destroy(acb->parent_dmat);
4092 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4096 /* DMA tag for our srb structures.... Allocate the freesrb memory */
4097 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat,
4100 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
4101 /*highaddr*/ BUS_SPACE_MAXADDR,
4104 /*maxsize*/ max_coherent_size,
4106 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
4108 #if __FreeBSD_version >= 501102
4112 &acb->srb_dmat) != 0)
4114 bus_dma_tag_destroy(acb->dm_segs_dmat);
4115 bus_dma_tag_destroy(acb->parent_dmat);
4116 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4119 /* Allocation for our srbs */
4120 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4121 bus_dma_tag_destroy(acb->srb_dmat);
4122 bus_dma_tag_destroy(acb->dm_segs_dmat);
4123 bus_dma_tag_destroy(acb->parent_dmat);
4124 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4127 /* And permanently map them */
4128 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4129 bus_dma_tag_destroy(acb->srb_dmat);
4130 bus_dma_tag_destroy(acb->dm_segs_dmat);
4131 bus_dma_tag_destroy(acb->parent_dmat);
4132 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4135 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4136 pci_command |= PCIM_CMD_BUSMASTEREN;
4137 pci_command |= PCIM_CMD_PERRESPEN;
4138 pci_command |= PCIM_CMD_MWRICEN;
4139 /* Enable Busmaster */
4140 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4141 switch(acb->adapter_type) {
4142 case ACB_ADAPTER_TYPE_A: {
4143 u_int32_t rid0 = PCIR_BAR(0);
4144 vm_offset_t mem_base0;
4146 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4147 if(acb->sys_res_arcmsr[0] == NULL) {
4148 arcmsr_free_resource(acb);
4149 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4152 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4153 arcmsr_free_resource(acb);
4154 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4157 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4158 if(mem_base0 == 0) {
4159 arcmsr_free_resource(acb);
4160 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4163 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4164 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4165 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4168 case ACB_ADAPTER_TYPE_B: {
4169 struct HBB_MessageUnit *phbbmu;
4170 struct CommandControlBlock *freesrb;
4171 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4172 vm_offset_t mem_base[]={0,0};
4174 if (vendor_dev_id == PCIDevVenIDARC1203)
4175 size = sizeof(struct HBB_DOORBELL_1203);
4177 size = sizeof(struct HBB_DOORBELL);
4178 for(i=0; i < 2; i++) {
4180 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid[i],
4183 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i],
4186 if(acb->sys_res_arcmsr[i] == NULL) {
4187 arcmsr_free_resource(acb);
4188 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4191 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4192 arcmsr_free_resource(acb);
4193 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4196 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4197 if(mem_base[i] == 0) {
4198 arcmsr_free_resource(acb);
4199 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4202 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4203 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4205 freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4206 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4207 phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4208 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4209 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4210 if (vendor_dev_id == PCIDevVenIDARC1203) {
4211 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell);
4212 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask);
4213 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell);
4214 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask);
4216 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell);
4217 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask);
4218 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell);
4219 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask);
4223 case ACB_ADAPTER_TYPE_C: {
4224 u_int32_t rid0 = PCIR_BAR(1);
4225 vm_offset_t mem_base0;
4227 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4228 if(acb->sys_res_arcmsr[0] == NULL) {
4229 arcmsr_free_resource(acb);
4230 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4233 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4234 arcmsr_free_resource(acb);
4235 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4238 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4239 if(mem_base0 == 0) {
4240 arcmsr_free_resource(acb);
4241 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4244 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4245 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4246 acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4249 case ACB_ADAPTER_TYPE_D: {
4250 struct HBD_MessageUnit0 *phbdmu;
4251 u_int32_t rid0 = PCIR_BAR(0);
4252 vm_offset_t mem_base0;
4254 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
4255 if(acb->sys_res_arcmsr[0] == NULL) {
4256 arcmsr_free_resource(acb);
4257 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4260 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4261 arcmsr_free_resource(acb);
4262 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4265 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4266 if(mem_base0 == 0) {
4267 arcmsr_free_resource(acb);
4268 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4271 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4272 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4273 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4274 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4275 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4279 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4280 arcmsr_free_resource(acb);
4281 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4284 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4285 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4287 ********************************************************************
4288 ** init raid volume state
4289 ********************************************************************
4291 for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4292 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4293 acb->devstate[i][j] = ARECA_RAID_GONE;
4296 arcmsr_iop_init(acb);
4300 ************************************************************************
4301 ************************************************************************
4303 static int arcmsr_attach(device_t dev)
4305 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4306 u_int32_t unit=device_get_unit(dev);
4307 struct ccb_setasync csa;
4308 struct cam_devq *devq; /* Device Queue to use for this SIM */
4309 struct resource *irqres;
4313 printf("arcmsr%d: cannot allocate softc\n", unit);
4316 arcmsr_mutex_init(acb);
4318 acb->pci_unit = unit;
4319 if(arcmsr_initialize(dev)) {
4320 printf("arcmsr%d: initialize failure!\n", unit);
4321 arcmsr_mutex_destroy(acb);
4324 /* After setting up the adapter, map our interrupt */
4326 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE);
4327 if(irqres == NULL ||
4328 #if __FreeBSD_version >= 700025
4329 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4331 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4333 arcmsr_free_resource(acb);
4334 arcmsr_mutex_destroy(acb);
4335 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4338 acb->irqres = irqres;
4340 * Now let the CAM generic SCSI layer find the SCSI devices on
4341 * the bus * start queue to reset to the idle loop. *
4342 * Create device queue of SIM(s) * (MAX_START_JOB - 1) :
4343 * max_sim_transactions
4345 devq = cam_simq_alloc(acb->maxOutstanding);
4347 arcmsr_free_resource(acb);
4348 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4349 arcmsr_mutex_destroy(acb);
4350 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4353 #if __FreeBSD_version >= 700025
4354 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4356 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4358 if(acb->psim == NULL) {
4359 arcmsr_free_resource(acb);
4360 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4361 cam_simq_free(devq);
4362 arcmsr_mutex_destroy(acb);
4363 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4366 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4367 #if __FreeBSD_version >= 700044
4368 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4370 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4372 arcmsr_free_resource(acb);
4373 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4374 cam_sim_free(acb->psim, /*free_devq*/TRUE);
4375 arcmsr_mutex_destroy(acb);
4376 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4379 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4380 arcmsr_free_resource(acb);
4381 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4382 xpt_bus_deregister(cam_sim_path(acb->psim));
4383 cam_sim_free(acb->psim, /* free_simq */ TRUE);
4384 arcmsr_mutex_destroy(acb);
4385 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4389 ****************************************************
4391 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4392 csa.ccb_h.func_code = XPT_SASYNC_CB;
4393 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4394 csa.callback = arcmsr_async;
4395 csa.callback_arg = acb->psim;
4396 xpt_action((union ccb *)&csa);
4397 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4398 /* Create the control device. */
4399 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4401 #if __FreeBSD_version < 503000
4402 acb->ioctl_dev->si_drv1 = acb;
4404 #if __FreeBSD_version > 500005
4405 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4407 arcmsr_callout_init(&acb->devmap_callout);
4408 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4413 ************************************************************************
4414 ************************************************************************
4416 static int arcmsr_probe(device_t dev)
4419 u_int16_t sub_device_id;
4420 static char buf[256];
4421 char x_type[]={"unknown"};
4425 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4428 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4429 switch(id = pci_get_devid(dev)) {
4430 case PCIDevVenIDARC1110:
4431 case PCIDevVenIDARC1200:
4432 case PCIDevVenIDARC1201:
4433 case PCIDevVenIDARC1210:
4436 case PCIDevVenIDARC1120:
4437 case PCIDevVenIDARC1130:
4438 case PCIDevVenIDARC1160:
4439 case PCIDevVenIDARC1170:
4440 case PCIDevVenIDARC1220:
4441 case PCIDevVenIDARC1230:
4442 case PCIDevVenIDARC1231:
4443 case PCIDevVenIDARC1260:
4444 case PCIDevVenIDARC1261:
4445 case PCIDevVenIDARC1270:
4446 case PCIDevVenIDARC1280:
4449 case PCIDevVenIDARC1212:
4450 case PCIDevVenIDARC1222:
4451 case PCIDevVenIDARC1380:
4452 case PCIDevVenIDARC1381:
4453 case PCIDevVenIDARC1680:
4454 case PCIDevVenIDARC1681:
4457 case PCIDevVenIDARC1880:
4458 case PCIDevVenIDARC1882:
4459 case PCIDevVenIDARC1213:
4460 case PCIDevVenIDARC1223:
4461 if (sub_device_id == ARECA_SUB_DEV_ID_1883)
4466 case PCIDevVenIDARC1214:
4467 case PCIDevVenIDARC1203:
4477 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4478 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4479 device_set_desc_copy(dev, buf);
4480 return (BUS_PROBE_DEFAULT);
4483 ************************************************************************
4484 ************************************************************************
4486 static int arcmsr_shutdown(device_t dev)
4489 u_int32_t intmask_org;
4490 struct CommandControlBlock *srb;
4491 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4493 /* stop adapter background rebuild */
4494 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4495 /* disable all outbound interrupt */
4496 intmask_org = arcmsr_disable_allintr(acb);
4497 arcmsr_stop_adapter_bgrb(acb);
4498 arcmsr_flush_adapter_cache(acb);
4499 /* abort all outstanding command */
4500 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4501 acb->acb_flags &= ~ACB_F_IOP_INITED;
4502 if(acb->srboutstandingcount != 0) {
4503 /*clear and abort all outbound posted Q*/
4504 arcmsr_done4abort_postqueue(acb);
4505 /* talk to iop 331 outstanding command aborted*/
4506 arcmsr_abort_allcmd(acb);
4507 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4508 srb = acb->psrb_pool[i];
4509 if(srb->srb_state == ARCMSR_SRB_START) {
4510 srb->srb_state = ARCMSR_SRB_ABORTED;
4511 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4512 arcmsr_srb_complete(srb, 1);
4516 acb->srboutstandingcount = 0;
4517 acb->workingsrb_doneindex = 0;
4518 acb->workingsrb_startindex = 0;
4519 acb->pktRequestCount = 0;
4520 acb->pktReturnCount = 0;
4521 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4525 ************************************************************************
4526 ************************************************************************
4528 static int arcmsr_detach(device_t dev)
4530 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4533 callout_stop(&acb->devmap_callout);
4534 bus_teardown_intr(dev, acb->irqres, acb->ih);
4535 arcmsr_shutdown(dev);
4536 arcmsr_free_resource(acb);
4537 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4538 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4540 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4541 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4542 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4543 xpt_free_path(acb->ppath);
4544 xpt_bus_deregister(cam_sim_path(acb->psim));
4545 cam_sim_free(acb->psim, TRUE);
4546 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4547 arcmsr_mutex_destroy(acb);
4551 #ifdef ARCMSR_DEBUG1
4552 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4554 if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4556 printf("Command Request Count =0x%x\n",acb->pktRequestCount);
4557 printf("Command Return Count =0x%x\n",acb->pktReturnCount);
4558 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4559 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount);