2 ********************************************************************************
4 ** FILE NAME : arcmsr.h
5 ** BY : Erich Chen, Ching Huang
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 ** SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 ** SPDX-License-Identifier: BSD-3-Clause
13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
15 ** Redistribution and use in source and binary forms,with or without
16 ** modification,are permitted provided that the following conditions
18 ** 1. Redistributions of source code must retain the above copyright
19 ** notice,this list of conditions and the following disclaimer.
20 ** 2. Redistributions in binary form must reproduce the above copyright
21 ** notice,this list of conditions and the following disclaimer in the
22 ** documentation and/or other materials provided with the distribution.
23 ** 3. The name of the author may not be used to endorse or promote products
24 ** derived from this software without specific prior written permission.
26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 **************************************************************************
39 #define ARCMSR_SCSI_INITIATOR_ID 255
40 #define ARCMSR_DEV_SECTOR_SIZE 512
41 #define ARCMSR_MAX_XFER_SECTORS 4096
42 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/
43 #define ARCMSR_MAX_TARGETLUN 8 /*8*/
44 #define ARCMSR_MAX_CHIPTYPE_NUM 4
45 #define ARCMSR_MAX_OUTSTANDING_CMD 256
46 #define ARCMSR_MAX_START_JOB 256
47 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
48 #define ARCMSR_MAX_FREESRB_NUM 384
49 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
50 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
51 #define ARCMSR_MAX_ADAPTER 4
52 #define ARCMSR_RELEASE_SIMQ_LEVEL 230
53 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
54 #define ARCMSR_MAX_HBD_POSTQUEUE 256
55 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */
56 #define ARCMSR_NUM_MSIX_VECTORS 4
58 *********************************************************************
67 # define INTR_ENTROPY 0
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
74 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF)
75 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l)
76 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l)
77 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l)
78 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l)
79 #define arcmsr_htole32(x) htole32(x)
80 typedef struct mtx arcmsr_lock_t;
83 **********************************************************************************
85 **********************************************************************************
87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */
94 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
95 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */
96 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
97 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */
98 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */
99 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
100 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */
101 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
102 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */
103 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
104 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */
105 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
106 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
107 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
108 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
109 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
110 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
111 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */
112 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */
114 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */
115 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */
116 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */
117 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */
118 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */
119 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */
120 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */
121 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */
122 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */
123 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */
125 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
126 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
127 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */
128 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */
129 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
130 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */
131 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
132 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */
133 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
134 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */
135 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */
136 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */
137 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
138 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */
139 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */
140 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
141 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */
142 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
143 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */
144 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
145 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
146 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
147 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
148 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
149 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
150 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
151 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
152 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
155 #define PCIR_BARS 0x10
156 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
159 #define PCI_BASE_ADDR0 0x10
160 #define PCI_BASE_ADDR1 0x14
161 #define PCI_BASE_ADDR2 0x18
162 #define PCI_BASE_ADDR3 0x1C
163 #define PCI_BASE_ADDR4 0x20
164 #define PCI_BASE_ADDR5 0x24
166 **********************************************************************************
168 **********************************************************************************
170 #define ARCMSR_SCSICMD_IOCTL 0x77
171 #define ARCMSR_CDEVSW_IOCTL 0x88
172 #define ARCMSR_MESSAGE_FAIL 0x0001
173 #define ARCMSR_MESSAGE_SUCCESS 0x0000
175 **********************************************************************************
177 **********************************************************************************
179 #define arcmsr_ccbsrb_ptr spriv_ptr0
180 #define arcmsr_ccbacb_ptr spriv_ptr1
181 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
182 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
183 #define get_min(x,y) ((x) < (y) ? (x) : (y))
184 #define get_max(x,y) ((x) < (y) ? (y) : (x))
186 **************************************************************************
187 **************************************************************************
189 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
190 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
191 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r)
192 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d)
194 **********************************************************************************
195 ** IOCTL CONTROL Mail Box
196 **********************************************************************************
199 u_int32_t HeaderLength;
200 u_int8_t Signature[8];
202 u_int32_t ControlCode;
203 u_int32_t ReturnCode;
207 struct CMD_MESSAGE_FIELD {
208 struct CMD_MESSAGE cmdmessage; /* ioctl header */
209 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */
212 /************************************************************************/
213 /************************************************************************/
215 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
216 #define ARCMSR_IOP_ERROR_VENDORID 0x0002
217 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002
218 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
219 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
220 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
221 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
222 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
223 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
224 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
225 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
228 #define ARECA_SATA_RAID 0x90000000
231 #define FUNCTION_READ_RQBUFFER 0x0801
232 #define FUNCTION_WRITE_WQBUFFER 0x0802
233 #define FUNCTION_CLEAR_RQBUFFER 0x0803
234 #define FUNCTION_CLEAR_WQBUFFER 0x0804
235 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
236 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806
237 #define FUNCTION_SAY_HELLO 0x0807
238 #define FUNCTION_SAY_GOODBYE 0x0808
239 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
241 ************************************************************************
242 ** IOCTL CONTROL CODE
243 ************************************************************************
245 /* ARECA IO CONTROL CODE*/
246 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD)
247 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD)
248 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD)
249 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
250 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
251 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
252 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD)
253 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
254 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
256 /* ARECA IOCTL ReturnCode */
257 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
258 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
259 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
260 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088
262 ************************************************************************
263 ** SPEC. for Areca HBA adapter
264 ************************************************************************
266 /* signature of set and get firmware config */
267 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
268 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
269 /* message code of inbound message register */
270 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
271 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
272 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
273 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
274 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
275 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
276 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
277 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
278 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
279 /* doorbell interrupt generator */
280 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
281 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
282 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
283 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
284 /* srb areca cdb flag */
285 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
286 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
287 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
288 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
289 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000
290 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001
291 /* outbound firmware ok */
292 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
294 #define ARCMSR_ARC1680_BUS_RESET 0x00000003
296 ************************************************************************
297 ** SPEC. for Areca HBB adapter
298 ************************************************************************
300 /* ARECA HBB COMMAND for its FIRMWARE */
301 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */
302 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
303 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */
304 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
306 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */
307 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874
308 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */
309 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C
311 /* ARECA FLAG LANGUAGE */
312 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
313 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
314 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
315 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
317 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
318 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
319 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
321 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
322 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
323 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
324 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
325 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
326 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
327 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
328 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
329 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
330 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
332 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
333 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
334 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
335 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
336 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
338 /* data tunnel buffer between user space program and its firmware */
339 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
340 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
341 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
342 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010
343 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018
344 #define ARCMSR_HBB_BASE0_LEN 0x00021000
345 #define ARCMSR_HBB_BASE1_LEN 0x00010000
347 ************************************************************************
348 ** SPEC. for Areca HBC adapter
349 ************************************************************************
351 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
352 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
353 /* Host Interrupt Mask */
354 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
355 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
356 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
357 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
358 /* Host Interrupt Status */
359 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
361 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
362 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
364 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
366 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
367 ** value. This bit clears only when Outbound Doorbell bits
368 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
369 ** Clear register clears bits in the Outbound Doorbell register.
371 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
373 ** Set whenever the Outbound Post List Producer/Consumer
374 ** Register (FIFO) is not empty. It clears when the Outbound
375 ** Post List FIFO is empty.
377 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
379 ** This bit indicates a SAS interrupt from a source external to
380 ** the PCIe core. This bit is not maskable.
383 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/
384 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/
385 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/
386 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/
387 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/
388 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/
389 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/
390 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/
391 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/
392 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/
393 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
394 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024
395 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080
398 ************************************************************************
399 ** SPEC. for Areca HBD adapter
400 ************************************************************************
402 #define ARCMSR_HBDMU_CHIP_ID 0x00004
403 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008
404 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034
405 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200
406 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C
407 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400
408 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404
409 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420
410 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424
411 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460
412 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480
413 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484
414 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000
415 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004
416 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018
417 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060
418 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064
419 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C
420 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070
421 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088
422 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C
424 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000
425 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100
426 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200
428 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16
429 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20
431 /* Host Interrupt Mask */
432 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */
433 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */
435 /* Host Interrupt Status */
436 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010
437 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000
438 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010
441 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001
442 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002
444 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001
445 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002
447 /*outbound message 0 ready*/
448 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
450 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003
452 /*outbound message cmd isr door bell clear*/
453 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000
456 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001
457 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
459 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
460 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
462 *******************************************************************************
463 ** SPEC. for Areca HBE adapter
464 *******************************************************************************
466 #define ARCMSR_SIGNATURE_1884 0x188417D3
467 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001
468 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
469 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */
471 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002
472 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004
473 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */
474 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002
475 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004
476 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
477 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */
478 /* ARC-1884 doorbell sync */
479 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
480 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
482 *********************************************************************
483 ** Message Unit structure
484 *********************************************************************
486 struct HBA_MessageUnit
488 u_int32_t resrved0[4]; /*0000 000F*/
489 u_int32_t inbound_msgaddr0; /*0010 0013*/
490 u_int32_t inbound_msgaddr1; /*0014 0017*/
491 u_int32_t outbound_msgaddr0; /*0018 001B*/
492 u_int32_t outbound_msgaddr1; /*001C 001F*/
493 u_int32_t inbound_doorbell; /*0020 0023*/
494 u_int32_t inbound_intstatus; /*0024 0027*/
495 u_int32_t inbound_intmask; /*0028 002B*/
496 u_int32_t outbound_doorbell; /*002C 002F*/
497 u_int32_t outbound_intstatus; /*0030 0033*/
498 u_int32_t outbound_intmask; /*0034 0037*/
499 u_int32_t reserved1[2]; /*0038 003F*/
500 u_int32_t inbound_queueport; /*0040 0043*/
501 u_int32_t outbound_queueport; /*0044 0047*/
502 u_int32_t reserved2[2]; /*0048 004F*/
503 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
504 u_int32_t reserved4[128]; /*0800 09FF 128*/
505 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
506 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
507 u_int32_t reserved5[32]; /*0E80 0EFF 32*/
508 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
509 u_int32_t reserved6[32]; /*0F80 0FFF 32*/
512 *********************************************************************
514 *********************************************************************
516 struct HBB_DOORBELL_1203
518 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */
519 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */
520 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */
521 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */
522 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */
526 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
527 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
528 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
529 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
530 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
533 *********************************************************************
535 *********************************************************************
539 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */
540 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
541 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
542 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
543 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
546 *********************************************************************
548 *********************************************************************
550 struct HBB_MessageUnit
552 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
553 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
554 int32_t postq_index; /* post queue index */
555 int32_t doneq_index; /* done queue index */
556 struct HBB_DOORBELL *hbb_doorbell;
557 struct HBB_RWBUFFER *hbb_rwbuffer;
558 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */
559 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */
560 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */
561 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */
565 *********************************************************************
567 *********************************************************************
569 struct HBC_MessageUnit {
570 u_int32_t message_unit_status; /*0000 0003*/
571 u_int32_t slave_error_attribute; /*0004 0007*/
572 u_int32_t slave_error_address; /*0008 000B*/
573 u_int32_t posted_outbound_doorbell; /*000C 000F*/
574 u_int32_t master_error_attribute; /*0010 0013*/
575 u_int32_t master_error_address_low; /*0014 0017*/
576 u_int32_t master_error_address_high; /*0018 001B*/
577 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
578 u_int32_t inbound_doorbell; /*0020 0023*/
579 u_int32_t diagnostic_rw_data; /*0024 0027*/
580 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
581 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
582 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
583 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
584 u_int32_t dcr_data; /*0038 003B*/
585 u_int32_t dcr_address; /*003C 003F*/
586 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
587 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
588 u_int32_t hcb_pci_address_low; /*0048 004B*/
589 u_int32_t hcb_pci_address_high; /*004C 004F*/
590 u_int32_t iop_int_status; /*0050 0053*/
591 u_int32_t iop_int_mask; /*0054 0057*/
592 u_int32_t iop_inbound_queue_port; /*0058 005B*/
593 u_int32_t iop_outbound_queue_port; /*005C 005F*/
594 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/
595 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/
596 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/
597 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/
598 u_int32_t inbound_doorbell_clear; /*0070 0073*/
599 u_int32_t i2o_message_unit_control; /*0074 0077*/
600 u_int32_t last_used_message_source_address_low; /*0078 007B*/
601 u_int32_t last_used_message_source_address_high; /*007C 007F*/
602 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/
603 u_int32_t message_dest_address_index; /*0090 0093*/
604 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
605 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
606 u_int32_t outbound_doorbell; /*009C 009F*/
607 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
608 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/
609 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/
610 u_int32_t reserved0; /*00AC 00AF*/
611 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
612 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
613 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
614 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
615 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
616 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
617 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
618 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
619 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
620 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
621 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
622 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
623 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/
624 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/
625 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/
626 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/
627 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/
628 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/
629 u_int32_t host_diagnostic; /*00F8 00FB*/
630 u_int32_t write_sequence; /*00FC 00FF*/
631 u_int32_t reserved1[34]; /*0100 0187*/
632 u_int32_t reserved2[1950]; /*0188 1FFF*/
633 u_int32_t message_wbuffer[32]; /*2000 207F*/
634 u_int32_t reserved3[32]; /*2080 20FF*/
635 u_int32_t message_rbuffer[32]; /*2100 217F*/
636 u_int32_t reserved4[32]; /*2180 21FF*/
637 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
640 *********************************************************************
642 *********************************************************************
645 uint32_t addressLow; //pointer to SRB block
646 uint32_t addressHigh;
647 uint32_t length; // in DWORDs
651 struct OutBound_SRB {
652 uint32_t addressLow; //pointer to SRB block
653 uint32_t addressHigh;
656 struct HBD_MessageUnit {
658 uint32_t chip_id; //0x0004
659 uint32_t cpu_mem_config; //0x0008
660 uint32_t reserved1[10]; //0x000C
661 uint32_t i2o_host_interrupt_mask; //0x0034
662 uint32_t reserved2[114]; //0x0038
663 uint32_t host_int_status; //0x0200
664 uint32_t host_int_enable; //0x0204
665 uint32_t reserved3[1]; //0x0208
666 uint32_t pcief0_int_enable; //0x020C
667 uint32_t reserved4[124]; //0x0210
668 uint32_t inbound_msgaddr0; //0x0400
669 uint32_t inbound_msgaddr1; //0x0404
670 uint32_t reserved5[6]; //0x0408
671 uint32_t outbound_msgaddr0; //0x0420
672 uint32_t outbound_msgaddr1; //0x0424
673 uint32_t reserved6[14]; //0x0428
674 uint32_t inbound_doorbell; //0x0460
675 uint32_t reserved7[7]; //0x0464
676 uint32_t outbound_doorbell; //0x0480
677 uint32_t outbound_doorbell_enable; //0x0484
678 uint32_t reserved8[734]; //0x0488
679 uint32_t inboundlist_base_low; //0x1000
680 uint32_t inboundlist_base_high; //0x1004
681 uint32_t reserved9[4]; //0x1008
682 uint32_t inboundlist_write_pointer; //0x1018
683 uint32_t inboundlist_read_pointer; //0x101C
684 uint32_t reserved10[16]; //0x1020
685 uint32_t outboundlist_base_low; //0x1060
686 uint32_t outboundlist_base_high; //0x1064
687 uint32_t reserved11; //0x1068
688 uint32_t outboundlist_copy_pointer; //0x106C
689 uint32_t outboundlist_read_pointer; //0x1070 0x1072
690 uint32_t reserved12[5]; //0x1074
691 uint32_t outboundlist_interrupt_cause; //0x1088
692 uint32_t outboundlist_interrupt_enable; //0x108C
693 uint32_t reserved13[988]; //0x1090
694 uint32_t message_wbuffer[32]; //0x2000
695 uint32_t reserved14[32]; //0x2080
696 uint32_t message_rbuffer[32]; //0x2100
697 uint32_t reserved15[32]; //0x2180
698 uint32_t msgcode_rwbuffer[256]; //0x2200
701 struct HBD_MessageUnit0 {
702 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
703 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
704 uint16_t postq_index;
705 uint16_t doneq_index;
706 struct HBD_MessageUnit *phbdmu;
709 *********************************************************************
711 *********************************************************************
713 struct HBE_MessageUnit {
714 u_int32_t iobound_doorbell; /*0000 0003*/
715 u_int32_t write_sequence_3xxx; /*0004 0007*/
716 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
717 u_int32_t posted_outbound_doorbell; /*000C 000F*/
718 u_int32_t master_error_attribute; /*0010 0013*/
719 u_int32_t master_error_address_low; /*0014 0017*/
720 u_int32_t master_error_address_high; /*0018 001B*/
721 u_int32_t hcb_size; /*001C 001F*/
722 u_int32_t inbound_doorbell; /*0020 0023*/
723 u_int32_t diagnostic_rw_data; /*0024 0027*/
724 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
725 u_int32_t diagnostic_rw_address_high; /*002C 002F*/
726 u_int32_t host_int_status; /*0030 0033 host interrupt status*/
727 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
728 u_int32_t dcr_data; /*0038 003B*/
729 u_int32_t dcr_address; /*003C 003F*/
730 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
731 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
732 u_int32_t hcb_pci_address_low; /*0048 004B*/
733 u_int32_t hcb_pci_address_high; /*004C 004F*/
734 u_int32_t iop_int_status; /*0050 0053*/
735 u_int32_t iop_int_mask; /*0054 0057*/
736 u_int32_t iop_inbound_queue_port; /*0058 005B*/
737 u_int32_t iop_outbound_queue_port; /*005C 005F*/
738 u_int32_t inbound_free_list_index; /*0060 0063*/
739 u_int32_t inbound_post_list_index; /*0064 0067*/
740 u_int32_t outbound_free_list_index; /*0068 006B*/
741 u_int32_t outbound_post_list_index; /*006C 006F*/
742 u_int32_t inbound_doorbell_clear; /*0070 0073*/
743 u_int32_t i2o_message_unit_control; /*0074 0077*/
744 u_int32_t last_used_message_source_address_low; /*0078 007B*/
745 u_int32_t last_used_message_source_address_high; /*007C 007F*/
746 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/
747 u_int32_t message_dest_address_index; /*0090 0093*/
748 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
749 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
750 u_int32_t outbound_doorbell; /*009C 009F*/
751 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
752 u_int32_t message_source_address_index; /*00A4 00A7*/
753 u_int32_t message_done_queue_index; /*00A8 00AB*/
754 u_int32_t reserved0; /*00AC 00AF*/
755 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
756 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
757 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
758 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
759 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
760 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
761 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
762 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
763 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
764 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
765 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
766 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
767 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/
768 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/
769 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/
770 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/
771 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/
772 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/
773 u_int32_t host_diagnostic; /*00F8 00FB*/
774 u_int32_t write_sequence; /*00FC 00FF*/
775 u_int32_t reserved1[46]; /*0100 01B7*/
776 u_int32_t reply_post_producer_index; /*01B8 01BB*/
777 u_int32_t reply_post_consumer_index; /*01BC 01BF*/
778 u_int32_t reserved2[1936]; /*01C0 1FFF*/
779 u_int32_t message_wbuffer[32]; /*2000 207F*/
780 u_int32_t reserved3[32]; /*2080 20FF*/
781 u_int32_t message_rbuffer[32]; /*2100 217F*/
782 u_int32_t reserved4[32]; /*2180 21FF*/
783 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
786 typedef struct deliver_completeQ {
789 u_int16_t cmdLMID; // reserved (0)
790 u_int16_t cmdFlag2; // reserved (0)
791 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q;
793 #define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128)
796 *********************************************************************
798 *********************************************************************
800 struct MessageUnit_UNION
803 struct HBA_MessageUnit hbamu;
804 struct HBB_MessageUnit hbbmu;
805 struct HBC_MessageUnit hbcmu;
806 struct HBD_MessageUnit0 hbdmu;
807 struct HBE_MessageUnit hbemu;
811 *************************************************************
812 ** structure for holding DMA address data
813 *************************************************************
815 #define IS_SG64_ADDR 0x01000000 /* bit24 */
817 ************************************************************************************************
818 ** ARECA FIRMWARE SPEC
819 ************************************************************************************************
820 ** Usage of IOP331 adapter
821 ** (All In/Out is in IOP331's view)
822 ** 1. Message 0 --> InitThread message and retrun code
823 ** 2. Doorbell is used for RS-232 emulation
824 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
825 ** bit1 -- data out has been read (DRIVER DATA READ OK)
826 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
827 ** bit1 -- data in has been read (IOP331 DATA READ OK)
828 ** 3. Index Memory Usage
829 ** offset 0xf00 : for RS232 out (request buffer)
830 ** offset 0xe00 : for RS232 in (scratch buffer)
831 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
832 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
833 ** 4. RS-232 emulation
834 ** Currently 128 byte buffer is used
835 ** 1st u_int32_t : Data length (1--124)
836 ** Byte 4--127 : Max 124 bytes of data
838 ** All SCSI Command must be sent through postQ:
839 ** (inbound queue port) Request frame must be 32 bytes aligned
840 ** # bit27--bit31 => flag for post ccb
841 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
842 ** bit31 : 0 : 256 bytes frame
843 ** 1 : 512 bytes frame
844 ** bit30 : 0 : normal request
849 ** -------------------------------------------------------------------------------
850 ** (outbount queue port) Request reply
851 ** # bit27--bit31 => flag for reply
852 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
853 ** bit31 : must be 0 (for this type of reply)
854 ** bit30 : reserved for BIOS handshake
856 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
857 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData
860 ** All BIOS request is the same with request from PostQ
862 ** Request frame is sent from configuration space
863 ** offset: 0x78 : Request Frame (bit30 == 1)
864 ** offset: 0x18 : writeonly to generate IRQ to IOP331
865 ** Completion of request:
866 ** (bit30 == 0, bit28==err flag)
867 ** 7. Definition of SGL entry (structure)
868 ** 8. Message1 Out - Diag Status Code (????)
869 ** 9. Message0 message code :
871 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
872 ** Signature 0x87974060(4)
873 ** Request len 0x00000200(4)
874 ** numbers of queue 0x00000100(4)
875 ** SDRAM Size 0x00000100(4)-->256 MB
876 ** IDE Channels 0x00000008(4)
877 ** vendor 40 bytes char
878 ** model 8 bytes char
879 ** FirmVer 16 bytes char
880 ** Device Map 16 bytes char
882 ** FirmwareVersion DWORD <== Added for checking of new firmware capability
883 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
884 ** Signature 0x87974063(4)
885 ** UPPER32 of Request Frame (4)-->Driver Only
886 ** 0x03 : Reset (Abort all queued Command)
887 ** 0x04 : Stop Background Activity
888 ** 0x05 : Flush Cache
889 ** 0x06 : Start Background Activity (re-start if background is halted)
890 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
891 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
892 ** byte 0 : 0xaa <-- signature
893 ** byte 1 : 0x55 <-- signature
894 ** byte 2 : year (04)
895 ** byte 3 : month (1..12)
896 ** byte 4 : date (1..31)
897 ** byte 5 : hour (0..23)
898 ** byte 6 : minute (0..59)
899 ** byte 7 : second (0..59)
900 ** *********************************************************************************
901 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
902 ** ==> Difference from IOP348
903 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
904 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP)
905 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code
906 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code
907 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver)
908 ** <A> use doorbell to generate interrupt
910 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
911 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
913 ** a. Message1: Out - Diag Status Code (????)
915 ** b. Message0: message code
917 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
918 ** Signature 0x87974060(4)
919 ** Request len 0x00000200(4)
920 ** numbers of queue 0x00000100(4)
921 ** SDRAM Size 0x00000100(4)-->256 MB
922 ** IDE Channels 0x00000008(4)
923 ** vendor 40 bytes char
924 ** model 8 bytes char
925 ** FirmVer 16 bytes char
926 ** Device Map 16 bytes char
927 ** cfgVersion ULONG <== Added for checking of new firmware capability
928 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
929 ** Signature 0x87974063(4)
930 ** UPPER32 of Request Frame (4)-->Driver Only
931 ** 0x03 : Reset (Abort all queued Command)
932 ** 0x04 : Stop Background Activity
933 ** 0x05 : Flush Cache
934 ** 0x06 : Start Background Activity (re-start if background is halted)
935 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
936 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
937 ** byte 0 : 0xaa <-- signature
938 ** byte 1 : 0x55 <-- signature
939 ** byte 2 : year (04)
940 ** byte 3 : month (1..12)
941 ** byte 4 : date (1..31)
942 ** byte 5 : hour (0..23)
943 ** byte 6 : minute (0..59)
944 ** byte 7 : second (0..59)
946 ** <2> Doorbell Register is used for RS-232 emulation
947 ** <A> different clear register
948 ** <B> different bit0 definition (bit0 is reserved)
950 ** inbound doorbell : at offset 0x20
951 ** inbound doorbell clear : at offset 0x70
953 ** inbound doorbell : bit0 -- reserved
954 ** bit1 -- data in ready (DRIVER DATA WRITE OK)
955 ** bit2 -- data out has been read (DRIVER DATA READ OK)
956 ** bit3 -- inbound message 0 ready
957 ** bit4 -- more than 12 request completed in a time
959 ** outbound doorbell : at offset 0x9C
960 ** outbound doorbell clear : at offset 0xA0
962 ** outbound doorbell : bit0 -- reserved
963 ** bit1 -- data out ready (IOP DATA WRITE OK)
964 ** bit2 -- data in has been read (IOP DATA READ OK)
965 ** bit3 -- outbound message 0 ready
967 ** <3> Index Memory Usage (Buffer Area)
968 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer)
969 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer)
970 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver)
971 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP)
973 ** <4> PostQ (Command Post Address)
974 ** All SCSI Command must be sent through postQ:
975 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43
976 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper)
977 ** outbound queue port32 at offset 0x44
978 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
979 ** <A> For 32bit queue, access low part is enough to send/receive request
980 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the
981 ** same for outbound queue port
982 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction
983 ** to post inbound request in a single instruction, and use 64bit instruction
984 ** to retrieve outbound request in a single instruction.
985 ** If in 32bit environment, when sending inbound queue, write high part first
986 ** then write low part. For receiving outbound request, read high part first
987 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF.
988 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the
989 ** consistency of the FIFO. Another way to check empty is to check status flag
991 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned)
992 ** For BIOS, 16bytes aligned is OK
993 ** For Driver, 32bytes alignment is recommended.
994 ** POST Command bit0 to bit3 is defined differently
995 ** ----------------------------
996 ** bit0:1 for PULL mode (must be 1)
997 ** ----------------------------
998 ** bit3/2/1: for arcmsr cdb size (arccdbsize)
999 ** 000: <= 0x0080 (128)
1000 ** 001: <= 0x0100 (256)
1001 ** 010: <= 0x0180 (384)
1002 ** 011: <= 0x0200 (512)
1003 ** 100: <= 0x0280 (640)
1004 ** 101: <= 0x0300 (768)
1005 ** 110: <= 0x0300 (reserved)
1006 ** 111: <= 0x0300 (reserved)
1007 ** -----------------------------
1008 ** if len > 0x300 the len always set as 0x300
1009 ** -----------------------------
1010 ** post addr = addr | ((len-1) >> 6) | 1
1011 ** -----------------------------
1012 ** page length in command buffer still required,
1014 ** if page length > 3,
1015 ** firmware will assume more request data need to be retrieved
1017 ** <D> Outbound Posting
1018 ** bit0:0 , no error, 1 with error, refer to status buffer
1019 ** bit1:0 , reserved (will be 0)
1020 ** bit2:0 , reserved (will be 0)
1021 ** bit3:0 , reserved (will be 0)
1022 ** bit63-4: Completed command address
1024 ** <E> BIOS support, no special support is required.
1025 ** LSI2108 support I/O register
1026 ** All driver functionality is supported through I/O address
1028 ************************************************************************************************
1031 **********************************
1033 **********************************
1036 /* 32bit Scatter-Gather list */
1037 struct SG32ENTRY { /* length bit 24 == 0 */
1038 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
1042 /* 64bit Scatter-Gather list */
1043 struct SG64ENTRY { /* length bit 24 == 1 */
1044 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
1046 u_int32_t addresshigh;
1048 struct SGENTRY_UNION {
1050 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
1051 struct SG64ENTRY sg64entry; /* 30h */
1055 **********************************
1057 **********************************
1064 **********************************
1066 typedef struct PHYS_ADDR64 {
1067 u_int32_t phyadd_low;
1068 u_int32_t phyadd_high;
1071 ************************************************************************************************
1073 ************************************************************************************************
1075 #define ARCMSR_FW_MODEL_OFFSET 15
1076 #define ARCMSR_FW_VERS_OFFSET 17
1077 #define ARCMSR_FW_DEVMAP_OFFSET 21
1078 #define ARCMSR_FW_CFGVER_OFFSET 25
1080 struct FIRMWARE_INFO {
1081 u_int32_t signature; /*0,00-03*/
1082 u_int32_t request_len; /*1,04-07*/
1083 u_int32_t numbers_queue; /*2,08-11*/
1084 u_int32_t sdram_size; /*3,12-15*/
1085 u_int32_t ide_channels; /*4,16-19*/
1086 char vendor[40]; /*5,20-59*/
1087 char model[8]; /*15,60-67*/
1088 char firmware_ver[16]; /*17,68-83*/
1089 char device_map[16]; /*21,84-99*/
1090 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
1091 char cfgSerial[16]; /*26,104-119*/
1092 u_int32_t cfgPicStatus; /*30,120-123*/
1094 /* (A) For cfgVersion in FIRMWARE_INFO
1095 ** if low BYTE (byte#0) >= 3 (version 3)
1096 ** then byte#1 report the capability of the firmware can xfer in a single request
1106 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages
1107 ** Driver support new xfer method need to set this field to indicate
1108 ** large CDB block in 0x100 unit (we use 0x100 byte as one page)
1109 ** e.g. If the length of CDB including MSG header and SGL is 0x1508
1110 ** driver need to set the msgPages to 0x16
1111 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length
1112 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag
1122 ************************************************************************************************
1124 ************************************************************************************************
1127 u_int8_t Bus; /* 00h should be 0 */
1128 u_int8_t TargetID; /* 01h should be 0--15 */
1129 u_int8_t LUN; /* 02h should be 0--7 */
1130 u_int8_t Function; /* 03h should be 1 */
1132 u_int8_t CdbLength; /* 04h not used now */
1133 u_int8_t sgcount; /* 05h */
1134 u_int8_t Flags; /* 06h */
1135 u_int8_t msgPages; /* 07h */
1137 u_int32_t Context; /* 08h Address of this request */
1138 u_int32_t DataLength; /* 0ch not used now */
1140 u_int8_t Cdb[16]; /* 10h SCSI CDB */
1142 ********************************************************
1143 ** Device Status : the same from SCSI bus if error occur
1144 ** SCSI bus status codes.
1145 ********************************************************
1147 u_int8_t DeviceStatus; /* 20h if error */
1149 u_int8_t SenseData[15]; /* 21h output */
1152 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
1153 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
1157 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */
1158 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */
1159 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */
1160 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
1161 #define ARCMSR_CDB_FLAG_HEADQ 0x08
1162 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
1164 #define SCSISTAT_GOOD 0x00
1165 #define SCSISTAT_CHECK_CONDITION 0x02
1166 #define SCSISTAT_CONDITION_MET 0x04
1167 #define SCSISTAT_BUSY 0x08
1168 #define SCSISTAT_INTERMEDIATE 0x10
1169 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14
1170 #define SCSISTAT_RESERVATION_CONFLICT 0x18
1171 #define SCSISTAT_COMMAND_TERMINATED 0x22
1172 #define SCSISTAT_QUEUE_FULL 0x28
1174 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
1175 #define ARCMSR_DEV_ABORTED 0xF1
1176 #define ARCMSR_DEV_INIT_FAIL 0xF2
1178 *********************************************************************
1179 ** Command Control Block (SrbExtension)
1180 ** SRB must be not cross page boundary,and the order from offset 0
1181 ** structure describing an ATA disk request
1182 ** this SRB length must be 32 bytes boundary
1183 *********************************************************************
1185 struct CommandControlBlock {
1186 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
1187 u_int32_t cdb_phyaddr_low; /* 504-507 */
1188 u_int32_t arc_cdb_size; /* 508-511 */
1189 /* ======================512+32 bytes============================ */
1190 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1191 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1192 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1193 u_int16_t srb_flags; /* 536-537 */
1194 u_int16_t srb_state; /* 538-539 */
1195 u_int32_t cdb_phyaddr_high; /* 540-543 */
1196 struct callout ccb_callout;
1198 /* ========================================================== */
1201 #define SRB_FLAG_READ 0x0000
1202 #define SRB_FLAG_WRITE 0x0001
1203 #define SRB_FLAG_ERROR 0x0002
1204 #define SRB_FLAG_FLUSHCACHE 0x0004
1205 #define SRB_FLAG_MASTER_ABORTED 0x0008
1206 #define SRB_FLAG_DMAVALID 0x0010
1207 #define SRB_FLAG_DMACONSISTENT 0x0020
1208 #define SRB_FLAG_DMAWRITE 0x0040
1209 #define SRB_FLAG_PKTBIND 0x0080
1210 #define SRB_FLAG_TIMER_START 0x0080
1212 #define ARCMSR_SRB_DONE 0x0000
1213 #define ARCMSR_SRB_UNBUILD 0x0000
1214 #define ARCMSR_SRB_TIMEOUT 0x1111
1215 #define ARCMSR_SRB_RETRY 0x2222
1216 #define ARCMSR_SRB_START 0x55AA
1217 #define ARCMSR_SRB_PENDING 0xAA55
1218 #define ARCMSR_SRB_RESET 0xA5A5
1219 #define ARCMSR_SRB_ABORTED 0x5A5A
1220 #define ARCMSR_SRB_ILLEGAL 0xFFFF
1222 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
1223 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
1226 *********************************************************************
1227 ** Adapter Control Block
1228 *********************************************************************
1230 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
1231 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
1232 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
1233 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
1234 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
1236 struct AdapterControlBlock {
1237 u_int32_t adapter_type; /* adapter A,B..... */
1239 bus_space_tag_t btag[2];
1240 bus_space_handle_t bhandle[2];
1241 bus_dma_tag_t parent_dmat;
1242 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
1243 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
1244 bus_dmamap_t srb_dmamap;
1246 struct cdev *ioctl_dev;
1249 struct resource *sys_res_arcmsr[2];
1250 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS];
1251 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */
1252 int irq_id[ARCMSR_NUM_MSIX_VECTORS];
1254 /* Hooks into the CAM XPT */
1255 struct cam_sim *psim;
1256 struct cam_path *ppath;
1257 u_int8_t *uncacheptr;
1258 unsigned long vir2phy_offset;
1260 unsigned long phyaddr;
1262 u_int32_t phyadd_low;
1263 u_int32_t phyadd_high;
1266 // unsigned long srb_phyaddr;
1267 /* Offset is used in making arc cdb physical to virtual calculations */
1268 u_int32_t outbound_int_enable;
1270 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
1272 u_int8_t adapter_index;
1274 u_int16_t acb_flags;
1276 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
1277 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
1278 int32_t workingsrb_doneindex; /* done srb array index */
1279 int32_t workingsrb_startindex; /* start srb array index */
1280 int32_t srboutstandingcount;
1282 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
1283 u_int32_t rqbuf_firstindex; /* first of read buffer */
1284 u_int32_t rqbuf_lastindex; /* last of read buffer */
1286 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
1287 u_int32_t wqbuf_firstindex; /* first of write buffer */
1288 u_int32_t wqbuf_lastindex; /* last of write buffer */
1290 arcmsr_lock_t isr_lock;
1291 arcmsr_lock_t srb_lock;
1292 arcmsr_lock_t postDone_lock;
1293 arcmsr_lock_t qbuffer_lock;
1295 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
1296 u_int32_t num_resets;
1297 u_int32_t num_aborts;
1298 u_int32_t firm_request_len; /*1,04-07*/
1299 u_int32_t firm_numbers_queue; /*2,08-11*/
1300 u_int32_t firm_sdram_size; /*3,12-15*/
1301 u_int32_t firm_ide_channels; /*4,16-19*/
1302 u_int32_t firm_cfg_version;
1303 char firm_model[12]; /*15,60-67*/
1304 char firm_version[20]; /*17,68-83*/
1305 char device_map[20]; /*21,84-99 */
1306 struct callout devmap_callout;
1307 u_int32_t pktRequestCount;
1308 u_int32_t pktReturnCount;
1309 u_int32_t vendor_device_id;
1310 u_int32_t adapter_bus_speed;
1311 u_int32_t maxOutstanding;
1312 u_int16_t sub_device_id;
1313 u_int32_t doneq_index;
1314 u_int32_t in_doorbell;
1315 u_int32_t out_doorbell;
1316 u_int32_t completionQ_entry;
1317 pCompletion_Q pCompletionQ;
1320 };/* HW_DEVICE_EXTENSION */
1322 #define ACB_F_SCSISTOPADAPTER 0x0001
1323 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
1324 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
1325 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
1326 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
1327 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
1328 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
1329 #define ACB_F_BUS_RESET 0x0080
1330 #define ACB_F_IOP_INITED 0x0100 /* iop init */
1331 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
1332 #define ACB_F_CAM_DEV_QFRZN 0x0400
1333 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */
1334 #define ACB_F_SRB_FUNCTION_POWER 0x1000
1335 #define ACB_F_MSIX_ENABLED 0x2000
1337 #define ARECA_RAID_GONE 0x55
1338 #define ARECA_RAID_GOOD 0xaa
1339 /* adapter_bus_speed */
1340 #define ACB_BUS_SPEED_3G 0
1341 #define ACB_BUS_SPEED_6G 1
1342 #define ACB_BUS_SPEED_12G 2
1344 *************************************************************
1345 *************************************************************
1348 u_int8_t ErrorCode:7;
1350 u_int8_t SegmentNumber;
1351 u_int8_t SenseKey:4;
1352 u_int8_t Reserved:1;
1353 u_int8_t IncorrectLength:1;
1354 u_int8_t EndOfMedia:1;
1355 u_int8_t FileMark:1;
1356 u_int8_t Information[4];
1357 u_int8_t AdditionalSenseLength;
1358 u_int8_t CommandSpecificInformation[4];
1359 u_int8_t AdditionalSenseCode;
1360 u_int8_t AdditionalSenseCodeQualifier;
1361 u_int8_t FieldReplaceableUnitCode;
1362 u_int8_t SenseKeySpecific[3];
1365 **********************************
1366 ** Peripheral Device Type definitions
1367 **********************************
1369 #define SCSI_DASD 0x00 /* Direct-access Device */
1370 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1371 #define SCSI_PRINTER 0x02 /* Printer device */
1372 #define SCSI_PROCESSOR 0x03 /* Processor device */
1373 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1374 #define SCSI_CDROM 0x05 /* CD-ROM device */
1375 #define SCSI_SCANNER 0x06 /* Scanner device */
1376 #define SCSI_OPTICAL 0x07 /* Optical memory device */
1377 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
1378 #define SCSI_COMM 0x09 /* Communications device */
1379 #define SCSI_NODEV 0x1F /* Unknown or no device type */
1381 ************************************************************************************************************
1382 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1383 ** 80331 PCI-to-PCI Bridge
1384 ** PCI Configuration Space
1386 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1387 ** Programming Interface
1388 ** ========================
1389 ** Configuration Register Address Space Groupings and Ranges
1390 ** =============================================================
1391 ** Register Group Configuration Offset
1392 ** -------------------------------------------------------------
1393 ** Standard PCI Configuration 00-3Fh
1394 ** -------------------------------------------------------------
1395 ** Device Specific Registers 40-A7h
1396 ** -------------------------------------------------------------
1398 ** -------------------------------------------------------------
1399 ** Enhanced Capability List CC-FFh
1400 ** ==========================================================================================================
1401 ** Standard PCI [Type 1] Configuration Space Address Map
1402 ** **********************************************************************************************************
1403 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1404 ** ----------------------------------------------------------------------------------------------------------
1405 ** | Device ID | Vendor ID | 00h
1406 ** ----------------------------------------------------------------------------------------------------------
1407 ** | Primary Status | Primary Command | 04h
1408 ** ----------------------------------------------------------------------------------------------------------
1409 ** | Class Code | RevID | 08h
1410 ** ----------------------------------------------------------------------------------------------------------
1411 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch
1412 ** ----------------------------------------------------------------------------------------------------------
1414 ** ----------------------------------------------------------------------------------------------------------
1416 ** ----------------------------------------------------------------------------------------------------------
1417 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h
1418 ** ----------------------------------------------------------------------------------------------------------
1419 ** | Secondary Status | I/O Limit | I/O Base | 1Ch
1420 ** ----------------------------------------------------------------------------------------------------------
1421 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h
1422 ** ----------------------------------------------------------------------------------------------------------
1423 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h
1424 ** ----------------------------------------------------------------------------------------------------------
1425 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h
1426 ** ----------------------------------------------------------------------------------------------------------
1427 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch
1428 ** ----------------------------------------------------------------------------------------------------------
1429 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h
1430 ** ----------------------------------------------------------------------------------------------------------
1431 ** | Reserved | Capabilities Pointer | 34h
1432 ** ----------------------------------------------------------------------------------------------------------
1434 ** ----------------------------------------------------------------------------------------------------------
1435 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch
1436 **=============================================================================================================
1439 **=============================================================================================================
1441 ** Bit Default Description
1442 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
1443 ** ID is unique per product speed as indicated.
1444 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
1445 **=============================================================================================================
1447 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/
1448 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/
1450 **==============================================================================
1451 ** 0x05-0x04 : command register
1452 ** Bit Default Description
1453 **15:11 00h Reserved
1454 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus.
1455 ** The bridge does not support interrupts.
1456 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back
1457 ** transactions on the primary bus.
1458 ** The bridge does not generate fast back to back
1459 ** transactions on the primary bus.
1460 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
1461 ** 0=The bridge does not assert P_SERR#.
1462 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria.
1463 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating
1464 ** that bridge does not perform address or data stepping,
1465 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
1466 ** 0=When a data parity error is detected bridge does not assert S_PERR#.
1467 ** Also bridge does not assert P_SERR# in response to
1468 ** a detected address or attribute parity error.
1469 ** 1=When a data parity error is detected bridge asserts S_PERR#.
1470 ** The bridge also asserts P_SERR#
1471 ** (when enabled globally via bit(8) of this register)
1472 ** in response to a detected address or attribute parity error.
1473 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions.
1474 ** VGA palette write transactions are I/O transactions
1475 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
1476 ** P_AD[15:10] are not decoded (i.e. aliases are claimed),
1477 ** or are fully decoding
1478 ** (i.e., must be all 0's depending upon the VGA
1479 ** aliasing bit in the Bridge Control Register, offset 3Eh.
1480 ** P_AD[31:16] equal to 0000h
1481 ** 0=The bridge ignores VGA palette write transactions,
1482 ** unless decoded by the standard I/O address range window.
1483 ** 1=The bridge responds to VGA palette write transactions
1484 ** with medium DEVSEL# timing and forwards them to the secondary bus.
1485 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions.
1486 ** MWI transactions targeting resources on the opposite side of the bridge,
1487 ** however, are forwarded as MWI transactions.
1488 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions.
1489 ** This bit is read only and always returns 0 when read
1490 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
1491 ** Initiation of configuration transactions is not affected by the state of this bit.
1492 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface.
1493 ** 1=The bridge is enabled to function as an initiator on the primary interface.
1494 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
1495 ** 0=The bridge target response to memory transactions on the primary interface is disabled.
1496 ** 1=The bridge target response to memory transactions on the primary interface is enabled.
1497 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
1498 ** 0=The bridge target response to I/O transactions on the primary interface is disabled.
1499 ** 1=The bridge target response to I/O transactions on the primary interface is enabled.
1500 **==============================================================================
1502 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/
1503 #define PCI_DISABLE_INTERRUPT 0x0400
1505 **==============================================================================
1506 ** 0x07-0x06 : status register
1507 ** Bit Default Description
1508 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1509 ** attribute or data parity error.
1510 ** This bit is set regardless of the state of the PER bit in the command register.
1511 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
1512 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when,
1513 ** acting as the initiator on the primary bus,
1514 ** its transaction (with the exception of special cycles)
1515 ** has been terminated with a Master Abort.
1516 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when,
1517 ** acting as the initiator on the primary bus,
1518 ** its transaction has been terminated with a Target Abort.
1519 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it,
1520 ** as the target of a transaction, terminates it with a Target Abort.
1521 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1522 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface.
1523 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1524 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1525 ** The bridge is the current master on the primary bus
1526 ** S_PERR# is detected asserted or is asserted by bridge
1527 ** The Parity Error Response bit is set in the Command register
1528 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge
1529 ** is able to respond to fast back to back transactions on its primary interface.
1531 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
1533 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities.
1534 ** Offset 34h (Capability Pointer register)
1535 ** provides the offset for the first entry
1536 ** in the linked list of enhanced capabilities.
1537 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function.
1538 ** The bridge does not support interrupts.
1539 ** 02:00 000 Reserved
1540 **==============================================================================
1542 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */
1543 #define ARCMSR_ADAP_66MHZ 0x20
1545 **==============================================================================
1546 ** 0x08 : revision ID
1547 ** Bit Default Description
1548 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1549 **==============================================================================
1551 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/
1553 **==============================================================================
1554 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1555 ** Bit Default Description
1556 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device.
1557 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
1558 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
1559 **==============================================================================
1561 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/
1563 **==============================================================================
1564 ** 0x0c : cache line size
1565 ** Bit Default Description
1566 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
1567 ** The contents of this register are factored into
1568 ** internal policy decisions associated with memory read prefetching,
1569 ** and the promotion of Memory Write transactions to MWI transactions.
1570 ** Valid cache line sizes are 8 and 16 dwords.
1571 ** When the cache line size is set to an invalid value,
1572 ** bridge behaves as though the cache line size was set to 00h.
1573 **==============================================================================
1575 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/
1577 **==============================================================================
1578 ** 0x0d : latency timer (number of pci clock 00-ff )
1579 ** Bit Default Description
1580 ** Primary Latency Timer (PTV):
1581 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
1582 ** referenced from the assertion of FRAME# to the expiration of the timer,
1583 ** when bridge may continue as master of the current transaction. All bits are writable,
1584 ** resulting in a granularity of 1 PCI clock cycle.
1585 ** When the timer expires (i.e., equals 00h)
1586 ** bridge relinquishes the bus after the first data transfer
1587 ** when its PCI bus grant has been deasserted.
1588 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
1589 ** Indicates the number of PCI clock cycles,
1590 ** referenced from the assertion of FRAME# to the expiration of the timer,
1591 ** when bridge may continue as master of the current transaction.
1592 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle.
1593 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1594 ** (Except in the case where MLT expires within 3 data phases
1595 ** of an ADB.In this case bridge continues on
1596 ** until it reaches the next ADB before relinquishing the bus.)
1597 **==============================================================================
1599 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/
1601 **==============================================================================
1602 ** 0x0e : (header type,single function )
1603 ** Bit Default Description
1604 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1605 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space.
1606 ** Returns ¡§01h¡¨ when read indicating
1607 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
1608 **==============================================================================
1610 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/
1612 **==============================================================================
1614 **==============================================================================
1617 **==============================================================================
1619 ** PCI CFG Base Address #0 (0x10)
1620 **==============================================================================
1623 **==============================================================================
1625 ** PCI CFG Base Address #1 (0x14)
1626 **==============================================================================
1629 **==============================================================================
1631 ** PCI CFG Base Address #2 (0x18)
1632 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1633 ** Bit Default Description
1634 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge.
1635 ** Any Type 1 configuration cycle
1636 ** on the primary bus whose bus number is greater than the secondary bus number,
1637 ** and less than or equal to the subordinate bus number
1638 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
1639 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected.
1640 ** Any Type 1 configuration cycle matching this bus number
1641 ** is translated to a Type 0 configuration cycle (or a Special Cycle)
1642 ** before being executed on bridge's secondary PCI bus.
1643 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number.
1644 ** Any Type 1 configuration cycle on the primary interface
1645 ** with a bus number that is less than the contents
1646 ** of this register field does not be claimed by bridge.
1647 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1648 ** Bit Default Description
1649 ** Secondary Latency Timer (STV):
1650 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer.
1651 ** Indicates the number of PCI clock cycles,
1652 ** referenced from the assertion of FRAME# to the expiration of the timer,
1653 ** when bridge may continue as master of the current transaction. All bits are writable,
1654 ** resulting in a granularity of 1 PCI clock cycle.
1655 ** When the timer expires (i.e., equals 00h)
1656 ** bridge relinquishes the bus after the first data transfer
1657 ** when its PCI bus grant has been deasserted.
1658 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
1659 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME#
1660 ** to the expiration of the timer,
1661 ** when bridge may continue as master of the current transaction. All bits are writable,
1662 ** resulting in a granularity of 1 PCI clock cycle.
1663 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
1664 ** (Except in the case where MLT expires within 3 data phases of an ADB.
1665 ** In this case bridge continues on until it reaches the next ADB
1666 ** before relinquishing the bus)
1667 **==============================================================================
1669 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/
1670 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/
1671 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/
1672 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/
1674 **==============================================================================
1676 ** PCI CFG Base Address #3 (0x1C)
1677 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1678 ** Bit Default Description
1679 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to
1680 ** determine when to forward I/O transactions from one interface to the other.
1681 ** These bits correspond to address lines 15:12 for 4KB alignment.
1682 ** Bits 11:0 are assumed to be FFFh.
1683 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
1684 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of
1685 ** an address range to determine when to forward I/O transactions
1686 ** from one interface to the other.
1687 ** These bits correspond to address lines 15:12 for 4KB alignment.
1688 ** Bits 11:0 are assumed to be 000h.
1689 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
1690 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1691 ** Bit Default Description
1692 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
1693 ** attribute or data parity error on its secondary interface.
1694 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
1695 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when,
1696 ** acting as the initiator on the secondary bus,
1697 ** it's transaction (with the exception of special cycles)
1698 ** has been terminated with a Master Abort.
1699 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when,
1700 ** acting as the initiator on the secondary bus,
1701 ** it's transaction has been terminated with a Target Abort.
1702 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it,
1703 ** as the target of a transaction, terminates it with a Target Abort.
1704 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
1705 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface.
1706 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
1707 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
1708 ** The bridge is the current master on the secondary bus
1709 ** S_PERR# is detected asserted or is asserted by bridge
1710 ** The Parity Error Response bit is set in the Command register
1711 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
1713 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
1715 ** 04:00 00h Reserved
1716 **==============================================================================
1718 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/
1719 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/
1720 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */
1722 **==============================================================================
1724 ** PCI CFG Base Address #4 (0x20)
1725 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1726 ** Bit Default Description
1727 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1728 ** the upper 1MB aligned value (exclusive) of the range.
1729 ** The incoming address must be less than or equal to this value.
1730 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1731 ** are assumed to be F FFFFh.
1732 ** 19:16 0h Reserved.
1733 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20]
1734 ** of the incoming address to determine the lower 1MB
1735 ** aligned value (inclusive) of the range.
1736 ** The incoming address must be greater than or equal to this value.
1737 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1738 ** are assumed to be 0 0000h.
1739 ** 03:00 0h Reserved.
1740 **==============================================================================
1742 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */
1743 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */
1745 **==============================================================================
1747 ** PCI CFG Base Address #5 (0x24)
1748 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1749 ** Bit Default Description
1750 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1751 ** the upper 1MB aligned value (exclusive) of the range.
1752 ** The incoming address must be less than or equal to this value.
1753 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1754 ** are assumed to be F FFFFh.
1755 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1756 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20]
1757 ** of the incoming address to determine the lower 1MB aligned value (inclusive)
1759 ** The incoming address must be greater than or equal to this value.
1760 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1761 ** are assumed to be 0 0000h.
1762 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1763 **==============================================================================
1765 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */
1766 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */
1768 **==============================================================================
1770 ** Bit Default Description
1771 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable
1772 ** bridge supports full 64-bit addressing.
1773 **==============================================================================
1775 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */
1777 **==============================================================================
1779 ** Bit Default Description
1780 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable
1781 ** bridge supports full 64-bit addressing.
1782 **==============================================================================
1784 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */
1786 **==============================================================================
1788 ** Bit Default Description
1789 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
1790 ** space. (Power Management Capability Registers)
1791 **==============================================================================
1793 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/
1795 **==============================================================================
1796 ** 0x3b-0x35 : reserved
1797 **==============================================================================
1800 **==============================================================================
1803 ** Bit Default Description
1804 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
1805 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
1806 **==============================================================================
1808 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/
1809 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/
1811 **==============================================================================
1813 ** Bit Default Description
1814 ** 15:12 0h Reserved
1815 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
1816 ** to a timer discard on either the primary or secondary interface.
1817 ** 0b=SERR# is not asserted.
1818 ** 1b=SERR# is asserted.
1819 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
1820 ** The delayed completion is then discarded.
1821 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles
1822 ** that bridge waits for an initiator on the secondary bus
1823 ** to repeat a delayed transaction request.
1824 ** The counter starts when the delayed transaction completion is ready
1825 ** to be returned to the initiator.
1826 ** When the initiator has not repeated the transaction
1827 ** at least once before the counter expires,bridge
1828 ** discards the delayed transaction from its queues.
1829 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles.
1830 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles.
1831 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles
1832 ** that bridge waits for an initiator on the primary bus
1833 ** to repeat a delayed transaction request.
1834 ** The counter starts when the delayed transaction completion
1835 ** is ready to be returned to the initiator.
1836 ** When the initiator has not repeated the transaction
1837 ** at least once before the counter expires,
1838 ** bridge discards the delayed transaction from its queues.
1839 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles.
1840 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles.
1841 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
1842 ** 06 0b Secondary Bus Reset (SBR):
1843 ** When cleared to 0b: The bridge deasserts S_RST#,
1844 ** when it had been asserted by writing this bit to a 1b.
1845 ** When set to 1b: The bridge asserts S_RST#.
1846 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus
1847 ** when a master abort termination occurs in response to
1848 ** a delayed transaction initiated by bridge on the target bus.
1849 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
1850 ** and returns FFFF FFFFh when a read.
1851 ** 1b=When the transaction had not yet been completed on the initiator bus
1852 ** (e.g.,delayed reads, or non-posted writes),
1853 ** then bridge returns a Target Abort in response to the original requester
1854 ** when it returns looking for its delayed completion on the initiator bus.
1855 ** When the transaction had completed on the initiator bus (e.g., a PMW),
1856 ** then bridge asserts P_SERR# (when enabled).
1857 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort
1858 ** while attempting to deliver a posted memory write on the destination bus.
1859 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit
1860 ** (also of this register),
1861 ** and the VGA Palette Snoop Enable bit (Command Register).
1862 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
1863 ** the VGA Aliasing bit for the corresponding enabled functionality,:
1864 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
1865 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
1866 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
1867 ** then this bit has no impact on bridge behavior.
1868 ** 03 0b VGA Enable: Setting this bit enables address decoding
1869 ** and transaction forwarding of the following VGA transactions from the primary bus
1870 ** to the secondary bus:
1871 ** frame buffer memory addresses 000A0000h:000BFFFFh,
1872 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares),
1873 ** or must be ¡§000000b¡¨
1874 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
1875 ** I/O and Memory Enable bits must be set in the Command register
1876 ** to enable forwarding of VGA cycles.
1877 ** 02 0b ISA Enable: Setting this bit enables special handling
1878 ** for the forwarding of ISA I/O transactions that fall within the address range
1879 ** specified by the I/O Base and Limit registers,
1880 ** and are within the lowest 64Kbyte of the I/O address map
1881 ** (i.e., 0000 0000h - 0000 FFFFh).
1882 ** 0b=All I/O transactions that fall within the I/O Base
1883 ** and Limit registers' specified range are forwarded
1884 ** from primary to secondary unfiltered.
1885 ** 1b=Blocks the forwarding from primary to secondary
1886 ** of the top 768 bytes of each 1Kbyte alias.
1887 ** On the secondary the top 768 bytes of each 1K alias
1888 ** are inversely decoded and forwarded
1889 ** from secondary to primary.
1890 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
1891 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected
1892 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
1893 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error
1894 ** that is detected on its secondary interface.
1895 ** 0b=When a data parity error is detected bridge does not assert S_PERR#.
1896 ** Also bridge does not assert P_SERR# in response to a detected address
1897 ** or attribute parity error.
1898 ** 1b=When a data parity error is detected bridge asserts S_PERR#.
1899 ** The bridge also asserts P_SERR# (when enabled globally via bit(8)
1900 ** of the Command register)
1901 ** in response to a detected address or attribute parity error.
1902 **==============================================================================
1904 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/
1906 **************************************************************************
1907 ** Device Specific Registers 40-A7h
1908 **************************************************************************
1909 ** ----------------------------------------------------------------------------------------------------------
1910 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1911 ** ----------------------------------------------------------------------------------------------------------
1912 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h
1913 ** ----------------------------------------------------------------------------------------------------------
1914 ** | Bridge Control 2 | Bridge Control 1 | 44h
1915 ** ----------------------------------------------------------------------------------------------------------
1916 ** | Reserved | Bridge Status | 48h
1917 ** ----------------------------------------------------------------------------------------------------------
1919 ** ----------------------------------------------------------------------------------------------------------
1920 ** | Prefetch Policy | Multi-Transaction Timer | 50h
1921 ** ----------------------------------------------------------------------------------------------------------
1922 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h
1923 ** ----------------------------------------------------------------------------------------------------------
1924 ** | Reserved | Reserved | Secondary Decode Enable | 58h
1925 ** ----------------------------------------------------------------------------------------------------------
1926 ** | Reserved | Secondary IDSEL | 5Ch
1927 ** ----------------------------------------------------------------------------------------------------------
1929 ** ----------------------------------------------------------------------------------------------------------
1930 ** | Reserved | 68h:CBh
1931 ** ----------------------------------------------------------------------------------------------------------
1932 **************************************************************************
1933 **==============================================================================
1934 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
1935 ** Bit Default Description
1936 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule
1937 ** (PCI=16 clocks,PCI-X=6 clocks).
1938 ** Note that this field is only meaningful when:
1939 ** # Bit[11] of this register is set to 1b,
1940 ** indicating that a Grant Time-out violation had occurred.
1941 ** # bridge internal arbiter is enabled.
1942 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number)
1943 ** 0000b REQ#/GNT#[0]
1944 ** 0001b REQ#/GNT#[1]
1945 ** 0010b REQ#/GNT#[2]
1946 ** 0011b REQ#/GNT#[3]
1947 ** 1111b Default Value (no violation detected)
1948 ** When bit[11] is cleared by software, this field reverts back to its default value.
1949 ** All other values are Reserved
1950 ** 11 0b Grant Time-out Occurred: When set to 1b,
1951 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
1952 ** Software clears this bit by writing a 1b to it.
1953 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
1954 ** 1=During bus idle, bridge parks the bus on itself.
1955 ** The bus grant is removed from the last master and internally asserted to bridge.
1956 ** 09:08 00b Reserved
1957 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority.
1958 ** Each bit of this field assigns its corresponding secondary
1959 ** bus master to either the high priority arbiter ring (1b)
1960 ** or to the low priority arbiter ring (0b).
1961 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively.
1962 ** Bit [6] corresponds to the bridge internal secondary bus request
1963 ** while Bit [7] corresponds to the SATU secondary bus request.
1964 ** Bits [5:4] are unused.
1965 ** 0b=Indicates that the master belongs to the low priority group.
1966 ** 1b=Indicates that the master belongs to the high priority group
1967 **=================================================================================
1968 ** 0x43: Bridge Control Register 0 - BCR0
1969 ** Bit Default Description
1970 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight
1971 ** and the Posted Write data is limited to 4KB.
1972 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to
1973 ** 14 Posted Memory Write transactions and 8KB of posted write data.
1974 ** 06:03 0H Reserved.
1975 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
1976 ** to perform upstream prefetch operations for Memory
1977 ** Read requests received on its secondary interface.
1978 ** This bit also controls the bridge's ability to generate advanced read commands
1979 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
1980 ** to a Conventional PCI bus.
1981 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
1982 ** The use of Memory Read Line and Memory Read
1983 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request
1984 ** to an upstream bus operating in Conventional PCI mode.
1985 ** 1b=bridge treats upstream PCI Memory Read requests as though
1986 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
1987 ** Read Block commands as Memory Read
1988 ** when the primary bus is operating
1989 ** in Conventional PCI mode.
1990 ** NOTE: This bit does not affect bridge ability to perform read prefetching
1991 ** when the received command is Memory Read Line or Memory Read Multiple.
1992 **=================================================================================
1993 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
1994 ** Bit Default Description
1995 ** 15:08 0000000b Reserved
1996 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands,
1997 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands.
1998 ** The three options for handling these alias commands are to either pass it as is,
1999 ** re-map to the actual block memory read/write command encoding, or ignore
2000 ** the transaction forcing a Master Abort to occur on the Origination Bus.
2001 ** Bit (7:6) Handling of command
2002 ** 0 0 Re-map to Memory Read/Write Block before forwarding
2003 ** 0 1 Enqueue and forward the alias command code unaltered
2004 ** 1 0 Ignore the transaction, forcing Master Abort
2006 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions.
2007 ** The watchdog timers are used to detect prohibitively long latencies in the system.
2008 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request,
2009 ** or Split Requests (PCI-X mode) is not completed within 2 24 events
2010 ** (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode,
2011 ** and as the number of times being retried when operating in Conventional PCI mode)
2012 ** 0b=All 2 24 watchdog timers are enabled.
2013 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to
2014 ** the number of attempts bridge makes when initiating a PMW,
2015 ** transacting a Delayed Transaction, or how long it waits for
2016 ** a split completion corresponding to one of its requests.
2017 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism.
2018 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
2019 ** 0b=The Secondary bus arbiter times out an agent
2020 ** that does not assert FRAME# within 16/6 clocks of receiving its grant,
2021 ** once the bus has gone idle.
2022 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted.
2023 ** An infringing agent does not receive a subsequent GNT#
2024 ** until it de-asserts its REQ# for at least one clock cycle.
2025 ** 1b=GNT# time-out mechanism is disabled.
2027 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
2028 ** The time out mechanism is used to ensure that initiators
2029 ** of delayed transactions return for their delayed completion data/status
2030 ** within a reasonable amount of time after it is available from bridge.
2031 ** 0b=The secondary master time-out counter is enabled
2032 ** and uses the value specified by the Secondary Discard Timer bit
2033 ** (see Bridge Control Register).
2034 ** 1b=The secondary master time-out counter is disabled.
2035 ** The bridge waits indefinitely for a secondary bus master
2036 ** to repeat a delayed transaction.
2037 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism.
2038 ** The time out mechanism is used to ensure that initiators
2039 ** of delayed transactions return for their delayed completion data/status
2040 ** within a reasonable amount of time after it is available from bridge.
2041 ** 0b=The primary master time-out counter is enabled and uses the value specified
2042 ** by the Primary Discard Timer bit (see Bridge Control Register).
2043 ** 1b=The secondary master time-out counter is disabled.
2044 ** The bridge waits indefinitely for a secondary bus master
2045 ** to repeat a delayed transaction.
2047 **=================================================================================
2048 ** 0x47-0x46: Bridge Control Register 2 - BCR2
2049 ** Bit Default Description
2050 ** 15:07 0000b Reserved.
2051 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
2052 ** This bit disables all of the secondary PCI clock outputs including
2053 ** the feedback clock S_CLKOUT.
2054 ** This means that the user is required to provide an S_CLKIN input source.
2055 ** 05:04 11 (66 MHz) Preserved.
2058 ** 03:00 Fh (100 MHz & 66 MHz)
2060 ** This 4 bit field provides individual enable/disable mask bits for each of bridge
2061 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
2062 ** default to being enabled following the rising edge of P_RST#, depending on the
2063 ** frequency of the secondary bus clock:
2064 ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with
2065 ** all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
2066 ** ¡E Designs with 133 MHz Secondary PCI clock power up
2067 ** with the lower order 3 S_CLKOs enabled by default.
2068 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
2069 ** to downstream device clock inputs.
2070 **=================================================================================
2071 ** 0x49-0x48: Bridge Status Register - BSR
2072 ** Bit Default Description
2073 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
2074 ** is conditionally asserted when the secondary discard timer expires.
2075 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
2076 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2077 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry.
2078 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
2079 ** when bridge discards an upstream split read request
2080 ** after waiting in excess of 2 24 clocks for the corresponding
2081 ** Split Completion to arrive.
2082 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
2083 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2084 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry.
2085 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
2086 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding
2087 ** Split Completion to arrive.
2088 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
2089 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
2090 ** by bridge, to retire a PMW upstream.
2091 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
2092 ** is conditionally asserted when a Target Abort occurs as a result of an attempt,
2093 ** by bridge, to retire a PMW upstream.
2094 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
2095 ** is conditionally asserted when bridge discards an upstream PMW transaction
2096 ** after receiving 2 24 target retries from the primary bus target
2097 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
2098 ** is conditionally asserted when a data parity error is detected by bridge
2099 ** while attempting to retire a PMW upstream
2100 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR#
2101 ** is conditionally asserted when bridge detects an address parity error on
2102 ** the secondary bus.
2103 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
2104 ** is conditionally asserted when the primary bus discard timer expires.
2105 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
2106 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2107 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries
2108 ** from the secondary bus target.
2109 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
2110 ** when bridge discards a downstream split read request
2111 ** after waiting in excess of 2 24 clocks for the corresponding
2112 ** Split Completion to arrive.
2113 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
2114 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
2115 ** when bridge discards a downstream delayed write transaction request
2116 ** after receiving 2 24 target retries from the secondary bus target.
2117 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
2118 ** is conditionally asserted when bridge discards a downstream
2119 ** split write request after waiting in excess of 2 24 clocks
2120 ** for the corresponding Split Completion to arrive.
2121 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR#
2122 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
2123 ** by bridge, to retire a PMW downstream.
2124 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted
2125 ** when a Target Abort occurs as a result of an attempt, by bridge,
2126 ** to retire a PMW downstream.
2127 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
2128 ** is conditionally asserted when bridge discards a downstream PMW transaction
2129 ** after receiving 2 24 target retries from the secondary bus target
2130 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
2131 ** is conditionally asserted when a data parity error is detected by bridge
2132 ** while attempting to retire a PMW downstream.
2133 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted
2134 ** when bridge detects an address parity error on the primary bus.
2135 **==================================================================================
2136 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
2137 ** Bit Default Description
2138 ** 15:13 000b Reserved
2139 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks)
2140 ** that a secondary bus master has its grant maintained in order to enable
2141 ** multiple transactions to execute within the same arbitration cycle.
2142 ** Bit[02:00] GNT# Extended Duration
2143 ** 000 MTT Disabled (Default=no GNT# extension)
2149 ** 110 Invalid (treated as 000)
2150 ** 111 Invalid (treated as 000)
2151 ** 09:08 00b Reserved
2152 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT#
2153 ** pair supported by bridge secondary arbiter.
2154 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair,
2155 ** bit(6) corresponds to bridge internal REQ#/GNT# pair,
2156 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc.
2157 ** When a given bit is set to 1b, its corresponding REQ#/GNT#
2158 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register.
2159 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
2160 **==================================================================================
2161 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
2162 ** Bit Default Description
2163 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor
2164 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied
2165 ** using the FirstRead parameter.
2166 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
2167 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
2168 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating
2169 ** the number of bytes to prefetch from the secondary bus interface
2170 ** on the initial PreFetch operation.
2171 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
2172 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
2173 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
2174 ** in calculating the number of bytes to prefetch from the primary
2175 ** bus interface on subsequent PreFetch operations given
2176 ** that the read demands were not satisfied using
2177 ** the FirstRead parameter.
2178 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a
2179 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines
2180 ** Memory Read Multiple 6 cache lines
2181 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
2182 ** in calculating the number of bytes to prefetch from
2183 ** the primary bus interface on the initial PreFetch operation.
2184 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
2185 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
2186 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
2187 ** algorithm for the secondary and the primary bus interfaces.
2188 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
2189 ** enable bits for REQ#/GNT#[2:0].
2190 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
2191 ** 1b: enables the staged pre-fetch feature
2192 ** 0b: disables staged pre-fetch,
2193 ** and hardwires read pre-fetch policy to the following for
2195 ** Memory Read Line,
2196 ** and Memory Read Multiple commands:
2197 ** Command Type Hardwired Pre-Fetch Amount...
2198 ** Memory Read 4 DWORDs
2199 ** Memory Read Line 1 cache line
2200 ** Memory Read Multiple 2 cache lines
2201 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands
2202 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
2203 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
2204 **==================================================================================
2205 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
2206 ** Bit Default Description
2207 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior
2208 ** in response to its discarding of a delayed transaction that was initiated from the primary bus.
2209 ** 0b=bridge asserts P_SERR#.
2210 ** 1b=bridge does not assert P_SERR#
2211 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2212 ** 0b=bridge asserts P_SERR#.
2213 ** 1b=bridge does not assert P_SERR#
2214 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2215 ** 0b=bridge asserts P_SERR#.
2216 ** 1b=bridge does not assert P_SERR#
2217 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following
2218 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream.
2219 ** 0b=bridge asserts P_SERR#.
2220 ** 1b=bridge does not assert P_SERR#
2221 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following
2222 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
2223 ** 0b=bridge asserts P_SERR#.
2224 ** 1b=bridge does not assert P_SERR#
2225 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that
2226 ** it discards an upstream posted write transaction.
2227 ** 0b=bridge asserts P_SERR#.
2228 ** 1b=bridge does not assert P_SERR#
2229 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
2230 ** when a data parity error is detected while attempting to retire on of its PMWs upstream.
2231 ** 0b=bridge asserts P_SERR#.
2232 ** 1b=bridge does not assert P_SERR#
2233 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior
2234 ** when it detects an address parity error on the secondary bus.
2235 ** 0b=bridge asserts P_SERR#.
2236 ** 1b=bridge does not assert P_SERR#
2237 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to
2238 ** its discarding of a delayed transaction that was initiated on the secondary bus.
2239 ** 0b=bridge asserts P_SERR#.
2240 ** 1b=bridge does not assert P_SERR#
2241 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2242 ** 0b=bridge asserts P_SERR#.
2243 ** 1b=bridge does not assert P_SERR#
2244 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
2245 ** 0b=bridge asserts P_SERR#.
2246 ** 1b=bridge does not assert P_SERR#
2247 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following
2248 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream.
2249 ** 0b=bridge asserts P_SERR#.
2250 ** 1b=bridge does not assert P_SERR#
2251 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following
2252 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
2253 ** 0b=bridge asserts P_SERR#.
2254 ** 1b=bridge does not assert P_SERR#
2255 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event
2256 ** that it discards a downstream posted write transaction.
2257 ** 0b=bridge asserts P_SERR#.
2258 ** 1b=bridge does not assert P_SERR#
2259 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
2260 ** when a data parity error is detected while attempting to retire on of its PMWs downstream.
2261 ** 0b=bridge asserts P_SERR#.
2262 ** 1b=bridge does not assert P_SERR#
2263 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior
2264 ** when it detects an address parity error on the primary bus.
2265 ** 0b=bridge asserts P_SERR#.
2266 ** 1b=bridge does not assert P_SERR#
2267 **===============================================================================
2268 ** 0x56: Pre-Boot Status Register - PBSR
2269 ** Bit Default Description
2271 ** 06 - Reserved - value indeterminate
2273 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting:
2274 ** This bit reflect captured S_133EN strap,
2275 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
2276 ** Max Allowable Secondary Bus Frequency
2277 ** ** S_133EN PCI-X Mode
2281 **===============================================================================
2282 ** 0x59-0x58: Secondary Decode Enable Register - SDER
2283 ** Bit Default Description
2284 ** 15:03 FFF1h Preserved.
2285 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set,
2286 ** bridge overrides its secondary inverse decode logic and not
2287 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
2288 ** This creates a private memory space on the Secondary PCI bus
2289 ** that allows peer-to-peer transactions.
2290 ** 01:00 10 2 Preserved.
2291 **===============================================================================
2292 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
2293 ** Bit Default Description
2294 ** 15:10 000000 2 Reserved.
2295 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set,
2296 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion.
2297 ** When this bit is clear,
2298 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
2299 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set,
2300 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion.
2301 ** When this bit is clear,
2302 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
2303 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set,
2304 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion.
2305 ** When this bit is clear,
2306 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
2307 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set,
2308 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion.
2309 ** When this bit is clear,
2310 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
2311 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set,
2312 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion.
2313 ** When this bit is clear,
2314 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
2315 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set,
2316 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion.
2317 ** When this bit is clear,
2318 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
2319 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set,
2320 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion.
2321 ** When this bit is clear,
2322 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
2323 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set,
2324 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion.
2325 ** When this bit is clear,
2326 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
2327 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set,
2328 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion.
2329 ** When this bit is clear,
2330 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
2331 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set,
2332 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion.
2333 ** When this bit is clear,
2334 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
2335 **************************************************************************
2338 **************************************************************************
2340 **************************************************************************
2343 **************************************************************************
2344 ** PCI Extended Enhanced Capabilities List CC-FFh
2345 **************************************************************************
2346 ** ----------------------------------------------------------------------------------------------------------
2347 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2348 ** ----------------------------------------------------------------------------------------------------------
2349 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh
2350 ** ----------------------------------------------------------------------------------------------------------
2351 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h
2352 ** ----------------------------------------------------------------------------------------------------------
2353 ** | Reserved | Reserved | Reserved | E4h
2354 ** ----------------------------------------------------------------------------------------------------------
2356 ** ----------------------------------------------------------------------------------------------------------
2357 ** | Reserved | Reserved | Reserved | Reserved | ECh
2358 ** ----------------------------------------------------------------------------------------------------------
2359 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h
2360 ** ----------------------------------------------------------------------------------------------------------
2361 ** | PCI-X Bridge Status | F4h
2362 ** ----------------------------------------------------------------------------------------------------------
2363 ** | PCI-X Upstream Split Transaction Control | F8h
2364 ** ----------------------------------------------------------------------------------------------------------
2365 ** | PCI-X Downstream Split Transaction Control | FCh
2366 ** ----------------------------------------------------------------------------------------------------------
2367 **===============================================================================
2368 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2369 ** Bit Default Description
2370 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block
2371 **===============================================================================
2372 ** 0xDD: Next Item Pointer - PM_NXTP
2373 ** Bit Default Description
2374 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
2375 **===============================================================================
2376 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2377 ** Bit Default Description
2378 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge.
2379 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
2380 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
2381 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
2382 ** This returns 000b as PME# wake-up for bridge is not implemented.
2383 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge.
2384 ** 04:03 00 Reserved
2385 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
2386 **===============================================================================
2387 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2388 ** Bit Default Description
2389 ** 15:09 00h Reserved
2390 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#.
2391 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
2392 ** 07:02 00h Reserved
2393 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of
2394 ** a function and to set the Function into a new power state.
2398 ** 11 - D3 hot state
2399 **===============================================================================
2400 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2401 ** Bit Default Description
2402 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
2403 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that
2404 ** is to occur as a direct result of programming the function to D3 hot.
2405 ** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
2406 ** 05:00 00h Reserved
2407 **===============================================================================
2408 ** 0xE3: Power Management Data Register - PMDR
2409 ** Bit Default Description
2410 ** 07:00 00h Reserved
2411 **===============================================================================
2412 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2413 ** Bit Default Description
2414 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list.
2415 **===============================================================================
2416 ** 0xF1: Next Item Pointer - PX_NXTP
2417 ** Bit Default Description
2418 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this
2419 ** register is 00h indicating that this is the last entry in the linked list of capabilities.
2420 **===============================================================================
2421 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2422 ** Bit Default Description
2423 ** 15:09 00h Reserved
2424 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
2426 ** ** BitsMax FrequencyClock Period
2427 ** ** 000PCI ModeN/A
2431 ** ** 1xxreservedreserved
2432 ** ** The default value for this register is the operating frequency of the secondary bus
2433 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the
2434 ** secondary bus to the primary bus because there is not enough room within the limit
2435 ** specified in the Split Transaction Commitment Limit field in the Downstream Split
2436 ** Transaction Control register. The bridge does not set this bit.
2437 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full.
2438 ** The bridge does not set this bit.
2439 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID
2440 ** equal to bridge secondary bus number, device number 00h,
2441 ** and function number 0 is received on the secondary interface.
2442 ** This bit is cleared by software writing a '1'.
2443 ** 02 0b Split Completion Discarded (SCD): This bit is set
2444 ** when bridge discards a split completion moving toward the secondary bus
2445 ** because the requester would not accept it. This bit cleared by software writing a '1'.
2446 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
2447 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
2448 **===============================================================================
2449 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2450 ** Bit Default Description
2452 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge.
2453 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge
2454 ** because bridge throttles traffic on the completion side.
2455 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
2456 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears
2457 ** this bit by writing a 1b to it.
2458 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
2459 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it.
2460 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
2461 ** 0=The maximum operating frequency is 66 MHz.
2462 ** 1=The maximum operating frequency is 133 MHz.
2463 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
2464 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2465 ** 1=Primary Interface is connected as a 64-bit PCI bus.
2466 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field
2467 ** of the BNUM register at offset 18h.
2468 ** Apparently it was deemed necessary reflect it here for diagnostic purposes.
2469 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes.
2470 ** May be updated whenever a PCI-X
2471 ** configuration write cycle that targets bridge scores a hit.
2472 ** 02:00 0h Function Number (FNUM): The bridge Function #
2473 **===============================================================================
2474 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2475 ** Bit Default Description
2476 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2477 ** Software is permitted to program this register to any value greater than or equal to
2478 ** the contents of the Split Transaction Capacity register. A value less than the contents
2479 ** of the Split Transaction Capacity register causes unspecified results.
2480 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2481 ** size regardless of the amount of buffer space available.
2482 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2483 ** split completions. This register controls behavior of the bridge buffers for forwarding
2484 ** Split Transactions from a primary bus requester to a secondary bus completer.
2485 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
2486 **===============================================================================
2487 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2488 ** Bit Default Description
2489 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
2490 ** Software is permitted to program this register to any value greater than or equal to
2491 ** the contents of the Split Transaction Capacity register. A value less than the contents
2492 ** of the Split Transaction Capacity register causes unspecified results.
2493 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
2494 ** size regardless of the amount of buffer space available.
2495 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
2496 ** split completions. This register controls behavior of the bridge buffers for forwarding
2497 ** Split Transactions from a primary bus requester to a secondary bus completer.
2498 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs
2500 **************************************************************************
2507 *************************************************************************************************************************************
2508 ** 80331 Address Translation Unit Register Definitions
2509 ** ATU Interface Configuration Header Format
2510 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2511 *************************************************************************************************************************************
2512 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset
2513 **===================================================================================================================================
2514 ** | ATU Device ID | Vendor ID | 00h
2515 ** ----------------------------------------------------------------------------------------------------------
2516 ** | Status | Command | 04H
2517 ** ----------------------------------------------------------------------------------------------------------
2518 ** | ATU Class Code | Revision ID | 08H
2519 ** ----------------------------------------------------------------------------------------------------------
2520 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH
2521 ** ----------------------------------------------------------------------------------------------------------
2522 ** | Inbound ATU Base Address 0 | 10H
2523 ** ----------------------------------------------------------------------------------------------------------
2524 ** | Inbound ATU Upper Base Address 0 | 14H
2525 ** ----------------------------------------------------------------------------------------------------------
2526 ** | Inbound ATU Base Address 1 | 18H
2527 ** ----------------------------------------------------------------------------------------------------------
2528 ** | Inbound ATU Upper Base Address 1 | 1CH
2529 ** ----------------------------------------------------------------------------------------------------------
2530 ** | Inbound ATU Base Address 2 | 20H
2531 ** ----------------------------------------------------------------------------------------------------------
2532 ** | Inbound ATU Upper Base Address 2 | 24H
2533 ** ----------------------------------------------------------------------------------------------------------
2535 ** ----------------------------------------------------------------------------------------------------------
2536 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH
2537 ** ----------------------------------------------------------------------------------------------------------
2538 ** | Expansion ROM Base Address | 30H
2539 ** ----------------------------------------------------------------------------------------------------------
2540 ** | Reserved Capabilities Pointer | 34H
2541 ** ----------------------------------------------------------------------------------------------------------
2543 ** ----------------------------------------------------------------------------------------------------------
2544 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH
2545 ** ----------------------------------------------------------------------------------------------------------
2546 *********************************************************************************************************************
2549 ***********************************************************************************
2550 ** ATU Vendor ID Register - ATUVID
2551 ** -----------------------------------------------------------------
2552 ** Bit Default Description
2553 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel.
2554 ** This register, combined with the DID, uniquely identify the PCI device.
2555 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID
2556 ** to simulate the interface of a standard mechanism currently used by existing application software.
2557 ***********************************************************************************
2559 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/
2561 ***********************************************************************************
2562 ** ATU Device ID Register - ATUDID
2563 ** -----------------------------------------------------------------
2564 ** Bit Default Description
2565 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU.
2566 ** This ID, combined with the VID, uniquely identify any PCI device.
2567 ***********************************************************************************
2569 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/
2571 ***********************************************************************************
2572 ** ATU Command Register - ATUCMD
2573 ** -----------------------------------------------------------------
2574 ** Bit Default Description
2575 ** 15:11 000000 2 Reserved
2576 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
2577 ** 0=enables the assertion of interrupt signal.
2578 ** 1=disables the assertion of its interrupt signal.
2579 ** 09 0 2 Fast Back to Back Enable - When cleared,
2580 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2581 ** Ignored when operating in the PCI-X mode.
2582 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
2583 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
2584 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles
2585 ** of address stepping for PCI-X mode.
2586 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error
2587 ** is detected. When cleared, parity checking is disabled.
2588 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore,
2589 ** does not perform VGA palette snooping.
2590 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands.
2591 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
2592 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way.
2593 ** Not implemented and a reserved bit field.
2594 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus.
2595 ** When cleared, disables the device from generating PCI accesses.
2596 ** When set, allows the device to behave as a PCI bus master.
2597 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless
2598 ** of the state of this bit.
2599 ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses.
2600 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
2601 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions.
2602 ** Not implemented and a reserved bit field.
2603 ***********************************************************************************
2605 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/
2607 ***********************************************************************************
2608 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2609 ** -----------------------------------------------------------------
2610 ** Bit Default Description
2611 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
2612 ** when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
2613 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
2614 ** ¡E Read Data Parity Error when the ATU is a requester (outbound read).
2615 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU).
2616 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
2617 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
2618 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
2619 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
2620 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
2621 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target,
2622 ** terminates the transaction on the PCI bus with a target abort.
2623 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL#
2624 ** timing for a target device in Conventional PCI Mode regardless of the operating mode
2625 ** (except configuration accesses).
2630 ** The ATU interface uses Medium timing.
2631 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions:
2632 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
2633 ** ¡E And the ATU acted as the requester
2634 ** for the operation in which the error occurred.
2635 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2636 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2637 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2638 ** 07 1 2 (Conventional mode)
2640 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
2641 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
2642 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
2643 ** 06 0 2 UDF Supported - User Definable Features are not supported
2644 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported.
2645 ** 04 1 2 Capabilities - When set, this function implements extended capabilities.
2646 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt
2647 ** when the Interrupt Disable bit in the command register is a 0.
2648 ** 0=ATU interrupt signal deasserted.
2649 ** 1=ATU interrupt signal asserted.
2650 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to
2651 ** Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU
2652 ** interrupt signal.
2653 ** 02:00 00000 2 Reserved.
2654 ***********************************************************************************
2656 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/
2658 ***********************************************************************************
2659 ** ATU Revision ID Register - ATURID
2660 ** -----------------------------------------------------------------
2661 ** Bit Default Description
2662 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
2663 ***********************************************************************************
2665 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/
2667 ***********************************************************************************
2668 ** ATU Class Code Register - ATUCCR
2669 ** -----------------------------------------------------------------
2670 ** Bit Default Description
2671 ** 23:16 05H Base Class - Memory Controller
2672 ** 15:08 80H Sub Class - Other Memory Controller
2673 ** 07:00 00H Programming Interface - None defined
2674 ***********************************************************************************
2676 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/
2678 ***********************************************************************************
2679 ** ATU Cacheline Size Register - ATUCLSR
2680 ** -----------------------------------------------------------------
2681 ** Bit Default Description
2682 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
2683 ***********************************************************************************
2685 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/
2687 ***********************************************************************************
2688 ** ATU Latency Timer Register - ATULT
2689 ** -----------------------------------------------------------------
2690 ** Bit Default Description
2691 ** 07:03 00000 2 (for Conventional mode)
2692 ** 01000 2 (for PCI-X mode)
2693 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.
2694 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
2695 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer.
2696 ***********************************************************************************
2698 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/
2700 ***********************************************************************************
2701 ** ATU Header Type Register - ATUHTR
2702 ** -----------------------------------------------------------------
2703 ** Bit Default Description
2704 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device.
2705 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
2706 ** header conforms to PCI Local Bus Specification, Revision 2.3.
2707 ***********************************************************************************
2709 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/
2711 ***********************************************************************************
2712 ** ATU BIST Register - ATUBISTR
2714 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
2715 ** initiated. This register is the interface between the host processor requesting BIST functions and
2716 ** the 80331 replying with the results from the software implementation of the BIST functionality.
2717 ** -----------------------------------------------------------------
2718 ** Bit Default Description
2719 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit.
2720 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
2721 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
2722 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results
2723 ** found in ATUBISTR register bits [3:0].
2724 ** When the ATUCR BIST Interrupt Enable bit is clear:
2725 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed.
2726 ** The Intel XScale core does not clear this bit.
2727 ** 05:04 00 2 Reserved
2728 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
2729 ** The Intel XScale core places the results of the software BIST in these bits.
2730 ** A nonzero value indicates a device-specific error.
2731 ***********************************************************************************
2733 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/
2736 ***************************************************************************************
2737 ** ATU Base Registers and Associated Limit Registers
2738 ***************************************************************************************
2739 ** Base Address Register Limit Register Description
2740 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus.
2741 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs.
2742 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus.
2743 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs.
2744 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus.
2745 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs.
2746 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus.
2747 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs.
2748 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
2749 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM.
2750 **--------------------------------------------------------------------------------------
2751 ** ATU Inbound Window 1 is not a translate window.
2752 ** The ATU does not claim any PCI accesses that fall within this range.
2753 ** This window is used to allocate host memory for use by Private Devices.
2754 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus.
2755 ***********************************************************************************
2759 ***********************************************************************************
2760 ** Inbound ATU Base Address Register 0 - IABAR0
2762 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0)
2763 ** defines the block of memory addresses where the inbound translation window 0 begins.
2764 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2765 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
2766 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0
2767 ** depending on the value located within the IALR0.
2768 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
2769 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
2770 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2772 ** When IALR0 is cleared prior to host configuration:
2773 ** the user should also clear the Prefetchable Indicator and the Type Indicator.
2774 ** Assuming IALR0 is not cleared:
2775 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2776 ** when the Prefetchable Indicator is cleared prior to host configuration,
2777 ** the user should also set the Type Indicator for 32 bit addressability.
2778 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
2779 ** when the Prefetchable Indicator is set prior to host configuration, the user
2780 ** should also set the Type Indicator for 64 bit addressability.
2781 ** This is the default for IABAR0.
2782 ** -----------------------------------------------------------------
2783 ** Bit Default Description
2784 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location
2785 ** the translation function is to respond to when addressed from the PCI bus.
2786 ** 11:04 00H Reserved.
2787 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2788 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window:
2789 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2790 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2791 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2792 ** The ATU does not occupy I/O space,
2793 ** thus this bit must be zero.
2794 ***********************************************************************************
2796 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/
2797 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08
2798 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04
2800 ***********************************************************************************
2801 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2803 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2804 ** Together with the Translation Base Address this register defines the actual location the translation
2805 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2806 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2808 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability,
2809 ** the IAUBAR0 register attributes are read-only.
2810 ** -----------------------------------------------------------------
2811 ** Bit Default Description
2812 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
2813 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
2814 ***********************************************************************************
2816 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/
2818 ***********************************************************************************
2819 ** Inbound ATU Base Address Register 1 - IABAR1
2821 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1)
2822 ** defines the block of memory addresses where the inbound translation window 1 begins.
2823 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2824 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2825 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus.
2827 ** When a non-zero value is not written to IALR1 prior to host configuration,
2828 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability.
2829 ** This is the default for IABAR1.
2830 ** Assuming a non-zero value is written to IALR1,
2831 ** the user may set the Prefetchable Indicator
2832 ** or the Type Indicator:
2833 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
2834 ** boundary, when the Prefetchable Indicator is not set prior to host configuration,
2835 ** the user should also leave the Type Indicator set for 32 bit addressability.
2836 ** This is the default for IABAR1.
2837 ** b. when the Prefetchable Indicator is set prior to host configuration,
2838 ** the user should also set the Type Indicator for 64 bit addressability.
2839 ** -----------------------------------------------------------------
2840 ** Bit Default Description
2841 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus.
2842 ** 11:04 00H Reserved.
2843 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2844 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2845 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2846 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2847 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2848 ** The ATU does not occupy I/O space,
2849 ** thus this bit must be zero.
2850 ***********************************************************************************
2852 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
2854 ***********************************************************************************
2855 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
2857 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes.
2858 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs).
2859 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2860 ** The programmed value within the base address register must comply with the PCI programming
2861 ** requirements for address alignment.
2862 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
2863 ** from the PCI bus.
2865 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability,
2866 ** the IAUBAR1 register attributes are read-only.
2867 ** This is the default for IABAR1.
2868 ** -----------------------------------------------------------------
2869 ** Bit Default Description
2870 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1
2871 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
2872 ***********************************************************************************
2874 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
2876 ***********************************************************************************
2877 ** Inbound ATU Base Address Register 2 - IABAR2
2879 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2)
2880 ** defines the block of memory addresses where the inbound translation window 2 begins.
2881 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2882 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
2883 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
2884 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2886 ** When a non-zero value is not written to IALR2 prior to host configuration,
2887 ** the user should not set either the Prefetchable Indicator
2888 ** or the Type Indicator for 64 bit addressability.
2889 ** This is the default for IABAR2.
2890 ** Assuming a non-zero value is written to IALR2,
2891 ** the user may set the Prefetchable Indicator
2892 ** or the Type Indicator:
2893 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2894 ** when the Prefetchable Indicator is not set prior to host configuration,
2895 ** the user should also leave the Type Indicator set for 32 bit addressability.
2896 ** This is the default for IABAR2.
2897 ** b. when the Prefetchable Indicator is set prior to host configuration,
2898 ** the user should also set the Type Indicator for 64 bit addressability.
2899 ** -----------------------------------------------------------------
2900 ** Bit Default Description
2901 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location
2902 ** the translation function is to respond to when addressed from the PCI bus.
2903 ** 11:04 00H Reserved.
2904 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2905 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2906 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2907 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2908 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2909 ** The ATU does not occupy I/O space,
2910 ** thus this bit must be zero.
2911 ***********************************************************************************
2913 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
2915 ***********************************************************************************
2916 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
2918 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2919 ** Together with the Translation Base Address this register defines the actual location
2920 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2921 ** The programmed value within the base address register must comply with the PCI programming
2922 ** requirements for address alignment.
2924 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
2925 ** the IAUBAR2 register attributes are read-only.
2926 ** This is the default for IABAR2.
2927 ** -----------------------------------------------------------------
2928 ** Bit Default Description
2929 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2
2930 ** these bits define the actual location the translation function is to respond to
2931 ** when addressed from the PCI bus for addresses > 4GBytes.
2932 ***********************************************************************************
2934 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
2936 ***********************************************************************************
2937 ** ATU Subsystem Vendor ID Register - ASVIR
2938 ** -----------------------------------------------------------------
2939 ** Bit Default Description
2940 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
2941 ***********************************************************************************
2943 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/
2945 ***********************************************************************************
2946 ** ATU Subsystem ID Register - ASIR
2947 ** -----------------------------------------------------------------
2948 ** Bit Default Description
2949 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem.
2950 ***********************************************************************************
2952 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/
2954 ***********************************************************************************
2955 ** Expansion ROM Base Address Register -ERBAR
2956 ** -----------------------------------------------------------------
2957 ** Bit Default Description
2958 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location
2959 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
2960 ** 11:01 000H Reserved
2961 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address
2962 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
2963 ***********************************************************************************
2965 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/
2966 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01
2968 ***********************************************************************************
2969 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
2970 ** -----------------------------------------------------------------
2971 ** Bit Default Description
2972 ** 07:00 C0H Capability List Pointer - This provides an offset in this function¡¦s configuration space
2973 ** that points to the 80331 PCl Bus Power Management extended capability.
2974 ***********************************************************************************
2976 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/
2978 ***********************************************************************************
2979 ** Determining Block Sizes for Base Address Registers
2980 ** The required address size and type can be determined by writing ones to a base address register and
2981 ** reading from the registers. By scanning the returned value from the least-significant bit of the base
2982 ** address registers upwards, the programmer can determine the required address space size. The
2983 ** binary-weighted value of the first non-zero bit found indicates the required amount of space.
2984 ** Table 105 describes the relationship between the values read back and the byte sizes the base
2985 ** address register requires.
2986 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
2987 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires
2988 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning
2989 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this
2990 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.
2991 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their
2992 ** associated limit registers to enable which bits within the base address register are read/write and
2993 ** which bits are read only (0). This allows the programming of these registers in a manner similar to
2994 ** other PCI devices even though the limit is variable.
2995 ** Table 105. Memory Block Size Read Response
2996 ** Response After Writing all 1s
2997 ** to the Base Address Register
3000 ** Response After Writing all 1s
3001 ** to the Base Address Register
3004 ** FFFFFFF0H 16 FFF00000H 1 M
3005 ** FFFFFFE0H 32 FFE00000H 2 M
3006 ** FFFFFFC0H 64 FFC00000H 4 M
3007 ** FFFFFF80H 128 FF800000H 8 M
3008 ** FFFFFF00H 256 FF000000H 16 M
3009 ** FFFFFE00H 512 FE000000H 32 M
3010 ** FFFFFC00H 1K FC000000H 64 M
3011 ** FFFFF800H 2K F8000000H 128 M
3012 ** FFFFF000H 4K F0000000H 256 M
3013 ** FFFFE000H 8K E0000000H 512 M
3014 ** FFFFC000H 16K C0000000H 1 G
3015 ** FFFF8000H 32K 80000000H 2 G
3028 ***************************************************************************************
3034 ***********************************************************************************
3035 ** ATU Interrupt Line Register - ATUILR
3036 ** -----------------------------------------------------------------
3037 ** Bit Default Description
3038 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt
3039 ** request line connects to the device's PCI interrupt request lines
3040 ** (as specified in the interrupt pin register).
3041 ** A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨.
3042 ***********************************************************************************
3044 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/
3046 ***********************************************************************************
3047 ** ATU Interrupt Pin Register - ATUIPR
3048 ** -----------------------------------------------------------------
3049 ** Bit Default Description
3050 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin.
3051 ***********************************************************************************
3053 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/
3055 ***********************************************************************************
3056 ** ATU Minimum Grant Register - ATUMGNT
3057 ** -----------------------------------------------------------------
3058 ** Bit Default Description
3059 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
3060 ***********************************************************************************
3062 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/
3064 ***********************************************************************************
3065 ** ATU Maximum Latency Register - ATUMLAT
3066 ** -----------------------------------------------------------------
3067 ** Bit Default Description
3068 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus
3069 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
3070 ***********************************************************************************
3072 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/
3074 ***********************************************************************************
3075 ** Inbound Address Translation
3077 ** The ATU allows external PCI bus initiators to directly access the internal bus.
3078 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space.
3079 ** The process of inbound address translation involves two steps:
3080 ** 1. Address Detection.
3081 ** ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
3082 ** within the address windows defined for the inbound ATU.
3083 ** ¡E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
3084 ** mode and with Decode A DEVSEL# timing in the PCI-X mode.
3085 ** 2. Address Translation.
3086 ** ¡E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address.
3087 ** The ATU uses the following registers in inbound address window 0 translation:
3088 ** ¡E Inbound ATU Base Address Register 0
3089 ** ¡E Inbound ATU Limit Register 0
3090 ** ¡E Inbound ATU Translate Value Register 0
3091 ** The ATU uses the following registers in inbound address window 2 translation:
3092 ** ¡E Inbound ATU Base Address Register 2
3093 ** ¡E Inbound ATU Limit Register 2
3094 ** ¡E Inbound ATU Translate Value Register 2
3095 ** The ATU uses the following registers in inbound address window 3 translation:
3096 ** ¡E Inbound ATU Base Address Register 3
3097 ** ¡E Inbound ATU Limit Register 3
3098 ** ¡E Inbound ATU Translate Value Register 3
3099 ** Note: Inbound Address window 1 is not a translate window.
3100 ** Instead, window 1 may be used to allocate host memory for Private Devices.
3101 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
3102 ** thus the host BIOS does not configure window 3.
3103 ** Window 3 is intended to be used as a special window into local memory for private PCI
3104 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
3105 ** PCI-to-PCI Bridge in 80331 or
3106 ** Inbound address detection is determined from the 32-bit PCI address,
3107 ** (64-bit PCI address during DACs) the base address register and the limit register.
3108 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison.
3110 ** The algorithm for detection is:
3112 ** Equation 1. Inbound Address Detection
3113 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only)
3114 ** the PCI Address is claimed by the Inbound ATU.
3116 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
3117 ** with the associated inbound limit register.
3118 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs),
3119 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
3121 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit.
3122 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
3123 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
3124 ** lower 32-bits are used during address translation.
3125 ** The algorithm is:
3128 ** Equation 2. Inbound Translation
3129 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
3131 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
3132 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
3133 ** the result is the internal bus address. This translation mechanism is used for all inbound memory
3134 ** read and write commands excluding inbound configuration read and writes.
3135 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear
3136 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
3137 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
3140 ** Base_Register=3A00 0000H
3141 ** Limit_Register=FF80 0000H (8 Mbyte limit value)
3142 ** Value_Register=B100 0000H
3143 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
3145 ** Address Detection (32-bit address)
3147 ** PCI_Address & Limit_Register == Base_Register
3148 ** 3A45 012CH & FF80 0000H == 3A00 0000H
3150 ** ANS: PCI_Address is in the Inbound Translation Window
3151 ** Address Translation (to get internal bus address)
3153 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg
3154 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H
3156 ** ANS:IB_Address=B145 012CH
3157 ***********************************************************************************
3163 ***********************************************************************************
3164 ** Inbound ATU Limit Register 0 - IALR0
3166 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
3167 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
3168 ** PCI addresses to internal bus addresses.
3169 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
3170 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
3171 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3172 ** Specification, Revision 2.3 for additional information on programming base address registers.
3173 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a
3174 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
3175 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
3176 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
3177 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the
3178 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register.
3179 ** -----------------------------------------------------------------
3180 ** Bit Default Description
3181 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for
3182 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
3183 ** 11:00 000H Reserved
3184 ***********************************************************************************
3186 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
3188 ***********************************************************************************
3189 ** Inbound ATU Translate Value Register 0 - IATVR0
3191 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
3192 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
3193 ** inbound ATU address translation.
3194 ** -----------------------------------------------------------------
3195 ** Bit Default Description
3196 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses.
3197 ** This value must be 64-bit aligned on the internal bus.
3198 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
3199 ** 11:00 000H Reserved
3200 ***********************************************************************************
3202 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
3204 ***********************************************************************************
3205 ** Expansion ROM Limit Register - ERLR
3207 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
3208 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR.
3209 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one
3210 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
3211 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
3212 ** the corresponding bit within the ERBAR read/write from PCI.
3213 ** -----------------------------------------------------------------
3214 ** Bit Default Description
3215 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default
3216 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0.
3217 ** 11:00 000H Reserved.
3218 ***********************************************************************************
3220 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/
3222 ***********************************************************************************
3223 ** Expansion ROM Translate Value Register - ERTVR
3225 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the
3226 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
3227 ** Expansion ROM address translation.
3228 ** -----------------------------------------------------------------
3229 ** Bit Default Description
3230 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses
3231 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus.
3232 ** 11:00 000H Reserved
3233 ***********************************************************************************
3235 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/
3237 ***********************************************************************************
3238 ** Inbound ATU Limit Register 1 - IALR1
3240 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a
3241 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
3242 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
3243 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
3244 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the
3245 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only
3247 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
3248 ** not process any PCI bus transactions to this memory range.
3249 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
3250 ** IAUBAR1, and IALR1.
3251 ** -----------------------------------------------------------------
3252 ** Bit Default Description
3253 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size
3254 ** required for the ATUs memory window 1.
3255 ** 11:00 000H Reserved
3256 ***********************************************************************************
3258 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/
3260 ***********************************************************************************
3261 ** Inbound ATU Limit Register 2 - IALR2
3263 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
3264 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
3265 ** PCI addresses to internal bus addresses.
3266 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
3267 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
3268 ** register provides the block size requirements for the base address register. The remaining registers
3269 ** used for performing address translation are discussed in Section 3.2.1.1.
3270 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
3271 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
3272 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3273 ** Specification, Revision 2.3 for additional information on programming base address registers.
3274 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a
3275 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
3276 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
3277 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
3278 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the
3279 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only
3281 ** -----------------------------------------------------------------
3282 ** Bit Default Description
3283 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size
3284 ** required for the ATUs memory window 2.
3285 ** 11:00 000H Reserved
3286 ***********************************************************************************
3288 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/
3290 ***********************************************************************************
3291 ** Inbound ATU Translate Value Register 2 - IATVR2
3293 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
3294 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
3295 ** inbound ATU address translation.
3296 ** -----------------------------------------------------------------
3297 ** Bit Default Description
3298 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses.
3299 ** This value must be 64-bit aligned on the internal bus.
3300 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers.
3301 ** 11:00 000H Reserved
3302 ***********************************************************************************
3304 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/
3306 ***********************************************************************************
3307 ** Outbound I/O Window Translate Value Register - OIOWTVR
3309 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
3310 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
3311 ** result of the outbound ATU address translation.
3312 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
3313 ** length of 64 Kbytes.
3314 ** -----------------------------------------------------------------
3315 ** Bit Default Description
3316 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses.
3317 ** 15:00 0000H Reserved
3318 ***********************************************************************************
3320 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/
3322 ***********************************************************************************
3323 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
3325 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
3326 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3327 ** driven on the PCI bus as a result of the outbound ATU address translation.
3328 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
3330 ** -----------------------------------------------------------------
3331 ** Bit Default Description
3332 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
3333 ** 25:02 00 0000H Reserved
3334 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
3335 ** Only linear incrementing mode is supported.
3336 ***********************************************************************************
3338 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/
3340 ***********************************************************************************
3341 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3343 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3344 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3345 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
3346 ** a SAC is generated on the PCI bus.
3347 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed
3348 ** length of 64 Mbytes.
3349 ** -----------------------------------------------------------------
3350 ** Bit Default Description
3351 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3352 ***********************************************************************************
3354 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/
3356 ***********************************************************************************
3357 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
3359 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
3360 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3361 ** driven on the PCI bus as a result of the outbound ATU address translation.
3362 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
3364 ** -----------------------------------------------------------------
3365 ** Bit Default Description
3366 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
3367 ** 25:02 00 0000H Reserved
3368 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
3369 ** Only linear incrementing mode is supported.
3370 ***********************************************************************************
3372 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/
3374 ***********************************************************************************
3375 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
3377 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
3378 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3379 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
3380 ** a SAC is generated on the PCI bus.
3381 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
3383 ** -----------------------------------------------------------------
3384 ** Bit Default Description
3385 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3386 ***********************************************************************************
3388 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/
3390 ***********************************************************************************
3391 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
3393 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
3394 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing
3395 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3396 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus.
3397 ** -----------------------------------------------------------------
3398 ** Bit Default Description
3399 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
3400 ***********************************************************************************
3402 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/
3404 ***********************************************************************************
3405 ** ATU Configuration Register - ATUCR
3407 ** The ATU Configuration Register controls the outbound address translation for address translation
3408 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
3409 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
3410 ** interrupt enabling.
3411 ** -----------------------------------------------------------------
3412 ** Bit Default Description
3413 ** 31:20 00H Reserved
3414 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a
3415 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
3416 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
3417 ** applicable in the PCI-X mode.
3418 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set,
3419 ** with Direct Addressing enabled (bit 7 of the ATUCR set),
3420 ** the ATU forwards internal bus cycles with an address between 0000.0040H and
3421 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
3422 ** When clear, no translation occurs.
3424 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until
3425 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified.
3426 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and
3427 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired.
3428 ** 14:10 00000 2 Reserved
3429 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
3430 ** when the ATU detects that SERR# was asserted. When clear,
3431 ** the Intel XScale core is not interrupted when SERR# is detected.
3432 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
3433 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
3434 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of
3436 ** 07:04 0000 2 Reserved
3437 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
3438 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7
3439 ** in the ATUBISTR register.
3441 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit.
3442 ** When cleared, disables the outbound ATU.
3444 ***********************************************************************************
3446 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/
3448 ***********************************************************************************
3449 ** PCI Configuration and Status Register - PCSR
3451 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring
3452 ** various features of the PCI bus interface.
3453 ** -----------------------------------------------------------------
3454 ** Bit Default Description
3455 ** 31:19 0000H Reserved
3456 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address
3457 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error
3458 ** Response bit is cleared. Set under the following conditions:
3459 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
3460 ** 17:16 Varies with
3467 ** PCI-X capability - These two bits define the mode of
3468 ** the PCI bus (conventional or PCI-X) as well as the
3469 ** operating frequency in the case of PCI-X mode.
3470 ** 00 - Conventional PCI mode
3474 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification,
3475 ** Revision 1.0a, the operating
3476 ** mode is determined by an initialization pattern on the PCI bus during
3477 ** P_RST# assertion:
3478 ** DEVSEL# STOP# TRDY# Mode
3479 ** Deasserted Deasserted Deasserted Conventional
3480 ** Deasserted Deasserted Asserted PCI-X 66
3481 ** Deasserted Asserted Deasserted PCI-X 100
3482 ** Deasserted Asserted Asserted PCI-X 133
3483 ** All other patterns are reserved.
3485 ** Outbound Transaction Queue Busy:
3486 ** 0=Outbound Transaction Queue Empty
3487 ** 1=Outbound Transaction Queue Busy
3489 ** Inbound Transaction Queue Busy:
3490 ** 0=Inbound Transaction Queue Empty
3491 ** 1=Inbound Transaction Queue Busy
3493 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
3494 ** for the four discard timers attached to the queues holding read data.
3495 ** A value of 0 indicates the time-out value is 2 15 clocks.
3496 ** A value of 1 indicates the time-out value is 2 10 clocks.
3503 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in
3504 ** Conventional PCI mode by the assertion of M66EN during bus initialization.
3505 ** When clear, the interface
3506 ** has been initialized as a 33 MHz bus.
3507 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
3514 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
3515 ** configured as 64-bit capable by
3516 ** the assertion of REQ64# on the rising edge of P_RST#. When set,
3517 ** the PCI interface is configured as
3519 ** 07:06 00 2 Reserved.
3520 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core
3521 ** and all units on the internal
3522 ** bus. In addition to the internal bus initialization,
3523 ** this bit triggers the assertion of the M_RST# pin for
3524 ** initialization of registered DIMMs. When set:
3525 ** When operating in the conventional PCI mode:
3526 ** ¡E All current PCI transactions being mastered by the ATU completes,
3527 ** and the ATU master interfaces
3528 ** proceeds to an idle state. No additional transactions is mastered by these units
3529 ** until the internal bus reset is complete.
3530 ** ¡E All current transactions being slaved by the ATU on either the PCI bus
3531 ** or the internal bus
3532 ** completes, and the ATU target interfaces proceeds to an idle state.
3533 ** All future slave transactions master aborts,
3534 ** with the exception of the completion cycle for the transaction that set the Reset
3535 ** Internal Bus bit in the PCSR.
3536 ** ¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion)
3537 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete.
3538 ** ¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32
3539 ** Internal Bus clocks.
3540 ** ¡E The 80331 hardware clears this bit after the reset operation completes.
3541 ** When operating in the PCI-X mode:
3542 ** The ATU hardware responds the same as in Conventional PCI-X mode.
3543 ** However, this may create a problem in PCI-X mode for split requests in
3544 ** that there may still be an outstanding split completion that the
3545 ** ATU is either waiting to receive (Outbound Request) or initiate
3546 ** (Inbound Read Request). For a cleaner
3547 ** internal bus reset, host software can take the following steps prior
3548 ** to asserting Reset Internal bus:
3549 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
3550 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
3551 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction
3552 ** queue busy bits to be clear.
3553 ** 3. Set the Reset Internal Bus bit
3554 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode,
3555 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split
3556 ** completion transactions.
3557 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
3558 ** guaranteed that any prior configuration cycles have properly completed since there is only a one
3559 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate
3560 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset.
3561 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the
3562 ** Bus Master Indicator signal P_BMI used
3563 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and
3564 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low).
3565 ** 03 Varies with external state of PRIVDEV during
3567 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device
3568 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register.
3569 ** 0=Private Device control Disabled - SISR register bits default to zero
3570 ** 1=Private Device control Enabled - SISR register bits default to one
3571 ** 02 Varies with external state of RETRY during P_RST#
3572 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all
3573 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate
3574 ** configuration cycles.
3575 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
3576 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is
3577 ** low, the bit is cleared.
3578 ** 01 Varies with external state of CORE_RST# during P_RST#
3579 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
3580 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
3581 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel
3582 ** XScale core reset.
3583 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
3584 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
3585 ** high, the bit is clear.
3586 ** 00 Varies with external state of PRIVMEM during P_RST#
3587 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device
3588 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.
3589 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
3590 ** 1=Private Memory control Enabled - SDER register bits 2 default to one
3591 ***********************************************************************************
3593 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/
3595 ***********************************************************************************
3596 ** ATU Interrupt Status Register - ATUISR
3598 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
3599 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
3600 ** of the 80331. All bits in this register are Read/Clear.
3601 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register
3602 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set
3603 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The
3604 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this
3606 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core.
3607 ** -----------------------------------------------------------------
3608 ** Bit Default Description
3609 ** 31:18 0000H Reserved
3610 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR
3611 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set,
3612 ** this bit results in the assertion of the ATU Configure Register Write Interrupt.
3614 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register.
3615 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt.
3616 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write
3617 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these
3618 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
3619 ** Configure Register Write Interrupt.
3620 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion
3621 ** Message on the PCI Bus with the Split Completion Error attribute bit set.
3622 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
3623 ** Message from the PCI Bus with the Split Completion Error attribute bit set.
3624 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status
3625 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and
3626 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
3627 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
3628 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD
3629 ** register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
3630 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
3631 ** ¡E Read Data Parity Error when the ATU is an initiator (outbound read).
3632 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
3633 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor
3634 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR
3635 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR
3636 ** register bits 3:0.
3637 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion
3638 ** of the ATU Configure Register Write Interrupt.
3639 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort.
3640 ** 06:05 00 2 Reserved.
3641 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
3642 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort.
3643 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort.
3644 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
3645 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following
3647 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
3648 ** ¡E And the ATU acted as the requester for the operation in which the error occurred.
3649 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
3650 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
3651 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
3652 ***********************************************************************************
3654 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/
3656 ***********************************************************************************
3657 ** ATU Interrupt Mask Register - ATUIMR
3659 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
3660 ** generated by the ATU.
3661 ** -----------------------------------------------------------------
3662 ** Bit Default Description
3663 ** 31:15 0 0000H Reserved
3664 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
3665 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
3669 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the
3670 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
3671 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR.
3674 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and
3675 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the
3676 ** IABAR1 register or the IAUBAR1 register.
3679 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
3680 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
3683 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR
3684 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the
3685 ** PCIXSR being set.
3688 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
3689 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the
3690 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
3693 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
3694 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
3697 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the
3698 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set.
3701 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master.
3702 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the
3703 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
3706 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error
3707 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set
3710 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation
3711 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set.
3714 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation
3715 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
3718 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the
3719 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an
3720 ** inbound write transaction.
3721 ** 0=SERR# Not Asserted due to error
3722 ** 1=SERR# Asserted due to error
3723 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC
3724 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs
3725 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is
3726 ** actually requested from the inbound read queue.
3727 ** 0=Disconnect with data
3728 ** (the data being up to 64 bits of 1¡¦s)
3730 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
3731 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
3732 ** independent of the setting of this bit.
3733 ***********************************************************************************
3735 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/
3737 ***********************************************************************************
3738 ** Inbound ATU Base Address Register 3 - IABAR3
3740 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block
3741 ** of memory addresses where the inbound translation window 3 begins.
3742 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
3743 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
3744 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3.
3745 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
3747 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH),
3748 ** IABAR3 is not configured by the host during normal system initialization.
3750 ** When a non-zero value is not written to IALR3,
3751 ** the user should not set either the Prefetchable Indicator
3752 ** or the Type Indicator for 64 bit addressability.
3753 ** This is the default for IABAR3.
3754 ** Assuming a non-zero value is written to IALR3,
3755 ** the user may set the Prefetchable Indicator
3756 ** or the Type Indicator:
3757 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
3758 ** when the Prefetchable Indicator is not set,
3759 ** the user should also leave the Type Indicator set for 32 bit addressability.
3760 ** This is the default for IABAR3.
3761 ** b. when the Prefetchable Indicator is set,
3762 ** the user should also set the Type Indicator for 64 bit addressability.
3763 ** -----------------------------------------------------------------
3764 ** Bit Default Description
3765 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location
3766 ** the translation function is to respond to when addressed from the PCI bus.
3767 ** 11:04 00H Reserved.
3768 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
3769 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
3770 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3771 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3772 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
3773 ** The ATU does not occupy I/O space,
3774 ** thus this bit must be zero.
3775 ***********************************************************************************
3777 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/
3779 ***********************************************************************************
3780 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3782 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
3783 ** Together with the Translation Base Address this register defines the actual location
3784 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
3785 ** The programmed value within the base address register must comply with the PCI programming
3786 ** requirements for address alignment.
3788 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability,
3789 ** the IAUBAR3 register attributes are read-only.
3790 ** This is the default for IABAR3.
3791 ** -----------------------------------------------------------------
3792 ** Bit Default Description
3793 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define
3794 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
3795 ***********************************************************************************
3797 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/
3799 ***********************************************************************************
3800 ** Inbound ATU Limit Register 3 - IALR3
3802 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
3803 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
3804 ** PCI addresses to internal bus addresses.
3805 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
3806 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
3807 ** register provides the block size requirements for the base address register. The remaining registers
3808 ** used for performing address translation are discussed in Section 3.2.1.1.
3809 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
3810 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
3811 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3812 ** Specification, Revision 2.3 for additional information on programming base address registers.
3813 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a
3814 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
3815 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
3816 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
3817 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the
3818 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only
3820 ** -----------------------------------------------------------------
3821 ** Bit Default Description
3822 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required
3823 ** for the ATUs memory window 3.
3824 ** 11:00 000H Reserved
3825 ***********************************************************************************
3827 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/
3829 ***********************************************************************************
3830 ** Inbound ATU Translate Value Register 3 - IATVR3
3832 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
3833 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
3834 ** inbound ATU address translation.
3835 ** -----------------------------------------------------------------
3836 ** Bit Default Description
3837 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses.
3838 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
3839 ** access the internal 80331 memory-mapped registers.
3840 ** 11:00 000H Reserved
3841 ***********************************************************************************
3843 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/
3845 ***********************************************************************************
3846 ** Outbound Configuration Cycle Address Register - OCCAR
3848 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3849 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then
3850 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or
3851 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the
3853 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently
3854 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
3855 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3856 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
3857 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
3858 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
3859 ** -----------------------------------------------------------------
3860 ** Bit Default Description
3861 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
3862 ** configuration read or write cycle.
3863 ***********************************************************************************
3865 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/
3867 ***********************************************************************************
3868 ** Outbound Configuration Cycle Data Register - OCCDR
3870 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
3871 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a
3872 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to
3873 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
3874 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ.
3875 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never
3876 ** actually entered into the data register (which does not physically exist).
3877 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value
3878 ** within the ATU configuration space.
3879 ** -----------------------------------------------------------------
3880 ** Bit Default Description
3881 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read
3883 ***********************************************************************************
3885 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/
3887 ***********************************************************************************
3888 ** VPD Capability Identifier Register - VPD_CAPID
3890 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3891 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3892 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability
3893 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
3894 ** -----------------------------------------------------------------
3895 ** Bit Default Description
3896 ** 07:00 03H Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability
3897 ** Headers as being the VPD capability registers.
3898 ***********************************************************************************
3900 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/
3902 ***********************************************************************************
3903 ** VPD Next Item Pointer Register - VPD_NXTP
3905 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3906 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3907 ** For the 80331, this the final capability list, and hence, this register is set to 00H.
3908 ** -----------------------------------------------------------------
3909 ** Bit Default Description
3910 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3911 ** next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of
3912 ** extended capabilities in the 80331, the register is set to 00H.
3913 ***********************************************************************************
3915 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/
3917 ***********************************************************************************
3918 ** VPD Address Register - VPD_AR
3920 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
3921 ** accessed. The register is read/write and the initial value at power-up is indeterminate.
3922 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
3923 ** the Flag setting to determine whether the configuration write was intended to initiate a read or
3924 ** write of the VPD through the VPD Data Register.
3925 ** -----------------------------------------------------------------
3926 ** Bit Default Description
3927 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage
3928 ** component has completed. Please see Section 3.9, ¡§Vital Product Data¡¨ on page 201 for more details on
3929 ** how the 80331 handles the data transfer.
3930 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write
3931 ** Vital Product Data from the VPD storage component.
3932 ***********************************************************************************
3934 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/
3936 ***********************************************************************************
3937 ** VPD Data Register - VPD_DR
3939 ** This register is used to transfer data between the 80331 and the VPD storage component.
3940 ** -----------------------------------------------------------------
3941 ** Bit Default Description
3942 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component.
3943 ***********************************************************************************
3945 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/
3947 ***********************************************************************************
3948 ** Power Management Capability Identifier Register -PM_CAPID
3950 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3951 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3952 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
3953 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
3954 ** Interface Specification, Revision 1.1.
3955 ** -----------------------------------------------------------------
3956 ** Bit Default Description
3957 ** 07:00 01H Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability
3958 ** Headers as being the PCI Power Management Registers.
3959 ***********************************************************************************
3961 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/
3963 ***********************************************************************************
3964 ** Power Management Next Item Pointer Register - PM_NXTP
3966 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3967 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3968 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H.
3969 ** -----------------------------------------------------------------
3970 ** Bit Default Description
3971 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3972 ** next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header.
3973 ***********************************************************************************
3975 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/
3977 ***********************************************************************************
3978 ** Power Management Capabilities Register - PM_CAP
3980 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
3981 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
3982 ** information on the capabilities of the ATU function related to power management.
3983 ** -----------------------------------------------------------------
3984 ** Bit Default Description
3985 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME#
3986 ** is not supported by the 80331.
3987 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
3988 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
3989 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the
3990 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
3991 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence
3992 ** following the transition to the D0 uninitialized state.
3994 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
3995 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management
3996 ** Interface Specification, Revision 1.1
3997 ***********************************************************************************
3999 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/
4001 ***********************************************************************************
4002 ** Power Management Control/Status Register - PM_CSR
4004 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
4005 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
4006 ** interface for the power management extended capability.
4007 ** -----------------------------------------------------------------
4008 ** Bit Default Description
4009 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
4010 ** supported by the 80331.
4011 ** 14:9 00H Reserved
4012 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME#
4013 ** generation from any power state.
4014 ** 7:2 000000 2 Reserved
4015 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state
4016 ** of a function and to set the function into a new power state. The definition of the values is:
4019 ** 10 2 - D2 (Unsupported)
4021 ** The 80331 supports only the D0 and D3 hot states.
4023 ***********************************************************************************
4025 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/
4027 ***********************************************************************************
4028 ** PCI-X Capability Identifier Register - PX_CAPID
4030 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
4031 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
4032 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
4033 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
4034 ** -----------------------------------------------------------------
4035 ** Bit Default Description
4036 ** 07:00 07H Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability
4037 ** Headers as being the PCI-X capability registers.
4038 ***********************************************************************************
4040 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/
4042 ***********************************************************************************
4043 ** PCI-X Next Item Pointer Register - PX_NXTP
4045 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
4046 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
4047 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
4049 ** However, this register may be written to B8H prior to host configuration to include the VPD
4050 ** capability located at off-set B8H.
4051 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may
4052 ** produce unpredictable system behavior.
4053 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be
4054 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
4055 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in
4056 ** this case (bit 1 of PCSR), as well. Please see Table 125, ¡§PCI Configuration and Status Register -
4057 ** PCSR¡¨ on page 253 for more details on the 80331 initialization modes.
4058 ** -----------------------------------------------------------------
4059 ** Bit Default Description
4060 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
4061 ** next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of
4062 ** extended capabilities in the 80331, the register is set to 00H.
4063 ** However, this field may be written prior to host configuration with B8H to extend the list to include the
4064 ** VPD extended capabilities header.
4065 ***********************************************************************************
4067 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/
4069 ***********************************************************************************
4070 ** PCI-X Command Register - PX_CMD
4072 ** This register controls various modes and features of ATU and Message Unit when operating in the
4074 ** -----------------------------------------------------------------
4075 ** Bit Default Description
4076 ** 15:7 000000000 2 Reserved.
4077 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
4078 ** the device is permitted to have outstanding at one time.
4079 ** Register Maximum Outstanding
4088 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
4089 ** initiating a Sequence with one of the burst memory read commands.
4090 ** Register Maximum Byte Count
4096 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes
4098 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
4099 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
4100 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
4101 ***********************************************************************************
4103 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/
4105 ***********************************************************************************
4106 ** PCI-X Status Register - PX_SR
4108 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message
4109 ** Unit when operating in the PCI-X mode.
4110 ** -----------------------------------------------------------------
4111 ** Bit Default Description
4112 ** 31:30 00 2 Reserved
4113 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
4114 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
4115 ** writes a 1 to this location.
4116 ** 0=no Split Completion error message received.
4117 ** 1=a Split Completion error message has been received.
4118 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
4119 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register:
4120 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
4121 ** 1 16 512 (Default)
4125 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
4126 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up
4128 ** 20 1 2 80331 is a complex device.
4129 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s
4130 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
4131 ** 0=no unexpected Split Completion has been received.
4132 ** 1=an unexpected Split Completion has been received.
4133 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the
4134 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
4135 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this
4137 ** 0=no Split Completion has been discarded.
4138 ** 1=a Split Completion has been discarded.
4139 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
4140 ** Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨
4141 ** 17 1 2 80331 is a 133 MHz capable device.
4142 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus,
4143 ** therefore this bit is always set.
4144 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0),
4145 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#).
4146 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled
4147 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
4148 ** 0=The bus is 32 bits wide.
4149 ** 1=The bus is 64 bits wide.
4150 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
4151 ** segment for the device containing this function. The function uses this number as part of its Requester
4152 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
4153 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0]
4154 ** of the attribute phase of the Configuration Write, regardless of which register in the function is
4155 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
4156 ** the following are true:
4157 ** 1. The transaction uses a Configuration Write command.
4158 ** 2. IDSEL is asserted during the address phase.
4159 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4160 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
4161 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
4162 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a
4163 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection
4164 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for
4165 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each
4166 ** time the function is addressed by a Configuration Write transaction, the device must update this register
4167 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which
4168 ** register in the function is addressed by the transaction. The function is addressed by a Configuration
4169 ** Write transaction when all of the following are true:
4170 ** 1. The transaction uses a Configuration Write command.
4171 ** 2. IDSEL is asserted during the address phase.
4172 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4173 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
4174 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this
4175 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
4176 ** configuration transaction to which this function responds. The function uses this number as part of its
4177 ** Requester ID and Completer ID.
4179 **************************************************************************
4181 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/
4184 **************************************************************************
4185 ** Inbound Read Transaction
4186 ** ========================================================================
4187 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
4188 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through
4189 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
4191 ** When operating in the conventional PCI mode, all inbound read transactions are processed as
4192 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
4193 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
4194 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for
4195 ** an inbound read transaction on the PCI bus is summarized in the following statements:
4196 ** ¡E The ATU claims the PCI read transaction when the PCI address is within the inbound
4197 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
4198 ** Address Register during DACs) and Inbound Limit Register.
4199 ** ¡E When operating in the conventional PCI mode, when the ITQ is currently holding transaction
4200 ** information from a previous delayed read, the current transaction information is compared to
4201 ** the previous transaction information (based on the setting of the DRC Alias bit in
4202 ** Section 3.10.39, ¡§ATU Configuration Register - ATUCR¡¨ on page 252). When there is a
4203 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
4204 ** match and the data is not available, a Retry is signaled with no other action taken. When there
4205 ** is not a match and when the ITQ has less than eight entries, capture the transaction
4206 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and
4207 ** when the ITQ is full, then signal a Retry with no other action taken.
4208 ** ¡X When an address parity error is detected, the address parity response defined in
4209 ** Section 3.7 is used.
4210 ** ¡E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
4211 ** the IRQ, it continues until one of the following is true:
4212 ** ¡X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
4214 ** ¡X An internal bus Target Abort was detected. In this case, the QWORD associated with the
4215 ** Target Abort is never entered into the IRQ, and therefore is never returned.
4216 ** ¡X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error.
4217 ** ¡X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
4218 ** the initiator on the last data word available.
4219 ** ¡E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
4220 ** command are latched into the available ITQ and a Split Response Termination is signalled to
4222 ** ¡E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
4223 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target
4224 ** before returning read data by generating the split completion transaction on the PCI-X bus.
4225 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the
4226 ** transfer by returning data in 1024 byte aligned chunks.
4227 ** ¡E When operating in the PCI-X mode, once a split completion transaction has started, it
4228 ** continues until one of the following is true:
4229 ** ¡X The requester (now the target) generates a Retry Termination, or a Disconnection at Next
4230 ** ADB (when the requester is a bridge)
4231 ** ¡X The byte count is satisfied.
4232 ** ¡X An internal bus Target Abort was detected. The ATU generates a Split Completion
4233 ** Message (message class=2h - completer error, and message index=81h - target abort) to
4234 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
4235 ** Refer to Section 3.7.1.
4236 ** ¡X An internal bus Master Abort was detected. The ATU generates a Split Completion
4237 ** Message (message class=2h - completer error, and message index=80h - Master abort) to
4238 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
4239 ** Refer to Section 3.7.1
4240 ** ¡E When operating in the conventional PCI mode, when the master inserts wait states on the PCI
4241 ** bus, the ATU PCI slave interface waits with no premature disconnects.
4242 ** ¡E When a data parity error occurs signified by PERR# asserted from the initiator, no action is
4243 ** taken by the target interface. Refer to Section 3.7.2.5.
4244 ** ¡E When operating in the conventional PCI mode, when the read on the internal bus is
4245 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is
4246 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
4247 ** target abort is used, when clear, a disconnect is used.
4248 ** ¡E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
4249 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
4250 ** a Split Completion Message (message class=2h - completer error, and message index=81h -
4251 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU
4252 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending
4253 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
4254 ** transaction is flushed. Refer to Section 3.7.1.
4255 ** ¡E When operating in the conventional PCI mode, when the transaction on the internal bus
4256 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the
4257 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1
4258 ** ¡E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
4259 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
4260 ** error, and message index=80h - internal bus master abort) to inform the requester about the
4261 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1.
4262 ** ¡E When operating in the PCI-X mode, when the Split Completion transaction completes with
4263 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that
4264 ** prevents it from accepting the completion it requested. In this case, since the Split Request
4265 ** addresses a location that has no read side effects, the completer must discard the Split
4266 ** Completion and take no further action.
4267 ** The data flow for an inbound read transaction on the internal bus is summarized in the following
4269 ** ¡E The ATU internal bus master interface requests the internal bus when a PCI address appears in
4270 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
4271 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
4272 ** always uses conventional PCI ordering rules.
4273 ** ¡E Once the internal bus is granted, the internal bus master interface drives the translated address
4274 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated.
4275 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded
4276 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
4277 ** master has been delivered the target abort).
4278 ** ¡E Once the translated address is on the bus and the transaction has been accepted, the internal
4279 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously
4280 ** received by the IRQ until one of the following is true:
4281 ** ¡X The full byte count requested by the ATU read request is received. The ATU internal bus
4282 ** initiator interface performs a initiator completion in this case.
4283 ** ¡X When operating in the conventional PCI mode, a Target Abort is received on the internal
4284 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
4286 ** ¡X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
4287 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
4288 ** Completion Message (message class=2h - completer error, and message index=81h -
4289 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The
4290 ** ITQ for this transaction is flushed.
4291 ** ¡X When operating in the conventional PCI mode, a single data phase disconnection is
4292 ** received from the internal bus target. When the data has not been received up to the next
4293 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
4294 ** When not, the bus returns to idle.
4295 ** ¡X When operating in the PCI-X mode, a single data phase disconnection is received from
4296 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
4297 ** obtain remaining data.
4298 ** ¡X When operating in the conventional PCI mode, a disconnection at Next ADB is received
4299 ** from the internal bus target. The bus returns to idle.
4300 ** ¡X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
4301 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
4303 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
4304 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read
4305 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue
4306 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the
4307 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
4308 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
4309 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
4310 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
4311 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the
4312 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
4313 ** commands did not match, only the address.
4314 **************************************************************************
4317 **************************************************************************
4318 ** Inbound Write Transaction
4319 **========================================================================
4320 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
4321 ** memory or a 80331 memory-mapped register.
4322 ** Data flow for an inbound write transaction on the PCI bus is summarized as:
4323 ** ¡E The ATU claims the PCI write transaction when the PCI address is within the inbound
4324 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
4325 ** Base Address Register during DACs) and Inbound Limit Register.
4326 ** ¡E When the IWADQ has at least one address entry available and the IWQ has at least one buffer
4327 ** available, the address is captured and the first data phase is accepted.
4328 ** ¡E The PCI interface continues to accept write data until one of the following is true:
4329 ** ¡X The initiator performs a disconnect.
4330 ** ¡X The transaction crosses a buffer boundary.
4331 ** ¡E When an address parity error is detected during the address phase of the transaction, the
4332 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address
4333 ** parity error response.
4334 ** ¡E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
4335 ** parity error mechanism described in Section 3.7.1 is used.
4336 ** ¡E When a data parity error is detected while accepting data, the slave interface sets the
4337 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6
4338 ** for details of the inbound write data parity error response.
4339 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
4340 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
4341 ** interface becomes aware of the inbound write. When there are additional write transactions ahead
4342 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been
4343 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
4344 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI
4345 ** interface, when operating in the PCI mode.
4346 ** In the PCI-X mode memory writes are always executed as immediate transactions, while
4347 ** configuration write transactions are processed as split transactions. The ATU generates a Split
4348 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
4349 ** 00h - Write Completion Message) once a configuration write is successfully executed.
4350 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions.
4351 ** The ATU handles such transactions as independent transactions.
4352 ** Data flow for the inbound write transaction on the internal bus is summarized as:
4353 ** ¡E The ATU internal bus master requests the internal bus when IWADQ has at least one entry
4354 ** with associated data in the IWQ.
4355 ** ¡E When the internal bus is granted, the internal bus master interface initiates the write
4356 ** transaction by driving the translated address onto the internal bus. For details on inbound
4357 ** address translation.
4358 ** ¡E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus.
4359 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI
4361 ** ¡E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
4362 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
4363 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
4364 ** from the IWQ to the internal bus when data is available and the internal bus interface retains
4365 ** internal bus ownership.
4366 ** ¡E The internal bus interface stops transferring data from the current transaction to the internal
4367 ** bus when one of the following conditions becomes true:
4368 ** ¡X The internal bus initiator interface loses bus ownership. The ATU internal initiator
4369 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB
4370 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
4371 ** complete the delivery of remaining data using the same sequence ID but with the
4372 ** modified starting address and byte count.
4373 ** ¡X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When
4374 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the
4375 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to
4376 ** complete the delivery of remaining data using the same sequence ID but with the
4377 ** modified starting address and byte count.
4378 ** ¡X A Single Data Phase Disconnect is signaled on the internal bus from the internal target.
4379 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle.
4380 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the
4381 ** bus to complete the delivery of remaining data using the same sequence ID but with the
4382 ** modified starting address and byte count.
4383 ** ¡X The data from the current transaction has completed (satisfaction of byte count). An
4384 ** initiator termination is performed and the bus returns to idle.
4385 ** ¡X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
4386 ** Data is flushed from the IWQ.
4387 *****************************************************************
4393 **************************************************************************
4394 ** Inbound Read Completions Data Parity Errors
4395 **========================================================================
4396 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4397 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
4398 ** completion transaction, the ATU attempts to complete the transaction normally and no further
4400 **************************************************************************
4404 **************************************************************************
4405 ** Inbound Configuration Write Completion Message Data Parity Errors
4406 **========================================================================
4407 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4408 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
4409 ** assertion during the split completion transaction, the ATU attempts to complete the transaction
4410 ** normally and no further action is taken.
4411 **************************************************************************
4415 **************************************************************************
4416 ** Inbound Read Request Data Parity Errors
4417 **===================== Immediate Data Transfer ==========================
4418 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes.
4419 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having
4420 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally
4421 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is
4422 ** required and no error bits are set.
4423 **=====================Split Response Termination=========================
4424 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4425 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may
4426 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no
4427 ** action is required and no error bits are set.
4428 **************************************************************************
4432 **************************************************************************
4433 ** Inbound Write Request Data Parity Errors
4434 **========================================================================
4435 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4436 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on
4437 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write
4438 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with
4439 ** the given constraints are taken by the ATU:
4440 ** ¡E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
4441 ** following the data phase in which the data parity error is detected on the bus. This is only
4442 ** done when the Parity Error Response bit in the ATUCMD is set.
4443 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4444 ** actions is taken:
4445 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4446 ** Detected Parity Error bit in the ATUISR. When set, no action.
4447 ***************************************************************************
4452 ***************************************************************************
4453 ** Inbound Configuration Write Request
4454 ** =====================================================================
4455 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4456 ** ===============================================
4457 ** Conventional PCI Mode
4458 ** ===============================================
4459 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the
4460 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a
4461 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following
4462 ** parts of the transactions:
4463 ** ¡E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
4464 ** address/command and data for delayed delivery to the internal configuration register.
4465 ** ¡E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
4466 ** of the operation back to the original master.
4467 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for
4468 ** inbound transactions during Delayed Write Request cycles with the given constraints:
4469 ** ¡E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
4470 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the
4471 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus.
4472 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
4473 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be
4474 ** forwarded to the internal bus. PERR# is not asserted.
4475 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4476 ** actions is taken:
4477 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4478 ** Detected Parity Error bit in the ATUISR. When set, no action.
4479 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI
4480 ** bus and the ATU returns the status from the internal bus, completing the transaction.
4481 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
4482 ** therefore does not agree with the status being returned from the internal bus (i.e. status being
4483 ** returned is normal completion) the ATU performs the following actions with the given constraints:
4484 ** ¡E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
4485 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in
4486 ** the IDWQ remains since the data of retried command did not match the data within the queue.
4487 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4488 ** actions is taken:
4489 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4490 ** Detected Parity Error bit in the ATUISR. When set, no action.
4491 ** ===================================================
4493 ** ===================================================
4494 ** Data parity errors occurring during configuration write operations received by the ATU may cause
4495 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
4496 ** occurs, the ATU accepts the write data and complete with a Split Response Termination.
4497 ** Specifically, the following actions with the given constraints are then taken by the ATU:
4498 ** ¡E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks
4499 ** cycles following the Split Response Termination in which the data parity error is detected on
4500 ** the bus. When the ATU asserts PERR#, additional actions is taken:
4501 ** ¡X A Split Write Data Parity Error message (with message class=2h - completer error and
4502 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
4503 ** that addresses the requester of the configuration write.
4504 ** ¡X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
4505 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no
4507 ** ¡X The Split Write Request is not enqueued and forwarded to the internal bus.
4508 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4509 ** actions is taken:
4510 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4511 ** Detected Parity Error bit in the ATUISR. When set, no action.
4513 ***************************************************************************
4517 ***************************************************************************
4518 ** Split Completion Messages
4519 ** =======================================================================
4520 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4521 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
4522 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
4523 ** ATU accepts the data and complete normally. Specifically, the following actions with the given
4524 ** constraints are taken by the ATU:
4525 ** ¡E PERR# is asserted three clocks cycles following the data phase in which the data parity error
4526 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD
4527 ** is set. When the ATU asserts PERR#, additional actions is taken:
4528 ** ¡X The Master Parity Error bit in the ATUSR is set.
4529 ** ¡X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
4530 ** PCI Master Parity Error bit in the ATUISR. When set, no action.
4531 ** ¡X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
4532 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
4533 ** When the ATU asserts SERR#, additional actions is taken:
4534 ** Set the SERR# Asserted bit in the ATUSR.
4535 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
4536 ** SERR# Asserted bit in the ATUISR. When set, no action.
4537 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
4538 ** SERR# Detected bit in the ATUISR. When clear, no action.
4539 ** ¡E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
4540 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set.
4541 ** When the ATU sets this bit, additional actions is taken:
4542 ** ¡X When the ATU Received Split Completion Error Message Interrupt Mask bit in the
4543 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR.
4544 ** When set, no action.
4545 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
4546 ** actions is taken:
4547 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
4548 ** Detected Parity Error bit in the ATUISR. When set, no action.
4549 ** ¡E The transaction associated with the Split Completion Message is discarded.
4550 ** ¡E When the discarded transaction was a read, a completion error message (with message
4551 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
4552 ** the internal bus of the 80331.
4553 *****************************************************************************
4558 ******************************************************************************************************
4559 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
4560 ** ==================================================================================================
4561 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331
4562 ** notifies the respective system when new data arrives.
4563 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
4564 ** window defined by:
4565 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
4566 ** 2.Inbound ATU Limit Register 0 (IALR0)
4567 ** All of the Messaging Unit errors are reported in the same manner as ATU errors.
4568 ** Error conditions and status can be found in :
4571 **====================================================================================================
4572 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt
4573 **----------------------------------------------------------------------------------------------------
4574 ** Message Registers 2 Inbound Optional Optional
4576 **----------------------------------------------------------------------------------------------------
4577 ** Doorbell Registers 1 Inbound Optional Optional
4579 **----------------------------------------------------------------------------------------------------
4580 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions
4581 **----------------------------------------------------------------------------------------------------
4582 ** Index Registers 1004 32-bit Memory Locations No Optional
4583 **====================================================================================================
4584 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
4585 **====================================================================================================
4590 **------------------------------------------------------------------------
4591 ** 0010H Inbound Message Register 0 ]
4592 ** 0014H Inbound Message Register 1 ]
4593 ** 0018H Outbound Message Register 0 ]
4594 ** 001CH Outbound Message Register 1 ] 4 Message Registers
4595 **------------------------------------------------------------------------
4596 ** 0020H Inbound Doorbell Register ]
4597 ** 0024H Inbound Interrupt Status Register ]
4598 ** 0028H Inbound Interrupt Mask Register ]
4599 ** 002CH Outbound Doorbell Register ]
4600 ** 0030H Outbound Interrupt Status Register ]
4601 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers
4602 **------------------------------------------------------------------------
4605 **------------------------------------------------------------------------
4606 ** 0040H Inbound Queue Port ]
4607 ** 0044H Outbound Queue Port ] 2 Queue Ports
4608 **------------------------------------------------------------------------
4611 **------------------------------------------------------------------------
4614 ** : Intel Xscale Microarchitecture Local Memory ]
4616 ** 0FFCH ] 1004 Index Registers
4617 *******************************************************************************
4620 *****************************************************************************
4621 ** Theory of MU Operation
4622 *****************************************************************************
4623 **--------------------
4624 ** inbound_msgaddr0:
4625 ** inbound_msgaddr1:
4626 ** outbound_msgaddr0:
4627 ** outbound_msgaddr1:
4628 ** . The MU has four independent messaging mechanisms.
4629 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers.
4630 ** Each holds a 32-bit value and generates an interrupt when written.
4631 **--------------------
4632 ** inbound_doorbell:
4633 ** outbound_doorbell:
4634 ** . The two Doorbell Registers support software interrupts.
4635 ** When a bit is set in a Doorbell Register, an interrupt is generated.
4636 **--------------------
4637 ** inbound_queueport:
4638 ** outbound_queueport:
4641 ** . The Circular Queues support a message passing scheme that uses 4 circular queues.
4642 ** The 4 circular queues are implemented in 80331 local memory.
4643 ** Two queues are used for inbound messages and two are used for outbound messages.
4644 ** Interrupts may be generated when the queue is written.
4645 **--------------------
4646 ** local_buffer 0x0050 ....0x0FFF
4647 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers.
4648 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
4649 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register.
4650 ** Each interrupt generated by the Messaging Unit can be masked.
4651 **--------------------
4652 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
4653 ** with the exception of Multi-DWORD reads to the index registers.
4654 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions
4655 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports.
4656 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response
4657 ** and the data is returned through split completion transaction(s).
4658 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch
4659 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus.
4660 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
4661 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
4662 **--------------------
4663 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers.
4664 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
4665 ** This PCI address window is used for PCI transactions that access the 80331 local memory.
4666 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register.
4667 **--------------------
4668 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
4669 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information.
4670 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
4671 ** The Messaging Unit reports all PCI errors in the ATU Status Register.
4672 **--------------------
4673 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
4674 ** The register interface, message registers, doorbell registers,
4675 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface.
4676 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads).
4677 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
4678 **************************************************************************
4681 **************************************************************************
4682 ** Message Registers
4683 ** ==============================
4684 ** . Messages can be sent and received by the 80331 through the use of the Message Registers.
4685 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
4686 ** . Inbound messages are sent by the host processor and received by the 80331.
4687 ** Outbound messages are sent by the 80331 and received by the host processor.
4688 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.
4689 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
4691 ** Inbound Messages:
4692 ** -----------------
4693 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core.
4694 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
4695 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register.
4696 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register.
4697 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software.
4698 ** The interrupt is cleared when the Intel XScale core writes a value of
4699 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
4700 ** ------------------------------------------------------------------------
4701 ** Inbound Message Register - IMRx
4703 ** . There are two Inbound Message Registers: IMR0 and IMR1.
4704 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
4705 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked
4706 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
4707 ** -----------------------------------------------------------------
4708 ** Bit Default Description
4709 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent.
4710 ** When written, an interrupt to the Intel XScale core may be generated.
4711 **************************************************************************
4713 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/
4714 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/
4716 **************************************************************************
4717 ** Outbound Message Register - OMRx
4718 ** --------------------------------
4719 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
4720 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
4721 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
4722 ** Interrupt Mask Register.
4724 ** Bit Default Description
4725 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an
4726 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register.
4727 **************************************************************************
4729 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
4730 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
4732 **************************************************************************
4733 ** Doorbell Registers
4734 ** ==============================
4735 ** There are two Doorbell Registers:
4736 ** Inbound Doorbell Register
4737 ** Outbound Doorbell Register
4738 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core.
4739 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
4740 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
4742 ** Inbound Doorbells:
4743 ** ------------------
4744 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core.
4745 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
4746 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated.
4747 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent.
4748 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4749 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
4750 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit.
4751 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt
4752 ** and not the values written to the Inbound Doorbell Register.
4753 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
4754 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set.
4755 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
4756 ** ------------------------------------------------------------------------
4757 ** Inbound Doorbell Register - IDR
4759 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core.
4760 ** . Bit 31 is reserved for generating an Error Doorbell interrupt.
4761 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core.
4762 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted,
4763 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
4764 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core.
4765 ** ------------------------------------------------------------------------
4766 ** Bit Default Description
4767 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
4768 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core.
4769 ** When all bits are clear, do not generate a Normal Interrupt.
4770 **************************************************************************
4772 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
4774 **************************************************************************
4775 ** Inbound Interrupt Status Register - IISR
4777 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status.
4778 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues.
4779 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core,
4780 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt;
4781 ** these two are routed to the Messaging Unit Error interrupt input.
4782 ** The generation of interrupts recorded in the Inbound Interrupt Status Register
4783 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register.
4784 ** Some of the bits in this register are Read Only.
4785 ** For those bits, the interrupt must be cleared through another register.
4787 ** Bit Default Description
4788 ** 31:07 0000000H 0 2 Reserved
4789 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4790 ** when an Index Register has been written after a PCI transaction.
4791 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4792 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4793 ** An Error interrupt is generated for this condition.
4794 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written.
4795 ** Once cleared, an interrupt does NOT be generated
4796 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
4797 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
4798 ** software must retain the information that the Inbound Post queue status is not empty.
4799 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
4800 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
4801 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
4802 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4803 ** Normal Interrupt bit in the Inbound Doorbell Register is set.
4804 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
4805 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
4806 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written.
4807 **************************************************************************
4809 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
4810 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40
4811 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20
4812 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10
4813 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08
4814 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04
4815 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02
4816 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01
4818 **************************************************************************
4819 ** Inbound Interrupt Mask Register - IIMR
4821 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit.
4822 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
4823 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register.
4824 ** They only affect the generation of the Intel XScale core interrupt.
4825 ** ------------------------------------------------------------------------
4826 ** Bit Default Description
4827 ** 31:07 000000H 0 2 Reserved
4828 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware
4829 ** when an Index Register has been written after a PCI transaction.
4830 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated
4831 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4832 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated
4833 ** by the MU hardware when the Inbound Post Queue has been written.
4834 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt
4835 ** when the Error Interrupt bit of the Inbound Doorbell Register is set.
4836 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated
4837 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
4838 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1
4839 ** Interrupt generated by a write to the Inbound Message 1 Register.
4840 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4841 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
4842 **************************************************************************
4844 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/
4845 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40
4846 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20
4847 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10
4848 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08
4849 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04
4850 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02
4851 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01
4853 **************************************************************************
4854 ** Outbound Doorbell Register - ODR
4856 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel
4857 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The
4858 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
4859 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
4860 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only
4861 ** be cleared by an external PCI agent.
4862 ** ----------------------------------------------------------------------
4863 ** Bit Default Description
4867 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output
4868 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4869 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled).
4870 ** When this bit is cleared, the P_INTC# interrupt output
4871 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4872 ** signal is deasserted.
4873 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output
4874 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4875 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled).
4876 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
4877 ** signal is deasserted.
4878 **************************************************************************
4880 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/
4882 **************************************************************************
4883 ** Outbound Interrupt Status Register - OISR
4885 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
4886 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular
4887 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
4888 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
4889 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another
4891 ** ----------------------------------------------------------------------
4892 ** Bit Default Description
4893 ** 31:05 000000H 000 2 Reserved
4894 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
4895 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared.
4896 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
4897 ** cleared when any prefetch data has been read from the Outbound Queue Port.
4898 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
4899 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
4900 ** Doorbell Register must all be clear.
4901 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
4902 ** written. Clearing this bit clears the interrupt.
4903 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
4904 ** written. Clearing this bit clears the interrupt.
4905 **************************************************************************
4907 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/
4908 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
4909 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
4910 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
4911 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
4912 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
4914 **************************************************************************
4915 ** Outbound Interrupt Mask Register - OIMR
4916 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
4917 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
4918 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
4919 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
4920 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They
4921 ** only affect the generation of the PCI interrupt.
4922 ** ----------------------------------------------------------------------
4923 ** Bit Default Description
4924 ** 31:05 000000H Reserved
4925 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28)
4926 ** in the Outbound Doorbell Register is set.
4927 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in
4928 ** the prefetch buffer is valid.
4929 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound
4930 ** Doorbell Register.
4931 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt
4932 ** generated by a write to the Outbound Message 1 Register.
4933 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt
4934 ** generated by a write to the Outbound Message 0 Register.
4935 **************************************************************************
4937 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/
4938 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
4939 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
4940 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
4941 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
4942 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
4943 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
4945 **************************************************************************
4947 **************************************************************************
4949 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
4950 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
4952 **************************************************************************
4954 ** ======================================================================
4955 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
4956 ** this case, inbound and outbound refer to the direction of the flow of posted messages.
4957 ** Inbound messages are either:
4958 ** ¡E posted messages by other processors for the Intel XScale core to process or
4959 ** ¡E free (or empty) messages that can be reused by other processors.
4960 ** Outbound messages are either:
4961 ** ¡E posted messages by the Intel XScale core for other processors to process or
4962 ** ¡E free (or empty) messages that can be reused by the Intel XScale core.
4963 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
4964 ** The four Circular Queues are used to pass messages in the following manner.
4965 ** . The two inbound queues are used to handle inbound messages
4966 ** and the two outbound queues are used to handle outbound messages.
4967 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages.
4968 ** The other inbound queue is designated the Post queue and it contains inbound posted messages.
4969 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue.
4971 ** =============================================================================================================
4972 ** Circular Queue Summary
4973 ** _____________________________________________________________________________________________________________
4974 ** | Queue Name | Purpose | Action on PCI Interface|
4975 ** |______________________|____________________________________________________________|_________________________|
4976 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written |
4977 ** | | waiting to be processed by the 80331 | |
4978 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read |
4979 ** | | available for use by other processors | |
4980 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read |
4981 ** | | that are being posted to the other processors | |
4982 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written |
4983 ** | | available for use by the 80331 | |
4984 ** |______________________|____________________________________________________________|_________________________|
4986 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
4987 ** queue and to receive free messages returning from the 80331.
4988 ** The host processor posts inbound messages,
4989 ** the Intel XScale core receives the posted message and when it is finished with the message,
4990 ** places it back on the inbound free queue for reuse by the host processor.
4992 ** The circular queues are accessed by external PCI agents through two port locations in the PCI
4994 ** Inbound Queue Port
4995 ** and Outbound Queue Port.
4996 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue.
4997 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
4998 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 )
4999 ** does not cause the MU hardware to increment the queue pointers.
5000 ** This is treated as when the PCI transaction did not occur.
5001 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
5002 ** ======================================================================================
5003 ** Overview of Circular Queue Operation
5004 ** ======================================================================================
5005 ** . The data storage for the circular queues must be provided by the 80331 local memory.
5006 ** . The base address of the circular queues is contained in the Queue Base Address Register.
5007 ** Each entry in the queue is a 32-bit data value.
5008 ** . Each read from or write to the queue may access only one queue entry.
5009 ** . Multi-DWORD accesses to the circular queues are not allowed.
5010 ** Sub-DWORD accesses are promoted to DWORD accesses.
5011 ** . Each circular queue has a head pointer and a tail pointer.
5012 ** The pointers are offsets from the Queue Base Address.
5013 ** . Writes to a queue occur at the head of the queue and reads occur from the tail.
5014 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
5015 ** Which unit maintains the pointer is determined by the writer of the queue.
5016 ** More details about the pointers are given in the queue descriptions below.
5017 ** The pointers are incremented after the queue access.
5018 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
5020 ** Messaging Unit...
5022 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
5023 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
5024 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
5025 ** . All four queues must be the same size and may be contiguous.
5026 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes.
5027 ** The Queue size is determined by the Queue Size field in the MU Configuration Register.
5028 ** . There is one base address for all four queues.
5029 ** It is stored in the Queue Base Address Register (QBAR).
5030 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field.
5031 ** here shows an example of how the circular queues should be set up based on the
5032 ** Intelligent I/O (I 2 O) Architecture Specification.
5033 ** Other ordering of the circular queues is possible.
5035 ** Queue Starting Address
5036 ** Inbound Free Queue QBAR
5037 ** Inbound Post Queue QBAR + Queue Size
5038 ** Outbound Post Queue QBAR + 2 * Queue Size
5039 ** Outbound Free Queue QBAR + 3 * Queue Size
5040 ** ===================================================================================
5041 ** Inbound Post Queue
5042 ** ------------------
5043 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
5044 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents.
5045 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
5046 ** For a PCI write transaction that accesses the Inbound Queue Port,
5047 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
5048 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
5049 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written.
5050 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
5051 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared.
5052 ** The interrupt can be masked by the Inbound Interrupt Mask Register.
5053 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee
5054 ** that the full condition is recognized by the core processor.
5055 ** In addition, to guarantee that the queue does not get overwritten,
5056 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
5057 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
5058 ** Only a new message posting the in the inbound queue generates a new interrupt.
5059 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
5060 ** software must retain the information that the Inbound Post queue status.
5061 ** From the time that the PCI write transaction is received until the data is written
5062 ** in local memory and the Inbound Post Head Pointer Register is incremented,
5063 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
5064 ** The Intel XScale core may read messages from the Inbound Post Queue
5065 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register.
5066 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register.
5067 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware),
5068 ** the hardware retries any PCI writes until a slot in the queue becomes available.
5069 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
5070 ** ===================================================================================
5071 ** Inbound Free Queue
5072 ** ------------------
5073 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
5074 ** This queue is read from the queue tail by external PCI agents.
5075 ** It is written to the queue head by the Intel XScale core.
5076 ** The tail pointer is maintained by the MU hardware.
5077 ** The head pointer is maintained by the Intel XScale core.
5078 ** For a PCI read transaction that accesses the Inbound Queue Port,
5079 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
5080 ** When the queue is not empty (head and tail pointers are not equal)
5081 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
5082 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware),
5083 ** the value of -1 (FFFF.FFFFH) is returned.
5084 ** When the queue was not empty and the MU succeeded in returning the data at the tail,
5085 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
5086 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue.
5087 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register.
5088 ** When the PCI read access occurs, the data is read directly from the prefetch register.
5089 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
5090 ** when the head and tail pointers are equal and the queue is empty.
5091 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty,
5092 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH
5093 ** and the Inbound Free Head Pointer Register is written.
5094 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
5095 ** A prefetch must appear atomic from the perspective of the external PCI agent.
5096 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
5097 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
5098 ** local memory location pointed to by the Inbound Free Head Pointer Register.
5099 ** The processor must then increment the Inbound Free Head Pointer Register.
5100 ** ==================================================================================
5101 ** Outbound Post Queue
5102 ** -------------------
5103 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale
5104 ** core for other processors to process. This queue is read from the queue tail by external PCI agents.
5105 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the
5106 ** MU hardware. The head pointer is maintained by the Intel XScale core.
5107 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
5108 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not
5109 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head
5110 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail
5111 ** pointers are equal and the head pointer was last updated by hardware), the value of -1
5112 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
5113 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
5115 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
5116 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
5117 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
5118 ** occurs, the data is read directly from the prefetch register.
5119 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
5120 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when
5121 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
5122 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
5123 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head
5124 ** Pointer Register when it adds messages to the queue.
5125 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
5126 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry
5127 ** until the prefetch is completed.
5128 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
5129 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
5130 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the
5131 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
5132 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
5133 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to
5134 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then
5135 ** increment the Outbound Post Head Pointer Register.
5136 ** ==================================================
5137 ** Outbound Free Queue
5138 ** -----------------------
5139 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel
5140 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is
5141 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
5142 ** XScale core. The head pointer is maintained by the MU hardware.
5143 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
5144 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the
5145 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
5146 ** Head Pointer Register.
5147 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
5148 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is
5149 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free
5150 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can
5151 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
5152 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
5154 ** From the time that a PCI write transaction is received until the data is written in local memory and
5155 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
5156 ** access the Outbound Free Queue Port is signalled a retry.
5157 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data
5158 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must
5159 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
5160 ** the hardware must retry any PCI writes until a slot in the queue becomes available.
5162 ** ==================================================================================
5163 ** Circular Queue Summary
5164 ** ----------------------
5165 ** ________________________________________________________________________________________________________________________________________________
5166 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by|
5167 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
5168 ** |Inbound Post | Inbound Queue | | | | |
5169 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale |
5170 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
5171 ** |Inbound Free | Inbound Queue | | | | |
5172 ** | Queue | Port | NO | NO | Intel XScale | MU hardware |
5173 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
5174 ** ==================================================================================
5175 ** Circular Queue Status Summary
5176 ** ----------------------
5177 ** ____________________________________________________________________________________________________
5178 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update |
5179 ** |_____________________|________________|_____________________|_______________________________________|
5180 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software |
5181 ** |_____________________|________________|_____________________|_______________________________________|
5182 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware |
5183 ** |_____________________|________________|_____________________|_______________________________________|
5184 **************************************************************************
5188 **************************************************************************
5190 ** ========================
5191 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core.
5192 ** These registers are for inbound messages only.
5193 ** The interrupt is recorded in the Inbound Interrupt Status Register.
5194 ** The storage for the Index Registers is allocated from the 80331 local memory.
5195 ** PCI write accesses to the Index Registers write the data to local memory.
5196 ** PCI read accesses to the Index Registers read the data from local memory.
5197 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H
5198 ** to Inbound ATU Translate Value Register + FFFH.
5199 ** . The address of the first write access is stored in the Index Address Register.
5200 ** This register is written during the earliest write access and provides a means to determine which Index Register was written.
5201 ** Once updated by the MU, the Index Address Register is not updated until the Index Register
5202 ** Interrupt bit in the Inbound Interrupt Status Register is cleared.
5203 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
5204 ** Writes by the Intel XScale core to the local memory used by the Index Registers
5205 ** does not cause an interrupt and does not update the Index Address Register.
5206 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
5207 **************************************************************************
5210 **************************************************************************
5211 ** Messaging Unit Internal Bus Memory Map
5212 ** =======================================
5213 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_
5214 ** FFFF E300H reserved |
5216 ** FFFF E30CH reserved |
5217 ** FFFF E310H Inbound Message Register 0 | Available through
5218 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window
5219 ** FFFF E318H Outbound Message Register 0 |
5220 ** FFFF E31CH Outbound Message Register 1 | or
5221 ** FFFF E320H Inbound Doorbell Register |
5222 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to
5223 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core
5224 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
5225 ** FFFF E330H Outbound Interrupt Status Register |
5226 ** FFFF E334H Outbound Interrupt Mask Register |
5227 ** ______________________________________________________________________|________________________________________
5228 ** FFFF E338H reserved |
5229 ** FFFF E33CH reserved |
5230 ** FFFF E340H reserved |
5231 ** FFFF E344H reserved |
5232 ** FFFF E348H reserved |
5233 ** FFFF E34CH reserved |
5234 ** FFFF E350H MU Configuration Register |
5235 ** FFFF E354H Queue Base Address Register |
5236 ** FFFF E358H reserved |
5237 ** FFFF E35CH reserved | must translate PCI address to
5238 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core
5239 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
5240 ** FFFF E368H Inbound Post Head pointer Register |
5241 ** FFFF E36CH Inbound Post Tail Pointer Register |
5242 ** FFFF E370H Outbound Free Head Pointer Register |
5243 ** FFFF E374H Outbound Free Tail Pointer Register |
5244 ** FFFF E378H Outbound Post Head pointer Register |
5245 ** FFFF E37CH Outbound Post Tail Pointer Register |
5246 ** FFFF E380H Index Address Register |
5247 ** FFFF E384H reserved |
5249 ** FFFF E3FCH reserved |
5250 ** ______________________________________________________________________|_______________________________________
5251 **************************************************************************
5254 **************************************************************************
5255 ** MU Configuration Register - MUCR FFFF.E350H
5257 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
5258 ** . The Circular Queue Enable bit enables or disables the Circular Queues.
5259 ** The Circular Queues are disabled at reset to allow the software to initialize the head
5260 ** and tail pointer registers before any PCI accesses to the Queue Ports.
5261 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
5262 ** ------------------------------------------------------------------------
5263 ** Bit Default Description
5264 ** 31:06 000000H 00 2 Reserved
5265 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue.
5266 ** All four queues are the same size.
5267 ** ¡E 00001 2 - 4K Entries (16 Kbytes)
5268 ** ¡E 00010 2 - 8K Entries (32 Kbytes)
5269 ** ¡E 00100 2 - 16K Entries (64 Kbytes)
5270 ** ¡E 01000 2 - 32K Entries (128 Kbytes)
5271 ** ¡E 10000 2 - 64K Entries (256 Kbytes)
5272 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular
5273 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores
5274 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when
5275 ** disabled. When set, the Circular Queues are fully enabled.
5276 **************************************************************************
5278 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350
5279 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020
5280 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010
5281 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008
5282 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004
5283 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002
5284 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/
5286 **************************************************************************
5287 ** Queue Base Address Register - QBAR
5289 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
5290 ** The base address is required to be located on a 1 Mbyte address boundary.
5291 ** . All Circular Queue head and tail pointers are based on the QBAR.
5292 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits.
5293 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
5295 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface
5296 ** ------------------------------------------------------------------------
5297 ** Bit Default Description
5298 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5299 ** 19:00 00000H Reserved
5300 **************************************************************************
5302 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354
5304 **************************************************************************
5305 ** Inbound Free Head Pointer Register - IFHPR
5307 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from
5308 ** the Queue Base Address of the head pointer for the Inbound Free Queue.
5309 ** The Head Pointer must be aligned on a DWORD address boundary.
5310 ** When read, the Queue Base Address is provided in the upper 12 bits of the register.
5311 ** Writes to the upper 12 bits of the register are ignored.
5312 ** This register is maintained by software.
5313 ** ------------------------------------------------------------------------
5314 ** Bit Default Description
5315 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5316 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue.
5317 ** 01:00 00 2 Reserved
5318 **************************************************************************
5320 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360
5322 **************************************************************************
5323 ** Inbound Free Tail Pointer Register - IFTPR
5325 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
5326 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a
5327 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5328 ** of the register. Writes to the upper 12 bits of the register are ignored.
5329 ** ------------------------------------------------------------------------
5330 ** Bit Default Description
5331 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5332 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue.
5333 ** 01:00 00 2 Reserved
5334 **************************************************************************
5336 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364
5338 **************************************************************************
5339 ** Inbound Post Head Pointer Register - IPHPR
5341 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
5342 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on
5343 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5344 ** of the register. Writes to the upper 12 bits of the register are ignored.
5345 ** ------------------------------------------------------------------------
5346 ** Bit Default Description
5347 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5348 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue.
5349 ** 01:00 00 2 Reserved
5350 **************************************************************************
5352 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368
5354 **************************************************************************
5355 ** Inbound Post Tail Pointer Register - IPTPR
5357 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
5358 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a
5359 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
5360 ** of the register. Writes to the upper 12 bits of the register are ignored.
5361 ** ------------------------------------------------------------------------
5362 ** Bit Default Description
5363 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
5364 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue.
5365 ** 01:00 00 2 Reserved
5366 **************************************************************************
5368 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C
5370 **************************************************************************
5371 ** Index Address Register - IAR
5373 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
5374 ** It is written by the MU when the Index Registers are written by a PCI agent.
5375 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.
5376 ** . The local memory address of the Index Register least recently accessed is computed
5377 ** by adding the Index Address Register to the Inbound ATU Translate Value Register.
5378 ** ------------------------------------------------------------------------
5379 ** Bit Default Description
5380 ** 31:12 000000H Reserved
5381 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH)
5382 ** 01:00 00 2 Reserved
5383 **************************************************************************
5385 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/
5387 **********************************************************************************************************
5388 ** RS-232 Interface for Areca Raid Controller
5389 ** The low level command interface is exclusive with VT100 terminal
5390 ** --------------------------------------------------------------------
5391 ** 1. Sequence of command execution
5392 ** --------------------------------------------------------------------
5393 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5394 ** (B) Command block : variable length of data including length, command code, data and checksum byte
5395 ** (C) Return data : variable length of data
5396 ** --------------------------------------------------------------------
5398 ** --------------------------------------------------------------------
5399 ** (A) 1st byte : command block length (low byte)
5400 ** (B) 2nd byte : command block length (high byte)
5401 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes
5402 ** (C) 3rd byte : command code
5403 ** (D) 4th and following bytes : variable length data bytes depends on command code
5404 ** (E) last byte : checksum byte (sum of 1st byte until last data byte)
5405 ** --------------------------------------------------------------------
5406 ** 3. Command code and associated data
5407 ** --------------------------------------------------------------------
5408 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management,
5409 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access.
5410 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command.
5413 ** GUI_SET_SERIAL=0x10,
5417 ** GUI_CHECK_PASSWORD,
5420 ** GUI_SET_ETHERNET_ADDR,
5424 ** GUI_GET_HW_MONITOR,
5426 ** // GUI_QUICK_CREATE=0x20, (function removed)
5427 ** GUI_GET_INFO_R=0x20,
5433 ** GUI_MUTE_BEEPER=0x30,
5434 ** GUI_BEEPER_SETTING,
5435 ** GUI_SET_PASSWORD,
5436 ** GUI_HOST_INTERFACE_MODE,
5437 ** GUI_REBUILD_PRIORITY,
5438 ** GUI_MAX_ATA_MODE,
5439 ** GUI_RESET_CONTROLLER,
5440 ** GUI_COM_PORT_SETTING,
5441 ** GUI_NO_OPERATION,
5444 ** GUI_CREATE_PASS_THROUGH=0x40,
5445 ** GUI_MODIFY_PASS_THROUGH,
5446 ** GUI_DELETE_PASS_THROUGH,
5447 ** GUI_IDENTIFY_DEVICE,
5449 ** GUI_CREATE_RAIDSET=0x50,
5450 ** GUI_DELETE_RAIDSET,
5451 ** GUI_EXPAND_RAIDSET,
5452 ** GUI_ACTIVATE_RAIDSET,
5453 ** GUI_CREATE_HOT_SPARE,
5454 ** GUI_DELETE_HOT_SPARE,
5456 ** GUI_CREATE_VOLUME=0x60,
5457 ** GUI_MODIFY_VOLUME,
5458 ** GUI_DELETE_VOLUME,
5459 ** GUI_START_CHECK_VOLUME,
5460 ** GUI_STOP_CHECK_VOLUME
5463 ** Command description :
5465 ** GUI_SET_SERIAL : Set the controller serial#
5466 ** byte 0,1 : length
5467 ** byte 2 : command code 0x10
5468 ** byte 3 : password length (should be 0x0f)
5469 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
5470 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
5471 ** GUI_SET_VENDOR : Set vendor string for the controller
5472 ** byte 0,1 : length
5473 ** byte 2 : command code 0x11
5474 ** byte 3 : password length (should be 0x08)
5475 ** byte 4-0x13 : should be "ArEcAvAr"
5476 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
5477 ** GUI_SET_MODEL : Set the model name of the controller
5478 ** byte 0,1 : length
5479 ** byte 2 : command code 0x12
5480 ** byte 3 : password length (should be 0x08)
5481 ** byte 4-0x13 : should be "ArEcAvAr"
5482 ** byte 0x14--0x1B : model string (must be 8 bytes)
5483 ** GUI_IDENTIFY : Identify device
5484 ** byte 0,1 : length
5485 ** byte 2 : command code 0x13
5486 ** return "Areca RAID Subsystem "
5487 ** GUI_CHECK_PASSWORD : Verify password
5488 ** byte 0,1 : length
5489 ** byte 2 : command code 0x14
5490 ** byte 3 : password length
5491 ** byte 4-0x?? : user password to be checked
5492 ** GUI_LOGOUT : Logout GUI (force password checking on next command)
5493 ** byte 0,1 : length
5494 ** byte 2 : command code 0x15
5495 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16)
5497 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address
5498 ** byte 0,1 : length
5499 ** byte 2 : command code 0x17
5500 ** byte 3 : password length (should be 0x08)
5501 ** byte 4-0x13 : should be "ArEcAvAr"
5502 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
5503 ** GUI_SET_LOGO : Set logo in HTTP
5504 ** byte 0,1 : length
5505 ** byte 2 : command code 0x18
5506 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
5507 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a
5508 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes)
5509 ** note .... page0 1st 2 byte must be actual length of the JPG file
5510 ** GUI_POLL_EVENT : Poll If Event Log Changed
5511 ** byte 0,1 : length
5512 ** byte 2 : command code 0x19
5513 ** GUI_GET_EVENT : Read Event
5514 ** byte 0,1 : length
5515 ** byte 2 : command code 0x1a
5516 ** byte 3 : Event Page (0:1st page/1/2/3:last page)
5517 ** GUI_GET_HW_MONITOR : Get HW monitor data
5518 ** byte 0,1 : length
5519 ** byte 2 : command code 0x1b
5520 ** byte 3 : # of FANs(example 2)
5521 ** byte 4 : # of Voltage sensor(example 3)
5522 ** byte 5 : # of temperature sensor(example 2)
5523 ** byte 6 : # of power
5524 ** byte 7/8 : Fan#0 (RPM)
5525 ** byte 9/10 : Fan#1
5526 ** byte 11/12 : Voltage#0 original value in *1000
5527 ** byte 13/14 : Voltage#0 value
5528 ** byte 15/16 : Voltage#1 org
5529 ** byte 17/18 : Voltage#1
5530 ** byte 19/20 : Voltage#2 org
5531 ** byte 21/22 : Voltage#2
5534 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1)
5535 ** byte 26 : UPS indicator
5536 ** GUI_QUICK_CREATE : Quick create raid/volume set
5537 ** byte 0,1 : length
5538 ** byte 2 : command code 0x20
5539 ** byte 3/4/5/6 : raw capacity
5540 ** byte 7 : raid level
5541 ** byte 8 : stripe size
5543 ** byte 10/11/12/13: device mask (the devices to create raid/volume)
5544 ** This function is removed, application like to implement quick create function
5545 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function.
5546 ** GUI_GET_INFO_R : Get Raid Set Information
5547 ** byte 0,1 : length
5548 ** byte 2 : command code 0x20
5549 ** byte 3 : raidset#
5551 ** typedef struct sGUI_RAIDSET
5553 ** BYTE grsRaidSetName[16];
5554 ** DWORD grsCapacity;
5555 ** DWORD grsCapacityX;
5556 ** DWORD grsFailMask;
5557 ** BYTE grsDevArray[32];
5558 ** BYTE grsMemberDevices;
5559 ** BYTE grsNewMemberDevices;
5560 ** BYTE grsRaidState;
5562 ** BYTE grsVolumeList[16];
5566 ** BYTE grsFreeSegments;
5567 ** DWORD grsRawStripes[8];
5569 ** DWORD grsRes5; // Total to 128 bytes
5570 ** DWORD grsRes6; // Total to 128 bytes
5571 ** } sGUI_RAIDSET, *pGUI_RAIDSET;
5572 ** GUI_GET_INFO_V : Get Volume Set Information
5573 ** byte 0,1 : length
5574 ** byte 2 : command code 0x21
5575 ** byte 3 : volumeset#
5577 ** typedef struct sGUI_VOLUMESET
5579 ** BYTE gvsVolumeName[16]; // 16
5580 ** DWORD gvsCapacity;
5581 ** DWORD gvsCapacityX;
5582 ** DWORD gvsFailMask;
5583 ** DWORD gvsStripeSize;
5584 ** DWORD gvsNewFailMask;
5585 ** DWORD gvsNewStripeSize;
5586 ** DWORD gvsVolumeStatus;
5587 ** DWORD gvsProgress; // 32
5588 ** sSCSI_ATTR gvsScsi;
5589 ** BYTE gvsMemberDisks;
5590 ** BYTE gvsRaidLevel; // 8
5592 ** BYTE gvsNewMemberDisks;
5593 ** BYTE gvsNewRaidLevel;
5594 ** BYTE gvsRaidSetNumber;
5595 ** BYTE gvsRes0; // 4
5596 ** BYTE gvsRes1[4]; // 64 bytes
5597 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET;
5599 ** GUI_GET_INFO_P : Get Physical Drive Information
5600 ** byte 0,1 : length
5601 ** byte 2 : command code 0x22
5602 ** byte 3 : drive # (from 0 to max-channels - 1)
5604 ** typedef struct sGUI_PHY_DRV
5606 ** BYTE gpdModelName[40];
5607 ** BYTE gpdSerialNumber[20];
5608 ** BYTE gpdFirmRev[8];
5609 ** DWORD gpdCapacity;
5610 ** DWORD gpdCapacityX; // Reserved for expansion
5611 ** BYTE gpdDeviceState;
5613 ** BYTE gpdCurrentUdmaMode;
5614 ** BYTE gpdUdmaMode;
5615 ** BYTE gpdDriveSelect;
5616 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set
5617 ** sSCSI_ATTR gpdScsi;
5618 ** BYTE gpdReserved[40]; // Total to 128 bytes
5619 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV;
5621 ** GUI_GET_INFO_S : Get System Information
5622 ** byte 0,1 : length
5623 ** byte 2 : command code 0x23
5625 ** typedef struct sCOM_ATTR
5627 ** BYTE comBaudRate;
5628 ** BYTE comDataBits;
5629 ** BYTE comStopBits;
5631 ** BYTE comFlowControl;
5632 ** } sCOM_ATTR, *pCOM_ATTR;
5634 ** typedef struct sSYSTEM_INFO
5636 ** BYTE gsiVendorName[40];
5637 ** BYTE gsiSerialNumber[16];
5638 ** BYTE gsiFirmVersion[16];
5639 ** BYTE gsiBootVersion[16];
5640 ** BYTE gsiMbVersion[16];
5641 ** BYTE gsiModelName[8];
5642 ** BYTE gsiLocalIp[4];
5643 ** BYTE gsiCurrentIp[4];
5644 ** DWORD gsiTimeTick;
5645 ** DWORD gsiCpuSpeed;
5649 ** DWORD gsiMemorySize;
5650 ** DWORD gsiMemorySpeed;
5652 ** BYTE gsiMacAddress[6];
5655 ** BYTE gsiChannelUsage;
5656 ** BYTE gsiMaxAtaMode;
5657 ** BYTE gsiSdramEcc; // 1:if ECC enabled
5658 ** BYTE gsiRebuildPriority;
5659 ** sCOM_ATTR gsiComA; // 5 bytes
5660 ** sCOM_ATTR gsiComB; // 5 bytes
5661 ** BYTE gsiIdeChannels;
5662 ** BYTE gsiScsiHostChannels;
5663 ** BYTE gsiIdeHostChannels;
5664 ** BYTE gsiMaxVolumeSet;
5665 ** BYTE gsiMaxRaidSet;
5666 ** BYTE gsiEtherPort; // 1:if ether net port supported
5667 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported
5669 ** } sSYSTEM_INFO, *pSYSTEM_INFO;
5671 ** GUI_CLEAR_EVENT : Clear System Event
5672 ** byte 0,1 : length
5673 ** byte 2 : command code 0x24
5675 ** GUI_MUTE_BEEPER : Mute current beeper
5676 ** byte 0,1 : length
5677 ** byte 2 : command code 0x30
5679 ** GUI_BEEPER_SETTING : Disable beeper
5680 ** byte 0,1 : length
5681 ** byte 2 : command code 0x31
5682 ** byte 3 : 0->disable, 1->enable
5684 ** GUI_SET_PASSWORD : Change password
5685 ** byte 0,1 : length
5686 ** byte 2 : command code 0x32
5687 ** byte 3 : pass word length ( must <= 15 )
5688 ** byte 4 : password (must be alpha-numerical)
5690 ** GUI_HOST_INTERFACE_MODE : Set host interface mode
5691 ** byte 0,1 : length
5692 ** byte 2 : command code 0x33
5693 ** byte 3 : 0->Independent, 1->cluster
5695 ** GUI_REBUILD_PRIORITY : Set rebuild priority
5696 ** byte 0,1 : length
5697 ** byte 2 : command code 0x34
5698 ** byte 3 : 0/1/2/3 (low->high)
5700 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used
5701 ** byte 0,1 : length
5702 ** byte 2 : command code 0x35
5703 ** byte 3 : 0/1/2/3 (133/100/66/33)
5705 ** GUI_RESET_CONTROLLER : Reset Controller
5706 ** byte 0,1 : length
5707 ** byte 2 : command code 0x36
5708 ** *Response with VT100 screen (discard it)
5710 ** GUI_COM_PORT_SETTING : COM port setting
5711 ** byte 0,1 : length
5712 ** byte 2 : command code 0x37
5713 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5714 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200)
5715 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit)
5716 ** byte 6 : stop bit (0:1, 1:2 stop bits)
5717 ** byte 7 : parity (0:none, 1:off, 2:even)
5718 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none)
5720 ** GUI_NO_OPERATION : No operation
5721 ** byte 0,1 : length
5722 ** byte 2 : command code 0x38
5724 ** GUI_DHCP_IP : Set DHCP option and local IP address
5725 ** byte 0,1 : length
5726 ** byte 2 : command code 0x39
5727 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled
5728 ** byte 4/5/6/7 : IP address
5730 ** GUI_CREATE_PASS_THROUGH : Create pass through disk
5731 ** byte 0,1 : length
5732 ** byte 2 : command code 0x40
5733 ** byte 3 : device #
5734 ** byte 4 : scsi channel (0/1)
5735 ** byte 5 : scsi id (0-->15)
5736 ** byte 6 : scsi lun (0-->7)
5737 ** byte 7 : tagged queue (1 : enabled)
5738 ** byte 8 : cache mode (1 : enabled)
5739 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5740 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5742 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk
5743 ** byte 0,1 : length
5744 ** byte 2 : command code 0x41
5745 ** byte 3 : device #
5746 ** byte 4 : scsi channel (0/1)
5747 ** byte 5 : scsi id (0-->15)
5748 ** byte 6 : scsi lun (0-->7)
5749 ** byte 7 : tagged queue (1 : enabled)
5750 ** byte 8 : cache mode (1 : enabled)
5751 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5752 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5754 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk
5755 ** byte 0,1 : length
5756 ** byte 2 : command code 0x42
5757 ** byte 3 : device# to be deleted
5759 ** GUI_IDENTIFY_DEVICE : Identify Device
5760 ** byte 0,1 : length
5761 ** byte 2 : command code 0x43
5762 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected)
5763 ** byte 4/5/6/7 : IDE device mask to be flashed
5764 ** note .... no response data available
5766 ** GUI_CREATE_RAIDSET : Create Raid Set
5767 ** byte 0,1 : length
5768 ** byte 2 : command code 0x50
5769 ** byte 3/4/5/6 : device mask
5770 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5772 ** GUI_DELETE_RAIDSET : Delete Raid Set
5773 ** byte 0,1 : length
5774 ** byte 2 : command code 0x51
5775 ** byte 3 : raidset#
5777 ** GUI_EXPAND_RAIDSET : Expand Raid Set
5778 ** byte 0,1 : length
5779 ** byte 2 : command code 0x52
5780 ** byte 3 : raidset#
5781 ** byte 4/5/6/7 : device mask for expansion
5782 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
5783 ** byte 11/12/13 : repeat for each volume in the raidset ....
5785 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set
5786 ** byte 0,1 : length
5787 ** byte 2 : command code 0x53
5788 ** byte 3 : raidset#
5790 ** GUI_CREATE_HOT_SPARE : Create hot spare disk
5791 ** byte 0,1 : length
5792 ** byte 2 : command code 0x54
5793 ** byte 3/4/5/6 : device mask for hot spare creation
5795 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk
5796 ** byte 0,1 : length
5797 ** byte 2 : command code 0x55
5798 ** byte 3/4/5/6 : device mask for hot spare deletion
5800 ** GUI_CREATE_VOLUME : Create volume set
5801 ** byte 0,1 : length
5802 ** byte 2 : command code 0x60
5803 ** byte 3 : raidset#
5804 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5805 ** byte 20-27 : volume capacity (blocks)
5806 ** byte 28 : raid level
5807 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5808 ** byte 30 : channel
5811 ** byte 33 : 1 enable tag
5812 ** byte 34 : 1 enable cache
5813 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5814 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5815 ** byte 36 : 1 to select quick init
5817 ** GUI_MODIFY_VOLUME : Modify volume Set
5818 ** byte 0,1 : length
5819 ** byte 2 : command code 0x61
5820 ** byte 3 : volumeset#
5821 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5822 ** byte 20-27 : new volume capacity (reserved)
5823 ** byte 28 : new raid level
5824 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5825 ** byte 30 : new channel
5827 ** byte 32 : new LUN
5828 ** byte 33 : 1 enable tag
5829 ** byte 34 : 1 enable cache
5830 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5831 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5833 ** GUI_DELETE_VOLUME : Delete volume set
5834 ** byte 0,1 : length
5835 ** byte 2 : command code 0x62
5836 ** byte 3 : volumeset#
5838 ** GUI_START_CHECK_VOLUME : Start volume consistency check
5839 ** byte 0,1 : length
5840 ** byte 2 : command code 0x63
5841 ** byte 3 : volumeset#
5843 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check
5844 ** byte 0,1 : length
5845 ** byte 2 : command code 0x64
5846 ** ---------------------------------------------------------------------
5848 ** ---------------------------------------------------------------------
5849 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5850 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte)
5851 ** (C) status or data :
5852 ** <1> If length == 1 ==> 1 byte status code
5853 ** #define GUI_OK 0x41
5854 ** #define GUI_RAIDSET_NOT_NORMAL 0x42
5855 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43
5856 ** #define GUI_NO_RAIDSET 0x44
5857 ** #define GUI_NO_VOLUMESET 0x45
5858 ** #define GUI_NO_PHYSICAL_DRIVE 0x46
5859 ** #define GUI_PARAMETER_ERROR 0x47
5860 ** #define GUI_UNSUPPORTED_COMMAND 0x48
5861 ** #define GUI_DISK_CONFIG_CHANGED 0x49
5862 ** #define GUI_INVALID_PASSWORD 0x4a
5863 ** #define GUI_NO_DISK_SPACE 0x4b
5864 ** #define GUI_CHECKSUM_ERROR 0x4c
5865 ** #define GUI_PASSWORD_REQUIRED 0x4d
5866 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code
5867 ** (E) Checksum : checksum of length and status or data byte
5868 **************************************************************************
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