2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
30 #define ASMC_MAXFANS 6
39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
40 struct sysctl_oid *sc_temp_tree;
41 struct sysctl_oid *sc_sms_tree;
42 struct sysctl_oid *sc_light_tree;
43 struct asmc_model *sc_model;
46 struct resource *sc_ioport;
47 struct resource *sc_irq;
50 struct taskqueue *sc_sms_tq;
51 struct task sc_sms_task;
52 uint8_t sc_sms_intr_works;
58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
59 #define ASMC_DATAPORT_WRITE(sc, val) \
60 bus_write_1(sc->sc_ioport, 0x00, val)
61 #define ASMC_STATUS_MASK 0x0f
66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
67 #define ASMC_CMDPORT_WRITE(sc, val) \
68 bus_write_1(sc->sc_ioport, 0x04, val)
69 #define ASMC_CMDREAD 0x10
70 #define ASMC_CMDWRITE 0x11
75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
82 * Fan control via SMC.
84 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
85 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
86 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
87 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
88 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
89 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
90 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
91 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
94 * Sudden Motion Sensor (SMS).
96 #define ASMC_SMS_INIT1 0xe0
97 #define ASMC_SMS_INIT2 0xf8
98 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
99 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
100 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
101 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
102 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
103 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
104 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
105 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
106 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
107 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
108 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
109 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
112 * Keyboard backlight.
114 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
115 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
116 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
121 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
126 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
131 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
132 * fourth the Mac Pro 8-core and finally the MacBook Air.
135 /* maximum array size for temperatures including the last NULL */
136 #define ASMC_TEMP_MAX 80
137 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
139 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
140 "northbridge2", "heatsink1", \
141 "heatsink2", "memory", }
142 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
143 "Northbridge Point 1", \
144 "Northbridge Point 2", "Heatsink 1", \
145 "Heatsink 2", "Memory Bank A", }
147 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
148 "TG0H", "TG0P", "TG0T", NULL }
150 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
151 "heatsink2", "memory", "graphics", \
152 "graphicssink", "unknown", }
154 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
155 "Heatsink 1", "Heatsink 2", \
156 "Memory Controller", \
157 "Graphics Chip", "Graphics Heatsink", \
160 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
161 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
162 "TTF0", "TW0P", NULL }
164 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
165 "heatsink3", "memory", "graphicssink", \
166 "graphics", "cpu", "cpu2", "unknown1", \
167 "unknown2", "wireless", }
169 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
170 "Main Heatsink 1", "Main Heatsink 2", \
172 "Memory Controller", \
173 "Graphics Chip Heatsink", \
174 "Graphics Chip Diode", \
175 "CPU Temperature Diode", "CPU Point 2", \
176 "Unknown", "Unknown", \
179 #define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
180 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
181 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
182 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
183 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
184 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
186 #define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
187 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
188 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
189 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
190 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
191 "Th2H", "memory", "Ts0P", "Ts0S" }
193 #define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
194 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
195 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
196 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
197 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
198 "Th2H", "Tm0P", "Ts0P", "Ts0S" }
200 #define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
201 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
202 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
203 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
204 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
205 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
206 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
207 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
210 #define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
211 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
212 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
213 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
214 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
215 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
216 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
217 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
220 #define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
221 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
222 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
223 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
224 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
225 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
226 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
227 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
230 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
231 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
232 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
233 "Northbridge Point 2" }
235 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
240 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
241 "cpu0_proximity", "hdd_bay", \
243 "northbridge_proximity", \
246 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
247 "CPU0 Heatsink Temperature", \
248 "CPU0 Proximity Temperature", \
249 "HDD Bay Temperature", \
250 "Northbridge Die Core Temperature", \
251 "Northbridge Proximity Temperature", \
252 "Wireless Module Temperature", }
254 #define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
255 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
256 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
257 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
258 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
259 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
260 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
263 #define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
264 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
265 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
266 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
267 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
268 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
269 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
271 #define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
272 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
273 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
274 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
275 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
276 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
277 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
279 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
280 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
281 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
282 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
283 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
284 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
285 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
286 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
287 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
288 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
289 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
290 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
291 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
292 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
293 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
296 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
297 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
298 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
299 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
300 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
301 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
302 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
303 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
304 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
305 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
306 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
307 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
308 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
309 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
310 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
312 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
313 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
314 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
315 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
316 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
317 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
318 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
319 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
320 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
321 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
322 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
323 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
324 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
325 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
326 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
328 #define ASMC_MBA_TEMPS { "TB0T", NULL }
329 #define ASMC_MBA_TEMPNAMES { "enclosure" }
330 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
332 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
333 "TC0D", "TC0E", "TC0P", NULL }
335 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
336 "TC0D", "TC0E", "TC0P" }
338 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
339 "TC0D", "TC0E", "TC0P" }