sys/dev/asmc/asmcvar.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  25  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  * POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  *
  30  */
  31
  32 #define ASMC_MAXFANS    6
  33
  34 struct asmc_softc {
  35         device_t                sc_dev;
  36         struct mtx              sc_mtx;
  37         int                     sc_nfan;
  38         int16_t                 sms_rest_x;
  39         int16_t                 sms_rest_y;
  40         int16_t                 sms_rest_z;
  41         struct sysctl_oid       *sc_fan_tree[ASMC_MAXFANS+1];
  42         struct sysctl_oid       *sc_temp_tree;
  43         struct sysctl_oid       *sc_sms_tree;
  44         struct sysctl_oid       *sc_light_tree;
  45         struct asmc_model       *sc_model;
  46         int                     sc_rid_port;
  47         int                     sc_rid_irq;
  48         struct resource         *sc_ioport;
  49         struct resource         *sc_irq;
  50         void                    *sc_cookie;
  51         int                     sc_sms_intrtype;
  52         struct taskqueue        *sc_sms_tq;
  53         struct task             sc_sms_task;
  54         uint8_t                 sc_sms_intr_works;
  55 };
  56
  57 /*
  58  * Data port.
  59  */
  60 #define ASMC_DATAPORT_READ(sc)  bus_read_1(sc->sc_ioport, 0x00)
  61 #define ASMC_DATAPORT_WRITE(sc, val) \
  62         bus_write_1(sc->sc_ioport, 0x00, val)
  63 #define ASMC_STATUS_MASK        0x0f
  64
  65 /*
  66  * Command port.
  67  */
  68 #define ASMC_CMDPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x04)
  69 #define ASMC_CMDPORT_WRITE(sc, val) \
  70         bus_write_1(sc->sc_ioport, 0x04, val)
  71 #define ASMC_CMDREAD            0x10
  72 #define ASMC_CMDWRITE           0x11
  73
  74 /*
  75  * Interrupt port.
  76  */
  77 #define ASMC_INTPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x1f)
  78
  79
  80 /* Number of keys */
  81 #define ASMC_NKEYS              "#KEY"  /* RO; 4 bytes */
  82
  83 /*
  84  * Fan control via SMC.
  85  */
  86 #define ASMC_KEY_FANCOUNT       "FNum"  /* RO; 1 byte */
  87 #define ASMC_KEY_FANMANUAL      "FS! "  /* RW; 2 bytes */
  88 #define ASMC_KEY_FANID          "F%dID" /* RO; 16 bytes */
  89 #define ASMC_KEY_FANSPEED       "F%dAc" /* RO; 2 bytes */
  90 #define ASMC_KEY_FANMINSPEED    "F%dMn" /* RO; 2 bytes */
  91 #define ASMC_KEY_FANMAXSPEED    "F%dMx" /* RO; 2 bytes */
  92 #define ASMC_KEY_FANSAFESPEED   "F%dSf" /* RO; 2 bytes */
  93 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
  94
  95 /*
  96  * Sudden Motion Sensor (SMS).
  97  */
  98 #define ASMC_SMS_INIT1          0xe0
  99 #define ASMC_SMS_INIT2          0xf8
 100 #define ASMC_KEY_SMS            "MOCN"  /* RW; 2 bytes */
 101 #define ASMC_KEY_SMS_X          "MO_X"  /* RO; 2 bytes */
 102 #define ASMC_KEY_SMS_Y          "MO_Y"  /* RO; 2 bytes */
 103 #define ASMC_KEY_SMS_Z          "MO_Z"  /* RO; 2 bytes */
 104 #define ASMC_KEY_SMS_LOW        "MOLT"  /* RW; 2 bytes */
 105 #define ASMC_KEY_SMS_HIGH       "MOHT"  /* RW; 2 bytes */
 106 #define ASMC_KEY_SMS_LOW_INT    "MOLD"  /* RW; 1 byte */
 107 #define ASMC_KEY_SMS_HIGH_INT   "MOHD"  /* RW; 1 byte */
 108 #define ASMC_KEY_SMS_FLAG       "MSDW"  /* RW; 1 byte */
 109 #define ASMC_SMS_INTFF          0x60    /* Free fall Interrupt */
 110 #define ASMC_SMS_INTHA          0x6f    /* High Acceleration Interrupt */
 111 #define ASMC_SMS_INTSH          0x80    /* Shock Interrupt */
 112
 113 /*
 114  * Keyboard backlight.
 115  */
 116 #define ASMC_KEY_LIGHTLEFT      "ALV0"  /* RO; 6 bytes */
 117 #define ASMC_KEY_LIGHTRIGHT     "ALV1"  /* RO; 6 bytes */
 118 #define ASMC_KEY_LIGHTVALUE     "LKSB"  /* WO; 2 bytes */
 119
 120 /*
 121  * Clamshell.
 122  */
 123 #define ASMC_KEY_CLAMSHELL      "MSLD"  /* RO; 1 byte */
 124
 125 /*
 126  * Interrupt keys.
 127  */
 128 #define ASMC_KEY_INTOK          "NTOK"  /* WO; 1 byte */
 129
 130 /*
 131  * Temperatures.
 132  *
 133  * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
 134  * fourth the Mac Pro 8-core and finally the MacBook Air.
 135  *
 136  */
 137 /* maximum array size for temperatures including the last NULL */
 138 #define ASMC_TEMP_MAX           80
 139 #define ASMC_MB_TEMPS           { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
 140                                   "TM0P", NULL }
 141 #define ASMC_MB_TEMPNAMES       { "enclosure", "northbridge1", \
 142                                   "northbridge2", "heatsink1", \
 143                                   "heatsink2", "memory", }
 144 #define ASMC_MB_TEMPDESCS       { "Enclosure Bottomside", \
 145                                   "Northbridge Point 1", \
 146                                   "Northbridge Point 2", "Heatsink 1", \
 147                                   "Heatsink 2", "Memory Bank A", }
 148
 149 #define ASMC_MB31_TEMPS         { "TB0T", "TN0P",  "Th0H", "Th1H", \
 150                                   "TM0P", NULL }
 151
 152 #define ASMC_MB31_TEMPNAMES     { "enclosure", "northbridge1", \
 153                                   "heatsink1", "heatsink2", \
 154                                   "memory", }
 155
 156 #define ASMC_MB31_TEMPDESCS     { "Enclosure Bottomside", \
 157                                   "Northbridge Point 1", \
 158                                   "Heatsink 1","Heatsink 2" \
 159                                   "Memory Bank A", }
 160
 161 #define ASMC_MBP_TEMPS          { "TB0T", "Th0H", "Th1H", "Tm0P",       \
 162                                   "TG0H", "TG0P", "TG0T", NULL }
 163
 164 #define ASMC_MBP_TEMPNAMES      { "enclosure", "heatsink1", \
 165                                   "heatsink2", "memory", "graphics", \
 166                                   "graphicssink", "unknown", }
 167
 168 #define ASMC_MBP_TEMPDESCS      { "Enclosure Bottomside", \
 169                                   "Heatsink 1", "Heatsink 2", \
 170                                   "Memory Controller", \
 171                                   "Graphics Chip", "Graphics Heatsink", \
 172                                   "Unknown", }
 173
 174 #define ASMC_MBP4_TEMPS         { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
 175                                   "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
 176                                   "TTF0", "TW0P", NULL }
 177
 178 #define ASMC_MBP4_TEMPNAMES     { "enclosure", "heatsink1", "heatsink2", \
 179                                   "heatsink3", "memory", "graphicssink", \
 180                                   "graphics", "cpu", "cpu2", "unknown1", \
 181                                   "unknown2", "wireless", }
 182
 183 #define ASMC_MBP4_TEMPDESCS     { "Enclosure Bottomside", \
 184                                   "Main Heatsink 1", "Main Heatsink 2", \
 185                                   "Main Heatsink 3", \
 186                                   "Memory Controller", \
 187                                   "Graphics Chip Heatsink", \
 188                                   "Graphics Chip Diode", \
 189                                   "CPU Temperature Diode", "CPU Point 2", \
 190                                   "Unknown", "Unknown", \
 191                                   "Wireless Module", }
 192
 193 #define ASMC_MBP5_TEMPS         { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \
 194                                   "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \
 195                                   "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \
 196                                   "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \
 197                                   NULL }
 198
 199 #define ASMC_MBP5_TEMPNAMES     { "enclosure_bottom_0", "enclosure_bottom_1", \
 200                                   "enclosure_bottom_2", "enclosure_bottom_3", \
 201                                   "cpu_diode", "cpu", \
 202                                   "cpu_pin", "gpu_diode", \
 203                                   "gpu", "gpu_heatsink", \
 204                                   "gpu_pin", "gpu_transistor", \
 205                                   "gpu_2_heatsink", "northbridge_diode", \
 206                                   "northbridge_pin", "unknown", \
 207                                   "heatsink_2", "memory_controller", \
 208                                   "pci_express_slot_pin", "pci_express_slot_unk" }
 209
 210 #define ASMC_MBP5_TEMPDESCS     { "Enclosure Bottom 0", "Enclosure Bottom 1", \
 211                                   "Enclosure Bottom 2", "Enclosure Bottom 3", \
 212                                   "CPU Diode", "CPU ???", \
 213                                   "CPU Pin", "GPU Diode", \
 214                                   "GPU ???", "GPU Heatsink", \
 215                                   "GPU Pin", "GPU Transistor", \
 216                                   "GPU 2 Heatsink", "Northbridge Diode", \
 217                                   "Northbridge Pin", "Unknown", \
 218                                   "Heatsink 2", "Memory Controller", \
 219                                   "PCI Express Slot Pin", "PCI Express Slot (unk)" }
 220
 221 #define ASMC_MBP8_TEMPS         { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
 222                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 223                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 224                                   "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
 225                                   "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
 226                                   "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
 227
 228 #define ASMC_MBP8_TEMPNAMES     { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
 229                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 230                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 231                                   "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
 232                                   "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
 233                                   "Th2H", "memory", "Ts0P", "Ts0S" }
 234
 235 #define ASMC_MBP8_TEMPDESCS     { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
 236                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 237                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 238                                   "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
 239                                   "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
 240                                   "Th2H", "Tm0P", "Ts0P", "Ts0S" }
 241
 242 #define ASMC_MBP112_TEMPS       { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 243                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 244                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 245                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 246                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 247                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 248                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 249                                   "Ts1S", NULL }
 250
 251 #define ASMC_MBP112_TEMPNAMES   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 252                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 253                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 254                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 255                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 256                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 257                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 258                                   "Ts1S" }
 259
 260 #define ASMC_MBP112_TEMPDESCS   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 261                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 262                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 263                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 264                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 265                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 266                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 267                                   "Ts1S" }
 268
 269 #define ASMC_MBP113_TEMPS       { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E",       \
 270                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 271                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 272                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 273                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 274                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 275                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 276                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 277                                   "Ts1S", NULL }
 278
 279 #define ASMC_MBP113_TEMPNAMES   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 280                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 281                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 282                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 283                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 284                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 285                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 286                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 287                                   "Ts1S" }
 288
 289 #define ASMC_MBP113_TEMPDESCS   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 290                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 291                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 292                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 293                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 294                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 295                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 296                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 297                                   "Ts1S" }
 298
 299
 300 #define ASMC_MM_TEMPS           { "TN0P", "TN1P", NULL }
 301 #define ASMC_MM_TEMPNAMES       { "northbridge1", "northbridge2" }
 302 #define ASMC_MM_TEMPDESCS       { "Northbridge Point 1", \
 303                                   "Northbridge Point 2" }
 304
 305 #define ASMC_MM31_TEMPS         { "TC0D", "TC0H", \
 306                                   "TC0P", "TH0P", \
 307                                   "TN0D", "TN0P", \
 308                                   "TW0P", NULL }
 309
 310 #define ASMC_MM31_TEMPNAMES     { "cpu0_die", "cpu0_heatsink", \
 311                                   "cpu0_proximity", "hdd_bay", \
 312                                   "northbridge_die", \
 313                                   "northbridge_proximity", \
 314                                   "wireless_proximity", }
 315
 316 #define ASMC_MM31_TEMPDESCS     { "CPU0 Die Core Temperature", \
 317                                   "CPU0 Heatsink Temperature", \
 318                                   "CPU0 Proximity Temperature", \
 319                                   "HDD Bay Temperature", \
 320                                   "Northbridge Die Core Temperature", \
 321                                   "Northbridge Proximity Temperature", \
 322                                   "Wireless Module Proximity Temperature", }
 323
 324 #define ASMC_MP_TEMPS           { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 325                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 326                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 327                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 328                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 329                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 330                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
 331                                   NULL }
 332
 333 #define ASMC_MP_TEMPNAMES       { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 334                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 335                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 336                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 337                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 338                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 339                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
 340
 341 #define ASMC_MP_TEMPDESCS       { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 342                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 343                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 344                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 345                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 346                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 347                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
 348
 349 #define ASMC_MP5_TEMPS          { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
 350                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 351                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 352                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 353                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 354                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 355                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 356                                   "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
 357                                   "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
 358                                   "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
 359                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 360                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 361                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 362                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 363                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
 364                                   NULL }
 365
 366 #define ASMC_MP5_TEMPNAMES      { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
 367                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 368                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 369                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 370                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 371                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 372                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 373                                   "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
 374                                   "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
 375                                   "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
 376                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 377                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 378                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 379                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 380                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
 381
 382 #define ASMC_MP5_TEMPDESCS      { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
 383                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 384                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 385                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 386                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 387                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 388                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 389                                   "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
 390                                   "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
 391                                   "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
 392                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 393                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 394                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 395                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 396                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
 397
 398 #define ASMC_MBA_TEMPS          { "TB0T", NULL }
 399 #define ASMC_MBA_TEMPNAMES      { "enclosure" }
 400 #define ASMC_MBA_TEMPDESCS      { "Enclosure Bottom" }
 401
 402 #define ASMC_MBA3_TEMPS         { "TB0T", "TB1T", "TB2T", \
 403                                   "TC0D", "TC0E", "TC0P", NULL }
 404
 405 #define ASMC_MBA3_TEMPNAMES     { "enclosure", "TB1T", "TB2T", \
 406                                   "TC0D", "TC0E", "TC0P" }
 407
 408 #define ASMC_MBA3_TEMPDESCS     { "Enclosure Bottom", "TB1T", "TB2T", \
 409                                   "TC0D", "TC0E", "TC0P" }
 410
 411 #define ASMC_MBA5_TEMPS         { "TB0T", "TB1T", "TB2T", "TC0C", \
 412                                   "TC0D", "TC0E", "TC0F", "TC0P", \
 413                                   "TC1C", "TC2C", "TCGC", "TCSA", \
 414                                   "TCXC", "THSP", "TM0P", "TPCD", \
 415                                   "Ta0P", "Th1H", "Tm0P", "Tm1P", \
 416                                   "Ts0P", "Ts0S", NULL }
 417
 418 #define ASMC_MBA5_TEMPNAMES     { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
 419                                   "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
 420                                   "cpucore1", "cpucore2", "cpupeci", "pecisa", \
 421                                   "TCXC", "THSP", "memorybank", "pchdie", \
 422                                   "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
 423                                   "palmrest", "memoryproximity" }
 424
 425 #define ASMC_MBA5_TEMPDESCS     { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
 426                                   "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
 427                                   "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
 428                                   "TCXC", "THSP", "Memory Bank A", "PCH Die", \
 429                                   "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
 430                                   "Palm Rest", "Memory Proximity" }