2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
32 #define ASMC_MAXFANS 6
41 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
42 struct sysctl_oid *sc_temp_tree;
43 struct sysctl_oid *sc_sms_tree;
44 struct sysctl_oid *sc_light_tree;
45 struct asmc_model *sc_model;
48 struct resource *sc_ioport;
49 struct resource *sc_irq;
52 struct taskqueue *sc_sms_tq;
53 struct task sc_sms_task;
54 uint8_t sc_sms_intr_works;
60 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
61 #define ASMC_DATAPORT_WRITE(sc, val) \
62 bus_write_1(sc->sc_ioport, 0x00, val)
63 #define ASMC_STATUS_MASK 0x0f
68 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
69 #define ASMC_CMDPORT_WRITE(sc, val) \
70 bus_write_1(sc->sc_ioport, 0x04, val)
71 #define ASMC_CMDREAD 0x10
72 #define ASMC_CMDWRITE 0x11
77 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
81 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
84 * Fan control via SMC.
86 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
87 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
88 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
89 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
90 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
91 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
92 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
93 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
96 * Sudden Motion Sensor (SMS).
98 #define ASMC_SMS_INIT1 0xe0
99 #define ASMC_SMS_INIT2 0xf8
100 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
101 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
102 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
103 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
104 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
105 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
106 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
107 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
108 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
109 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
110 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
111 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
114 * Keyboard backlight.
116 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
117 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
118 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
123 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
128 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
133 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
134 * fourth the Mac Pro 8-core and finally the MacBook Air.
137 /* maximum array size for temperatures including the last NULL */
138 #define ASMC_TEMP_MAX 80
139 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
141 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
142 "northbridge2", "heatsink1", \
143 "heatsink2", "memory", }
144 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
145 "Northbridge Point 1", \
146 "Northbridge Point 2", "Heatsink 1", \
147 "Heatsink 2", "Memory Bank A", }
149 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \
152 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \
153 "heatsink1", "heatsink2", \
156 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \
157 "Northbridge Point 1", \
158 "Heatsink 1","Heatsink 2" \
161 #define ASMC_MB71_TEMPS { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \
162 "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \
163 "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \
164 "Ts0P", "Ts0S", NULL }
166 #define ASMC_MB71_TEMPNAMES { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \
167 "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \
168 "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \
169 "palm_rest", "memory_proximity", }
171 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \
172 "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \
173 "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \
174 "Palm Rest", "Memory Proximity", }
176 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
177 "TG0H", "TG0P", "TG0T", NULL }
179 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
180 "heatsink2", "memory", "graphics", \
181 "graphicssink", "unknown", }
183 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
184 "Heatsink 1", "Heatsink 2", \
185 "Memory Controller", \
186 "Graphics Chip", "Graphics Heatsink", \
189 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
190 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
191 "TTF0", "TW0P", NULL }
193 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
194 "heatsink3", "memory", "graphicssink", \
195 "graphics", "cpu", "cpu2", "unknown1", \
196 "unknown2", "wireless", }
198 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
199 "Main Heatsink 1", "Main Heatsink 2", \
201 "Memory Controller", \
202 "Graphics Chip Heatsink", \
203 "Graphics Chip Diode", \
204 "CPU Temperature Diode", "CPU Point 2", \
205 "Unknown", "Unknown", \
208 #define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \
209 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \
210 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \
211 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \
214 #define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \
215 "enclosure_bottom_2", "enclosure_bottom_3", \
216 "cpu_diode", "cpu", \
217 "cpu_pin", "gpu_diode", \
218 "gpu", "gpu_heatsink", \
219 "gpu_pin", "gpu_transistor", \
220 "gpu_2_heatsink", "northbridge_diode", \
221 "northbridge_pin", "unknown", \
222 "heatsink_2", "memory_controller", \
223 "pci_express_slot_pin", "pci_express_slot_unk" }
225 #define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \
226 "Enclosure Bottom 2", "Enclosure Bottom 3", \
227 "CPU Diode", "CPU ???", \
228 "CPU Pin", "GPU Diode", \
229 "GPU ???", "GPU Heatsink", \
230 "GPU Pin", "GPU Transistor", \
231 "GPU 2 Heatsink", "Northbridge Diode", \
232 "Northbridge Pin", "Unknown", \
233 "Heatsink 2", "Memory Controller", \
234 "PCI Express Slot Pin", "PCI Express Slot (unk)" }
236 #define ASMC_MBP81_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
237 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
238 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
239 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
242 #define ASMC_MBP81_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
243 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
244 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
245 "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \
248 #define ASMC_MBP81_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
249 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
250 "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
251 "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
254 #define ASMC_MBP82_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
255 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
256 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
257 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
258 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
259 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
261 #define ASMC_MBP82_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
262 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
263 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
264 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
265 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
266 "Th2H", "memory", "Ts0P", "Ts0S" }
268 #define ASMC_MBP82_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
269 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
270 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
271 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
272 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
273 "Th2H", "Tm0P", "Ts0P", "Ts0S" }
275 #define ASMC_MBP9_TEMPS { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
276 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
277 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
278 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
281 #define ASMC_MBP9_TEMPNAMES { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
282 "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
283 "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
284 "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
287 #define ASMC_MBP9_TEMPDESCS { "Palm Rest", "Memory Proximity", "Airflow 1", \
288 "Battery 1", "Battery 2", "Battery TS_MAX", \
289 "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \
290 "TC0J", "CPU 1 Proximity", "TCFC", \
291 "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \
292 "GPU Die", "Memory Bank A1", "Memory Module A1", \
296 #define ASMC_MBP112_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
297 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
298 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
299 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
300 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
301 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
302 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
305 #define ASMC_MBP112_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
306 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
307 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
308 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
309 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
310 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
311 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
314 #define ASMC_MBP112_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
315 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
316 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
317 "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
318 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
319 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
320 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
323 #define ASMC_MBP113_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
324 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
325 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
326 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
327 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
328 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
329 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
330 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
333 #define ASMC_MBP113_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
334 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
335 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
336 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
337 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
338 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
339 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
340 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
343 #define ASMC_MBP113_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
344 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
345 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
346 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
347 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
348 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
349 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
350 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
354 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
355 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
356 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
357 "Northbridge Point 2" }
359 #define ASMC_MM21_TEMPS { "TA0P", "TC0D", \
364 #define ASMC_MM21_TEMPNAMES { "ambient_air", "cpu_die", \
365 "cpu_heatsink", "cpu_proximity1", \
366 "cpu_proximity2", "northbridge_proximity1", \
367 "northbridge_proximity2", }
369 #define ASMC_MM21_TEMPDESCS { "Ambient Air Temperature" \
370 "CPU Die Core Temperature", \
371 "CPU Heatsink Temperature", \
372 "CPU Proximity 1 Temperature", \
373 "CPU Proximity 2 Temperature", \
374 "Northbridge Proximity 1 Temperature", \
375 "Northbridge Proximity 2 Temperature", }
377 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
382 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
383 "cpu0_proximity", "hdd_bay", \
385 "northbridge_proximity", \
386 "wireless_proximity", }
388 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
389 "CPU0 Heatsink Temperature", \
390 "CPU0 Proximity Temperature", \
391 "HDD Bay Temperature", \
392 "Northbridge Die Core Temperature", \
393 "Northbridge Proximity Temperature", \
394 "Wireless Module Proximity Temperature", }
396 #define ASMC_MM41_TEMPS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
397 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
398 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
399 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
400 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
401 "TW0P", "Tm0P", "Tp0C", NULL }
403 #define ASMC_MM41_TEMPNAMES { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
404 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
405 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
406 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
407 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
408 "TW0P", "Tm0P", "Tp0C", NULL }
410 #define ASMC_MM41_TEMPDESCS { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
411 "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
412 "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
413 "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
414 "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
415 "TW0P", "Tm0P", "Tp0C", NULL }
417 #define ASMC_MM52_TEMPS { "TA0P", "TA1P", \
427 #define ASMC_MM52_TEMPNAMES { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \
428 "cpu_die", "cpu_proximity", \
429 "gpu_diode1", "gpu_diode2", \
430 "gpu_proximity", "gpu_integrated_switcher", \
431 "thunderbolt_proximity", \
432 "memory_slot1", "memory_slot2", \
433 "memory_proximity", "pch_controller_proximity", \
434 "pch_controller_die", "pwr_supply", \
435 "wireless_proximity", }
437 #define ASMC_MM52_TEMPDESCS { "Ambient Air Proximity Temperature", \
438 "Combo Ambient CPU PCH Wireless DIMM Temperature", \
439 "CPU Die Temperature", "CPU Proximity Temperature", \
440 "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \
441 "GPU Proximity Temperature", \
442 "Integrated Graphics/GPU Switcher Temperature", \
443 "Thunderbolt Proximity Temperature", \
444 "Memory Slot 1 Temperature", \
445 "Memory Slot 2 Temperature", \
446 "Memory Slots Proximity Temperature", \
447 "Platform Controller Hub Proximity Temperature", \
448 "Platform Controller Hub Die Temperature", \
449 "Power Supply Temperature", \
450 "Wireless Module Proximity Temperature", }
452 #define ASMC_MP1_TEMPS { "TA0P", \
454 "TC0P", "TC0C", "TC1C", \
455 "TC2C", "TC3C", "THTG", \
458 "TM0P", "TM1P", "TM2P", \
459 "TM8P", "TM9P", "TMAP", \
460 "TM0S", "TM1S", "TM2P", "TM3S", \
461 "TM8S", "TM9S", "TMAS", "TMBS", \
463 "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL }
465 #define ASMC_MP1_TEMPNAMES { "ambient", \
466 "cpu_a_heatsink", "cpu_b_heatsink", \
467 "cpu_a_proximity", "cpu_core0", "cpu_core1", \
468 "cpu_core2", "cpu_core3", "THTG", \
469 "hdd_bay0", "hdd_bay1", \
470 "hdd_bay2", "hdd_bay3", \
471 "memory_card_a_proximity0", \
472 "memory_card_a_proximity1", \
473 "memory_card_a_proximity2", \
474 "memory_card_b_proximity0", \
475 "memory_card_b_proximity1", \
476 "memory_card_b_proximity2", \
477 "memory_card_a_slot0", \
478 "memory_card_a_slot1", \
479 "memory_card_a_slot2", \
480 "memory_card_a_slot3", \
481 "memory_card_b_slot0", \
482 "memory_card_b_slot1", \
483 "memory_card_b_slot2", \
484 "memory_card_b_slot3", \
485 "mch_heatsink", "expansion_slots", \
486 "power_supply_loc0", "power_supply_loc1", \
489 #define ASMC_MP1_TEMPDESCS { "Ambient Air", \
490 "CPU A Heatsink", "CPU B Heatsink", \
492 "CPU Core 1", "CPU Core 2", \
493 "CPU Core 3", "CPU Core 4", "THTG", \
494 "Hard Drive Bay 1", "Hard Drive Bay 2", \
495 "Hard Drive Bay 3", "Hard Drive Bay 4", \
496 "Memory Riser A, Proximity 1", \
497 "Memory Riser A, Proximity 2", \
498 "Memory Riser A, Proximity 3", \
499 "Memory Riser B, Proximity 1", \
500 "Memory Riser B, Proximity 2", \
501 "Memory Riser B, Proximity 3", \
502 "Memory Riser A, Slot 1", \
503 "Memory Riser A, Slot 2", \
504 "Memory Riser A, Slot 3", \
505 "Memory Riser A, Slot 4", \
506 "Memory Riser B, Slot 1", \
507 "Memory Riser B, Slot 2", \
508 "Memory Riser B, Slot 3", \
509 "Memory Riser B, Slot 4", \
510 "MCH Heatsink", "Expansion Slots", \
511 "Power Supply, Location 1", \
512 "Power Supply, Location 2", \
515 #define ASMC_MP2_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
516 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
517 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
518 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
519 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
520 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
521 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
524 #define ASMC_MP2_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
525 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
526 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
527 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
528 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
529 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
530 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
532 #define ASMC_MP2_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
533 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
534 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
535 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
536 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
537 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
538 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
540 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
541 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
542 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
543 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
544 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
545 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
546 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
547 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
548 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
549 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
550 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
551 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
552 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
553 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
554 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
557 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
558 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
559 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
560 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
561 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
562 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
563 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
564 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
565 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
566 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
567 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
568 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
569 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
570 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
571 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
573 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
574 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
575 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
576 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
577 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
578 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
579 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
580 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
581 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
582 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
583 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
584 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
585 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
586 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
587 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
589 #define ASMC_MBA_TEMPS { "TB0T", NULL }
590 #define ASMC_MBA_TEMPNAMES { "enclosure" }
591 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
593 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
594 "TC0D", "TC0E", "TC0P", NULL }
596 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
597 "TC0D", "TC0E", "TC0P" }
599 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
600 "TC0D", "TC0E", "TC0P" }
602 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \
603 "TC0D", "TC0E", "TC0F", "TC0P", \
604 "TC1C", "TC2C", "TCGC", "TCSA", \
605 "TCXC", "THSP", "TM0P", "TPCD", \
606 "Ta0P", "Th1H", "Tm0P", "Tm1P", \
607 "Ts0P", "Ts0S", NULL }
609 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
610 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
611 "cpucore1", "cpucore2", "cpupeci", "pecisa", \
612 "TCXC", "THSP", "memorybank", "pchdie", \
613 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
614 "palmrest", "memoryproximity" }
616 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
617 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
618 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
619 "TCXC", "THSP", "Memory Bank A", "PCH Die", \
620 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
621 "Palm Rest", "Memory Proximity" }
623 #define ASMC_MBA7_TEMPS { "TB0T", "TB1T", "TB2T", \
624 "TC0E", "TC0F", "TC0P", \
626 "TCGC", "TCSA", "TCXC", \
627 "THSP", "TM0P", "TPCD", \
628 "TW0P" "Ta0P", "Th1H", \
629 "Tm0P", "Ts0P", "Ts0S", NULL }
631 #define ASMC_MBA7_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", \
632 "cputemp1", "cputemp2", "cpuproximity", \
633 "cpucore1", "cpucore2", \
634 "pecigpu", "pecisa", "pecicpu", \
635 "thunderboltproximity", "memorybank", "pchdie", \
636 "wirelessproximity", "airflowproximity", "heatpipe", \
637 "mainboardproximity", "palmrest", "memoryproximity" }
639 #define ASMC_MBA7_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \
640 "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
641 "CPU Core 1", "CPU Core 2", \
642 "PECI GPU", "PECI SA", "PECI CPU", \
643 "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \
644 "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \
645 "Mainboard Proximity", "Palm Rest", "Memory Proximity" }