sys/dev/asmc/asmcvar.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  25  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  * POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  *
  30  */
  31
  32 #define ASMC_MAXFANS    6
  33
  34 struct asmc_softc {
  35         device_t                sc_dev;
  36         struct mtx              sc_mtx;
  37         int                     sc_nfan;
  38         int16_t                 sms_rest_x;
  39         int16_t                 sms_rest_y;
  40         int16_t                 sms_rest_z;
  41         struct sysctl_oid       *sc_fan_tree[ASMC_MAXFANS+1];
  42         struct sysctl_oid       *sc_temp_tree;
  43         struct sysctl_oid       *sc_sms_tree;
  44         struct sysctl_oid       *sc_light_tree;
  45         struct asmc_model       *sc_model;
  46         int                     sc_rid_port;
  47         int                     sc_rid_irq;
  48         struct resource         *sc_ioport;
  49         struct resource         *sc_irq;
  50         void                    *sc_cookie;
  51         int                     sc_sms_intrtype;
  52         struct taskqueue        *sc_sms_tq;
  53         struct task             sc_sms_task;
  54         uint8_t                 sc_sms_intr_works;
  55 };
  56
  57 /*
  58  * Data port.
  59  */
  60 #define ASMC_DATAPORT_READ(sc)  bus_read_1(sc->sc_ioport, 0x00)
  61 #define ASMC_DATAPORT_WRITE(sc, val) \
  62         bus_write_1(sc->sc_ioport, 0x00, val)
  63 #define ASMC_STATUS_MASK        0x0f
  64
  65 /*
  66  * Command port.
  67  */
  68 #define ASMC_CMDPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x04)
  69 #define ASMC_CMDPORT_WRITE(sc, val) \
  70         bus_write_1(sc->sc_ioport, 0x04, val)
  71 #define ASMC_CMDREAD            0x10
  72 #define ASMC_CMDWRITE           0x11
  73
  74 /*
  75  * Interrupt port.
  76  */
  77 #define ASMC_INTPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x1f)
  78
  79 /* Number of keys */
  80 #define ASMC_NKEYS              "#KEY"  /* RO; 4 bytes */
  81
  82 /*
  83  * Fan control via SMC.
  84  */
  85 #define ASMC_KEY_FANCOUNT       "FNum"  /* RO; 1 byte */
  86 #define ASMC_KEY_FANMANUAL      "FS! "  /* RW; 2 bytes */
  87 #define ASMC_KEY_FANID          "F%dID" /* RO; 16 bytes */
  88 #define ASMC_KEY_FANSPEED       "F%dAc" /* RO; 2 bytes */
  89 #define ASMC_KEY_FANMINSPEED    "F%dMn" /* RO; 2 bytes */
  90 #define ASMC_KEY_FANMAXSPEED    "F%dMx" /* RO; 2 bytes */
  91 #define ASMC_KEY_FANSAFESPEED   "F%dSf" /* RO; 2 bytes */
  92 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
  93
  94 /*
  95  * Sudden Motion Sensor (SMS).
  96  */
  97 #define ASMC_SMS_INIT1          0xe0
  98 #define ASMC_SMS_INIT2          0xf8
  99 #define ASMC_KEY_SMS            "MOCN"  /* RW; 2 bytes */
 100 #define ASMC_KEY_SMS_X          "MO_X"  /* RO; 2 bytes */
 101 #define ASMC_KEY_SMS_Y          "MO_Y"  /* RO; 2 bytes */
 102 #define ASMC_KEY_SMS_Z          "MO_Z"  /* RO; 2 bytes */
 103 #define ASMC_KEY_SMS_LOW        "MOLT"  /* RW; 2 bytes */
 104 #define ASMC_KEY_SMS_HIGH       "MOHT"  /* RW; 2 bytes */
 105 #define ASMC_KEY_SMS_LOW_INT    "MOLD"  /* RW; 1 byte */
 106 #define ASMC_KEY_SMS_HIGH_INT   "MOHD"  /* RW; 1 byte */
 107 #define ASMC_KEY_SMS_FLAG       "MSDW"  /* RW; 1 byte */
 108 #define ASMC_SMS_INTFF          0x60    /* Free fall Interrupt */
 109 #define ASMC_SMS_INTHA          0x6f    /* High Acceleration Interrupt */
 110 #define ASMC_SMS_INTSH          0x80    /* Shock Interrupt */
 111
 112 /*
 113  * Keyboard backlight.
 114  */
 115 #define ASMC_KEY_LIGHTLEFT      "ALV0"  /* RO; 6 bytes */
 116 #define ASMC_KEY_LIGHTRIGHT     "ALV1"  /* RO; 6 bytes */
 117 #define ASMC_KEY_LIGHTVALUE     "LKSB"  /* WO; 2 bytes */
 118
 119 /*
 120  * Clamshell.
 121  */
 122 #define ASMC_KEY_CLAMSHELL      "MSLD"  /* RO; 1 byte */
 123
 124 /*
 125  * Interrupt keys.
 126  */
 127 #define ASMC_KEY_INTOK          "NTOK"  /* WO; 1 byte */
 128
 129 /*
 130  * Temperatures.
 131  *
 132  * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
 133  * fourth the Mac Pro 8-core and finally the MacBook Air.
 134  *
 135  */
 136 /* maximum array size for temperatures including the last NULL */
 137 #define ASMC_TEMP_MAX           80
 138 #define ASMC_MB_TEMPS           { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
 139                                   "TM0P", NULL }
 140 #define ASMC_MB_TEMPNAMES       { "enclosure", "northbridge1", \
 141                                   "northbridge2", "heatsink1", \
 142                                   "heatsink2", "memory", }
 143 #define ASMC_MB_TEMPDESCS       { "Enclosure Bottomside", \
 144                                   "Northbridge Point 1", \
 145                                   "Northbridge Point 2", "Heatsink 1", \
 146                                   "Heatsink 2", "Memory Bank A", }
 147
 148 #define ASMC_MB31_TEMPS         { "TB0T", "TN0P",  "Th0H", "Th1H", \
 149                                   "TM0P", NULL }
 150
 151 #define ASMC_MB31_TEMPNAMES     { "enclosure", "northbridge1", \
 152                                   "heatsink1", "heatsink2", \
 153                                   "memory", }
 154
 155 #define ASMC_MB31_TEMPDESCS     { "Enclosure Bottomside", \
 156                                   "Northbridge Point 1", \
 157                                   "Heatsink 1","Heatsink 2" \
 158                                   "Memory Bank A", }
 159
 160 #define ASMC_MB71_TEMPS         { "TB0T", "TB1T", "TB2T", "TC0D", "TC0P", \
 161                                   "TH0P", "TN0D", "TN0P", "TN0S", "TN1D", \
 162                                   "TN1E", "TN1F", "TN1G", "TN1S", "Th1H", \
 163                                   "Ts0P", "Ts0S", NULL }
 164
 165 #define ASMC_MB71_TEMPNAMES     { "enclosure_bottom0", "battery_1", "battery_2", "cpu_package", "cpu_proximity", \
 166                                   "hdd_bay", "northbridge0_diode", "northbridge0_proximity", "TN0S", "mpc_die2", \
 167                                   "TN1E", "TN1F", "TN1G", "TN1S", "heatsink1", \
 168                                   "palm_rest", "memory_proximity", }
 169
 170 #define ASMC_MB71_TEMPDESCS     { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU Proximity", \
 171                                   "HDD Bay", "Northbridge Diode", "Northbridge Proximity", "TN0S", "MPC Die 2", \
 172                                   "TN1E", "TN1F", "TN1G", "TN1S", "Heatsink 1", \
 173                                   "Palm Rest", "Memory Proximity", }
 174
 175 #define ASMC_MBP_TEMPS          { "TB0T", "Th0H", "Th1H", "Tm0P",       \
 176                                   "TG0H", "TG0P", "TG0T", NULL }
 177
 178 #define ASMC_MBP_TEMPNAMES      { "enclosure", "heatsink1", \
 179                                   "heatsink2", "memory", "graphics", \
 180                                   "graphicssink", "unknown", }
 181
 182 #define ASMC_MBP_TEMPDESCS      { "Enclosure Bottomside", \
 183                                   "Heatsink 1", "Heatsink 2", \
 184                                   "Memory Controller", \
 185                                   "Graphics Chip", "Graphics Heatsink", \
 186                                   "Unknown", }
 187
 188 #define ASMC_MBP4_TEMPS         { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
 189                                   "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
 190                                   "TTF0", "TW0P", NULL }
 191
 192 #define ASMC_MBP4_TEMPNAMES     { "enclosure", "heatsink1", "heatsink2", \
 193                                   "heatsink3", "memory", "graphicssink", \
 194                                   "graphics", "cpu", "cpu2", "unknown1", \
 195                                   "unknown2", "wireless", }
 196
 197 #define ASMC_MBP4_TEMPDESCS     { "Enclosure Bottomside", \
 198                                   "Main Heatsink 1", "Main Heatsink 2", \
 199                                   "Main Heatsink 3", \
 200                                   "Memory Controller", \
 201                                   "Graphics Chip Heatsink", \
 202                                   "Graphics Chip Diode", \
 203                                   "CPU Temperature Diode", "CPU Point 2", \
 204                                   "Unknown", "Unknown", \
 205                                   "Wireless Module", }
 206
 207 #define ASMC_MBP5_TEMPS         { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \
 208                                   "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \
 209                                   "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \
 210                                   "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \
 211                                   NULL }
 212
 213 #define ASMC_MBP5_TEMPNAMES     { "enclosure_bottom_0", "enclosure_bottom_1", \
 214                                   "enclosure_bottom_2", "enclosure_bottom_3", \
 215                                   "cpu_diode", "cpu", \
 216                                   "cpu_pin", "gpu_diode", \
 217                                   "gpu", "gpu_heatsink", \
 218                                   "gpu_pin", "gpu_transistor", \
 219                                   "gpu_2_heatsink", "northbridge_diode", \
 220                                   "northbridge_pin", "unknown", \
 221                                   "heatsink_2", "memory_controller", \
 222                                   "pci_express_slot_pin", "pci_express_slot_unk" }
 223
 224 #define ASMC_MBP5_TEMPDESCS     { "Enclosure Bottom 0", "Enclosure Bottom 1", \
 225                                   "Enclosure Bottom 2", "Enclosure Bottom 3", \
 226                                   "CPU Diode", "CPU ???", \
 227                                   "CPU Pin", "GPU Diode", \
 228                                   "GPU ???", "GPU Heatsink", \
 229                                   "GPU Pin", "GPU Transistor", \
 230                                   "GPU 2 Heatsink", "Northbridge Diode", \
 231                                   "Northbridge Pin", "Unknown", \
 232                                   "Heatsink 2", "Memory Controller", \
 233                                   "PCI Express Slot Pin", "PCI Express Slot (unk)" }
 234
 235 #define ASMC_MBP81_TEMPS        { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
 236                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 237                                   "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
 238                                   "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
 239                                   "Ts0S", NULL }
 240
 241 #define ASMC_MBP81_TEMPNAMES    { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
 242                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 243                                   "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
 244                                   "TP0P", "TPCD", "wireless", "Th1H", "Ts0P", \
 245                                   "Ts0S" }
 246
 247 #define ASMC_MBP81_TEMPDESCS    { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
 248                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 249                                   "TCFC", "TCGC", "TCSA", "TM0S", "TMBS", \
 250                                   "TP0P", "TPCD", "TW0P", "Th1H", "Ts0P", \
 251                                   "Ts0S" }
 252
 253 #define ASMC_MBP82_TEMPS        { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
 254                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 255                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 256                                   "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
 257                                   "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
 258                                   "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
 259
 260 #define ASMC_MBP82_TEMPNAMES    { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
 261                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 262                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 263                                   "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
 264                                   "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
 265                                   "Th2H", "memory", "Ts0P", "Ts0S" }
 266
 267 #define ASMC_MBP82_TEMPDESCS    { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
 268                                   "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
 269                                   "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
 270                                   "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
 271                                   "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
 272                                   "Th2H", "Tm0P", "Ts0P", "Ts0S" }
 273
 274 #define ASMC_MBP9_TEMPS         { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
 275                                   "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
 276                                   "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
 277                                   "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
 278                                   "TPCD", NULL }
 279
 280 #define ASMC_MBP9_TEMPNAMES     { "Ts0P", "Ts0S", "TA0P", "TB1T", "TB2T", \
 281                                   "TB0T", "TC1C", "TC2C", "TC0E", "TC0F", \
 282                                   "TC0J", "TC0P", "TCFC", "TCGC", "TCSA", \
 283                                   "TCTD", "TCXC", "TG1D", "TM0P", "TM0S", \
 284                                   "TPCD" }
 285
 286 #define ASMC_MBP9_TEMPDESCS     { "Palm Rest", "Memory Proximity", "Airflow 1", \
 287                                   "Battery 1", "Battery 2", "Battery TS_MAX", \
 288                                   "CPU Core 1", "CPU Core 2", "CPU1", "CPU1", \
 289                                   "TC0J", "CPU 1 Proximity", "TCFC", \
 290                                   "PECI GPU", "PECI SA", "TCTD", "PECI CPU", \
 291                                   "GPU Die", "Memory Bank A1", "Memory Module A1", \
 292                                   "PCH Die" }
 293
 294 #define ASMC_MBP112_TEMPS       { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 295                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 296                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 297                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 298                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 299                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 300                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 301                                   "Ts1S", NULL }
 302
 303 #define ASMC_MBP112_TEMPNAMES   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 304                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 305                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 306                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 307                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 308                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 309                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 310                                   "Ts1S" }
 311
 312 #define ASMC_MBP112_TEMPDESCS   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 313                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 314                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 315                                   "TCXC", "TH0A", "TH0B", "TH0F", "TH0R", \
 316                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 317                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 318                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 319                                   "Ts1S" }
 320
 321 #define ASMC_MBP113_TEMPS       { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E",       \
 322                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 323                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 324                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 325                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 326                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 327                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 328                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 329                                   "Ts1S", NULL }
 330
 331 #define ASMC_MBP113_TEMPNAMES   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 332                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 333                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 334                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 335                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 336                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 337                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 338                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 339                                   "Ts1S" }
 340
 341 #define ASMC_MBP113_TEMPDESCS   { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
 342                                   "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
 343                                   "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
 344                                   "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
 345                                   "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
 346                                   "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
 347                                   "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
 348                                   "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
 349                                   "Ts1S" }
 350 #define ASMC_MM_TEMPS           { "TN0P", "TN1P", NULL }
 351 #define ASMC_MM_TEMPNAMES       { "northbridge1", "northbridge2" }
 352 #define ASMC_MM_TEMPDESCS       { "Northbridge Point 1", \
 353                                   "Northbridge Point 2" }
 354
 355 #define ASMC_MM21_TEMPS         { "TA0P", "TC0D", \
 356                                   "TC0H", "TC0P", \
 357                                   "TC1P", "TN0P", \
 358                                   "TN1P", NULL }
 359
 360 #define ASMC_MM21_TEMPNAMES     { "ambient_air", "cpu_die", \
 361                                   "cpu_heatsink", "cpu_proximity1", \
 362                                   "cpu_proximity2", "northbridge_proximity1", \
 363                                   "northbridge_proximity2", }
 364
 365 #define ASMC_MM21_TEMPDESCS     { "Ambient Air Temperature" \
 366                                   "CPU Die Core Temperature", \
 367                                   "CPU Heatsink Temperature", \
 368                                   "CPU Proximity 1 Temperature", \
 369                                   "CPU Proximity 2 Temperature", \
 370                                   "Northbridge Proximity 1 Temperature", \
 371                                   "Northbridge Proximity 2 Temperature", }
 372
 373 #define ASMC_MM31_TEMPS         { "TC0D", "TC0H", \
 374                                   "TC0P", "TH0P", \
 375                                   "TN0D", "TN0P", \
 376                                   "TW0P", NULL }
 377
 378 #define ASMC_MM31_TEMPNAMES     { "cpu0_die", "cpu0_heatsink", \
 379                                   "cpu0_proximity", "hdd_bay", \
 380                                   "northbridge_die", \
 381                                   "northbridge_proximity", \
 382                                   "wireless_proximity", }
 383
 384 #define ASMC_MM31_TEMPDESCS     { "CPU0 Die Core Temperature", \
 385                                   "CPU0 Heatsink Temperature", \
 386                                   "CPU0 Proximity Temperature", \
 387                                   "HDD Bay Temperature", \
 388                                   "Northbridge Die Core Temperature", \
 389                                   "Northbridge Proximity Temperature", \
 390                                   "Wireless Module Proximity Temperature", }
 391
 392 #define ASMC_MM41_TEMPS         { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
 393                                   "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
 394                                   "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
 395                                   "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
 396                                   "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
 397                                   "TW0P", "Tm0P", "Tp0C", NULL }
 398
 399 #define ASMC_MM41_TEMPNAMES     { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
 400                                   "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
 401                                   "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
 402                                   "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
 403                                   "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
 404                                   "TW0P", "Tm0P", "Tp0C", NULL }
 405
 406 #define ASMC_MM41_TEMPDESCS     { "TA0P", "TC0D", "TC0G", "TC0H", "TC0P", \
 407                                   "TC0p", "TCPG", "TH0G", "TH0P", "TH0p", \
 408                                   "TM0G", "TM0P", "TM0p", "TN0D", "TN0G", \
 409                                   "TN0P", "TN0p", "TN1D", "TN1E", "TN1F", \
 410                                   "TN1G", "TN1S", "TNPG", "TO0P", "TO0p", \
 411                                   "TW0P", "Tm0P", "Tp0C", NULL }
 412
 413 #define ASMC_MM52_TEMPS         { "TA0P", "TA1P", \
 414                                   "TC0D", "TC0P", \
 415                                   "TG0D", "TG1D", \
 416                                   "TG0P", "TG0M", \
 417                                   "TI0P", \
 418                                   "TM0S", "TMBS", \
 419                                   "TM0P", "TP0P", \
 420                                   "TPCD", "Tp0C", \
 421                                   "TW0P", NULL }
 422
 423 #define ASMC_MM52_TEMPNAMES     { "ambient_air_proximity", "ambient_cpu_pch_wireless_dimm", \
 424                                   "cpu_die", "cpu_proximity", \
 425                                   "gpu_diode1", "gpu_diode2", \
 426                                   "gpu_proximity", "gpu_integrated_switcher", \
 427                                   "thunderbolt_proximity", \
 428                                   "memory_slot1", "memory_slot2", \
 429                                   "memory_proximity", "pch_controller_proximity", \
 430                                   "pch_controller_die", "pwr_supply", \
 431                                   "wireless_proximity", }
 432
 433 #define ASMC_MM52_TEMPDESCS     { "Ambient Air Proximity Temperature", \
 434                                   "Combo Ambient CPU PCH Wireless DIMM Temperature", \
 435                                   "CPU Die Temperature", "CPU Proximity Temperature", \
 436                                   "GPU Diode 1 Temperature" , "GPU Diode 2 Temperature", \
 437                                   "GPU Proximity Temperature", \
 438                                   "Integrated Graphics/GPU Switcher Temperature", \
 439                                   "Thunderbolt Proximity Temperature", \
 440                                   "Memory Slot 1 Temperature", \
 441                                   "Memory Slot 2 Temperature", \
 442                                   "Memory Slots Proximity Temperature", \
 443                                   "Platform Controller Hub Proximity Temperature", \
 444                                   "Platform Controller Hub Die Temperature", \
 445                                   "Power Supply Temperature", \
 446                                   "Wireless Module Proximity Temperature", }
 447
 448 #define ASMC_MP1_TEMPS          { "TA0P", \
 449                                   "TCAH", "TCBH", \
 450                                   "TC0P", "TC0C", "TC1C", \
 451                                   "TC2C", "TC3C", "THTG", \
 452                                   "TH0P", "TH1P", \
 453                                   "TH2P", "TH3P", \
 454                                   "TM0P", "TM1P", "TM2P", \
 455                                   "TM8P", "TM9P", "TMAP", \
 456                                   "TM0S", "TM1S", "TM2P", "TM3S", \
 457                                   "TM8S", "TM9S", "TMAS", "TMBS", \
 458                                   "TN0H", "TS0C", \
 459                                   "Tp0C", "Tp1C", "Tv0S", "Tv1S", NULL }
 460
 461 #define ASMC_MP1_TEMPNAMES      { "ambient", \
 462                                   "cpu_a_heatsink", "cpu_b_heatsink", \
 463                                   "cpu_a_proximity", "cpu_core0", "cpu_core1", \
 464                                   "cpu_core2", "cpu_core3", "THTG", \
 465                                   "hdd_bay0", "hdd_bay1", \
 466                                   "hdd_bay2", "hdd_bay3", \
 467                                   "memory_card_a_proximity0", \
 468                                   "memory_card_a_proximity1", \
 469                                   "memory_card_a_proximity2", \
 470                                   "memory_card_b_proximity0", \
 471                                   "memory_card_b_proximity1", \
 472                                   "memory_card_b_proximity2", \
 473                                   "memory_card_a_slot0", \
 474                                   "memory_card_a_slot1", \
 475                                   "memory_card_a_slot2", \
 476                                   "memory_card_a_slot3", \
 477                                   "memory_card_b_slot0", \
 478                                   "memory_card_b_slot1", \
 479                                   "memory_card_b_slot2", \
 480                                   "memory_card_b_slot3", \
 481                                   "mch_heatsink", "expansion_slots", \
 482                                   "power_supply_loc0", "power_supply_loc1", \
 483                                   "Tv0S", "Tv1S", }
 484
 485 #define ASMC_MP1_TEMPDESCS      { "Ambient Air", \
 486                                   "CPU A Heatsink", "CPU B Heatsink", \
 487                                   "CPU A Proximity", \
 488                                   "CPU Core 1", "CPU Core 2", \
 489                                   "CPU Core 3", "CPU Core 4", "THTG", \
 490                                   "Hard Drive Bay 1", "Hard Drive Bay 2", \
 491                                   "Hard Drive Bay 3", "Hard Drive Bay 4", \
 492                                   "Memory Riser A, Proximity 1", \
 493                                   "Memory Riser A, Proximity 2", \
 494                                   "Memory Riser A, Proximity 3", \
 495                                   "Memory Riser B, Proximity 1", \
 496                                   "Memory Riser B, Proximity 2", \
 497                                   "Memory Riser B, Proximity 3", \
 498                                   "Memory Riser A, Slot 1", \
 499                                   "Memory Riser A, Slot 2", \
 500                                   "Memory Riser A, Slot 3", \
 501                                   "Memory Riser A, Slot 4", \
 502                                   "Memory Riser B, Slot 1", \
 503                                   "Memory Riser B, Slot 2", \
 504                                   "Memory Riser B, Slot 3", \
 505                                   "Memory Riser B, Slot 4", \
 506                                   "MCH Heatsink", "Expansion Slots", \
 507                                   "Power Supply, Location 1", \
 508                                   "Power Supply, Location 2", \
 509                                   "Tv0S", "Tv1S", }
 510
 511 #define ASMC_MP2_TEMPS          { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 512                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 513                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 514                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 515                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 516                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 517                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
 518                                   NULL }
 519
 520 #define ASMC_MP2_TEMPNAMES      { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 521                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 522                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 523                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 524                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 525                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 526                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
 527
 528 #define ASMC_MP2_TEMPDESCS      { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 529                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 530                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 531                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 532                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 533                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 534                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
 535
 536 #define ASMC_MP5_TEMPS          { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
 537                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 538                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 539                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 540                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 541                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 542                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 543                                   "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
 544                                   "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
 545                                   "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
 546                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 547                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 548                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 549                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 550                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
 551                                   NULL }
 552
 553 #define ASMC_MP5_TEMPNAMES      { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
 554                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 555                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 556                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 557                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 558                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 559                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 560                                   "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
 561                                   "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
 562                                   "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
 563                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 564                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 565                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 566                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 567                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
 568
 569 #define ASMC_MP5_TEMPDESCS      { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
 570                                   "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
 571                                   "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
 572                                   "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
 573                                   "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
 574                                   "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
 575                                   "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
 576                                   "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
 577                                   "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
 578                                   "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
 579                                   "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
 580                                   "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
 581                                   "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
 582                                   "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
 583                                   "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
 584 #define ASMC_MBA_TEMPS          { "TB0T", NULL }
 585 #define ASMC_MBA_TEMPNAMES      { "enclosure" }
 586 #define ASMC_MBA_TEMPDESCS      { "Enclosure Bottom" }
 587
 588 #define ASMC_MBA3_TEMPS         { "TB0T", "TB1T", "TB2T", \
 589                                   "TC0D", "TC0E", "TC0P", NULL }
 590
 591 #define ASMC_MBA3_TEMPNAMES     { "enclosure", "TB1T", "TB2T", \
 592                                   "TC0D", "TC0E", "TC0P" }
 593
 594 #define ASMC_MBA3_TEMPDESCS     { "Enclosure Bottom", "TB1T", "TB2T", \
 595                                   "TC0D", "TC0E", "TC0P" }
 596
 597 #define ASMC_MBA5_TEMPS         { "TB0T", "TB1T", "TB2T", "TC0C", \
 598                                   "TC0D", "TC0E", "TC0F", "TC0P", \
 599                                   "TC1C", "TC2C", "TCGC", "TCSA", \
 600                                   "TCXC", "THSP", "TM0P", "TPCD", \
 601                                   "Ta0P", "Th1H", "Tm0P", "Tm1P", \
 602                                   "Ts0P", "Ts0S", NULL }
 603
 604 #define ASMC_MBA5_TEMPNAMES     { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
 605                                   "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
 606                                   "cpucore1", "cpucore2", "cpupeci", "pecisa", \
 607                                   "TCXC", "THSP", "memorybank", "pchdie", \
 608                                   "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
 609                                   "palmrest", "memoryproximity" }
 610
 611 #define ASMC_MBA5_TEMPDESCS     { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
 612                                   "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
 613                                   "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
 614                                   "TCXC", "THSP", "Memory Bank A", "PCH Die", \
 615                                   "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
 616                                   "Palm Rest", "Memory Proximity" }
 617
 618 #define ASMC_MBA7_TEMPS         { "TB0T", "TB1T", "TB2T", \
 619                                   "TC0E", "TC0F", "TC0P", \
 620                                   "TC1C", "TC2C", \
 621                                   "TCGC", "TCSA", "TCXC", \
 622                                   "THSP", "TM0P", "TPCD", \
 623                                   "TW0P" "Ta0P", "Th1H", \
 624                                   "Tm0P", "Ts0P", "Ts0S", NULL }
 625
 626 #define ASMC_MBA7_TEMPNAMES     { "enclosure1", "enclosure2", "enclosure3", \
 627                                   "cputemp1", "cputemp2", "cpuproximity", \
 628                                   "cpucore1", "cpucore2", \
 629                                   "pecigpu", "pecisa", "pecicpu", \
 630                                   "thunderboltproximity", "memorybank", "pchdie", \
 631                                   "wirelessproximity", "airflowproximity", "heatpipe", \
 632                                   "mainboardproximity", "palmrest", "memoryproximity" }
 633
 634 #define ASMC_MBA7_TEMPDESCS     { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", \
 635                                   "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
 636                                   "CPU Core 1", "CPU Core 2", \
 637                                   "PECI GPU", "PECI SA", "PECI CPU", \
 638                                   "Thunderbolt Proximity", "Memory Bank A", "PCH Die", \
 639                                   "Wireless Proximity", "Airflow Proxmity", "Heatpipe", \
 640                                   "Mainboard Proximity", "Palm Rest", "Memory Proximity" }