2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
30 #define ASMC_MAXFANS 6
39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
40 struct sysctl_oid *sc_temp_tree;
41 struct sysctl_oid *sc_sms_tree;
42 struct sysctl_oid *sc_light_tree;
43 struct asmc_model *sc_model;
46 struct resource *sc_ioport;
47 struct resource *sc_irq;
50 struct taskqueue *sc_sms_tq;
51 struct task sc_sms_task;
52 uint8_t sc_sms_intr_works;
58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
59 #define ASMC_DATAPORT_WRITE(sc, val) \
60 bus_write_1(sc->sc_ioport, 0x00, val)
61 #define ASMC_STATUS_MASK 0x0f
66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
67 #define ASMC_CMDPORT_WRITE(sc, val) \
68 bus_write_1(sc->sc_ioport, 0x04, val)
69 #define ASMC_CMDREAD 0x10
70 #define ASMC_CMDWRITE 0x11
75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
79 #define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
82 * Fan control via SMC.
84 #define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
85 #define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
86 #define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
87 #define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
88 #define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
89 #define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
90 #define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
91 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
94 * Sudden Motion Sensor (SMS).
96 #define ASMC_SMS_INIT1 0xe0
97 #define ASMC_SMS_INIT2 0xf8
98 #define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
99 #define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
100 #define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
101 #define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
102 #define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
103 #define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
104 #define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
105 #define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
106 #define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
107 #define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
108 #define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
109 #define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
112 * Keyboard backlight.
114 #define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
115 #define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
116 #define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
121 #define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
126 #define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
131 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
132 * fourth the Mac Pro 8-core and finally the MacBook Air.
135 /* maximum array size for temperatures including the last NULL */
136 #define ASMC_TEMP_MAX 80
137 #define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
139 #define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
140 "northbridge2", "heatsink1", \
141 "heatsink2", "memory", }
142 #define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
143 "Northbridge Point 1", \
144 "Northbridge Point 2", "Heatsink 1", \
145 "Heatsink 2", "Memory Bank A", }
147 #define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \
150 #define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \
151 "heatsink1", "heatsink2", \
154 #define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \
155 "Northbridge Point 1", \
156 "Heatsink 1","Heatsink 2" \
159 #define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
160 "TG0H", "TG0P", "TG0T", NULL }
162 #define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
163 "heatsink2", "memory", "graphics", \
164 "graphicssink", "unknown", }
166 #define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
167 "Heatsink 1", "Heatsink 2", \
168 "Memory Controller", \
169 "Graphics Chip", "Graphics Heatsink", \
172 #define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
173 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
174 "TTF0", "TW0P", NULL }
176 #define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
177 "heatsink3", "memory", "graphicssink", \
178 "graphics", "cpu", "cpu2", "unknown1", \
179 "unknown2", "wireless", }
181 #define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
182 "Main Heatsink 1", "Main Heatsink 2", \
184 "Memory Controller", \
185 "Graphics Chip Heatsink", \
186 "Graphics Chip Diode", \
187 "CPU Temperature Diode", "CPU Point 2", \
188 "Unknown", "Unknown", \
191 #define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
192 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
193 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
194 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
195 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
196 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
198 #define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
199 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
200 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
201 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \
202 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
203 "Th2H", "memory", "Ts0P", "Ts0S" }
205 #define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
206 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
207 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
208 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
209 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
210 "Th2H", "Tm0P", "Ts0P", "Ts0S" }
212 #define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
213 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
214 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
215 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
216 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
217 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
218 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
219 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
222 #define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
223 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
224 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
225 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
226 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
227 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
228 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
229 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
232 #define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
233 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
234 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
235 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
236 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
237 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
238 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
239 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
242 #define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
243 #define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
244 #define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
245 "Northbridge Point 2" }
247 #define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
252 #define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
253 "cpu0_proximity", "hdd_bay", \
255 "northbridge_proximity", \
258 #define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
259 "CPU0 Heatsink Temperature", \
260 "CPU0 Proximity Temperature", \
261 "HDD Bay Temperature", \
262 "Northbridge Die Core Temperature", \
263 "Northbridge Proximity Temperature", \
264 "Wireless Module Temperature", }
266 #define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
267 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
268 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
269 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
270 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
271 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
272 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
275 #define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
276 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
277 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
278 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
279 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
280 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
281 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
283 #define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
284 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
285 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
286 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
287 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
288 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
289 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
291 #define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
292 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
293 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
294 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
295 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
296 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
297 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
298 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
299 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
300 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
301 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
302 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
303 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
304 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
305 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
308 #define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
309 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
310 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
311 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
312 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
313 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
314 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
315 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
316 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
317 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
318 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
319 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
320 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
321 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
322 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
324 #define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
325 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
326 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
327 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
328 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \
329 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
330 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
331 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
332 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
333 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
334 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
335 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
336 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
337 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
338 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
340 #define ASMC_MBA_TEMPS { "TB0T", NULL }
341 #define ASMC_MBA_TEMPNAMES { "enclosure" }
342 #define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
344 #define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
345 "TC0D", "TC0E", "TC0P", NULL }
347 #define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
348 "TC0D", "TC0E", "TC0P" }
350 #define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
351 "TC0D", "TC0E", "TC0P" }
353 #define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \
354 "TC0D", "TC0E", "TC0F", "TC0P", \
355 "TC1C", "TC2C", "TCGC", "TCSA", \
356 "TCXC", "THSP", "TM0P", "TPCD", \
357 "Ta0P", "Th1H", "Tm0P", "Tm1P", \
358 "Ts0P", "Ts0S", NULL }
360 #define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
361 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
362 "cpucore1", "cpucore2", "cpupeci", "pecisa", \
363 "TCXC", "THSP", "memorybank", "pchdie", \
364 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
365 "palmrest", "memoryproximity" }
367 #define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
368 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
369 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
370 "TCXC", "THSP", "Memory Bank A", "PCH Die", \
371 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
372 "Palm Rest", "Memory Proximity" }