2 * Copyright (c) 1998 - 2005 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 /* ATA register defines */
32 #define ATA_DATA 0 /* (RW) data */
34 #define ATA_FEATURE 1 /* (W) feature */
35 #define ATA_F_DMA 0x01 /* enable DMA */
36 #define ATA_F_OVL 0x02 /* enable overlap */
38 #define ATA_COUNT 2 /* (W) sector count */
40 #define ATA_SECTOR 3 /* (RW) sector # */
41 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
42 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
43 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
44 #define ATA_D_LBA 0x40 /* use LBA addressing */
45 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
47 #define ATA_COMMAND 7 /* (W) command */
49 #define ATA_ERROR 8 /* (R) error */
50 #define ATA_E_ILI 0x01 /* illegal length */
51 #define ATA_E_NM 0x02 /* no media */
52 #define ATA_E_ABORT 0x04 /* command aborted */
53 #define ATA_E_MCR 0x08 /* media change request */
54 #define ATA_E_IDNF 0x10 /* ID not found */
55 #define ATA_E_MC 0x20 /* media changed */
56 #define ATA_E_UNC 0x40 /* uncorrectable data */
57 #define ATA_E_ICRC 0x80 /* UDMA crc error */
58 #define ATA_E_MASK 0x0f /* error mask */
59 #define ATA_SK_MASK 0xf0 /* sense key mask */
60 #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */
61 #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */
62 #define ATA_SK_NOT_READY 0x20 /* no access to drive */
63 #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */
64 #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */
65 #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */
66 #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */
67 #define ATA_SK_DATA_PROTECT 0x70 /* write protect */
68 #define ATA_SK_BLANK_CHECK 0x80 /* blank check */
69 #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */
70 #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */
71 #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */
72 #define ATA_SK_EQUAL 0xc0 /* equal */
73 #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */
74 #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */
75 #define ATA_SK_RESERVED 0xf0
77 #define ATA_IREASON 9 /* (R) interrupt reason */
78 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
79 #define ATA_I_IN 0x02 /* read (1) | write (0) */
80 #define ATA_I_RELEASE 0x04 /* released bus (1) */
81 #define ATA_I_TAGMASK 0xf8 /* tag mask */
83 #define ATA_STATUS 10 /* (R) status */
84 #define ATA_ALTSTAT 11 /* (R) alternate status */
85 #define ATA_S_ERROR 0x01 /* error */
86 #define ATA_S_INDEX 0x02 /* index */
87 #define ATA_S_CORR 0x04 /* data corrected */
88 #define ATA_S_DRQ 0x08 /* data request */
89 #define ATA_S_DSC 0x10 /* drive seek completed */
90 #define ATA_S_SERVICE 0x10 /* drive needs service */
91 #define ATA_S_DWF 0x20 /* drive write fault */
92 #define ATA_S_DMA 0x20 /* DMA ready */
93 #define ATA_S_READY 0x40 /* drive ready */
94 #define ATA_S_BUSY 0x80 /* busy */
96 #define ATA_CONTROL 12 /* (W) control */
98 #define ATA_CTLOFFSET 0x206 /* control register offset */
99 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
100 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
101 #define ATA_A_IDS 0x02 /* disable interrupts */
102 #define ATA_A_RESET 0x04 /* RESET controller */
103 #define ATA_A_4BIT 0x08 /* 4 head bits */
104 #define ATA_A_HOB 0x80 /* High Order Byte enable */
106 /* SATA register defines */
107 #define ATA_SSTATUS 13
108 #define ATA_SS_DET_MASK 0x0000000f
109 #define ATA_SS_DET_NO_DEVICE 0x00000000
110 #define ATA_SS_DET_DEV_PRESENT 0x00000001
111 #define ATA_SS_DET_PHY_ONLINE 0x00000003
112 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
114 #define ATA_SS_SPD_MASK 0x000000f0
115 #define ATA_SS_SPD_NO_SPEED 0x00000000
116 #define ATA_SS_SPD_GEN1 0x00000010
117 #define ATA_SS_SPD_GEN2 0x00000020
119 #define ATA_SS_IPM_MASK 0x00000f00
120 #define ATA_SS_IPM_NO_DEVICE 0x00000000
121 #define ATA_SS_IPM_ACTIVE 0x00000100
122 #define ATA_SS_IPM_PARTIAL 0x00000200
123 #define ATA_SS_IPM_SLUMBER 0x00000600
125 #define ATA_SS_CONWELL_MASK \
126 (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
127 #define ATA_SS_CONWELL_GEN1 \
128 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
129 #define ATA_SS_CONWELL_GEN2 \
130 (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
132 #define ATA_SERROR 14
133 #define ATA_SE_DATA_CORRECTED 0x00000001
134 #define ATA_SE_COMM_CORRECTED 0x00000002
135 #define ATA_SE_DATA_ERR 0x00000100
136 #define ATA_SE_COMM_ERR 0x00000200
137 #define ATA_SE_PROT_ERR 0x00000400
138 #define ATA_SE_HOST_ERR 0x00000800
139 #define ATA_SE_PHY_CHANGED 0x00010000
140 #define ATA_SE_PHY_IERROR 0x00020000
141 #define ATA_SE_COMM_WAKE 0x00040000
142 #define ATA_SE_DECODE_ERR 0x00080000
143 #define ATA_SE_PARITY_ERR 0x00100000
144 #define ATA_SE_CRC_ERR 0x00200000
145 #define ATA_SE_HANDSHAKE_ERR 0x00400000
146 #define ATA_SE_LINKSEQ_ERR 0x00800000
147 #define ATA_SE_TRANSPORT_ERR 0x01000000
148 #define ATA_SE_UNKNOWN_FIS 0x02000000
150 #define ATA_SCONTROL 15
151 #define ATA_SC_DET_MASK 0x0000000f
152 #define ATA_SC_DET_IDLE 0x00000000
153 #define ATA_SC_DET_RESET 0x00000001
154 #define ATA_SC_DET_DISABLE 0x00000004
156 #define ATA_SC_SPD_MASK 0x000000f0
157 #define ATA_SC_SPD_NO_SPEED 0x00000000
158 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
159 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
161 #define ATA_SC_IPM_MASK 0x00000f00
162 #define ATA_SC_IPM_NONE 0x00000000
163 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
164 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
166 #define ATA_SACTIVE 16
168 /* SATA AHCI v1.0 register defines */
169 #define ATA_AHCI_CAP 0x00
170 #define ATA_AHCI_NPMASK 0x1f
172 #define ATA_AHCI_GHC 0x04
173 #define ATA_AHCI_GHC_AE 0x80000000
174 #define ATA_AHCI_GHC_IE 0x00000002
175 #define ATA_AHCI_GHC_HR 0x80000001
177 #define ATA_AHCI_IS 0x08
178 #define ATA_AHCI_PI 0x0c
179 #define ATA_AHCI_VS 0x10
181 #define ATA_AHCI_OFFSET 0x80
183 #define ATA_AHCI_P_CLB 0x100
184 #define ATA_AHCI_P_CLBU 0x104
185 #define ATA_AHCI_P_FB 0x108
186 #define ATA_AHCI_P_FBU 0x10c
187 #define ATA_AHCI_P_IS 0x110
188 #define ATA_AHCI_P_IE 0x114
189 #define ATA_AHCI_P_IX_DHR 0x00000001
190 #define ATA_AHCI_P_IX_PS 0x00000002
191 #define ATA_AHCI_P_IX_DS 0x00000004
192 #define ATA_AHCI_P_IX_SDB 0x00000008
193 #define ATA_AHCI_P_IX_UF 0x00000010
194 #define ATA_AHCI_P_IX_DP 0x00000020
195 #define ATA_AHCI_P_IX_PC 0x00000040
196 #define ATA_AHCI_P_IX_DI 0x00000080
198 #define ATA_AHCI_P_IX_PRC 0x00400000
199 #define ATA_AHCI_P_IX_IPM 0x00800000
200 #define ATA_AHCI_P_IX_OF 0x01000000
201 #define ATA_AHCI_P_IX_INF 0x04000000
202 #define ATA_AHCI_P_IX_IF 0x08000000
203 #define ATA_AHCI_P_IX_HBD 0x10000000
204 #define ATA_AHCI_P_IX_HBF 0x20000000
205 #define ATA_AHCI_P_IX_TFE 0x40000000
206 #define ATA_AHCI_P_IX_CPD 0x80000000
208 #define ATA_AHCI_P_CMD 0x118
209 #define ATA_AHCI_P_CMD_ST 0x00000001
210 #define ATA_AHCI_P_CMD_SUD 0x00000002
211 #define ATA_AHCI_P_CMD_POD 0x00000004
212 #define ATA_AHCI_P_CMD_CLO 0x00000008
213 #define ATA_AHCI_P_CMD_FRE 0x00000010
214 #define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
215 #define ATA_AHCI_P_CMD_ISS 0x00002000
216 #define ATA_AHCI_P_CMD_FR 0x00004000
217 #define ATA_AHCI_P_CMD_CR 0x00008000
218 #define ATA_AHCI_P_CMD_CPS 0x00010000
219 #define ATA_AHCI_P_CMD_PMA 0x00020000
220 #define ATA_AHCI_P_CMD_HPCP 0x00040000
221 #define ATA_AHCI_P_CMD_ISP 0x00080000
222 #define ATA_AHCI_P_CMD_CPD 0x00100000
223 #define ATA_AHCI_P_CMD_ATAPI 0x01000000
224 #define ATA_AHCI_P_CMD_DLAE 0x02000000
225 #define ATA_AHCI_P_CMD_ALPE 0x04000000
226 #define ATA_AHCI_P_CMD_ASP 0x08000000
227 #define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
228 #define ATA_AHCI_P_CMD_NOOP 0x00000000
229 #define ATA_AHCI_P_CMD_ACTIVE 0x10000000
230 #define ATA_AHCI_P_CMD_PARTIAL 0x20000000
231 #define ATA_AHCI_P_CMD_SLUMPER 0x60000000
233 #define ATA_AHCI_P_TFD 0x120
234 #define ATA_AHCI_P_SIG 0x124
235 #define ATA_AHCI_P_SSTS 0x128
236 #define ATA_AHCI_P_SCTL 0x12c
237 #define ATA_AHCI_P_SERR 0x130
238 #define ATA_AHCI_P_SACT 0x134
239 #define ATA_AHCI_P_CI 0x138
241 #define ATA_AHCI_CL_SIZE 32
242 #define ATA_AHCI_CL_OFFSET 0
243 #define ATA_AHCI_FB_OFFSET 1024
244 #define ATA_AHCI_CT_OFFSET 1024+256
245 #define ATA_AHCI_CT_SG_OFFSET 128
246 #define ATA_AHCI_CT_SIZE 256
248 /* DMA register defines */
249 #define ATA_DMA_ENTRIES 256
250 #define ATA_DMA_EOT 0x80000000
252 #define ATA_BMCMD_PORT 17
253 #define ATA_BMCMD_START_STOP 0x01
254 #define ATA_BMCMD_WRITE_READ 0x08
256 #define ATA_BMDEVSPEC_0 18
257 #define ATA_BMSTAT_PORT 19
258 #define ATA_BMSTAT_ACTIVE 0x01
259 #define ATA_BMSTAT_ERROR 0x02
260 #define ATA_BMSTAT_INTERRUPT 0x04
261 #define ATA_BMSTAT_MASK 0x07
262 #define ATA_BMSTAT_DMA_MASTER 0x20
263 #define ATA_BMSTAT_DMA_SLAVE 0x40
264 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
266 #define ATA_BMDEVSPEC_1 20
267 #define ATA_BMDTP_PORT 21
269 #define ATA_IDX_ADDR 22
270 #define ATA_IDX_DATA 23
271 #define ATA_MAX_RES 24
274 #define ATA_PRIMARY 0x1f0
275 #define ATA_SECONDARY 0x170
276 #define ATA_PC98_BANK 0x432
277 #define ATA_IOSIZE 0x08
278 #define ATA_PC98_IOSIZE 0x10
279 #define ATA_CTLIOSIZE 0x01
280 #define ATA_BMIOSIZE 0x08
281 #define ATA_PC98_BANKIOSIZE 0x01
282 #define ATA_IOADDR_RID 0
283 #define ATA_CTLADDR_RID 1
284 #define ATA_BMADDR_RID 0x20
285 #define ATA_PC98_CTLADDR_RID 8
286 #define ATA_PC98_BANKADDR_RID 9
287 #define ATA_IRQ_RID 0
288 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
289 #define ATA_CFA_MAGIC 0x848A
290 #define ATAPI_MAGIC_LSB 0x14
291 #define ATAPI_MAGIC_MSB 0xeb
292 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
293 #define ATAPI_P_WRITE (ATA_S_DRQ)
294 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
295 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
296 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
297 #define ATAPI_P_ABORT 0
298 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
299 #define ATA_OP_CONTINUES 0
300 #define ATA_OP_FINISHED 1
301 #define ATA_MAX_28BIT_LBA 268435455UL
303 /* ATAPI request sense structure */
305 u_int8_t error_code :7; /* current or deferred errors */
306 u_int8_t valid :1; /* follows ATAPI spec */
307 u_int8_t segment; /* Segment number */
308 u_int8_t sense_key :4; /* sense key */
309 u_int8_t reserved2_4 :1; /* reserved */
310 u_int8_t ili :1; /* incorrect length indicator */
311 u_int8_t eom :1; /* end of medium */
312 u_int8_t filemark :1; /* filemark */
313 u_int32_t cmd_info __packed; /* cmd information */
314 u_int8_t sense_length; /* additional sense len (n-7) */
315 u_int32_t cmd_specific_info __packed; /* additional cmd spec info */
316 u_int8_t asc; /* additional sense code */
317 u_int8_t ascq; /* additional sense code qual */
318 u_int8_t replaceable_unit_code; /* replaceable unit code */
319 u_int8_t sk_specific :7; /* sense key specific */
320 u_int8_t sksv :1; /* sense key specific info OK */
321 u_int8_t sk_specific1; /* sense key specific */
322 u_int8_t sk_specific2; /* sense key specific */
325 /* structure used for composite atomic operations */
326 #define MAX_COMPOSITES 32 /* u_int32_t bits */
327 struct ata_composite {
328 struct mtx lock; /* control lock */
329 u_int32_t rd_needed; /* needed read subdisks */
330 u_int32_t rd_done; /* done read subdisks */
331 u_int32_t wr_needed; /* needed write subdisks */
332 u_int32_t wr_depend; /* write depends on subdisks */
333 u_int32_t wr_done; /* done write subdisks */
334 struct ata_request *request[MAX_COMPOSITES];
335 u_int32_t residual; /* bytes still to transfer */
340 /* structure used to queue an ATA/ATAPI request */
342 device_t dev; /* device handle */
345 u_int8_t command; /* command reg */
346 u_int16_t feature; /* feature reg */
347 u_int16_t count; /* count reg */
348 u_int64_t lba; /* lba reg */
351 u_int8_t ccb[16]; /* ATAPI command block */
352 struct atapi_sense sense_data; /* ATAPI request sense data */
353 u_int8_t sense_key; /* ATAPI request sense key */
354 u_int8_t sense_cmd; /* ATAPI saved command */
357 u_int32_t bytecount; /* bytes to transfer */
358 u_int32_t transfersize; /* bytes pr transfer */
359 caddr_t data; /* pointer to data buf */
361 #define ATA_R_CONTROL 0x00000001
362 #define ATA_R_READ 0x00000002
363 #define ATA_R_WRITE 0x00000004
364 #define ATA_R_ATAPI 0x00000008
365 #define ATA_R_DMA 0x00000010
366 #define ATA_R_QUIET 0x00000020
367 #define ATA_R_TIMEOUT 0x00000040
369 #define ATA_R_ORDERED 0x00000100
370 #define ATA_R_AT_HEAD 0x00000200
371 #define ATA_R_REQUEUE 0x00000400
372 #define ATA_R_THREAD 0x00000800
373 #define ATA_R_DIRECT 0x00001000
375 #define ATA_R_DEBUG 0x10000000
377 u_int8_t status; /* ATA status */
378 u_int8_t error; /* ATA error */
379 u_int8_t dmastat; /* DMA status */
380 u_int32_t donecount; /* bytes transferred */
381 int result; /* result error code */
382 void (*callback)(struct ata_request *request);
383 struct sema done; /* request done sema */
384 int retries; /* retry count */
385 int timeout; /* timeout for this cmd */
386 struct callout callout; /* callout management */
387 struct task task; /* task management */
388 struct bio *bio; /* bio for this request */
389 int this; /* this request ID */
390 struct ata_composite *composite; /* for composite atomic ops */
391 void *driver; /* driver specific */
392 TAILQ_ENTRY(ata_request) chain; /* list management */
395 /* define this for debugging request processing */
397 #define ATA_DEBUG_RQ(request, string) \
399 if (request->flags & ATA_R_DEBUG) \
400 device_printf(request->dev, "req=%p %s " string "\n", \
401 request, ata_cmd2str(request)); \
404 #define ATA_DEBUG_RQ(request, string)
408 /* structure describing an ATA/ATAPI device */
410 device_t dev; /* device handle */
411 int unit; /* physical unit */
412 #define ATA_MASTER 0x00
413 #define ATA_SLAVE 0x10
415 struct ata_params param; /* ata param structure */
416 int mode; /* current transfermode */
417 u_int32_t max_iosize; /* max IO size */
418 int cmd; /* last cmd executed */
420 #define ATA_D_USE_CHS 0x0001
421 #define ATA_D_MEDIA_CHANGED 0x0002
422 #define ATA_D_ENC_PRESENT 0x0004
423 #define ATA_D_48BIT_ACTIVE 0x0008
426 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
427 struct ata_dma_prdentry {
432 /* structure used by the setprd function */
433 struct ata_dmasetprd_args {
439 /* structure holding DMA related information */
441 bus_dma_tag_t dmatag; /* parent DMA tag */
442 bus_dma_tag_t sg_tag; /* SG list DMA tag */
443 bus_dmamap_t sg_map; /* SG list DMA map */
444 void *sg; /* DMA transfer table */
445 bus_addr_t sg_bus; /* bus address of dmatab */
446 bus_dma_tag_t data_tag; /* data DMA tag */
447 bus_dmamap_t data_map; /* data DMA map */
448 bus_dma_tag_t work_tag; /* workspace DMA tag */
449 bus_dmamap_t work_map; /* workspace DMA map */
450 u_int8_t *work; /* workspace */
451 bus_addr_t work_bus; /* bus address of dmatab */
453 u_int32_t alignment; /* DMA SG list alignment */
454 u_int32_t boundary; /* DMA SG list boundary */
455 u_int32_t segsize; /* DMA SG list segment size */
456 u_int32_t max_iosize; /* DMA data max IO size */
457 u_int32_t cur_iosize; /* DMA data current IO size */
459 #define ATA_DMA_READ 0x01 /* transaction is a read */
460 #define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
461 #define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
463 void (*alloc)(device_t dev);
464 void (*free)(device_t dev);
465 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
466 int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
467 int (*unload)(device_t dev);
468 int (*start)(device_t dev);
469 int (*stop)(device_t dev);
470 void (*reset)(device_t dev);
473 /* structure holding lowlevel functions */
474 struct ata_lowlevel {
475 int (*begin_transaction)(struct ata_request *request);
476 int (*end_transaction)(struct ata_request *request);
477 int (*command)(struct ata_request *request);
480 /* structure holding resources for an ATA channel */
481 struct ata_resource {
482 struct resource *res;
486 /* structure describing an ATA channel */
488 device_t dev; /* device handle */
489 int unit; /* physical channel */
490 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
491 struct resource *r_irq; /* interrupt of this channel */
492 void *ih; /* interrupt handle */
493 struct ata_lowlevel hw; /* lowlevel HW functions */
494 struct ata_dma *dma; /* DMA data / functions */
495 int flags; /* channel flags */
496 #define ATA_NO_SLAVE 0x01
497 #define ATA_USE_16BIT 0x02
498 #define ATA_ATAPI_DMA_RO 0x04
499 #define ATA_NO_48BIT_DMA 0x08
501 int devices; /* what is present */
502 #define ATA_ATA_MASTER 0x01
503 #define ATA_ATA_SLAVE 0x02
504 #define ATA_ATAPI_MASTER 0x04
505 #define ATA_ATAPI_SLAVE 0x08
507 struct mtx state_mtx; /* state lock */
508 int state; /* ATA channel state */
509 #define ATA_IDLE 0x0000
510 #define ATA_ACTIVE 0x0001
511 #define ATA_STALL_QUEUE 0x0002
513 struct mtx queue_mtx; /* queue lock */
514 TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
515 struct ata_request *freezepoint; /* composite freezepoint */
516 struct ata_request *running; /* currently running request */
519 /* disk bay/enclosure related */
520 #define ATA_LED_OFF 0x00
521 #define ATA_LED_RED 0x01
522 #define ATA_LED_GREEN 0x02
523 #define ATA_LED_ORANGE 0x03
524 #define ATA_LED_MASK 0x03
527 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
528 extern devclass_t ata_devclass;
531 /* public prototypes */
533 int ata_probe(device_t dev);
534 int ata_attach(device_t dev);
535 int ata_detach(device_t dev);
536 int ata_reinit(device_t dev);
537 int ata_suspend(device_t dev);
538 int ata_resume(device_t dev);
539 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
540 int ata_identify(device_t dev);
541 void ata_default_registers(device_t dev);
542 void ata_modify_if_48bit(struct ata_request *request);
543 void ata_udelay(int interval);
544 char *ata_mode2str(int mode);
545 int ata_pmode(struct ata_params *ap);
546 int ata_wmode(struct ata_params *ap);
547 int ata_umode(struct ata_params *ap);
548 int ata_limit_mode(device_t dev, int mode, int maxmode);
551 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
552 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
553 void ata_queue_request(struct ata_request *request);
554 void ata_start(device_t dev);
555 void ata_finish(struct ata_request *request);
556 void ata_timeout(struct ata_request *);
557 void ata_catch_inflight(device_t dev);
558 void ata_fail_requests(device_t dev);
559 char *ata_cmd2str(struct ata_request *request);
561 /* ata-lowlevel.c: */
562 void ata_generic_hw(device_t dev);
563 void ata_generic_reset(device_t dev);
564 int ata_generic_command(struct ata_request *request);
566 /* macros for alloc/free of struct ata_request */
567 extern uma_zone_t ata_request_zone;
568 #define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO)
569 #define ata_free_request(request) uma_zfree(ata_request_zone, request)
571 /* macros for alloc/free of struct ata_composite */
572 extern uma_zone_t ata_composite_zone;
573 #define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO)
574 #define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite)
576 MALLOC_DECLARE(M_ATA);
578 /* misc newbus defines */
579 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
581 /* macros to hide busspace uglyness */
582 #define ATA_INB(res, offset) \
583 bus_space_read_1(rman_get_bustag((res)), \
584 rman_get_bushandle((res)), (offset))
586 #define ATA_INW(res, offset) \
587 bus_space_read_2(rman_get_bustag((res)), \
588 rman_get_bushandle((res)), (offset))
589 #define ATA_INL(res, offset) \
590 bus_space_read_4(rman_get_bustag((res)), \
591 rman_get_bushandle((res)), (offset))
592 #define ATA_INSW(res, offset, addr, count) \
593 bus_space_read_multi_2(rman_get_bustag((res)), \
594 rman_get_bushandle((res)), \
595 (offset), (addr), (count))
596 #define ATA_INSW_STRM(res, offset, addr, count) \
597 bus_space_read_multi_stream_2(rman_get_bustag((res)), \
598 rman_get_bushandle((res)), \
599 (offset), (addr), (count))
600 #define ATA_INSL(res, offset, addr, count) \
601 bus_space_read_multi_4(rman_get_bustag((res)), \
602 rman_get_bushandle((res)), \
603 (offset), (addr), (count))
604 #define ATA_INSL_STRM(res, offset, addr, count) \
605 bus_space_read_multi_stream_4(rman_get_bustag((res)), \
606 rman_get_bushandle((res)), \
607 (offset), (addr), (count))
608 #define ATA_OUTB(res, offset, value) \
609 bus_space_write_1(rman_get_bustag((res)), \
610 rman_get_bushandle((res)), (offset), (value))
611 #define ATA_OUTW(res, offset, value) \
612 bus_space_write_2(rman_get_bustag((res)), \
613 rman_get_bushandle((res)), (offset), (value))
614 #define ATA_OUTL(res, offset, value) \
615 bus_space_write_4(rman_get_bustag((res)), \
616 rman_get_bushandle((res)), (offset), (value))
617 #define ATA_OUTSW(res, offset, addr, count) \
618 bus_space_write_multi_2(rman_get_bustag((res)), \
619 rman_get_bushandle((res)), \
620 (offset), (addr), (count))
621 #define ATA_OUTSW_STRM(res, offset, addr, count) \
622 bus_space_write_multi_stream_2(rman_get_bustag((res)), \
623 rman_get_bushandle((res)), \
624 (offset), (addr), (count))
625 #define ATA_OUTSL(res, offset, addr, count) \
626 bus_space_write_multi_4(rman_get_bustag((res)), \
627 rman_get_bushandle((res)), \
628 (offset), (addr), (count))
629 #define ATA_OUTSL_STRM(res, offset, addr, count) \
630 bus_space_write_multi_stream_4(rman_get_bustag((res)), \
631 rman_get_bushandle((res)), \
632 (offset), (addr), (count))
634 #define ATA_IDX_INB(ch, idx) \
635 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
637 #define ATA_IDX_INW(ch, idx) \
638 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
640 #define ATA_IDX_INL(ch, idx) \
641 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
643 #define ATA_IDX_INSW(ch, idx, addr, count) \
644 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
646 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
647 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
649 #define ATA_IDX_INSL(ch, idx, addr, count) \
650 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
652 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
653 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
655 #define ATA_IDX_OUTB(ch, idx, value) \
656 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
658 #define ATA_IDX_OUTW(ch, idx, value) \
659 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
661 #define ATA_IDX_OUTL(ch, idx, value) \
662 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
664 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
665 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
667 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
668 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
670 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
671 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
673 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
674 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)