2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break
33 * some modern devices */
36 /* ATA register defines */
37 #define ATA_DATA 0 /* (RW) data */
39 #define ATA_FEATURE 1 /* (W) feature */
40 #define ATA_F_DMA 0x01 /* enable DMA */
41 #define ATA_F_OVL 0x02 /* enable overlap */
43 #define ATA_COUNT 2 /* (W) sector count */
45 #define ATA_SECTOR 3 /* (RW) sector # */
46 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
47 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
48 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
49 #define ATA_D_LBA 0x40 /* use LBA addressing */
50 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
52 #define ATA_COMMAND 7 /* (W) command */
54 #define ATA_ERROR 8 /* (R) error */
55 #define ATA_E_ILI 0x01 /* illegal length */
56 #define ATA_E_NM 0x02 /* no media */
57 #define ATA_E_ABORT 0x04 /* command aborted */
58 #define ATA_E_MCR 0x08 /* media change request */
59 #define ATA_E_IDNF 0x10 /* ID not found */
60 #define ATA_E_MC 0x20 /* media changed */
61 #define ATA_E_UNC 0x40 /* uncorrectable data */
62 #define ATA_E_ICRC 0x80 /* UDMA crc error */
63 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
65 #define ATA_IREASON 9 /* (R) interrupt reason */
66 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
67 #define ATA_I_IN 0x02 /* read (1) | write (0) */
68 #define ATA_I_RELEASE 0x04 /* released bus (1) */
69 #define ATA_I_TAGMASK 0xf8 /* tag mask */
71 #define ATA_STATUS 10 /* (R) status */
72 #define ATA_ALTSTAT 11 /* (R) alternate status */
73 #define ATA_S_ERROR 0x01 /* error */
74 #define ATA_S_INDEX 0x02 /* index */
75 #define ATA_S_CORR 0x04 /* data corrected */
76 #define ATA_S_DRQ 0x08 /* data request */
77 #define ATA_S_DSC 0x10 /* drive seek completed */
78 #define ATA_S_SERVICE 0x10 /* drive needs service */
79 #define ATA_S_DWF 0x20 /* drive write fault */
80 #define ATA_S_DMA 0x20 /* DMA ready */
81 #define ATA_S_READY 0x40 /* drive ready */
82 #define ATA_S_BUSY 0x80 /* busy */
84 #define ATA_CONTROL 12 /* (W) control */
86 #define ATA_CTLOFFSET 0x206 /* control register offset */
87 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
88 #define ATA_A_IDS 0x02 /* disable interrupts */
89 #define ATA_A_RESET 0x04 /* RESET controller */
90 #ifdef ATA_LEGACY_SUPPORT
91 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */
93 #define ATA_A_4BIT 0x00
95 #define ATA_A_HOB 0x80 /* High Order Byte enable */
97 /* SATA register defines */
98 #define ATA_SSTATUS 13
99 #define ATA_SS_DET_MASK 0x0000000f
100 #define ATA_SS_DET_NO_DEVICE 0x00000000
101 #define ATA_SS_DET_DEV_PRESENT 0x00000001
102 #define ATA_SS_DET_PHY_ONLINE 0x00000003
103 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
105 #define ATA_SS_SPD_MASK 0x000000f0
106 #define ATA_SS_SPD_NO_SPEED 0x00000000
107 #define ATA_SS_SPD_GEN1 0x00000010
108 #define ATA_SS_SPD_GEN2 0x00000020
109 #define ATA_SS_SPD_GEN3 0x00000030
111 #define ATA_SS_IPM_MASK 0x00000f00
112 #define ATA_SS_IPM_NO_DEVICE 0x00000000
113 #define ATA_SS_IPM_ACTIVE 0x00000100
114 #define ATA_SS_IPM_PARTIAL 0x00000200
115 #define ATA_SS_IPM_SLUMBER 0x00000600
117 #define ATA_SERROR 14
118 #define ATA_SE_DATA_CORRECTED 0x00000001
119 #define ATA_SE_COMM_CORRECTED 0x00000002
120 #define ATA_SE_DATA_ERR 0x00000100
121 #define ATA_SE_COMM_ERR 0x00000200
122 #define ATA_SE_PROT_ERR 0x00000400
123 #define ATA_SE_HOST_ERR 0x00000800
124 #define ATA_SE_PHY_CHANGED 0x00010000
125 #define ATA_SE_PHY_IERROR 0x00020000
126 #define ATA_SE_COMM_WAKE 0x00040000
127 #define ATA_SE_DECODE_ERR 0x00080000
128 #define ATA_SE_PARITY_ERR 0x00100000
129 #define ATA_SE_CRC_ERR 0x00200000
130 #define ATA_SE_HANDSHAKE_ERR 0x00400000
131 #define ATA_SE_LINKSEQ_ERR 0x00800000
132 #define ATA_SE_TRANSPORT_ERR 0x01000000
133 #define ATA_SE_UNKNOWN_FIS 0x02000000
135 #define ATA_SCONTROL 15
136 #define ATA_SC_DET_MASK 0x0000000f
137 #define ATA_SC_DET_IDLE 0x00000000
138 #define ATA_SC_DET_RESET 0x00000001
139 #define ATA_SC_DET_DISABLE 0x00000004
141 #define ATA_SC_SPD_MASK 0x000000f0
142 #define ATA_SC_SPD_NO_SPEED 0x00000000
143 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
144 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
145 #define ATA_SC_SPD_SPEED_GEN3 0x00000030
147 #define ATA_SC_IPM_MASK 0x00000f00
148 #define ATA_SC_IPM_NONE 0x00000000
149 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
150 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
152 #define ATA_SACTIVE 16
154 /* DMA register defines */
155 #define ATA_DMA_ENTRIES MAX(17, btoc(maxphys) + 1)
156 #define ATA_DMA_EOT 0x80000000
158 #define ATA_BMCMD_PORT 17
159 #define ATA_BMCMD_START_STOP 0x01
160 #define ATA_BMCMD_WRITE_READ 0x08
162 #define ATA_BMDEVSPEC_0 18
163 #define ATA_BMSTAT_PORT 19
164 #define ATA_BMSTAT_ACTIVE 0x01
165 #define ATA_BMSTAT_ERROR 0x02
166 #define ATA_BMSTAT_INTERRUPT 0x04
167 #define ATA_BMSTAT_MASK 0x07
168 #define ATA_BMSTAT_DMA_MASTER 0x20
169 #define ATA_BMSTAT_DMA_SLAVE 0x40
170 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
172 #define ATA_BMDEVSPEC_1 20
173 #define ATA_BMDTP_PORT 21
175 #define ATA_IDX_ADDR 22
176 #define ATA_IDX_DATA 23
177 #define ATA_MAX_RES 24
180 #define ATA_PRIMARY 0x1f0
181 #define ATA_SECONDARY 0x170
182 #define ATA_IOSIZE 0x08
183 #define ATA_CTLIOSIZE 0x01
184 #define ATA_BMIOSIZE 0x08
185 #define ATA_IOADDR_RID 0
186 #define ATA_CTLADDR_RID 1
187 #define ATA_BMADDR_RID 0x20
188 #define ATA_IRQ_RID 0
189 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0)
190 #define ATA_CFA_MAGIC1 0x844A
191 #define ATA_CFA_MAGIC2 0x848A
192 #define ATA_CFA_MAGIC3 0x8400
193 #define ATAPI_MAGIC_LSB 0x14
194 #define ATAPI_MAGIC_MSB 0xeb
195 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
196 #define ATAPI_P_WRITE (ATA_S_DRQ)
197 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
198 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
199 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
200 #define ATAPI_P_ABORT 0
201 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
202 #define ATA_OP_CONTINUES 0
203 #define ATA_OP_FINISHED 1
204 #define ATA_MAX_28BIT_LBA 268435455UL
206 /* structure used for composite atomic operations */
207 #define MAX_COMPOSITES 32 /* u_int32_t bits */
208 struct ata_composite {
209 struct mtx lock; /* control lock */
210 u_int32_t rd_needed; /* needed read subdisks */
211 u_int32_t rd_done; /* done read subdisks */
212 u_int32_t wr_needed; /* needed write subdisks */
213 u_int32_t wr_depend; /* write depends on subdisks */
214 u_int32_t wr_done; /* done write subdisks */
215 struct ata_request *request[MAX_COMPOSITES];
216 u_int32_t residual; /* bytes still to transfer */
221 /* structure used to queue an ATA/ATAPI request */
223 device_t dev; /* device handle */
224 device_t parent; /* channel handle */
225 int unit; /* physical unit */
228 u_int8_t command; /* command reg */
229 u_int16_t feature; /* feature reg */
230 u_int16_t count; /* count reg */
231 u_int64_t lba; /* lba reg */
234 u_int8_t ccb[16]; /* ATAPI command block */
235 struct atapi_sense sense; /* ATAPI request sense data */
236 u_int8_t saved_cmd; /* ATAPI saved command */
239 u_int32_t bytecount; /* bytes to transfer */
240 u_int32_t transfersize; /* bytes pr transfer */
241 caddr_t data; /* pointer to data buf */
242 u_int32_t tag; /* HW tag of this request */
244 #define ATA_R_CONTROL 0x00000001
245 #define ATA_R_READ 0x00000002
246 #define ATA_R_WRITE 0x00000004
247 #define ATA_R_ATAPI 0x00000008
248 #define ATA_R_DMA 0x00000010
249 #define ATA_R_QUIET 0x00000020
250 #define ATA_R_TIMEOUT 0x00000040
251 #define ATA_R_48BIT 0x00000080
253 #define ATA_R_ORDERED 0x00000100
254 #define ATA_R_AT_HEAD 0x00000200
255 #define ATA_R_REQUEUE 0x00000400
256 #define ATA_R_THREAD 0x00000800
257 #define ATA_R_DIRECT 0x00001000
258 #define ATA_R_NEEDRESULT 0x00002000
259 #define ATA_R_DATA_IN_CCB 0x00004000
261 #define ATA_R_ATAPI16 0x00010000
262 #define ATA_R_ATAPI_INTR 0x00020000
264 #define ATA_R_DEBUG 0x10000000
265 #define ATA_R_DANGER1 0x20000000
266 #define ATA_R_DANGER2 0x40000000
268 struct ata_dmaslot *dma; /* DMA slot of this request */
269 u_int8_t status; /* ATA status */
270 u_int8_t error; /* ATA error */
271 u_int32_t donecount; /* bytes transferred */
272 int result; /* result error code */
273 void (*callback)(struct ata_request *request);
274 struct sema done; /* request done sema */
275 int retries; /* retry count */
276 int timeout; /* timeout for this cmd */
277 struct callout callout; /* callout management */
278 struct task task; /* task management */
279 struct bio *bio; /* bio for this request */
280 int this; /* this request ID */
281 struct ata_composite *composite; /* for composite atomic ops */
282 void *driver; /* driver specific */
283 TAILQ_ENTRY(ata_request) chain; /* list management */
287 /* define this for debugging request processing */
289 #define ATA_DEBUG_RQ(request, string) \
291 if (request->flags & ATA_R_DEBUG) \
292 device_printf(request->parent, "req=%p %s " string "\n", \
293 request, ata_cmd2str(request)); \
296 #define ATA_DEBUG_RQ(request, string)
299 /* structure describing an ATA/ATAPI device */
301 device_t dev; /* device handle */
302 int unit; /* physical unit */
303 #define ATA_MASTER 0x00
304 #define ATA_SLAVE 0x01
307 struct ata_params param; /* ata param structure */
308 int mode; /* current transfermode */
309 u_int32_t max_iosize; /* max IO size */
310 int spindown; /* idle spindown timeout */
311 struct callout spindown_timer;
314 #define ATA_D_USE_CHS 0x0001
315 #define ATA_D_MEDIA_CHANGED 0x0002
316 #define ATA_D_ENC_PRESENT 0x0004
319 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
320 struct ata_dma_prdentry {
325 /* structure used by the setprd function */
326 struct ata_dmasetprd_args {
333 u_int8_t status; /* DMA status */
334 bus_dma_tag_t sg_tag; /* SG list DMA tag */
335 bus_dmamap_t sg_map; /* SG list DMA map */
336 void *sg; /* DMA transfer table */
337 bus_addr_t sg_bus; /* bus address of dmatab */
338 bus_dma_tag_t data_tag; /* data DMA tag */
339 bus_dmamap_t data_map; /* data DMA map */
342 /* structure holding DMA related information */
344 bus_dma_tag_t dmatag; /* parent DMA tag */
345 bus_dma_tag_t work_tag; /* workspace DMA tag */
346 bus_dmamap_t work_map; /* workspace DMA map */
347 u_int8_t *work; /* workspace */
348 bus_addr_t work_bus; /* bus address of dmatab */
350 #define ATA_DMA_SLOTS 1
351 int dma_slots; /* DMA slots allocated */
352 struct ata_dmaslot slot[ATA_DMA_SLOTS];
353 u_int32_t alignment; /* DMA SG list alignment */
354 u_int32_t boundary; /* DMA SG list boundary */
355 u_int32_t segsize; /* DMA SG list segment size */
356 u_int32_t max_iosize; /* DMA data max IO size */
357 u_int64_t max_address; /* highest DMA'able address */
359 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */
361 void (*alloc)(device_t dev);
362 void (*free)(device_t dev);
363 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
364 int (*load)(struct ata_request *request, void *addr, int *nsegs);
365 int (*unload)(struct ata_request *request);
366 int (*start)(struct ata_request *request);
367 int (*stop)(struct ata_request *request);
368 void (*reset)(device_t dev);
371 /* structure holding lowlevel functions */
372 struct ata_lowlevel {
373 u_int32_t (*softreset)(device_t dev, int pmport);
374 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result);
375 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value);
376 int (*status)(device_t dev);
377 int (*begin_transaction)(struct ata_request *request);
378 int (*end_transaction)(struct ata_request *request);
379 int (*command)(struct ata_request *request);
380 void (*tf_read)(struct ata_request *request);
381 void (*tf_write)(struct ata_request *request);
384 /* structure holding resources for an ATA channel */
385 struct ata_resource {
386 struct resource *res;
390 struct ata_cam_device {
398 /* structure describing an ATA channel */
400 device_t dev; /* device handle */
401 int unit; /* physical channel */
402 int attached; /* channel is attached */
403 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
404 struct resource *r_irq; /* interrupt of this channel */
405 void *ih; /* interrupt handle */
406 struct ata_lowlevel hw; /* lowlevel HW functions */
407 struct ata_dma dma; /* DMA data / functions */
408 int flags; /* channel flags */
409 #define ATA_NO_SLAVE 0x01
410 #define ATA_USE_16BIT 0x02
411 #define ATA_ATAPI_DMA_RO 0x04
412 #define ATA_NO_48BIT_DMA 0x08
413 #define ATA_ALWAYS_DMASTAT 0x10
414 #define ATA_CHECKS_CABLE 0x20
415 #define ATA_NO_ATAPI_DMA 0x40
416 #define ATA_SATA 0x80
417 #define ATA_DMA_BEFORE_CMD 0x100
418 #define ATA_KNOWN_PRESENCE 0x200
419 #define ATA_STATUS_IS_LONG 0x400
420 #define ATA_PERIODIC_POLL 0x800
422 int pm_level; /* power management level */
423 int devices; /* what is present */
424 #define ATA_ATA_MASTER 0x00000001
425 #define ATA_ATA_SLAVE 0x00000002
426 #define ATA_PORTMULTIPLIER 0x00008000
427 #define ATA_ATAPI_MASTER 0x00010000
428 #define ATA_ATAPI_SLAVE 0x00020000
430 struct mtx state_mtx; /* state lock */
431 int state; /* ATA channel state */
432 #define ATA_IDLE 0x0000
433 #define ATA_ACTIVE 0x0001
434 #define ATA_STALL_QUEUE 0x0002
436 struct ata_request *running; /* currently running request */
437 struct task conntask; /* PHY events handling task */
439 struct cam_path *path;
440 struct ata_cam_device user[16]; /* User-specified settings */
441 struct ata_cam_device curr[16]; /* Current settings */
442 int requestsense; /* CCB waiting for SENSE. */
443 struct callout poll_callout; /* Periodic status poll. */
444 struct ata_request request;
447 /* disk bay/enclosure related */
448 #define ATA_LED_OFF 0x00
449 #define ATA_LED_RED 0x01
450 #define ATA_LED_GREEN 0x02
451 #define ATA_LED_ORANGE 0x03
452 #define ATA_LED_MASK 0x03
455 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
456 extern struct intr_config_hook *ata_delayed_attach;
457 extern devclass_t ata_devclass;
459 extern int ata_setmax;
460 extern int ata_dma_check_80pin;
462 /* public prototypes */
464 int ata_probe(device_t dev);
465 int ata_attach(device_t dev);
466 int ata_detach(device_t dev);
467 int ata_reinit(device_t dev);
468 int ata_suspend(device_t dev);
469 int ata_resume(device_t dev);
470 void ata_interrupt(void *data);
471 int ata_getparam(struct ata_device *atadev, int init);
472 void ata_default_registers(device_t dev);
473 void ata_udelay(int interval);
474 const char *ata_cmd2str(struct ata_request *request);
475 const char *ata_mode2str(int mode);
476 void ata_setmode(device_t dev);
477 void ata_print_cable(device_t dev, u_int8_t *who);
478 int ata_atapi(device_t dev, int target);
479 void ata_timeout(void *);
481 /* ata-lowlevel.c: */
482 void ata_generic_hw(device_t dev);
483 int ata_begin_transaction(struct ata_request *);
484 int ata_end_transaction(struct ata_request *);
485 void ata_generic_reset(device_t dev);
486 int ata_generic_command(struct ata_request *request);
489 void ata_dmainit(device_t);
490 void ata_dmafini(device_t dev);
493 void ata_sata_phy_check_events(device_t dev, int port);
494 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val);
495 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val);
496 int ata_sata_phy_reset(device_t dev, int port, int quick);
497 int ata_sata_setmode(device_t dev, int target, int mode);
498 int ata_sata_getrev(device_t dev, int target);
499 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
500 void ata_pm_identify(device_t dev);
502 MALLOC_DECLARE(M_ATA);
504 /* misc newbus defines */
505 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
507 /* macros to hide busspace uglyness */
508 #define ATA_INB(res, offset) \
509 bus_read_1((res), (offset))
511 #define ATA_INW(res, offset) \
512 bus_read_2((res), (offset))
513 #define ATA_INW_STRM(res, offset) \
514 bus_read_stream_2((res), (offset))
515 #define ATA_INL(res, offset) \
516 bus_read_4((res), (offset))
517 #define ATA_INSW(res, offset, addr, count) \
518 bus_read_multi_2((res), (offset), (addr), (count))
519 #define ATA_INSW_STRM(res, offset, addr, count) \
520 bus_read_multi_stream_2((res), (offset), (addr), (count))
521 #define ATA_INSL(res, offset, addr, count) \
522 bus_read_multi_4((res), (offset), (addr), (count))
523 #define ATA_INSL_STRM(res, offset, addr, count) \
524 bus_read_multi_stream_4((res), (offset), (addr), (count))
525 #define ATA_OUTB(res, offset, value) \
526 bus_write_1((res), (offset), (value))
527 #define ATA_OUTW(res, offset, value) \
528 bus_write_2((res), (offset), (value))
529 #define ATA_OUTW_STRM(res, offset, value) \
530 bus_write_stream_2((res), (offset), (value))
531 #define ATA_OUTL(res, offset, value) \
532 bus_write_4((res), (offset), (value))
533 #define ATA_OUTSW(res, offset, addr, count) \
534 bus_write_multi_2((res), (offset), (addr), (count))
535 #define ATA_OUTSW_STRM(res, offset, addr, count) \
536 bus_write_multi_stream_2((res), (offset), (addr), (count))
537 #define ATA_OUTSL(res, offset, addr, count) \
538 bus_write_multi_4((res), (offset), (addr), (count))
539 #define ATA_OUTSL_STRM(res, offset, addr, count) \
540 bus_write_multi_stream_4((res), (offset), (addr), (count))
542 #define ATA_IDX_INB(ch, idx) \
543 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
545 #define ATA_IDX_INW(ch, idx) \
546 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
548 #define ATA_IDX_INW_STRM(ch, idx) \
549 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset)
551 #define ATA_IDX_INL(ch, idx) \
552 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
554 #define ATA_IDX_INSW(ch, idx, addr, count) \
555 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
557 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
558 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
560 #define ATA_IDX_INSL(ch, idx, addr, count) \
561 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
563 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
564 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
566 #define ATA_IDX_OUTB(ch, idx, value) \
567 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
569 #define ATA_IDX_OUTW(ch, idx, value) \
570 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
572 #define ATA_IDX_OUTW_STRM(ch, idx, value) \
573 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value)
575 #define ATA_IDX_OUTL(ch, idx, value) \
576 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
578 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
579 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
581 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
582 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
584 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
585 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
587 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
588 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)