2 * Copyright (c) 1998 - 2003 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/taskqueue.h>
41 #include <machine/stdarg.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/ata/ata-all.h>
48 #include <dev/ata/ata-pci.h>
51 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
52 #define ATAPI_DEVICE(atadev) \
53 ((atadev->unit == ATA_MASTER && \
54 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
55 (atadev->unit == ATA_SLAVE && \
56 atadev->channel->devices & ATA_ATAPI_SLAVE))
58 /* local prototypes */
59 static int ata_generic_chipinit(device_t);
60 static void ata_generic_intr(void *);
61 static void ata_generic_setmode(struct ata_device *, int);
62 static int ata_acard_chipinit(device_t);
63 static void ata_acard_intr(void *);
64 static void ata_acard_850_setmode(struct ata_device *, int);
65 static void ata_acard_86X_setmode(struct ata_device *, int);
66 static int ata_ali_chipinit(device_t);
67 static void ata_ali_setmode(struct ata_device *, int);
68 static int ata_amd_chipinit(device_t);
69 static int ata_cyrix_chipinit(device_t);
70 static void ata_cyrix_setmode(struct ata_device *, int);
71 static int ata_cypress_chipinit(device_t);
72 static void ata_cypress_setmode(struct ata_device *, int);
73 static int ata_highpoint_chipinit(device_t);
74 static void ata_highpoint_intr(void *);
75 static void ata_highpoint_setmode(struct ata_device *, int);
76 static int ata_highpoint_check_80pin(struct ata_device *, int);
77 static int ata_intel_chipinit(device_t);
78 static void ata_intel_old_setmode(struct ata_device *, int);
79 static void ata_intel_new_setmode(struct ata_device *, int);
80 static int ata_national_chipinit(device_t);
81 static void ata_national_setmode(struct ata_device *, int);
82 static int ata_nvidia_chipinit(device_t);
83 static int ata_via_chipinit(device_t);
84 static void ata_via_family_setmode(struct ata_device *, int);
85 static void ata_via_southbridge_fixup(device_t);
86 static int ata_promise_chipinit(device_t);
87 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
88 static void ata_promise_old_intr(void *);
89 static void ata_promise_tx2_intr(void *);
90 static void ata_promise_mio_intr(void *);
91 static void ata_promise_setmode(struct ata_device *, int);
92 static void ata_promise_new_dmainit(struct ata_channel *);
93 static int ata_promise_new_dmastart(struct ata_channel *);
94 static int ata_promise_new_dmastop(struct ata_channel *);
95 static void ata_promise_mio_dmainit(struct ata_channel *);
96 static int ata_promise_mio_dmastart(struct ata_channel *);
97 static int ata_promise_mio_dmastop(struct ata_channel *);
98 static int ata_serverworks_chipinit(device_t);
99 static void ata_serverworks_setmode(struct ata_device *, int);
100 static int ata_sii_chipinit(device_t);
101 static int ata_sii_mio_allocate(device_t, struct ata_channel *);
102 static void ata_sii_intr(void *);
103 static void ata_cmd_intr(void *);
104 static void ata_sii_setmode(struct ata_device *, int);
105 static void ata_cmd_setmode(struct ata_device *, int);
106 static int ata_sis_chipinit(device_t);
107 static void ata_sis_setmode(struct ata_device *, int);
108 static int ata_check_80pin(struct ata_device *, int);
109 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
110 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
111 static int ata_setup_interrupt(device_t);
112 static void ata_serialize(struct ata_channel *, int);
113 static int ata_mode2idx(int);
115 /* generic or unknown ATA chipset init code */
117 ata_generic_ident(device_t dev)
119 struct ata_pci_controller *ctlr = device_get_softc(dev);
121 device_set_desc(dev, "GENERIC ATA controller");
122 ctlr->chipinit = ata_generic_chipinit;
127 ata_generic_chipinit(device_t dev)
129 struct ata_pci_controller *ctlr = device_get_softc(dev);
131 if (ata_setup_interrupt(dev))
133 ctlr->setmode = ata_generic_setmode;
138 ata_generic_intr(void *data)
140 struct ata_pci_controller *ctlr = data;
141 struct ata_channel *ch;
144 /* implement this as a toggle instead to balance load XXX */
145 for (unit = 0; unit < 2; unit++) {
146 if (!(ch = ctlr->interrupt[unit].argument))
149 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
151 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
152 ATA_BMSTAT_INTERRUPT)
154 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
157 ctlr->interrupt[unit].function(ch);
162 ata_generic_setmode(struct ata_device *atadev, int mode)
164 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
165 mode = ata_check_80pin(atadev, mode);
166 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
171 ata_sata_setmode(struct ata_device *atadev, int mode)
173 mode = ata_limit_mode(atadev, mode, ATA_DMA_MAX);
174 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
179 * Acard chipset support functions
182 ata_acard_ident(device_t dev)
184 struct ata_pci_controller *ctlr = device_get_softc(dev);
185 struct ata_chip_id *idx;
186 static struct ata_chip_id ids[] =
187 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
188 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
189 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
190 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
191 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
192 { 0, 0, 0, 0, 0, 0}};
195 if (!(idx = ata_match_chip(dev, ids)))
198 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
199 device_set_desc_copy(dev, buffer);
201 ctlr->chipinit = ata_acard_chipinit;
206 ata_acard_chipinit(device_t dev)
208 struct ata_pci_controller *ctlr = device_get_softc(dev);
209 int rid = ATA_IRQ_RID;
211 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
212 RF_SHAREABLE | RF_ACTIVE))) {
213 device_printf(dev, "unable to map interrupt\n");
216 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
217 ata_acard_intr, ctlr, &ctlr->handle))) {
218 device_printf(dev, "unable to setup interrupt\n");
221 if (ctlr->chip->cfg1 == ATPOLD) {
222 ctlr->setmode = ata_acard_850_setmode;
223 ctlr->locking = ata_serialize;
226 ctlr->setmode = ata_acard_86X_setmode;
231 ata_acard_intr(void *data)
233 struct ata_pci_controller *ctlr = data;
234 struct ata_channel *ch;
237 /* implement this as a toggle instead to balance load XXX */
238 for (unit = 0; unit < 2; unit++) {
239 if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
241 if (!(ch = ctlr->interrupt[unit].argument))
244 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
246 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
247 ATA_BMSTAT_INTERRUPT)
249 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
251 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
252 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
255 ctlr->interrupt[unit].function(ch);
260 ata_acard_850_setmode(struct ata_device *atadev, int mode)
262 device_t parent = device_get_parent(atadev->channel->dev);
263 struct ata_pci_controller *ctlr = device_get_softc(parent);
264 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
267 mode = ata_limit_mode(atadev, mode,
268 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
270 /* XXX missing WDMA0+1 + PIO modes */
271 if (mode >= ATA_WDMA2) {
272 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
274 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
275 (error) ? "FAILURE " : "",
276 ata_mode2str(mode), ctlr->chip->text);
278 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
280 reg54 &= ~(0x03 << (devno << 1));
281 if (mode >= ATA_UDMA0)
282 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
283 pci_write_config(parent, 0x54, reg54, 1);
284 pci_write_config(parent, 0x4a, 0xa6, 1);
285 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
290 /* we could set PIO mode timings, but we assume the BIOS did that */
294 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
296 device_t parent = device_get_parent(atadev->channel->dev);
297 struct ata_pci_controller *ctlr = device_get_softc(parent);
298 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
302 mode = ata_limit_mode(atadev, mode,
303 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
305 mode = ata_check_80pin(atadev, mode);
307 /* XXX missing WDMA0+1 + PIO modes */
308 if (mode >= ATA_WDMA2) {
309 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
311 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
312 (error) ? "FAILURE " : "",
313 ata_mode2str(mode), ctlr->chip->text);
315 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
317 reg44 &= ~(0x000f << (devno << 2));
318 if (mode >= ATA_UDMA0)
319 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
320 pci_write_config(parent, 0x44, reg44, 2);
321 pci_write_config(parent, 0x4a, 0xa6, 1);
322 pci_write_config(parent, 0x40 + devno, 0x31, 1);
327 /* we could set PIO mode timings, but we assume the BIOS did that */
331 * Acer Labs Inc (ALI) chipset support functions
334 ata_ali_ident(device_t dev)
336 struct ata_pci_controller *ctlr = device_get_softc(dev);
337 struct ata_chip_id *idx;
338 static struct ata_chip_id ids[] =
339 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
340 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
341 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
342 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
343 { 0, 0, 0, 0, 0, 0}};
346 if (!(idx = ata_match_chip(dev, ids)))
349 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
350 device_set_desc_copy(dev, buffer);
352 ctlr->chipinit = ata_ali_chipinit;
357 ata_ali_chipinit(device_t dev)
359 struct ata_pci_controller *ctlr = device_get_softc(dev);
361 if (ata_setup_interrupt(dev))
364 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
365 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
367 /* enable cable detection and UDMA support on newer chips */
368 if (ctlr->chip->cfg2 & ALINEW)
369 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
370 ctlr->setmode = ata_ali_setmode;
375 ata_ali_setmode(struct ata_device *atadev, int mode)
377 device_t parent = device_get_parent(atadev->channel->dev);
378 struct ata_pci_controller *ctlr = device_get_softc(parent);
379 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
382 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
384 if (ctlr->chip->cfg2 & ALINEW) {
385 if (mode > ATA_UDMA2 &&
386 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
388 "DMA limited to UDMA33, non-ATA66 cable or device\n");
393 mode = ata_check_80pin(atadev, mode);
395 if (ctlr->chip->cfg2 & ALIOLD) {
396 /* doesn't support ATAPI DMA on write */
397 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
398 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
399 atadev->channel->devices & ATA_ATAPI_SLAVE) {
400 /* doesn't support ATAPI DMA on two ATAPI devices */
401 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
402 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
406 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
409 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
410 (error) ? "FAILURE " : "",
411 ata_mode2str(mode), ctlr->chip->text);
413 if (mode >= ATA_UDMA0) {
414 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
415 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
417 word54 &= ~(0x000f000f << (devno << 2));
418 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
419 pci_write_config(parent, 0x54, word54, 4);
420 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
424 u_int32_t piotimings[] =
425 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
426 0x00310001, 0x00440001, 0x00330001, 0x00310001};
428 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
429 ~(0x0008000f << (devno << 2)), 4);
430 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
431 piotimings[ata_mode2idx(mode)], 4);
438 * American Micro Devices (AMD) support function
441 ata_amd_ident(device_t dev)
443 struct ata_pci_controller *ctlr = device_get_softc(dev);
444 struct ata_chip_id *idx;
445 static struct ata_chip_id ids[] =
446 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
447 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
448 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
449 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
450 { 0, 0, 0, 0, 0, 0}};
453 if (!(idx = ata_match_chip(dev, ids)))
456 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
457 device_set_desc_copy(dev, buffer);
459 ctlr->chipinit = ata_amd_chipinit;
464 ata_amd_chipinit(device_t dev)
466 struct ata_pci_controller *ctlr = device_get_softc(dev);
468 if (ata_setup_interrupt(dev))
471 /* set prefetch, postwrite */
472 if (ctlr->chip->cfg2 & AMDBUG)
473 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
475 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
477 ctlr->setmode = ata_via_family_setmode;
482 * Cyrix chipset support functions
485 ata_cyrix_ident(device_t dev)
487 struct ata_pci_controller *ctlr = device_get_softc(dev);
489 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
490 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
491 ctlr->chipinit = ata_cyrix_chipinit;
498 ata_cyrix_chipinit(device_t dev)
500 struct ata_pci_controller *ctlr = device_get_softc(dev);
502 if (ata_setup_interrupt(dev))
506 ctlr->setmode = ata_cyrix_setmode;
508 ctlr->setmode = ata_generic_setmode;
513 ata_cyrix_setmode(struct ata_device *atadev, int mode)
515 struct ata_channel *ch = atadev->channel;
516 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
517 u_int32_t piotiming[] =
518 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
519 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
520 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
523 atadev->channel->dma->alignment = 16;
524 atadev->channel->dma->max_iosize = 63 * 1024;
526 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
528 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
531 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
532 (error) ? "FAILURE " : "", ata_mode2str(mode));
534 if (mode >= ATA_UDMA0) {
535 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
536 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
538 else if (mode >= ATA_WDMA0) {
539 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
540 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
544 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
551 * Cypress chipset support functions
554 ata_cypress_ident(device_t dev)
556 struct ata_pci_controller *ctlr = device_get_softc(dev);
559 * the Cypress chip is a mess, it contains two ATA functions, but
560 * both channels are visible on the first one.
561 * simply ignore the second function for now, as the right
562 * solution (ignoring the second channel on the first function)
563 * doesn't work with the crappy ATA interrupt setup on the alpha.
565 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
566 pci_get_function(dev) == 1 &&
567 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
568 device_set_desc(dev, "Cypress 82C693 ATA controller");
569 ctlr->chipinit = ata_cypress_chipinit;
576 ata_cypress_chipinit(device_t dev)
578 struct ata_pci_controller *ctlr = device_get_softc(dev);
580 if (ata_setup_interrupt(dev))
583 ctlr->setmode = ata_cypress_setmode;
588 ata_cypress_setmode(struct ata_device *atadev, int mode)
590 device_t parent = device_get_parent(atadev->channel->dev);
593 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
595 /* XXX missing WDMA0+1 + PIO modes */
596 if (mode == ATA_WDMA2) {
597 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
599 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
600 error ? "FAILURE " : "");
602 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
607 /* we could set PIO mode timings, but we assume the BIOS did that */
611 * HighPoint chipset support functions
614 ata_highpoint_ident(device_t dev)
616 struct ata_pci_controller *ctlr = device_get_softc(dev);
617 struct ata_chip_id *idx;
618 static struct ata_chip_id ids[] =
619 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
620 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
621 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
622 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
623 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
624 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
625 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
626 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
627 { 0, 0, 0, 0, 0, 0}};
630 if (!(idx = ata_match_chip(dev, ids)))
633 strcpy(buffer, idx->text);
634 if (idx->cfg1 == HPT374) {
635 if (pci_get_function(dev) == 0)
636 strcat(buffer, " (channel 0+1)");
637 else if (pci_get_function(dev) == 1)
638 strcat(buffer, " (channel 2+3)");
640 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
641 device_set_desc_copy(dev, buffer);
643 ctlr->chipinit = ata_highpoint_chipinit;
648 ata_highpoint_chipinit(device_t dev)
650 struct ata_pci_controller *ctlr = device_get_softc(dev);
651 int rid = ATA_IRQ_RID;
653 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
654 RF_SHAREABLE | RF_ACTIVE))) {
655 device_printf(dev, "unable to map interrupt\n");
658 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
659 ata_highpoint_intr, ctlr, &ctlr->handle))) {
660 device_printf(dev, "unable to setup interrupt\n");
664 if (ctlr->chip->cfg2 == HPTOLD) {
665 /* turn off interrupt prediction */
666 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
669 /* turn off interrupt prediction */
670 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
671 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
673 /* turn on interrupts */
674 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
677 if (ctlr->chip->cfg1 < HPT372)
678 pci_write_config(dev, 0x5b, 0x22, 1);
680 pci_write_config(dev, 0x5b,
681 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
683 ctlr->setmode = ata_highpoint_setmode;
688 ata_highpoint_intr(void *data)
690 struct ata_pci_controller *ctlr = data;
691 struct ata_channel *ch;
694 /* implement this as a toggle instead to balance load XXX */
695 for (unit = 0; unit < 2; unit++) {
696 if (!(ch = ctlr->interrupt[unit].argument))
699 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
701 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
702 ATA_BMSTAT_INTERRUPT)
704 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
707 ctlr->interrupt[unit].function(ch);
712 ata_highpoint_setmode(struct ata_device *atadev, int mode)
714 device_t parent = device_get_parent(atadev->channel->dev);
715 struct ata_pci_controller *ctlr = device_get_softc(parent);
716 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
718 u_int32_t timings33[][4] = {
719 /* HPT366 HPT370 HPT372 HPT374 mode */
720 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
721 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
722 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
723 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
724 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
725 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
726 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
727 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
728 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
729 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
730 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
731 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
732 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
733 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
734 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
737 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
739 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
740 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
742 mode = ata_highpoint_check_80pin(atadev, mode);
744 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
747 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
748 (error) ? "FAILURE " : "", ata_mode2str(mode));
750 pci_write_config(parent, 0x40 + (devno << 2),
751 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
756 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
758 device_t parent = device_get_parent(atadev->channel->dev);
759 struct ata_pci_controller *ctlr = device_get_softc(parent);
760 u_int8_t reg, val, res;
762 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
763 reg = atadev->channel->unit ? 0x57 : 0x53;
764 val = pci_read_config(parent, reg, 1);
765 pci_write_config(parent, reg, val | 0x80, 1);
769 val = pci_read_config(parent, reg, 1);
770 pci_write_config(parent, reg, val & 0xfe, 1);
772 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
773 pci_write_config(parent, reg, val, 1);
775 if (mode > ATA_UDMA2 && res) {
776 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
783 * Intel chipset support functions
786 ata_intel_ident(device_t dev)
788 struct ata_pci_controller *ctlr = device_get_softc(dev);
789 struct ata_chip_id *idx;
790 static struct ata_chip_id ids[] =
791 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
792 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
793 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
794 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
795 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
796 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
797 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
798 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
799 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
800 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
801 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
802 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
803 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
804 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
805 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
806 { ATA_I82801EB_1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
807 { 0, 0, 0, 0, 0, 0}};
810 if (!(idx = ata_match_chip(dev, ids)))
813 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
814 device_set_desc_copy(dev, buffer);
816 ctlr->chipinit = ata_intel_chipinit;
821 ata_intel_chipinit(device_t dev)
823 struct ata_pci_controller *ctlr = device_get_softc(dev);
825 if (ata_setup_interrupt(dev))
828 if (ctlr->chip->chipid == ATA_I82371FB)
829 ctlr->setmode = ata_intel_old_setmode;
830 else if (ctlr->chip->max_dma < ATA_SA150)
831 ctlr->setmode = ata_intel_new_setmode;
833 ctlr->setmode = ata_sata_setmode;
838 ata_intel_old_setmode(struct ata_device *atadev, int mode)
844 ata_intel_new_setmode(struct ata_device *atadev, int mode)
846 device_t parent = device_get_parent(atadev->channel->dev);
847 struct ata_pci_controller *ctlr = device_get_softc(parent);
848 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
849 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
850 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
851 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
852 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
853 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
854 u_int32_t mask40 = 0, new40 = 0;
855 u_int8_t mask44 = 0, new44 = 0;
857 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
858 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
860 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
862 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
863 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
867 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
870 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
871 (error) ? "FAILURE " : "",
872 ata_mode2str(mode), ctlr->chip->text);
876 if (mode >= ATA_UDMA0) {
877 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
878 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
879 (0x01 + !(mode & 0x01)), 2);
882 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
883 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
885 if (mode >= ATA_UDMA2)
886 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
888 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
890 if (mode >= ATA_UDMA5)
891 pci_write_config(parent, 0x54, reg54 | (0x10000 << devno), 2);
893 pci_write_config(parent, 0x54, reg54 & ~(0x10000 << devno), 2);
895 reg40 &= ~0x00ff00ff;
898 if (atadev->unit == ATA_MASTER) {
900 new40 = timings[ata_mode2idx(mode)] << 8;
904 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
905 (timings[ata_mode2idx(mode)] & 0x03);
907 if (atadev->channel->unit) {
913 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
914 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
920 * National chipset support functions
923 ata_national_ident(device_t dev)
925 struct ata_pci_controller *ctlr = device_get_softc(dev);
927 /* this chip is a clone of the Cyrix chip, bugs and all */
928 if (pci_get_devid(dev) == ATA_SC1100) {
929 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
930 ctlr->chipinit = ata_national_chipinit;
936 static device_t nat_host = NULL;
939 ata_national_chipinit(device_t dev)
941 struct ata_pci_controller *ctlr = device_get_softc(dev);
945 if (ata_setup_interrupt(dev))
948 /* locate the ISA part in the southbridge and enable UDMA33 */
949 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
950 for (i = 0; i < nchildren; i++) {
951 if (pci_get_devid(children[i]) == 0x0510100b) {
952 nat_host = children[i];
956 free(children, M_TEMP);
958 ctlr->setmode = ata_national_setmode;
963 ata_national_setmode(struct ata_device *atadev, int mode)
965 device_t parent = device_get_parent(atadev->channel->dev);
966 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
967 u_int32_t piotiming[] =
968 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
969 0x00803020, 0x20102010, 0x00100010,
970 0x00100010, 0x00100010, 0x00100010 };
971 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
972 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
975 atadev->channel->dma->alignment = 16;
976 atadev->channel->dma->max_iosize = 63 * 1024;
978 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
980 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
983 ata_prtdev(atadev, "%s setting %s on National chip\n",
984 (error) ? "failed" : "success", ata_mode2str(mode));
986 if (mode >= ATA_UDMA0) {
987 pci_write_config(parent, 0x44 + (devno << 3),
988 udmatiming[mode & ATA_MODE_MASK], 4);
990 else if (mode >= ATA_WDMA0) {
991 pci_write_config(parent, 0x44 + (devno << 3),
992 dmatiming[mode & ATA_MODE_MASK], 4);
995 pci_write_config(parent, 0x44 + (devno << 3),
996 pci_read_config(parent, 0x44 + (devno << 3), 4) |
999 pci_write_config(parent, 0x40 + (devno << 3),
1000 piotiming[ata_mode2idx(mode)], 4);
1001 atadev->mode = mode;
1006 * nVidia chipset support functions
1009 ata_nvidia_ident(device_t dev)
1011 struct ata_pci_controller *ctlr = device_get_softc(dev);
1012 struct ata_chip_id *idx;
1013 static struct ata_chip_id ids[] =
1014 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA5, "nVidia nForce" },
1015 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce2" },
1016 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1017 { 0, 0, 0, 0, 0, 0}};
1020 if (!(idx = ata_match_chip(dev, ids)))
1023 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1024 device_set_desc_copy(dev, buffer);
1026 ctlr->chipinit = ata_nvidia_chipinit;
1031 ata_nvidia_chipinit(device_t dev)
1033 struct ata_pci_controller *ctlr = device_get_softc(dev);
1035 if (ata_setup_interrupt(dev))
1038 /* set prefetch, postwrite */
1039 if (ctlr->chip->cfg2 & AMDBUG)
1040 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1042 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) | 0xf0, 1);
1044 ctlr->setmode = ata_via_family_setmode;
1049 * Promise chipset support functions
1052 ata_promise_ident(device_t dev)
1054 struct ata_pci_controller *ctlr = device_get_softc(dev);
1055 struct ata_chip_id *idx;
1056 static struct ata_chip_id ids[] =
1057 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1058 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1059 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1060 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1061 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1062 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1063 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1064 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1065 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1066 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1067 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1068 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1069 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1070 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1071 { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" },
1072 { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" },
1073 { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" },
1074 { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" },
1075 { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" },
1076 { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" },
1077 { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" },
1078 { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" },
1079 { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" },
1080 { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" },
1081 { 0, 0, 0, 0, 0, 0}};
1083 uintptr_t devid = 0;
1085 if (!(idx = ata_match_chip(dev, ids)))
1088 /* if we are on a SuperTrak SX6000 dont attach */
1089 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1090 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1091 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1092 devid == ATA_I960RM)
1095 strcpy(buffer, idx->text);
1096 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1097 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1098 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1099 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1100 devid == ATA_DEC_21150) {
1101 static long start = 0, end = 0;
1103 if (pci_get_slot(dev) == 1) {
1104 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1105 strcat(buffer, " (channel 0+1)");
1107 else if (pci_get_slot(dev) == 2 && start && end) {
1108 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1110 strcat(buffer, " (channel 2+3)");
1116 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1117 device_set_desc_copy(dev, buffer);
1119 ctlr->chipinit = ata_promise_chipinit;
1124 ata_promise_chipinit(device_t dev)
1126 struct ata_pci_controller *ctlr = device_get_softc(dev);
1127 int rid = ATA_IRQ_RID;
1129 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1130 RF_SHAREABLE | RF_ACTIVE))) {
1131 device_printf(dev, "unable to map interrupt\n");
1135 switch (ctlr->chip->cfg1) {
1138 ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) | 0x0a);
1140 ctlr->dmainit = ata_promise_new_dmainit;
1144 /* enable burst mode */
1145 ATA_OUTB(ctlr->r_io1, 0x1f, ATA_INB(ctlr->r_io1, 0x1f) | 0x01);
1147 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1148 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1149 device_printf(dev, "unable to setup interrupt\n");
1155 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1156 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1157 device_printf(dev, "unable to setup interrupt\n");
1164 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1165 0, ~0, 1, RF_ACTIVE)))
1168 ctlr->dmainit = ata_promise_mio_dmainit;
1169 ctlr->allocate = ata_promise_mio_allocate;
1171 if (ctlr->chip->cfg2 & PRDUAL) {
1172 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x01) > 0) +
1173 ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 2;
1175 else if (ctlr->chip->cfg2 & PRSATA) {
1176 ATA_OUTL(ctlr->r_io2, 0x06c, 0x00ff0033);
1177 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 3;
1182 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1183 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1184 device_printf(dev, "unable to setup interrupt\n");
1189 ctlr->setmode = ata_promise_setmode;
1194 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1196 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1199 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1200 ch->r_io[i].res = ctlr->r_io2;
1201 ch->r_io[i].offset = 0x200 + (i << 2) + (ch->unit << 7);
1203 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1204 ch->r_io[ATA_ALTSTAT].offset = 0x238 + (ch->unit << 7);
1205 ch->r_io[ATA_BMCTL_PORT].res = ctlr->r_io2;
1206 ch->r_io[ATA_BMCTL_PORT].offset = 0x260 + (ch->unit << 7);
1207 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1208 ch->r_io[ATA_BMDTP_PORT].offset = 0x244 + (ch->unit << 7);
1209 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1210 ch->r_io[ATA_BMDEVSPEC_0].offset = ((ch->unit + 1) << 2);
1211 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1213 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1214 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1216 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1218 ch->flags |= (ATA_NO_SLAVE | ATA_USE_16BIT);
1224 ata_promise_old_intr(void *data)
1226 struct ata_pci_controller *ctlr = data;
1227 struct ata_channel *ch;
1230 /* implement this as a toggle instead to balance load XXX */
1231 for (unit = 0; unit < 2; unit++) {
1232 if (!(ch = ctlr->interrupt[unit].argument))
1234 if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
1236 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1238 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1239 ATA_BMSTAT_INTERRUPT)
1241 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1244 ctlr->interrupt[unit].function(ch);
1250 ata_promise_tx2_intr(void *data)
1252 struct ata_pci_controller *ctlr = data;
1253 struct ata_channel *ch;
1256 /* implement this as a toggle instead to balance load XXX */
1257 for (unit = 0; unit < 2; unit++) {
1258 if (!(ch = ctlr->interrupt[unit].argument))
1260 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1261 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1263 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1265 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1266 ATA_BMSTAT_INTERRUPT)
1268 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1271 ctlr->interrupt[unit].function(ch);
1277 ata_promise_mio_intr(void *data)
1279 struct ata_pci_controller *ctlr = data;
1280 struct ata_channel *ch;
1281 u_int32_t irq_vector;
1284 irq_vector = ATA_INL(ctlr->r_io2, 0x0040);
1285 for (unit = 0; unit < ctlr->channels; unit++) {
1286 if (irq_vector & (1 << (unit + 1))) {
1287 if ((ch = ctlr->interrupt[unit].argument)) {
1288 ctlr->interrupt[unit].function(ch);
1289 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1290 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1292 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1299 ata_promise_setmode(struct ata_device *atadev, int mode)
1301 device_t parent = device_get_parent(atadev->channel->dev);
1302 struct ata_pci_controller *ctlr = device_get_softc(parent);
1303 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1305 u_int32_t timings33[][2] = {
1306 /* PROLD PRNEW mode */
1307 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
1308 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
1309 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
1310 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
1311 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
1312 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
1313 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
1314 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
1315 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
1316 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
1317 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
1318 { 0, 0x00424ef6 }, /* UDMA 3 */
1319 { 0, 0x004127f3 }, /* UDMA 4 */
1320 { 0, 0x004127f3 } /* UDMA 5 */
1323 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1325 switch (ctlr->chip->cfg1) {
1328 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
1329 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
1331 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1334 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
1335 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
1339 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
1340 if (mode > ATA_UDMA2 &&
1341 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
1343 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1349 if (mode > ATA_UDMA2 &&
1350 (ATA_IDX_INL(atadev->channel, ATA_BMCTL_PORT) & 0x01000000)) {
1352 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1358 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1361 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1362 (error) ? "FAILURE " : "",
1363 ata_mode2str(mode), ctlr->chip->text);
1365 if (ctlr->chip->cfg1 < PRTX)
1366 pci_write_config(parent, 0x60 + (devno << 2),
1367 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
1368 atadev->mode = mode;
1374 ata_promise_new_dmainit(struct ata_channel *ch)
1378 ch->dma->start = ata_promise_new_dmastart;
1379 ch->dma->stop = ata_promise_new_dmastop;
1384 ata_promise_new_dmastart(struct ata_channel *ch)
1386 struct ata_pci_controller *ctlr =
1387 device_get_softc(device_get_parent(ch->dev));
1389 if (ch->flags & ATA_48BIT_ACTIVE) {
1390 ATA_OUTB(ctlr->r_io1, 0x11,
1391 ATA_INB(ctlr->r_io1, 0x11) | (ch->unit ? 0x08 : 0x02));
1392 ATA_OUTL(ctlr->r_io1, 0x20,
1393 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1394 (ch->dma->cur_iosize >> 1));
1396 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1397 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1398 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1399 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1400 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
1401 ATA_BMCMD_START_STOP);
1406 ata_promise_new_dmastop(struct ata_channel *ch)
1408 struct ata_pci_controller *ctlr =
1409 device_get_softc(device_get_parent(ch->dev));
1412 if (ch->flags & ATA_48BIT_ACTIVE) {
1413 ATA_OUTB(ctlr->r_io1, 0x11,
1414 ATA_INB(ctlr->r_io1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
1415 ATA_OUTL(ctlr->r_io1, 0x20, 0);
1417 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
1418 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1419 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1420 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1425 ata_promise_mio_dmainit(struct ata_channel *ch)
1429 ch->dma->start = ata_promise_mio_dmastart;
1430 ch->dma->stop = ata_promise_mio_dmastop;
1435 ata_promise_mio_dmastart(struct ata_channel *ch)
1437 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1438 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1439 (ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x000000c0) |
1440 ((ch->dma->flags & ATA_DMA_READ) ? 0x00000080 : 0x000000c0));
1445 ata_promise_mio_dmastop(struct ata_channel *ch)
1447 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1448 ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x00000080);
1453 * ServerWorks chipset support functions
1456 ata_serverworks_ident(device_t dev)
1458 struct ata_pci_controller *ctlr = device_get_softc(dev);
1459 struct ata_chip_id *idx;
1460 static struct ata_chip_id ids[] =
1461 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
1462 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
1463 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
1464 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
1465 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
1466 { 0, 0, 0, 0, 0, 0}};
1469 if (!(idx = ata_match_chip(dev, ids)))
1472 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1473 device_set_desc_copy(dev, buffer);
1475 ctlr->chipinit = ata_serverworks_chipinit;
1480 ata_serverworks_chipinit(device_t dev)
1482 struct ata_pci_controller *ctlr = device_get_softc(dev);
1484 if (ata_setup_interrupt(dev))
1487 if (ctlr->chip->cfg1 == SWKS33) {
1491 /* locate the ISA part in the southbridge and enable UDMA33 */
1492 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1493 for (i = 0; i < nchildren; i++) {
1494 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
1495 pci_write_config(children[i], 0x64,
1496 (pci_read_config(children[i], 0x64, 4) &
1497 ~0x00002000) | 0x00004000, 4);
1501 free(children, M_TEMP);
1505 pci_write_config(dev, 0x5a,
1506 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
1507 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
1509 ctlr->setmode = ata_serverworks_setmode;
1514 ata_serverworks_setmode(struct ata_device *atadev, int mode)
1516 device_t parent = device_get_parent(atadev->channel->dev);
1517 struct ata_pci_controller *ctlr = device_get_softc(parent);
1518 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1519 int offset = devno ^ 0x01;
1521 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1522 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1523 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1525 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1527 mode = ata_check_80pin(atadev, mode);
1529 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1532 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1533 (error) ? "FAILURE " : "",
1534 ata_mode2str(mode), ctlr->chip->text);
1536 if (mode >= ATA_UDMA0) {
1537 pci_write_config(parent, 0x56,
1538 (pci_read_config(parent, 0x56, 2) &
1539 ~(0xf << (devno << 2))) |
1540 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1542 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) |
1543 (0x01 << devno), 1);
1544 pci_write_config(parent, 0x44,
1545 (pci_read_config(parent, 0x44, 4) &
1546 ~(0xff << (offset << 8))) |
1547 (dmatimings[2] << (offset << 8)), 4);
1549 else if (mode >= ATA_WDMA0) {
1550 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1551 ~(0x01 << devno), 1);
1552 pci_write_config(parent, 0x44,
1553 (pci_read_config(parent, 0x44, 4) &
1554 ~(0xff << (offset << 8))) |
1555 (dmatimings[mode & ATA_MODE_MASK]<<(offset<<8)),4);
1558 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1559 ~(0x01 << devno), 1);
1561 pci_write_config(parent, 0x40,
1562 (pci_read_config(parent, 0x40, 4) &
1563 ~(0xff << (offset << 8))) |
1564 (piotimings[ata_mode2idx(mode)] << (offset << 8)), 4);
1565 atadev->mode = mode;
1570 * Silicon Image (former CMD) chipset support functions
1573 ata_sii_ident(device_t dev)
1575 struct ata_pci_controller *ctlr = device_get_softc(dev);
1576 struct ata_chip_id *idx;
1577 static struct ata_chip_id ids[] =
1578 {{ ATA_SII3112, 0x00, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1579 { ATA_SII3112_1, 0x00, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1580 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
1581 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
1582 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
1583 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
1584 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
1585 { 0, 0, 0, 0, 0, 0}};
1588 if (!(idx = ata_match_chip(dev, ids)))
1591 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1592 device_set_desc_copy(dev, buffer);
1594 ctlr->chipinit = ata_sii_chipinit;
1599 ata_sii_chipinit(device_t dev)
1601 struct ata_pci_controller *ctlr = device_get_softc(dev);
1602 int rid = ATA_IRQ_RID;
1604 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1605 RF_SHAREABLE | RF_ACTIVE))) {
1606 device_printf(dev, "unable to map interrupt\n");
1610 if (ctlr->chip->cfg1 == SIIMEMIO) {
1611 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1612 ata_sii_intr, ctlr, &ctlr->handle))) {
1613 device_printf(dev, "unable to setup interrupt\n");
1617 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1618 0, ~0, 1, RF_ACTIVE)))
1621 if (ctlr->chip->cfg2 & SIISETCLK) {
1622 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1623 pci_write_config(dev, 0x8a,
1624 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
1625 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1626 device_printf(dev, "%s could not set ATA133 clock\n",
1630 /* enable interrupt as BIOS might not */
1631 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
1633 ctlr->allocate = ata_sii_mio_allocate;
1634 if (ctlr->chip->max_dma >= ATA_SA150)
1635 ctlr->setmode = ata_sata_setmode;
1637 ctlr->setmode = ata_sii_setmode;
1640 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1641 ctlr->chip->cfg2 & SIIINTR ?
1642 ata_cmd_intr : ata_generic_intr,
1643 ctlr, &ctlr->handle))) {
1644 device_printf(dev, "unable to setup interrupt\n");
1648 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
1649 device_printf(dev, "HW has secondary channel disabled\n");
1653 /* enable interrupt as BIOS might not */
1654 pci_write_config(dev, 0x71, 0x01, 1);
1656 ctlr->setmode = ata_cmd_setmode;
1662 ata_sii_mio_allocate(device_t dev, struct ata_channel *ch)
1664 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1667 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1668 ch->r_io[i].res = ctlr->r_io2;
1669 ch->r_io[i].offset = 0x80 + i + (ch->unit << 6);
1671 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1672 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (ch->unit << 6);
1673 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2;
1674 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (ch->unit << 3);
1675 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_io2;
1676 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (ch->unit << 3);
1677 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1678 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (ch->unit << 3);
1679 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1680 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (ch->unit << 6);
1681 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1683 if (ctlr->chip->max_dma >= ATA_SA150)
1684 ch->flags |= ATA_NO_SLAVE;
1690 ata_sii_intr(void *data)
1692 struct ata_pci_controller *ctlr = data;
1693 struct ata_channel *ch;
1696 /* implement this as a toggle instead to balance load XXX */
1697 for (unit = 0; unit < 2; unit++) {
1698 if (!(ch = ctlr->interrupt[unit].argument))
1700 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
1702 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1704 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1705 ATA_BMSTAT_INTERRUPT)
1707 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1710 ctlr->interrupt[unit].function(ch);
1716 ata_cmd_intr(void *data)
1718 struct ata_pci_controller *ctlr = data;
1719 struct ata_channel *ch;
1723 /* implement this as a toggle instead to balance load XXX */
1724 for (unit = 0; unit < 2; unit++) {
1725 if (!(ch = ctlr->interrupt[unit].argument))
1727 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
1728 (ch->unit ? 0x08 : 0x04))) {
1729 pci_write_config(device_get_parent(ch->dev), 0x71,
1730 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
1732 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1734 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1735 ATA_BMSTAT_INTERRUPT)
1737 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1740 ctlr->interrupt[unit].function(ch);
1746 ata_sii_setmode(struct ata_device *atadev, int mode)
1748 device_t parent = device_get_parent(atadev->channel->dev);
1749 struct ata_pci_controller *ctlr = device_get_softc(parent);
1750 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
1751 int mreg = atadev->channel->unit ? 0x84 : 0x80;
1752 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
1753 int mval = pci_read_config(parent, mreg, 1) & ~mask;
1756 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1758 if (ctlr->chip->max_dma < ATA_UDMA2) {
1759 mode = ata_check_80pin(atadev, mode);
1761 else if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
1762 (atadev->channel->unit ? 0x02 : 0x01))) {
1763 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
1767 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1770 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1771 (error) ? "FAILURE " : "",
1772 ata_mode2str(mode), ctlr->chip->text);
1776 if (mode >= ATA_UDMA0) {
1777 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1778 u_int8_t ureg = 0xac + rego;
1780 pci_write_config(parent, mreg,
1781 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
1782 pci_write_config(parent, ureg,
1783 (pci_read_config(parent, ureg, 1) & ~0x3f) |
1784 udmatimings[mode & ATA_MODE_MASK], 1);
1787 else if (mode >= ATA_WDMA0) {
1788 u_int8_t dreg = 0xa8 + rego;
1789 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
1791 pci_write_config(parent, mreg,
1792 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
1793 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
1797 u_int8_t preg = 0xa4 + rego;
1798 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
1800 pci_write_config(parent, mreg,
1801 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
1802 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
1804 atadev->mode = mode;
1808 ata_cmd_setmode(struct ata_device *atadev, int mode)
1810 device_t parent = device_get_parent(atadev->channel->dev);
1811 struct ata_pci_controller *ctlr = device_get_softc(parent);
1812 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1815 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1817 mode = ata_check_80pin(atadev, mode);
1819 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1822 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1823 (error) ? "FAILURE " : "",
1824 ata_mode2str(mode), ctlr->chip->text);
1826 int treg = 0x54 + (devno < 3) ? (devno << 1) : 7;
1827 int ureg = atadev->channel->unit ? 0x7b : 0x73;
1829 if (mode >= ATA_UDMA0) {
1830 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
1831 { 0x11, 0x42 }, { 0x25, 0x8a },
1832 { 0x15, 0x4a }, { 0x05, 0x0a } };
1834 u_int8_t umode = pci_read_config(parent, ureg, 1);
1836 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
1837 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
1838 pci_write_config(parent, ureg, umode, 1);
1840 else if (mode >= ATA_WDMA0) {
1841 int dmatimings[] = { 0x87, 0x32, 0x3f };
1843 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
1844 pci_write_config(parent, ureg,
1845 pci_read_config(parent, ureg, 1) &
1846 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1849 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1850 pci_write_config(parent, treg,
1851 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
1852 pci_write_config(parent, ureg,
1853 pci_read_config(parent, ureg, 1) &
1854 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1856 atadev->mode = mode;
1861 * SiS chipset support functions
1864 ata_sis_ident(device_t dev)
1866 struct ata_pci_controller *ctlr = device_get_softc(dev);
1867 struct ata_chip_id *idx;
1868 static struct ata_chip_id ids[] =
1869 {{ ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
1870 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
1872 { ATA_SIS755, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 755" }, /* ext south */
1873 { ATA_SIS752, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 752" }, /* unknown */
1874 { ATA_SIS751, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 751" }, /* unknown */
1875 { ATA_SIS750, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 750" }, /* unknown */
1876 { ATA_SIS748, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 748" }, /* unknown */
1877 { ATA_SIS746, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 746" }, /* ext south */
1878 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
1879 { ATA_SIS740, 0x00, SIS_SOUTH, 0, ATA_UDMA5, "SiS 740" }, /* ext south */
1880 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
1881 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
1882 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
1884 { ATA_SIS658, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 658" }, /* ext south */
1885 { ATA_SIS655, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 655" }, /* ext south */
1886 { ATA_SIS652, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 652" }, /* unknown */
1887 { ATA_SIS651, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 651" }, /* ext south */
1888 { ATA_SIS650, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 650" }, /* ext south */
1889 { ATA_SIS648, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 648" }, /* ext south */
1890 { ATA_SIS646, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645DX"},/* ext south */
1891 { ATA_SIS645, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645" }, /* ext south */
1892 { ATA_SIS640, 0x00, SIS_SOUTH, 0, ATA_UDMA4, "SiS 640" }, /* ext south */
1893 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
1894 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
1895 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
1896 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
1897 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
1899 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
1900 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
1901 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
1903 { ATA_SIS5513, 0xc2, SIS33, 0, ATA_UDMA2, "SiS 5513" },
1904 { ATA_SIS5513, 0x00, SIS33, 0, ATA_WDMA2, "SiS 5513" },
1905 { 0, 0, 0, 0, 0, 0 }};
1908 if (!(idx = ata_find_chip(dev, ids, -1)))
1911 if (idx->cfg1 == SIS_SOUTH) {
1912 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) & 0x7f, 1);
1913 if (pci_read_config(dev, 0x00, 4) == ATA_SIS5518) {
1914 idx->cfg1 = SIS133NEW;
1915 sprintf(buffer, "SiS 96X %s controller",ata_mode2str(idx->max_dma));
1918 struct ata_chip_id id[] =
1919 {{ ATA_SISSOUTH, 0x10, 0, 0, ATA_UDMA6, "SiS 961" },
1920 { 0, 0, 0, 0, 0, 0 }};
1922 if (ata_find_chip(dev, id, pci_get_slot(dev)))
1923 idx->cfg1 = SIS133OLD;
1925 idx->max_dma = ATA_UDMA5;
1926 idx->cfg1 = SIS100NEW;
1928 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
1930 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) | 0x80, 1);
1933 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
1934 device_set_desc_copy(dev, buffer);
1936 ctlr->chipinit = ata_sis_chipinit;
1941 ata_sis_chipinit(device_t dev)
1943 struct ata_pci_controller *ctlr = device_get_softc(dev);
1945 if (ata_setup_interrupt(dev))
1948 switch (ctlr->chip->cfg1) {
1953 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) | 0x04, 1);
1957 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) | 0x01, 1);
1960 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) & 0xfff7, 2);
1961 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) & 0xfff7, 2);
1966 ctlr->setmode = ata_sis_setmode;
1971 ata_sis_setmode(struct ata_device *atadev, int mode)
1973 device_t parent = device_get_parent(atadev->channel->dev);
1974 struct ata_pci_controller *ctlr = device_get_softc(parent);
1975 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1978 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1980 if (ctlr->chip->cfg1 == SIS133NEW) {
1981 if (mode > ATA_UDMA2 &&
1982 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
1984 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1989 if (mode > ATA_UDMA2 &&
1990 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
1992 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1997 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2000 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2001 (error) ? "FAILURE " : "",
2002 ata_mode2str(mode), ctlr->chip->text);
2004 switch (ctlr->chip->cfg1) {
2006 u_int32_t timings[] =
2007 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2008 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2009 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2012 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2013 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2017 u_int16_t timings[] =
2018 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2019 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2021 u_int16_t reg = 0x40 + (devno << 1);
2023 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2027 u_int16_t timings[] =
2028 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2029 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2030 u_int16_t reg = 0x40 + (devno << 1);
2032 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2038 u_int16_t timings[] =
2039 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2040 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2041 u_int16_t reg = 0x40 + (devno << 1);
2043 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2047 atadev->mode = mode;
2053 ata_via_ident(device_t dev)
2055 struct ata_pci_controller *ctlr = device_get_softc(dev);
2056 struct ata_chip_id *idx;
2057 static struct ata_chip_id ids[] =
2058 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2059 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2060 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2061 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2062 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2063 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2064 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2065 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2066 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2067 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2068 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2069 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2070 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2071 { 0, 0, 0, 0, 0, 0 }};
2072 static struct ata_chip_id new_ids[] =
2073 {{ ATA_VIA8237, 0x00, 0x00, 0x00, ATA_SA150, "VIA 8237" },
2074 { 0, 0, 0, 0, 0, 0 }};
2077 if (pci_get_devid(dev) == ATA_VIA82C571) {
2078 if (!(idx = ata_find_chip(dev, ids, pci_get_slot(dev))))
2082 if (!(idx = ata_match_chip(dev, new_ids)))
2086 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2087 device_set_desc_copy(dev, buffer);
2089 ctlr->chipinit = ata_via_chipinit;
2094 ata_via_chipinit(device_t dev)
2096 struct ata_pci_controller *ctlr = device_get_softc(dev);
2098 if (ata_setup_interrupt(dev))
2101 if (ctlr->chip->max_dma >= ATA_SA150) {
2102 ctlr->setmode = ata_sata_setmode;
2106 /* prepare for ATA-66 on the 82C686a and 82C596b */
2107 if (ctlr->chip->cfg2 & VIACLK)
2108 pci_write_config(dev, 0x50, 0x030b030b, 4);
2110 /* the southbridge might need the data corruption fix */
2111 if (ctlr->chip->cfg2 & VIABUG)
2112 ata_via_southbridge_fixup(dev);
2114 /* set prefetch, postwrite */
2115 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
2117 /* set fifo configuration half'n'half */
2118 pci_write_config(dev, 0x43,
2119 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2121 /* set status register read retry */
2122 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2124 /* set DMA read & end-of-sector fifo flush */
2125 pci_write_config(dev, 0x46,
2126 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2128 /* set sector size */
2129 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2130 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2132 ctlr->setmode = ata_via_family_setmode;
2137 ata_via_southbridge_fixup(device_t dev)
2142 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2145 for (i = 0; i < nchildren; i++) {
2146 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2147 pci_get_devid(children[i]) == ATA_VIA8371 ||
2148 pci_get_devid(children[i]) == ATA_VIA8662 ||
2149 pci_get_devid(children[i]) == ATA_VIA8361) {
2150 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2152 if ((reg76 & 0xf0) != 0xd0) {
2154 "Correcting VIA config for southbridge data corruption bug\n");
2155 pci_write_config(children[i], 0x75, 0x80, 1);
2156 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2161 free(children, M_TEMP);
2164 /* common code for VIA, AMD & nVidia */
2166 ata_via_family_setmode(struct ata_device *atadev, int mode)
2168 device_t parent = device_get_parent(atadev->channel->dev);
2169 struct ata_pci_controller *ctlr = device_get_softc(parent);
2170 u_int8_t timings[] = { 0xff, 0xff, 0xff, 0x55, 0x51, 0xff, 0x55, 0x51,
2171 0x51, 0x51, 0x51, 0x51, 0x51, 0x51 };
2173 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2174 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2175 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2176 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2177 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2178 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2179 int reg = 0x53 - devno;
2182 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2184 if (ctlr->chip->cfg2 & AMDCABLE) {
2185 if (mode > ATA_UDMA2 &&
2186 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2188 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2193 mode = ata_check_80pin(atadev, mode);
2195 if (ctlr->chip->cfg2 & NVIDIA)
2198 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2200 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2203 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2204 (error) ? "FAILURE " : "", ata_mode2str(mode),
2207 if (mode >= ATA_UDMA0)
2208 pci_write_config(parent, reg,
2209 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2211 pci_write_config(parent, reg, 0x8b, 1);
2212 atadev->mode = mode;
2216 /* misc functions */
2217 static struct ata_chip_id *
2218 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2223 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2226 while (index->chipid != 0) {
2227 for (i = 0; i < nchildren; i++) {
2228 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || slot < 0)&&
2229 pci_get_devid(children[i]) == index->chipid &&
2230 pci_get_revid(children[i]) >= index->chiprev) {
2231 free(children, M_TEMP);
2237 free(children, M_TEMP);
2241 static struct ata_chip_id *
2242 ata_match_chip(device_t dev, struct ata_chip_id *index)
2244 while (index->chipid != 0) {
2245 if (pci_get_devid(dev) == index->chipid &&
2246 pci_get_revid(dev) >= index->chiprev)
2254 ata_setup_interrupt(device_t dev)
2256 struct ata_pci_controller *ctlr = device_get_softc(dev);
2257 int rid = ATA_IRQ_RID;
2259 if (!ATA_MASTERDEV(dev)) {
2260 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2261 RF_SHAREABLE | RF_ACTIVE))) {
2262 device_printf(dev, "unable to map interrupt\n");
2265 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2266 ata_generic_intr, ctlr, &ctlr->handle))) {
2267 device_printf(dev, "unable to setup interrupt\n");
2275 ata_serialize(struct ata_channel *ch, int flags)
2277 struct ata_pci_controller *scp =
2278 device_get_softc(device_get_parent(ch->dev));
2282 if (scp->locked_ch == ch->unit)
2284 while (!atomic_cmpset_acq_int(&scp->locked_ch, -1, ch->unit))
2285 tsleep(ch->locking, PRIBIO, "atasrl", 1);
2289 if (scp->locked_ch == -1 || scp->locked_ch != ch->unit)
2291 atomic_store_rel_int(&scp->locked_ch, -1);
2292 wakeup(ch->locking);
2299 ata_check_80pin(struct ata_device *atadev, int mode)
2301 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
2302 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
2309 ata_mode2idx(int mode)
2311 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
2312 return (mode & ATA_MODE_MASK) + 8;
2313 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
2314 return (mode & ATA_MODE_MASK) + 5;
2315 return (mode & ATA_MODE_MASK) - ATA_PIO0;