2 * Copyright (c) 1998 - 2003 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/taskqueue.h>
41 #include <machine/stdarg.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/ata/ata-all.h>
48 #include <dev/ata/ata-pci.h>
51 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
52 #define ATAPI_DEVICE(atadev) \
53 ((atadev->unit == ATA_MASTER && \
54 atadev->channel->devices & ATA_ATAPI_MASTER) ||\
55 (atadev->unit == ATA_SLAVE && \
56 atadev->channel->devices & ATA_ATAPI_SLAVE))
58 /* local prototypes */
59 static int ata_generic_chipinit(device_t);
60 static void ata_generic_intr(void *);
61 static void ata_generic_setmode(struct ata_device *, int);
62 static int ata_acard_chipinit(device_t);
63 static void ata_acard_intr(void *);
64 static void ata_acard_850_setmode(struct ata_device *, int);
65 static void ata_acard_86X_setmode(struct ata_device *, int);
66 static int ata_ali_chipinit(device_t);
67 static void ata_ali_setmode(struct ata_device *, int);
68 static int ata_amd_chipinit(device_t);
69 static int ata_cyrix_chipinit(device_t);
70 static void ata_cyrix_setmode(struct ata_device *, int);
71 static int ata_cypress_chipinit(device_t);
72 static void ata_cypress_setmode(struct ata_device *, int);
73 static int ata_highpoint_chipinit(device_t);
74 static void ata_highpoint_intr(void *);
75 static void ata_highpoint_setmode(struct ata_device *, int);
76 static int ata_highpoint_check_80pin(struct ata_device *, int);
77 static int ata_intel_chipinit(device_t);
78 static void ata_intel_old_setmode(struct ata_device *, int);
79 static void ata_intel_new_setmode(struct ata_device *, int);
80 static int ata_national_chipinit(device_t);
81 static void ata_national_setmode(struct ata_device *, int);
82 static int ata_nvidia_chipinit(device_t);
83 static int ata_via_chipinit(device_t);
84 static void ata_via_family_setmode(struct ata_device *, int);
85 static void ata_via_southbridge_fixup(device_t);
86 static int ata_promise_chipinit(device_t);
87 static int ata_promise_mio_allocate(device_t, struct ata_channel *);
88 static void ata_promise_old_intr(void *);
89 static void ata_promise_tx2_intr(void *);
90 static void ata_promise_mio_intr(void *);
91 static void ata_promise_setmode(struct ata_device *, int);
92 static void ata_promise_new_dmainit(struct ata_channel *);
93 static int ata_promise_new_dmastart(struct ata_channel *);
94 static int ata_promise_new_dmastop(struct ata_channel *);
95 static void ata_promise_mio_dmainit(struct ata_channel *);
96 static int ata_promise_mio_dmastart(struct ata_channel *);
97 static int ata_promise_mio_dmastop(struct ata_channel *);
98 static int ata_serverworks_chipinit(device_t);
99 static void ata_serverworks_setmode(struct ata_device *, int);
100 static int ata_sii_chipinit(device_t);
101 static int ata_sii_mio_allocate(device_t, struct ata_channel *);
102 static void ata_sii_intr(void *);
103 static void ata_cmd_intr(void *);
104 static void ata_cmd_old_intr(void *);
105 static void ata_sii_setmode(struct ata_device *, int);
106 static void ata_cmd_setmode(struct ata_device *, int);
107 static int ata_sis_chipinit(device_t);
108 static void ata_sis_setmode(struct ata_device *, int);
109 static int ata_check_80pin(struct ata_device *, int);
110 static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int);
111 static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *);
112 static int ata_setup_interrupt(device_t);
113 static void ata_serialize(struct ata_channel *, int);
114 static int ata_mode2idx(int);
116 /* generic or unknown ATA chipset init code */
118 ata_generic_ident(device_t dev)
120 struct ata_pci_controller *ctlr = device_get_softc(dev);
122 device_set_desc(dev, "GENERIC ATA controller");
123 ctlr->chipinit = ata_generic_chipinit;
128 ata_generic_chipinit(device_t dev)
130 struct ata_pci_controller *ctlr = device_get_softc(dev);
132 if (ata_setup_interrupt(dev))
134 ctlr->setmode = ata_generic_setmode;
139 ata_generic_intr(void *data)
141 struct ata_pci_controller *ctlr = data;
142 struct ata_channel *ch;
145 /* implement this as a toggle instead to balance load XXX */
146 for (unit = 0; unit < 2; unit++) {
147 if (!(ch = ctlr->interrupt[unit].argument))
150 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
152 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
153 ATA_BMSTAT_INTERRUPT)
155 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
158 ctlr->interrupt[unit].function(ch);
163 ata_generic_setmode(struct ata_device *atadev, int mode)
165 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
166 mode = ata_check_80pin(atadev, mode);
167 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
172 ata_sata_setmode(struct ata_device *atadev, int mode)
175 * we limit the transfer mode to UDMA5/ATA100 as some chips/drive
176 * comboes that use the Marvell SATA->PATA converters has trouble
177 * with UDMA6/ATA133. This doesn't really matter as real SATA
178 * devices doesn't use this anyway.
180 mode = ata_limit_mode(atadev, mode, ATA_UDMA5);
181 if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
186 * Acard chipset support functions
189 ata_acard_ident(device_t dev)
191 struct ata_pci_controller *ctlr = device_get_softc(dev);
192 struct ata_chip_id *idx;
193 static struct ata_chip_id ids[] =
194 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" },
195 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" },
196 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" },
197 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" },
198 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" },
199 { 0, 0, 0, 0, 0, 0}};
202 if (!(idx = ata_match_chip(dev, ids)))
205 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
206 device_set_desc_copy(dev, buffer);
208 ctlr->chipinit = ata_acard_chipinit;
213 ata_acard_chipinit(device_t dev)
215 struct ata_pci_controller *ctlr = device_get_softc(dev);
216 int rid = ATA_IRQ_RID;
218 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
219 RF_SHAREABLE | RF_ACTIVE))) {
220 device_printf(dev, "unable to map interrupt\n");
223 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
224 ata_acard_intr, ctlr, &ctlr->handle))) {
225 device_printf(dev, "unable to setup interrupt\n");
228 if (ctlr->chip->cfg1 == ATPOLD) {
229 ctlr->setmode = ata_acard_850_setmode;
230 ctlr->locking = ata_serialize;
233 ctlr->setmode = ata_acard_86X_setmode;
238 ata_acard_intr(void *data)
240 struct ata_pci_controller *ctlr = data;
241 struct ata_channel *ch;
244 /* implement this as a toggle instead to balance load XXX */
245 for (unit = 0; unit < 2; unit++) {
246 if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
248 if (!(ch = ctlr->interrupt[unit].argument))
251 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
253 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
254 ATA_BMSTAT_INTERRUPT)
256 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
258 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
259 ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
262 ctlr->interrupt[unit].function(ch);
267 ata_acard_850_setmode(struct ata_device *atadev, int mode)
269 device_t parent = device_get_parent(atadev->channel->dev);
270 struct ata_pci_controller *ctlr = device_get_softc(parent);
271 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
274 mode = ata_limit_mode(atadev, mode,
275 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
277 /* XXX missing WDMA0+1 + PIO modes */
278 if (mode >= ATA_WDMA2) {
279 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
281 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
282 (error) ? "FAILURE " : "",
283 ata_mode2str(mode), ctlr->chip->text);
285 u_int8_t reg54 = pci_read_config(parent, 0x54, 1);
287 reg54 &= ~(0x03 << (devno << 1));
288 if (mode >= ATA_UDMA0)
289 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
290 pci_write_config(parent, 0x54, reg54, 1);
291 pci_write_config(parent, 0x4a, 0xa6, 1);
292 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
297 /* we could set PIO mode timings, but we assume the BIOS did that */
301 ata_acard_86X_setmode(struct ata_device *atadev, int mode)
303 device_t parent = device_get_parent(atadev->channel->dev);
304 struct ata_pci_controller *ctlr = device_get_softc(parent);
305 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
309 mode = ata_limit_mode(atadev, mode,
310 ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma);
312 mode = ata_check_80pin(atadev, mode);
314 /* XXX missing WDMA0+1 + PIO modes */
315 if (mode >= ATA_WDMA2) {
316 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
318 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
319 (error) ? "FAILURE " : "",
320 ata_mode2str(mode), ctlr->chip->text);
322 u_int16_t reg44 = pci_read_config(parent, 0x44, 2);
324 reg44 &= ~(0x000f << (devno << 2));
325 if (mode >= ATA_UDMA0)
326 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
327 pci_write_config(parent, 0x44, reg44, 2);
328 pci_write_config(parent, 0x4a, 0xa6, 1);
329 pci_write_config(parent, 0x40 + devno, 0x31, 1);
334 /* we could set PIO mode timings, but we assume the BIOS did that */
338 * Acer Labs Inc (ALI) chipset support functions
341 ata_ali_ident(device_t dev)
343 struct ata_pci_controller *ctlr = device_get_softc(dev);
344 struct ata_chip_id *idx;
345 static struct ata_chip_id ids[] =
346 {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" },
347 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" },
348 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" },
349 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" },
350 { 0, 0, 0, 0, 0, 0}};
353 if (!(idx = ata_match_chip(dev, ids)))
356 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
357 device_set_desc_copy(dev, buffer);
359 ctlr->chipinit = ata_ali_chipinit;
364 ata_ali_chipinit(device_t dev)
366 struct ata_pci_controller *ctlr = device_get_softc(dev);
368 if (ata_setup_interrupt(dev))
371 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
372 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
374 /* enable cable detection and UDMA support on newer chips */
375 if (ctlr->chip->cfg2 & ALINEW)
376 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
377 ctlr->setmode = ata_ali_setmode;
382 ata_ali_setmode(struct ata_device *atadev, int mode)
384 device_t parent = device_get_parent(atadev->channel->dev);
385 struct ata_pci_controller *ctlr = device_get_softc(parent);
386 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
389 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
391 if (ctlr->chip->cfg2 & ALINEW) {
392 if (mode > ATA_UDMA2 &&
393 pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) {
395 "DMA limited to UDMA33, non-ATA66 cable or device\n");
400 mode = ata_check_80pin(atadev, mode);
402 if (ctlr->chip->cfg2 & ALIOLD) {
403 /* doesn't support ATAPI DMA on write */
404 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
405 if (atadev->channel->devices & ATA_ATAPI_MASTER &&
406 atadev->channel->devices & ATA_ATAPI_SLAVE) {
407 /* doesn't support ATAPI DMA on two ATAPI devices */
408 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
409 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
413 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
416 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
417 (error) ? "FAILURE " : "",
418 ata_mode2str(mode), ctlr->chip->text);
420 if (mode >= ATA_UDMA0) {
421 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
422 u_int32_t word54 = pci_read_config(parent, 0x54, 4);
424 word54 &= ~(0x000f000f << (devno << 2));
425 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
426 pci_write_config(parent, 0x54, word54, 4);
427 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
431 u_int32_t piotimings[] =
432 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
433 0x00310001, 0x00440001, 0x00330001, 0x00310001};
435 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) &
436 ~(0x0008000f << (devno << 2)), 4);
437 pci_write_config(parent, 0x58 + (atadev->channel->unit << 2),
438 piotimings[ata_mode2idx(mode)], 4);
445 * American Micro Devices (AMD) support function
448 ata_amd_ident(device_t dev)
450 struct ata_pci_controller *ctlr = device_get_softc(dev);
451 struct ata_chip_id *idx;
452 static struct ata_chip_id ids[] =
453 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" },
454 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" },
455 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" },
456 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "AMD 8111" },
457 { 0, 0, 0, 0, 0, 0}};
460 if (!(idx = ata_match_chip(dev, ids)))
463 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
464 device_set_desc_copy(dev, buffer);
466 ctlr->chipinit = ata_amd_chipinit;
471 ata_amd_chipinit(device_t dev)
473 struct ata_pci_controller *ctlr = device_get_softc(dev);
475 if (ata_setup_interrupt(dev))
478 /* set prefetch, postwrite */
479 if (ctlr->chip->cfg2 & AMDBUG)
480 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
482 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
484 ctlr->setmode = ata_via_family_setmode;
489 * Cyrix chipset support functions
492 ata_cyrix_ident(device_t dev)
494 struct ata_pci_controller *ctlr = device_get_softc(dev);
496 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
497 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
498 ctlr->chipinit = ata_cyrix_chipinit;
505 ata_cyrix_chipinit(device_t dev)
507 struct ata_pci_controller *ctlr = device_get_softc(dev);
509 if (ata_setup_interrupt(dev))
513 ctlr->setmode = ata_cyrix_setmode;
515 ctlr->setmode = ata_generic_setmode;
520 ata_cyrix_setmode(struct ata_device *atadev, int mode)
522 struct ata_channel *ch = atadev->channel;
523 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
524 u_int32_t piotiming[] =
525 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
526 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
527 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
530 atadev->channel->dma->alignment = 16;
531 atadev->channel->dma->max_iosize = 63 * 1024;
533 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
535 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
538 ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n",
539 (error) ? "FAILURE " : "", ata_mode2str(mode));
541 if (mode >= ATA_UDMA0) {
542 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
543 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
545 else if (mode >= ATA_WDMA0) {
546 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
547 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
550 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
551 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
558 * Cypress chipset support functions
561 ata_cypress_ident(device_t dev)
563 struct ata_pci_controller *ctlr = device_get_softc(dev);
566 * the Cypress chip is a mess, it contains two ATA functions, but
567 * both channels are visible on the first one.
568 * simply ignore the second function for now, as the right
569 * solution (ignoring the second channel on the first function)
570 * doesn't work with the crappy ATA interrupt setup on the alpha.
572 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
573 pci_get_function(dev) == 1 &&
574 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
575 device_set_desc(dev, "Cypress 82C693 ATA controller");
576 ctlr->chipinit = ata_cypress_chipinit;
583 ata_cypress_chipinit(device_t dev)
585 struct ata_pci_controller *ctlr = device_get_softc(dev);
587 if (ata_setup_interrupt(dev))
590 ctlr->setmode = ata_cypress_setmode;
595 ata_cypress_setmode(struct ata_device *atadev, int mode)
597 device_t parent = device_get_parent(atadev->channel->dev);
600 mode = ata_limit_mode(atadev, mode, ATA_WDMA2);
602 /* XXX missing WDMA0+1 + PIO modes */
603 if (mode == ATA_WDMA2) {
604 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode);
606 ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n",
607 error ? "FAILURE " : "");
609 pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2);
614 /* we could set PIO mode timings, but we assume the BIOS did that */
618 * HighPoint chipset support functions
621 ata_highpoint_ident(device_t dev)
623 struct ata_pci_controller *ctlr = device_get_softc(dev);
624 struct ata_chip_id *idx;
625 static struct ata_chip_id ids[] =
626 {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
627 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" },
628 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" },
629 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" },
630 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" },
631 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" },
632 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" },
633 { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" },
634 { 0, 0, 0, 0, 0, 0}};
637 if (!(idx = ata_match_chip(dev, ids)))
640 strcpy(buffer, idx->text);
641 if (idx->cfg1 == HPT374) {
642 if (pci_get_function(dev) == 0)
643 strcat(buffer, " (channel 0+1)");
644 else if (pci_get_function(dev) == 1)
645 strcat(buffer, " (channel 2+3)");
647 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
648 device_set_desc_copy(dev, buffer);
650 ctlr->chipinit = ata_highpoint_chipinit;
655 ata_highpoint_chipinit(device_t dev)
657 struct ata_pci_controller *ctlr = device_get_softc(dev);
658 int rid = ATA_IRQ_RID;
660 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
661 RF_SHAREABLE | RF_ACTIVE))) {
662 device_printf(dev, "unable to map interrupt\n");
665 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
666 ata_highpoint_intr, ctlr, &ctlr->handle))) {
667 device_printf(dev, "unable to setup interrupt\n");
671 if (ctlr->chip->cfg2 == HPTOLD) {
672 /* turn off interrupt prediction */
673 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
676 /* turn off interrupt prediction */
677 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
678 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
680 /* turn on interrupts */
681 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
684 if (ctlr->chip->cfg1 < HPT372)
685 pci_write_config(dev, 0x5b, 0x22, 1);
687 pci_write_config(dev, 0x5b,
688 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
690 ctlr->setmode = ata_highpoint_setmode;
695 ata_highpoint_intr(void *data)
697 struct ata_pci_controller *ctlr = data;
698 struct ata_channel *ch;
701 /* implement this as a toggle instead to balance load XXX */
702 for (unit = 0; unit < 2; unit++) {
703 if (!(ch = ctlr->interrupt[unit].argument))
706 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
708 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
709 ATA_BMSTAT_INTERRUPT)
711 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
714 ctlr->interrupt[unit].function(ch);
719 ata_highpoint_setmode(struct ata_device *atadev, int mode)
721 device_t parent = device_get_parent(atadev->channel->dev);
722 struct ata_pci_controller *ctlr = device_get_softc(parent);
723 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
725 u_int32_t timings33[][4] = {
726 /* HPT366 HPT370 HPT372 HPT374 mode */
727 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
728 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
729 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
730 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
731 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
732 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
733 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
734 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
735 { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */
736 { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */
737 { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */
738 { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */
739 { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */
740 { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */
741 { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */
744 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
746 if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev))
747 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
749 mode = ata_highpoint_check_80pin(atadev, mode);
751 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
754 ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n",
755 (error) ? "FAILURE " : "", ata_mode2str(mode));
757 pci_write_config(parent, 0x40 + (devno << 2),
758 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
763 ata_highpoint_check_80pin(struct ata_device *atadev, int mode)
765 device_t parent = device_get_parent(atadev->channel->dev);
766 struct ata_pci_controller *ctlr = device_get_softc(parent);
767 u_int8_t reg, val, res;
769 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) {
770 reg = atadev->channel->unit ? 0x57 : 0x53;
771 val = pci_read_config(parent, reg, 1);
772 pci_write_config(parent, reg, val | 0x80, 1);
776 val = pci_read_config(parent, reg, 1);
777 pci_write_config(parent, reg, val & 0xfe, 1);
779 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
780 pci_write_config(parent, reg, val, 1);
782 if (mode > ATA_UDMA2 && res) {
783 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
790 * Intel chipset support functions
793 ata_intel_ident(device_t dev)
795 struct ata_pci_controller *ctlr = device_get_softc(dev);
796 struct ata_chip_id *idx;
797 static struct ata_chip_id ids[] =
798 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" },
799 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" },
800 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
801 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
802 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" },
803 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" },
804 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
805 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" },
806 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
807 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" },
808 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
809 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" },
810 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
811 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" },
812 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" },
813 { ATA_I82801EB_1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" },
814 { 0, 0, 0, 0, 0, 0}};
817 if (!(idx = ata_match_chip(dev, ids)))
820 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
821 device_set_desc_copy(dev, buffer);
823 ctlr->chipinit = ata_intel_chipinit;
828 ata_intel_chipinit(device_t dev)
830 struct ata_pci_controller *ctlr = device_get_softc(dev);
832 if (ata_setup_interrupt(dev))
835 if (ctlr->chip->chipid == ATA_I82371FB)
836 ctlr->setmode = ata_intel_old_setmode;
837 else if (ctlr->chip->max_dma < ATA_SA150)
838 ctlr->setmode = ata_intel_new_setmode;
840 ctlr->setmode = ata_sata_setmode;
845 ata_intel_old_setmode(struct ata_device *atadev, int mode)
851 ata_intel_new_setmode(struct ata_device *atadev, int mode)
853 device_t parent = device_get_parent(atadev->channel->dev);
854 struct ata_pci_controller *ctlr = device_get_softc(parent);
855 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
856 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
857 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
858 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
859 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
860 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
861 u_int32_t mask40 = 0, new40 = 0;
862 u_int8_t mask44 = 0, new44 = 0;
864 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
865 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
867 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
869 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
870 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
874 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
877 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
878 (error) ? "FAILURE " : "",
879 ata_mode2str(mode), ctlr->chip->text);
883 if (mode >= ATA_UDMA0) {
884 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
885 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) |
886 (0x01 + !(mode & 0x01)), 2);
889 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
890 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
892 if (mode >= ATA_UDMA2)
893 pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2);
895 pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2);
897 if (mode >= ATA_UDMA5)
898 pci_write_config(parent, 0x54, reg54 | (0x10000 << devno), 2);
900 pci_write_config(parent, 0x54, reg54 & ~(0x10000 << devno), 2);
902 reg40 &= ~0x00ff00ff;
905 if (atadev->unit == ATA_MASTER) {
907 new40 = timings[ata_mode2idx(mode)] << 8;
911 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
912 (timings[ata_mode2idx(mode)] & 0x03);
914 if (atadev->channel->unit) {
920 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
921 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
927 * National chipset support functions
930 ata_national_ident(device_t dev)
932 struct ata_pci_controller *ctlr = device_get_softc(dev);
934 /* this chip is a clone of the Cyrix chip, bugs and all */
935 if (pci_get_devid(dev) == ATA_SC1100) {
936 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
937 ctlr->chipinit = ata_national_chipinit;
943 static device_t nat_host = NULL;
946 ata_national_chipinit(device_t dev)
948 struct ata_pci_controller *ctlr = device_get_softc(dev);
952 if (ata_setup_interrupt(dev))
955 /* locate the ISA part in the southbridge and enable UDMA33 */
956 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
957 for (i = 0; i < nchildren; i++) {
958 if (pci_get_devid(children[i]) == 0x0510100b) {
959 nat_host = children[i];
963 free(children, M_TEMP);
965 ctlr->setmode = ata_national_setmode;
970 ata_national_setmode(struct ata_device *atadev, int mode)
972 device_t parent = device_get_parent(atadev->channel->dev);
973 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
974 u_int32_t piotiming[] =
975 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
976 0x00803020, 0x20102010, 0x00100010,
977 0x00100010, 0x00100010, 0x00100010 };
978 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
979 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
982 atadev->channel->dma->alignment = 16;
983 atadev->channel->dma->max_iosize = 63 * 1024;
985 mode = ata_limit_mode(atadev, mode, ATA_UDMA2);
987 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
990 ata_prtdev(atadev, "%s setting %s on National chip\n",
991 (error) ? "failed" : "success", ata_mode2str(mode));
993 if (mode >= ATA_UDMA0) {
994 pci_write_config(parent, 0x44 + (devno << 3),
995 udmatiming[mode & ATA_MODE_MASK], 4);
997 else if (mode >= ATA_WDMA0) {
998 pci_write_config(parent, 0x44 + (devno << 3),
999 dmatiming[mode & ATA_MODE_MASK], 4);
1002 pci_write_config(parent, 0x44 + (devno << 3),
1003 pci_read_config(parent, 0x44 + (devno << 3), 4) |
1006 pci_write_config(parent, 0x40 + (devno << 3),
1007 piotiming[ata_mode2idx(mode)], 4);
1008 atadev->mode = mode;
1013 * nVidia chipset support functions
1016 ata_nvidia_ident(device_t dev)
1018 struct ata_pci_controller *ctlr = device_get_softc(dev);
1019 struct ata_chip_id *idx;
1020 static struct ata_chip_id ids[] =
1021 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA5, "nVidia nForce" },
1022 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce2" },
1023 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nVidia nForce3" },
1024 { 0, 0, 0, 0, 0, 0}};
1027 if (!(idx = ata_match_chip(dev, ids)))
1030 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1031 device_set_desc_copy(dev, buffer);
1033 ctlr->chipinit = ata_nvidia_chipinit;
1038 ata_nvidia_chipinit(device_t dev)
1040 struct ata_pci_controller *ctlr = device_get_softc(dev);
1042 if (ata_setup_interrupt(dev))
1045 /* set prefetch, postwrite */
1046 if (ctlr->chip->cfg2 & AMDBUG)
1047 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
1049 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) | 0xf0, 1);
1051 ctlr->setmode = ata_via_family_setmode;
1056 * Promise chipset support functions
1059 ata_promise_ident(device_t dev)
1061 struct ata_pci_controller *ctlr = device_get_softc(dev);
1062 struct ata_chip_id *idx;
1063 static struct ata_chip_id ids[] =
1064 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" },
1065 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" },
1066 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" },
1067 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" },
1068 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" },
1069 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" },
1070 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" },
1071 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" },
1072 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" },
1073 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" },
1074 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" },
1075 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" },
1076 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" },
1077 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" },
1078 { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" },
1079 { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" },
1080 { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" },
1081 { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" },
1082 { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" },
1083 { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" },
1084 { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" },
1085 { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" },
1086 { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" },
1087 { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" },
1088 { 0, 0, 0, 0, 0, 0}};
1090 uintptr_t devid = 0;
1092 if (!(idx = ata_match_chip(dev, ids)))
1095 /* if we are on a SuperTrak SX6000 dont attach */
1096 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1097 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1098 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1099 devid == ATA_I960RM)
1102 strcpy(buffer, idx->text);
1103 /* if we are on a FastTrak TX4, adjust the interrupt resource */
1104 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
1105 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
1106 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
1107 devid == ATA_DEC_21150) {
1108 static long start = 0, end = 0;
1110 if (pci_get_slot(dev) == 1) {
1111 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
1112 strcat(buffer, " (channel 0+1)");
1114 else if (pci_get_slot(dev) == 2 && start && end) {
1115 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
1117 strcat(buffer, " (channel 2+3)");
1123 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1124 device_set_desc_copy(dev, buffer);
1126 ctlr->chipinit = ata_promise_chipinit;
1131 ata_promise_chipinit(device_t dev)
1133 struct ata_pci_controller *ctlr = device_get_softc(dev);
1134 int rid = ATA_IRQ_RID;
1136 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1137 RF_SHAREABLE | RF_ACTIVE))) {
1138 device_printf(dev, "unable to map interrupt\n");
1142 switch (ctlr->chip->cfg1) {
1145 ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) | 0x0a);
1147 ctlr->dmainit = ata_promise_new_dmainit;
1151 /* enable burst mode */
1152 ATA_OUTB(ctlr->r_io1, 0x1f, ATA_INB(ctlr->r_io1, 0x1f) | 0x01);
1154 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1155 ata_promise_old_intr, ctlr, &ctlr->handle))) {
1156 device_printf(dev, "unable to setup interrupt\n");
1162 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1163 ata_promise_tx2_intr, ctlr, &ctlr->handle))) {
1164 device_printf(dev, "unable to setup interrupt\n");
1171 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1172 0, ~0, 1, RF_ACTIVE)))
1175 ctlr->dmainit = ata_promise_mio_dmainit;
1176 ctlr->allocate = ata_promise_mio_allocate;
1178 if (ctlr->chip->cfg2 & PRDUAL) {
1179 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x01) > 0) +
1180 ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 2;
1182 else if (ctlr->chip->cfg2 & PRSATA) {
1183 ATA_OUTL(ctlr->r_io2, 0x06c, 0x00ff0033);
1184 ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 3;
1189 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1190 ata_promise_mio_intr, ctlr, &ctlr->handle))) {
1191 device_printf(dev, "unable to setup interrupt\n");
1196 ctlr->setmode = ata_promise_setmode;
1201 ata_promise_mio_allocate(device_t dev, struct ata_channel *ch)
1203 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1206 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1207 ch->r_io[i].res = ctlr->r_io2;
1208 ch->r_io[i].offset = 0x200 + (i << 2) + (ch->unit << 7);
1210 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1211 ch->r_io[ATA_ALTSTAT].offset = 0x238 + (ch->unit << 7);
1212 ch->r_io[ATA_BMCTL_PORT].res = ctlr->r_io2;
1213 ch->r_io[ATA_BMCTL_PORT].offset = 0x260 + (ch->unit << 7);
1214 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1215 ch->r_io[ATA_BMDTP_PORT].offset = 0x244 + (ch->unit << 7);
1216 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1217 ch->r_io[ATA_BMDEVSPEC_0].offset = ((ch->unit + 1) << 2);
1218 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1220 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1221 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1223 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1225 ch->flags |= (ATA_NO_SLAVE | ATA_USE_16BIT);
1231 ata_promise_old_intr(void *data)
1233 struct ata_pci_controller *ctlr = data;
1234 struct ata_channel *ch;
1237 /* implement this as a toggle instead to balance load XXX */
1238 for (unit = 0; unit < 2; unit++) {
1239 if (!(ch = ctlr->interrupt[unit].argument))
1241 if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
1243 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1245 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1246 ATA_BMSTAT_INTERRUPT)
1248 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1251 ctlr->interrupt[unit].function(ch);
1257 ata_promise_tx2_intr(void *data)
1259 struct ata_pci_controller *ctlr = data;
1260 struct ata_channel *ch;
1263 /* implement this as a toggle instead to balance load XXX */
1264 for (unit = 0; unit < 2; unit++) {
1265 if (!(ch = ctlr->interrupt[unit].argument))
1267 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
1268 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
1270 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1272 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1273 ATA_BMSTAT_INTERRUPT)
1275 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1278 ctlr->interrupt[unit].function(ch);
1284 ata_promise_mio_intr(void *data)
1286 struct ata_pci_controller *ctlr = data;
1287 struct ata_channel *ch;
1288 u_int32_t irq_vector;
1291 irq_vector = ATA_INL(ctlr->r_io2, 0x0040);
1292 for (unit = 0; unit < ctlr->channels; unit++) {
1293 if (irq_vector & (1 << (unit + 1))) {
1294 if ((ch = ctlr->interrupt[unit].argument)) {
1295 ctlr->interrupt[unit].function(ch);
1296 ATA_IDX_OUTL(ch, ATA_BMCMD_PORT,
1297 (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00003f9f) |
1299 ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001);
1306 ata_promise_setmode(struct ata_device *atadev, int mode)
1308 device_t parent = device_get_parent(atadev->channel->dev);
1309 struct ata_pci_controller *ctlr = device_get_softc(parent);
1310 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1312 u_int32_t timings33[][2] = {
1313 /* PROLD PRNEW mode */
1314 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
1315 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
1316 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
1317 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
1318 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
1319 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
1320 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
1321 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
1322 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
1323 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
1324 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
1325 { 0, 0x00424ef6 }, /* UDMA 3 */
1326 { 0, 0x004127f3 }, /* UDMA 4 */
1327 { 0, 0x004127f3 } /* UDMA 5 */
1330 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1332 switch (ctlr->chip->cfg1) {
1335 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) &
1336 (atadev->channel->unit ? 1 << 11 : 1 << 10))) {
1338 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1341 if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX)
1342 mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX);
1346 ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b);
1347 if (mode > ATA_UDMA2 &&
1348 ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) {
1350 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1356 if (mode > ATA_UDMA2 &&
1357 (ATA_IDX_INL(atadev->channel, ATA_BMCTL_PORT) & 0x01000000)) {
1359 "DMA limited to UDMA33, non-ATA66 cable or device\n");
1365 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1368 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1369 (error) ? "FAILURE " : "",
1370 ata_mode2str(mode), ctlr->chip->text);
1372 if (ctlr->chip->cfg1 < PRTX)
1373 pci_write_config(parent, 0x60 + (devno << 2),
1374 timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
1375 atadev->mode = mode;
1381 ata_promise_new_dmainit(struct ata_channel *ch)
1385 ch->dma->start = ata_promise_new_dmastart;
1386 ch->dma->stop = ata_promise_new_dmastop;
1391 ata_promise_new_dmastart(struct ata_channel *ch)
1393 struct ata_pci_controller *ctlr =
1394 device_get_softc(device_get_parent(ch->dev));
1396 if (ch->flags & ATA_48BIT_ACTIVE) {
1397 ATA_OUTB(ctlr->r_io1, 0x11,
1398 ATA_INB(ctlr->r_io1, 0x11) | (ch->unit ? 0x08 : 0x02));
1399 ATA_OUTL(ctlr->r_io1, 0x20,
1400 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
1401 (ch->dma->cur_iosize >> 1));
1403 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
1404 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1405 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1406 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1407 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
1408 ATA_BMCMD_START_STOP);
1413 ata_promise_new_dmastop(struct ata_channel *ch)
1415 struct ata_pci_controller *ctlr =
1416 device_get_softc(device_get_parent(ch->dev));
1419 if (ch->flags & ATA_48BIT_ACTIVE) {
1420 ATA_OUTB(ctlr->r_io1, 0x11,
1421 ATA_INB(ctlr->r_io1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
1422 ATA_OUTL(ctlr->r_io1, 0x20, 0);
1424 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
1425 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
1426 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1432 ata_promise_mio_dmainit(struct ata_channel *ch)
1436 ch->dma->start = ata_promise_mio_dmastart;
1437 ch->dma->stop = ata_promise_mio_dmastop;
1442 ata_promise_mio_dmastart(struct ata_channel *ch)
1444 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab);
1445 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1446 (ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x000000c0) |
1447 ((ch->dma->flags & ATA_DMA_READ) ? 0x00000080 : 0x000000c0));
1452 ata_promise_mio_dmastop(struct ata_channel *ch)
1454 ATA_IDX_OUTL(ch, ATA_BMCTL_PORT,
1455 ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x00000080);
1460 * ServerWorks chipset support functions
1463 ata_serverworks_ident(device_t dev)
1465 struct ata_pci_controller *ctlr = device_get_softc(dev);
1466 struct ata_chip_id *idx;
1467 static struct ata_chip_id ids[] =
1468 {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" },
1469 { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" },
1470 { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" },
1471 { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" },
1472 { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" },
1473 { 0, 0, 0, 0, 0, 0}};
1476 if (!(idx = ata_match_chip(dev, ids)))
1479 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1480 device_set_desc_copy(dev, buffer);
1482 ctlr->chipinit = ata_serverworks_chipinit;
1487 ata_serverworks_chipinit(device_t dev)
1489 struct ata_pci_controller *ctlr = device_get_softc(dev);
1491 if (ata_setup_interrupt(dev))
1494 if (ctlr->chip->cfg1 == SWKS33) {
1498 /* locate the ISA part in the southbridge and enable UDMA33 */
1499 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
1500 for (i = 0; i < nchildren; i++) {
1501 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
1502 pci_write_config(children[i], 0x64,
1503 (pci_read_config(children[i], 0x64, 4) &
1504 ~0x00002000) | 0x00004000, 4);
1508 free(children, M_TEMP);
1512 pci_write_config(dev, 0x5a,
1513 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
1514 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
1516 ctlr->setmode = ata_serverworks_setmode;
1521 ata_serverworks_setmode(struct ata_device *atadev, int mode)
1523 device_t parent = device_get_parent(atadev->channel->dev);
1524 struct ata_pci_controller *ctlr = device_get_softc(parent);
1525 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1526 int offset = devno ^ 0x01;
1528 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1529 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1530 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1532 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1534 mode = ata_check_80pin(atadev, mode);
1536 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1539 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1540 (error) ? "FAILURE " : "",
1541 ata_mode2str(mode), ctlr->chip->text);
1543 if (mode >= ATA_UDMA0) {
1544 pci_write_config(parent, 0x56,
1545 (pci_read_config(parent, 0x56, 2) &
1546 ~(0xf << (devno << 2))) |
1547 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1549 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) |
1550 (0x01 << devno), 1);
1551 pci_write_config(parent, 0x44,
1552 (pci_read_config(parent, 0x44, 4) &
1553 ~(0xff << (offset << 8))) |
1554 (dmatimings[2] << (offset << 8)), 4);
1556 else if (mode >= ATA_WDMA0) {
1557 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1558 ~(0x01 << devno), 1);
1559 pci_write_config(parent, 0x44,
1560 (pci_read_config(parent, 0x44, 4) &
1561 ~(0xff << (offset << 8))) |
1562 (dmatimings[mode & ATA_MODE_MASK]<<(offset<<8)),4);
1565 pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) &
1566 ~(0x01 << devno), 1);
1568 pci_write_config(parent, 0x40,
1569 (pci_read_config(parent, 0x40, 4) &
1570 ~(0xff << (offset << 8))) |
1571 (piotimings[ata_mode2idx(mode)] << (offset << 8)), 4);
1572 atadev->mode = mode;
1577 * Silicon Image (former CMD) chipset support functions
1580 ata_sii_ident(device_t dev)
1582 struct ata_pci_controller *ctlr = device_get_softc(dev);
1583 struct ata_chip_id *idx;
1584 static struct ata_chip_id ids[] =
1585 {{ ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1586 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
1587 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
1588 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
1589 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
1590 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
1591 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
1592 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
1593 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
1594 { 0, 0, 0, 0, 0, 0}};
1597 if (!(idx = ata_match_chip(dev, ids)))
1600 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
1601 device_set_desc_copy(dev, buffer);
1603 ctlr->chipinit = ata_sii_chipinit;
1608 ata_sii_chipinit(device_t dev)
1610 struct ata_pci_controller *ctlr = device_get_softc(dev);
1611 int rid = ATA_IRQ_RID;
1613 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1614 RF_SHAREABLE | RF_ACTIVE))) {
1615 device_printf(dev, "unable to map interrupt\n");
1619 if (ctlr->chip->cfg1 == SIIMEMIO) {
1620 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1621 ata_sii_intr, ctlr, &ctlr->handle))) {
1622 device_printf(dev, "unable to setup interrupt\n");
1626 if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1627 0, ~0, 1, RF_ACTIVE)))
1630 if (ctlr->chip->cfg2 & SIISETCLK) {
1631 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1632 pci_write_config(dev, 0x8a,
1633 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
1634 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
1635 device_printf(dev, "%s could not set ATA133 clock\n",
1639 /* enable interrupt as BIOS might not */
1640 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
1642 /* setup chipset defaults as BIOS might not */
1643 pci_write_config(dev, 0xa2, 0x328a, 2);
1644 pci_write_config(dev, 0xa4, 0x328a328a, 4);
1645 pci_write_config(dev, 0xa8, 0x22082208, 4);
1646 pci_write_config(dev, 0xac, 0x40094009, 4);
1647 pci_write_config(dev, 0xe2, 0x328a, 2);
1648 pci_write_config(dev, 0xe4, 0x328a328a, 4);
1649 pci_write_config(dev, 0xe8, 0x22082208, 4);
1650 pci_write_config(dev, 0xec, 0x40094009, 4);
1652 ctlr->allocate = ata_sii_mio_allocate;
1653 if (ctlr->chip->max_dma >= ATA_SA150) {
1654 ctlr->setmode = ata_sata_setmode;
1655 ctlr->locking = ata_serialize;
1658 ctlr->setmode = ata_sii_setmode;
1661 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
1662 ctlr->chip->cfg2 & SIIINTR ?
1663 ata_cmd_intr : ata_cmd_old_intr,
1664 ctlr, &ctlr->handle))) {
1665 device_printf(dev, "unable to setup interrupt\n");
1669 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
1670 device_printf(dev, "HW has secondary channel disabled\n");
1674 /* enable interrupt as BIOS might not */
1675 pci_write_config(dev, 0x71, 0x01, 1);
1677 ctlr->setmode = ata_cmd_setmode;
1683 ata_sii_mio_allocate(device_t dev, struct ata_channel *ch)
1685 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1688 for (i = ATA_DATA; i <= ATA_STATUS; i++) {
1689 ch->r_io[i].res = ctlr->r_io2;
1690 ch->r_io[i].offset = 0x80 + i + (ch->unit << 6);
1692 ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2;
1693 ch->r_io[ATA_ALTSTAT].offset = 0x8a + (ch->unit << 6);
1694 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2;
1695 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (ch->unit << 3);
1696 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_io2;
1697 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (ch->unit << 3);
1698 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2;
1699 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (ch->unit << 3);
1700 ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2;
1701 ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (ch->unit << 6);
1702 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2;
1704 if (ctlr->chip->max_dma >= ATA_SA150)
1705 ch->flags |= ATA_NO_SLAVE;
1707 if (ctlr->chip->cfg2 & SIIBUG)
1708 ch->dma->boundary = 8 * 1024;
1713 ata_sii_intr(void *data)
1715 struct ata_pci_controller *ctlr = data;
1716 struct ata_channel *ch;
1719 /* implement this as a toggle instead to balance load XXX */
1720 for (unit = 0; unit < 2; unit++) {
1721 if (!(ch = ctlr->interrupt[unit].argument))
1723 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
1725 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1727 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1728 ATA_BMSTAT_INTERRUPT)
1730 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1733 ctlr->interrupt[unit].function(ch);
1739 ata_cmd_intr(void *data)
1741 struct ata_pci_controller *ctlr = data;
1742 struct ata_channel *ch;
1746 /* implement this as a toggle instead to balance load XXX */
1747 for (unit = 0; unit < 2; unit++) {
1748 if (!(ch = ctlr->interrupt[unit].argument))
1750 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
1751 (ch->unit ? 0x08 : 0x04))) {
1752 pci_write_config(device_get_parent(ch->dev), 0x71,
1753 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
1755 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1757 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1758 ATA_BMSTAT_INTERRUPT)
1760 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1763 ctlr->interrupt[unit].function(ch);
1769 ata_cmd_old_intr(void *data)
1771 struct ata_pci_controller *ctlr = data;
1772 struct ata_channel *ch;
1775 /* implement this as a toggle instead to balance load XXX */
1776 for (unit = 0; unit < 2; unit++) {
1777 if (!(ch = ctlr->interrupt[unit].argument))
1779 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
1780 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1782 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
1783 ATA_BMSTAT_INTERRUPT)
1785 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
1788 ctlr->interrupt[unit].function(ch);
1793 ata_sii_setmode(struct ata_device *atadev, int mode)
1795 device_t parent = device_get_parent(atadev->channel->dev);
1796 struct ata_pci_controller *ctlr = device_get_softc(parent);
1797 int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1);
1798 int mreg = atadev->channel->unit ? 0x84 : 0x80;
1799 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
1800 int mval = pci_read_config(parent, mreg, 1) & ~mask;
1803 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1805 if (ctlr->chip->max_dma < ATA_UDMA2) {
1806 mode = ata_check_80pin(atadev, mode);
1808 else if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
1809 (atadev->channel->unit ? 0x02 : 0x01))) {
1810 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
1814 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1817 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1818 (error) ? "FAILURE " : "",
1819 ata_mode2str(mode), ctlr->chip->text);
1823 if (mode >= ATA_UDMA0) {
1824 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1825 u_int8_t ureg = 0xac + rego;
1827 pci_write_config(parent, mreg,
1828 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
1829 pci_write_config(parent, ureg,
1830 (pci_read_config(parent, ureg, 1) & ~0x3f) |
1831 udmatimings[mode & ATA_MODE_MASK], 1);
1834 else if (mode >= ATA_WDMA0) {
1835 u_int8_t dreg = 0xa8 + rego;
1836 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
1838 pci_write_config(parent, mreg,
1839 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
1840 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
1844 u_int8_t preg = 0xa4 + rego;
1845 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
1847 pci_write_config(parent, mreg,
1848 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
1849 pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2);
1851 atadev->mode = mode;
1855 ata_cmd_setmode(struct ata_device *atadev, int mode)
1857 device_t parent = device_get_parent(atadev->channel->dev);
1858 struct ata_pci_controller *ctlr = device_get_softc(parent);
1859 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
1862 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
1864 mode = ata_check_80pin(atadev, mode);
1866 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1869 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
1870 (error) ? "FAILURE " : "",
1871 ata_mode2str(mode), ctlr->chip->text);
1873 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
1874 int ureg = atadev->channel->unit ? 0x7b : 0x73;
1876 if (mode >= ATA_UDMA0) {
1877 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
1878 { 0x11, 0x42 }, { 0x25, 0x8a },
1879 { 0x15, 0x4a }, { 0x05, 0x0a } };
1881 u_int8_t umode = pci_read_config(parent, ureg, 1);
1883 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
1884 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
1885 pci_write_config(parent, ureg, umode, 1);
1887 else if (mode >= ATA_WDMA0) {
1888 int dmatimings[] = { 0x87, 0x32, 0x3f };
1890 pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1);
1891 pci_write_config(parent, ureg,
1892 pci_read_config(parent, ureg, 1) &
1893 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1896 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1897 pci_write_config(parent, treg,
1898 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
1899 pci_write_config(parent, ureg,
1900 pci_read_config(parent, ureg, 1) &
1901 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
1903 atadev->mode = mode;
1908 * SiS chipset support functions
1911 ata_sis_ident(device_t dev)
1913 struct ata_pci_controller *ctlr = device_get_softc(dev);
1914 struct ata_chip_id *idx;
1915 static struct ata_chip_id ids[] =
1916 {{ ATA_SIS964_1,0x00, SISSATA, 0, ATA_SA150, "SiS 964" }, /* south */
1917 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 964" }, /* south */
1918 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */
1919 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */
1921 { ATA_SIS755, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 755" }, /* ext south */
1922 { ATA_SIS752, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 752" }, /* unknown */
1923 { ATA_SIS751, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 751" }, /* unknown */
1924 { ATA_SIS750, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 750" }, /* unknown */
1925 { ATA_SIS748, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 748" }, /* unknown */
1926 { ATA_SIS746, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 746" }, /* ext south */
1927 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */
1928 { ATA_SIS740, 0x00, SIS_SOUTH, 0, ATA_UDMA5, "SiS 740" }, /* ext south */
1929 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */
1930 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */
1931 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */
1933 { ATA_SIS658, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 658" }, /* ext south */
1934 { ATA_SIS655, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 655" }, /* ext south */
1935 { ATA_SIS652, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 652" }, /* unknown */
1936 { ATA_SIS651, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 651" }, /* ext south */
1937 { ATA_SIS650, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 650" }, /* ext south */
1938 { ATA_SIS648, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 648" }, /* ext south */
1939 { ATA_SIS646, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645DX"},/* ext south */
1940 { ATA_SIS645, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645" }, /* ext south */
1941 { ATA_SIS640, 0x00, SIS_SOUTH, 0, ATA_UDMA4, "SiS 640" }, /* ext south */
1942 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */
1943 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */
1944 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */
1945 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */
1946 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */
1948 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" },
1949 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" },
1950 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" },
1952 { ATA_SIS5513, 0xc2, SIS33, 0, ATA_UDMA2, "SiS 5513" },
1953 { ATA_SIS5513, 0x00, SIS33, 0, ATA_WDMA2, "SiS 5513" },
1954 { 0, 0, 0, 0, 0, 0 }};
1957 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
1960 if (idx->cfg1 == SIS_SOUTH) {
1961 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) & 0x7f, 1);
1962 if (pci_read_config(dev, 0x00, 4) == ATA_SIS5518) {
1963 idx->cfg1 = SIS133NEW;
1964 sprintf(buffer, "SiS 96X %s controller",ata_mode2str(idx->max_dma));
1967 struct ata_chip_id id[] =
1968 {{ ATA_SISSOUTH, 0x10, 0, 0, ATA_UDMA6, "SiS 961" },
1969 { 0, 0, 0, 0, 0, 0 }};
1971 if (ata_find_chip(dev, id, pci_get_slot(dev)))
1972 idx->cfg1 = SIS133OLD;
1974 idx->max_dma = ATA_UDMA5;
1975 idx->cfg1 = SIS100NEW;
1977 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
1979 pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) | 0x80, 1);
1982 sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma));
1983 device_set_desc_copy(dev, buffer);
1985 ctlr->chipinit = ata_sis_chipinit;
1990 ata_sis_chipinit(device_t dev)
1992 struct ata_pci_controller *ctlr = device_get_softc(dev);
1994 if (ata_setup_interrupt(dev))
1997 switch (ctlr->chip->cfg1) {
2002 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) | 0x04, 1);
2006 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) | 0x01, 1);
2009 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) & 0xfff7, 2);
2010 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) & 0xfff7, 2);
2013 pci_write_config(dev, 0x04, pci_read_config(dev, 0x04, 2) & ~0x0400, 2);
2014 ctlr->setmode = ata_sata_setmode;
2019 ctlr->setmode = ata_sis_setmode;
2024 ata_sis_setmode(struct ata_device *atadev, int mode)
2026 device_t parent = device_get_parent(atadev->channel->dev);
2027 struct ata_pci_controller *ctlr = device_get_softc(parent);
2028 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2031 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2033 if (ctlr->chip->cfg1 == SIS133NEW) {
2034 if (mode > ATA_UDMA2 &&
2035 pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){
2037 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2042 if (mode > ATA_UDMA2 &&
2043 pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){
2045 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2050 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2053 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2054 (error) ? "FAILURE " : "",
2055 ata_mode2str(mode), ctlr->chip->text);
2057 switch (ctlr->chip->cfg1) {
2059 u_int32_t timings[] =
2060 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
2061 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
2062 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
2065 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
2066 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
2070 u_int16_t timings[] =
2071 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
2072 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
2074 u_int16_t reg = 0x40 + (devno << 1);
2076 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2080 u_int16_t timings[] =
2081 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
2082 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
2083 u_int16_t reg = 0x40 + (devno << 1);
2085 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2091 u_int16_t timings[] =
2092 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
2093 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
2094 u_int16_t reg = 0x40 + (devno << 1);
2096 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
2100 atadev->mode = mode;
2106 ata_via_ident(device_t dev)
2108 struct ata_pci_controller *ctlr = device_get_softc(dev);
2109 struct ata_chip_id *idx;
2110 static struct ata_chip_id ids[] =
2111 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" },
2112 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" },
2113 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" },
2114 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" },
2115 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"},
2116 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" },
2117 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" },
2118 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" },
2119 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" },
2120 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" },
2121 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" },
2122 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" },
2123 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8237" },
2124 { 0, 0, 0, 0, 0, 0 }};
2125 static struct ata_chip_id new_ids[] =
2126 {{ ATA_VIA8237, 0x00, 0x00, 0x00, ATA_SA150, "VIA 8237" },
2127 { 0, 0, 0, 0, 0, 0 }};
2130 if (pci_get_devid(dev) == ATA_VIA82C571) {
2131 if (!(idx = ata_find_chip(dev, ids, pci_get_slot(dev))))
2135 if (!(idx = ata_match_chip(dev, new_ids)))
2139 sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
2140 device_set_desc_copy(dev, buffer);
2142 ctlr->chipinit = ata_via_chipinit;
2147 ata_via_chipinit(device_t dev)
2149 struct ata_pci_controller *ctlr = device_get_softc(dev);
2151 if (ata_setup_interrupt(dev))
2154 if (ctlr->chip->max_dma >= ATA_SA150) {
2155 ctlr->setmode = ata_sata_setmode;
2159 /* prepare for ATA-66 on the 82C686a and 82C596b */
2160 if (ctlr->chip->cfg2 & VIACLK)
2161 pci_write_config(dev, 0x50, 0x030b030b, 4);
2163 /* the southbridge might need the data corruption fix */
2164 if (ctlr->chip->cfg2 & VIABUG)
2165 ata_via_southbridge_fixup(dev);
2167 /* set prefetch, postwrite */
2168 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
2170 /* set fifo configuration half'n'half */
2171 pci_write_config(dev, 0x43,
2172 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
2174 /* set status register read retry */
2175 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
2177 /* set DMA read & end-of-sector fifo flush */
2178 pci_write_config(dev, 0x46,
2179 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
2181 /* set sector size */
2182 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
2183 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
2185 ctlr->setmode = ata_via_family_setmode;
2190 ata_via_southbridge_fixup(device_t dev)
2195 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2198 for (i = 0; i < nchildren; i++) {
2199 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
2200 pci_get_devid(children[i]) == ATA_VIA8371 ||
2201 pci_get_devid(children[i]) == ATA_VIA8662 ||
2202 pci_get_devid(children[i]) == ATA_VIA8361) {
2203 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
2205 if ((reg76 & 0xf0) != 0xd0) {
2207 "Correcting VIA config for southbridge data corruption bug\n");
2208 pci_write_config(children[i], 0x75, 0x80, 1);
2209 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
2214 free(children, M_TEMP);
2217 /* common code for VIA, AMD & nVidia */
2219 ata_via_family_setmode(struct ata_device *atadev, int mode)
2221 device_t parent = device_get_parent(atadev->channel->dev);
2222 struct ata_pci_controller *ctlr = device_get_softc(parent);
2223 u_int8_t timings[] = { 0xff, 0xff, 0xff, 0x55, 0x51, 0xff, 0x55, 0x51,
2224 0x51, 0x51, 0x51, 0x51, 0x51, 0x51 };
2226 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
2227 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
2228 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
2229 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
2230 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
2231 int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit);
2232 int reg = 0x53 - devno;
2235 mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
2237 if (ctlr->chip->cfg2 & AMDCABLE) {
2238 if (mode > ATA_UDMA2 &&
2239 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
2241 "DMA limited to UDMA33, non-ATA66 cable or device\n");
2246 mode = ata_check_80pin(atadev, mode);
2248 if (ctlr->chip->cfg2 & NVIDIA)
2251 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
2253 error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2256 ata_prtdev(atadev, "%ssetting %s on %s chip\n",
2257 (error) ? "FAILURE " : "", ata_mode2str(mode),
2260 if (mode >= ATA_UDMA0)
2261 pci_write_config(parent, reg,
2262 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
2264 pci_write_config(parent, reg, 0x8b, 1);
2265 atadev->mode = mode;
2269 /* misc functions */
2270 static struct ata_chip_id *
2271 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
2276 if (device_get_children(device_get_parent(dev), &children, &nchildren))
2279 while (index->chipid != 0) {
2280 for (i = 0; i < nchildren; i++) {
2281 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
2282 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
2283 pci_get_devid(children[i]) == index->chipid &&
2284 pci_get_revid(children[i]) >= index->chiprev) {
2285 free(children, M_TEMP);
2291 free(children, M_TEMP);
2295 static struct ata_chip_id *
2296 ata_match_chip(device_t dev, struct ata_chip_id *index)
2298 while (index->chipid != 0) {
2299 if (pci_get_devid(dev) == index->chipid &&
2300 pci_get_revid(dev) >= index->chiprev)
2308 ata_setup_interrupt(device_t dev)
2310 struct ata_pci_controller *ctlr = device_get_softc(dev);
2311 int rid = ATA_IRQ_RID;
2313 if (!ATA_MASTERDEV(dev)) {
2314 if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2315 RF_SHAREABLE | RF_ACTIVE))) {
2316 device_printf(dev, "unable to map interrupt\n");
2319 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
2320 ata_generic_intr, ctlr, &ctlr->handle))) {
2321 device_printf(dev, "unable to setup interrupt\n");
2329 ata_serialize(struct ata_channel *ch, int flags)
2331 struct ata_pci_controller *scp =
2332 device_get_softc(device_get_parent(ch->dev));
2336 if (scp->locked_ch == ch->unit)
2338 while (!atomic_cmpset_acq_int(&scp->locked_ch, -1, ch->unit))
2339 tsleep(ch->locking, PRIBIO, "atasrl", 1);
2343 if (scp->locked_ch == -1 || scp->locked_ch != ch->unit)
2345 atomic_store_rel_int(&scp->locked_ch, -1);
2346 wakeup(ch->locking);
2353 ata_check_80pin(struct ata_device *atadev, int mode)
2355 if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) {
2356 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
2363 ata_mode2idx(int mode)
2365 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
2366 return (mode & ATA_MODE_MASK) + 8;
2367 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
2368 return (mode & ATA_MODE_MASK) + 5;
2369 return (mode & ATA_MODE_MASK) - ATA_PIO0;