2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/malloc.h>
37 #include <pci/pcivar.h>
38 #include <machine/bus.h>
40 #include <dev/ata/ata-all.h>
43 static void ata_dmacreate(struct ata_device *, int, int);
44 static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int);
45 static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int);
46 static void cyrix_timing(struct ata_device *, int, int);
47 static void promise_timing(struct ata_device *, int, int);
48 static void hpt_timing(struct ata_device *, int, int);
49 static int hpt_cable80(struct ata_device *);
52 #define ATAPI_DEVICE(atadev) \
53 ((atadev->unit == ATA_MASTER && \
54 atadev->channel->devices & ATA_ATAPI_MASTER) || \
55 (atadev->unit == ATA_SLAVE && \
56 atadev->channel->devices & ATA_ATAPI_SLAVE))
58 #define MAXSEGSZ PAGE_SIZE
59 #define MAXTABSZ PAGE_SIZE
60 #define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS))
62 struct ata_dc_cb_args {
68 ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
70 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc;
72 if (!(cba->error = error))
73 cba->maddr = segs[0].ds_addr;
77 ata_dmaalloc(struct ata_device *atadev)
79 struct ata_channel *ch;
80 struct ata_dc_cb_args ccba;
81 struct ata_dmastate *ds;
85 ds = &atadev->dmastate;
87 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE,
88 BUS_SPACE_MAXADDR_32BIT,
89 BUS_SPACE_MAXADDR, NULL, NULL,
90 MAXTABSZ, 1, MAXTABSZ,
91 BUS_DMA_ALLOCNOW, &ds->cdmatag)))
95 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0,
96 BUS_SPACE_MAXADDR_32BIT,
97 BUS_SPACE_MAXADDR, NULL, NULL,
98 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ,
99 BUS_DMA_ALLOCNOW, &ds->ddmatag)))
103 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0,
107 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab,
108 MAXTABSZ, ata_dmasetupc_cb, &ccba,
109 0)) != 0 || ccba.error != 0) {
110 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap);
113 ds->mdmatab = ccba.maddr;
116 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0)
123 ata_dmafree(struct ata_device *atadev)
125 struct ata_dmastate *ds;
127 ds = &atadev->dmastate;
129 bus_dmamap_unload(ds->cdmatag, ds->cdmamap);
130 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap);
136 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap);
140 bus_dma_tag_destroy(ds->cdmatag);
144 bus_dma_tag_destroy(ds->ddmatag);
150 ata_dmafreetags(struct ata_channel *ch)
154 bus_dma_tag_destroy(ch->dmatag);
160 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
164 if (!atadev->channel->dmatag) {
165 if (bus_dma_tag_create(NULL, 1, 0,
166 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
167 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES,
168 BUS_SPACE_MAXSIZE_32BIT, 0,
169 &atadev->channel->dmatag)) {
170 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n");
171 ata_dmainit(atadev, apiomode, -1, -1);
177 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
179 device_t parent = device_get_parent(atadev->channel->dev);
180 int chiptype = atadev->channel->chiptype;
181 int chiprev = pci_get_revid(parent);
182 int channel = atadev->channel->unit;
183 int device = ATA_DEV(atadev->unit);
184 int devno = (channel << 1) + device;
187 /* set our most pessimistic default mode */
188 atadev->mode = ATA_PIO;
190 if (!atadev->channel->r_bmio)
193 /* if simplex controller, only allow DMA on primary channel */
195 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
196 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
197 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
198 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
199 ATA_BMSTAT_DMA_SIMPLEX) {
200 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
205 /* DMA engine address alignment is usually 1 word (2 bytes) */
206 atadev->channel->alignment = 0x1;
209 if (udmamode > 2 && !atadev->param->hwres_cblid) {
210 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
216 case 0x24cb8086: /* Intel ICH4 */
217 case 0x248a8086: /* Intel ICH3 mobile */
218 case 0x248b8086: /* Intel ICH3 */
219 case 0x244a8086: /* Intel ICH2 mobile */
220 case 0x244b8086: /* Intel ICH2 */
222 int32_t mask48, new48;
225 word54 = pci_read_config(parent, 0x54, 2);
226 if (word54 & (0x10 << devno)) {
227 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
228 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
230 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
231 (error) ? "failed" : "success");
233 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
234 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
235 pci_write_config(parent, 0x48,
236 (pci_read_config(parent, 0x48, 4) &
237 ~mask48) | new48, 4);
238 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
239 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
244 /* make sure eventual ATA100 mode from the BIOS is disabled */
245 pci_write_config(parent, 0x54,
246 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
249 case 0x24118086: /* Intel ICH */
250 case 0x76018086: /* Intel ICH */
252 int32_t mask48, new48;
255 word54 = pci_read_config(parent, 0x54, 2);
256 if (word54 & (0x10 << devno)) {
257 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
260 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
261 (error) ? "failed" : "success");
263 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
264 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
265 pci_write_config(parent, 0x48,
266 (pci_read_config(parent, 0x48, 4) &
267 ~mask48) | new48, 4);
268 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
269 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
274 /* make sure eventual ATA66 mode from the BIOS is disabled */
275 pci_write_config(parent, 0x54,
276 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
279 case 0x71118086: /* Intel PIIX4 */
280 case 0x84CA8086: /* Intel PIIX4 */
281 case 0x71998086: /* Intel PIIX4e */
282 case 0x24218086: /* Intel ICH0 */
284 int32_t mask48, new48;
286 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
287 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
289 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
290 (error) ? "failed" : "success");
292 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
293 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
294 pci_write_config(parent, 0x48,
295 (pci_read_config(parent, 0x48, 4) &
296 ~mask48) | new48, 4);
297 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
301 /* make sure eventual ATA33 mode from the BIOS is disabled */
302 pci_write_config(parent, 0x48,
303 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
306 case 0x70108086: /* Intel PIIX3 */
307 if (wdmamode >= 2 && apiomode >= 4) {
308 int32_t mask40, new40, mask44, new44;
310 /* if SITRE not set doit for both channels */
311 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){
312 new40 = pci_read_config(parent, 0x40, 4);
313 new44 = pci_read_config(parent, 0x44, 4);
314 if (!(new40 & 0x00004000)) {
315 new44 &= ~0x0000000f;
316 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
318 if (!(new40 & 0x40000000)) {
319 new44 &= ~0x000000f0;
320 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
323 pci_write_config(parent, 0x40, new40, 4);
324 pci_write_config(parent, 0x44, new44, 4);
326 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
327 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
329 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
330 (error) ? "failed" : "success");
332 if (device == ATA_MASTER) {
350 pci_write_config(parent, 0x40,
351 (pci_read_config(parent, 0x40, 4) & ~mask40)|
353 pci_write_config(parent, 0x44,
354 (pci_read_config(parent, 0x44, 4) & ~mask44)|
356 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
360 /* we could set PIO mode timings, but we assume the BIOS did that */
363 case 0x12308086: /* Intel PIIX */
364 if (wdmamode >= 2 && apiomode >= 4) {
367 word40 = pci_read_config(parent, 0x40, 4);
368 word40 >>= channel * 16;
370 /* Check for timing config usable for DMA on controller */
371 if (!((word40 & 0x3300) == 0x2300 &&
372 ((word40 >> (device ? 4 : 0)) & 1) == 1))
375 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
376 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
378 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
379 (error) ? "failed" : "success");
381 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
387 case 0x522910b9: /* AcerLabs Aladdin IV/V */
388 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
389 if (chiprev < 0xc2 &&
390 atadev->channel->devices & ATA_ATAPI_MASTER &&
391 atadev->channel->devices & ATA_ATAPI_SLAVE) {
392 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
395 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
396 if (udmamode >= 5 && chiprev >= 0xc4) {
397 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
398 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
400 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
401 (error) ? "failed" : "success");
403 int32_t word54 = pci_read_config(parent, 0x54, 4);
405 pci_write_config(parent, 0x4b,
406 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
407 word54 &= ~(0x000f000f << (devno << 2));
408 word54 |= (0x000f0005 << (devno << 2));
409 pci_write_config(parent, 0x54, word54, 4);
410 pci_write_config(parent, 0x53,
411 pci_read_config(parent, 0x53, 1) | 0x03, 1);
412 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
416 if (udmamode >= 4 && chiprev >= 0xc2) {
417 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
418 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
420 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
421 (error) ? "failed" : "success");
423 int32_t word54 = pci_read_config(parent, 0x54, 4);
425 pci_write_config(parent, 0x4b,
426 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
427 word54 &= ~(0x000f000f << (devno << 2));
428 word54 |= (0x00080005 << (devno << 2));
429 pci_write_config(parent, 0x54, word54, 4);
430 pci_write_config(parent, 0x53,
431 pci_read_config(parent, 0x53, 1) | 0x03, 1);
432 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
436 if (udmamode >= 2 && chiprev >= 0x20) {
437 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
438 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
440 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
441 (error) ? "failed" : "success");
443 int32_t word54 = pci_read_config(parent, 0x54, 4);
445 word54 &= ~(0x000f000f << (devno << 2));
446 word54 |= (0x000a0005 << (devno << 2));
447 pci_write_config(parent, 0x54, word54, 4);
448 pci_write_config(parent, 0x53,
449 pci_read_config(parent, 0x53, 1) | 0x03, 1);
450 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
451 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
456 /* make sure eventual UDMA mode from the BIOS is disabled */
457 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
458 ~(0x0008 << (devno << 2)), 2);
460 if (wdmamode >= 2 && apiomode >= 4) {
461 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
462 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
464 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
465 (error) ? "failed" : "success");
467 pci_write_config(parent, 0x53,
468 pci_read_config(parent, 0x53, 1) | 0x03, 1);
469 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
470 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
474 pci_write_config(parent, 0x53,
475 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
476 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
478 ATA_C_F_SETXFER, ATA_WAIT_READY);
480 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
481 (error) ? "failed" : "success",
482 (apiomode >= 0) ? apiomode : 0);
484 int32_t word54 = pci_read_config(parent, 0x54, 4);
487 switch(ATA_PIO0 + apiomode) {
488 case ATA_PIO0: timing = 0x006d0003;
489 case ATA_PIO1: timing = 0x00580002;
490 case ATA_PIO2: timing = 0x00440001;
491 case ATA_PIO3: timing = 0x00330001;
492 case ATA_PIO4: timing = 0x00310001;
493 default: timing = 0x006d0003;
495 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
496 word54 &= ~(0x000f000f << (devno << 2));
497 word54 |= (0x00000004 << (devno << 2));
498 pci_write_config(parent, 0x54, word54, 4);
499 atadev->mode = ATA_PIO0 + apiomode;
504 case 0x01bc10de: /* nVIDIA nForce */
505 case 0x74411022: /* AMD 768 */
506 case 0x74111022: /* AMD 766 */
507 case 0x74091022: /* AMD 756 */
508 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
510 int via_modes[5][7] = {
511 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
512 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
513 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
514 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
515 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0x00 }}; /* AMD/nVIDIA */
519 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
520 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */
521 udmamode = imin(udmamode, 6);
522 reg_val = via_modes[3];
524 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
525 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
526 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
527 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
528 udmamode = imin(udmamode, 5);
529 reg_val = via_modes[2];
531 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
532 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
533 udmamode = imin(udmamode, 4);
534 reg_val = via_modes[1];
536 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
537 udmamode = imin(udmamode, 2);
538 reg_val = via_modes[1];
540 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
541 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
542 udmamode = imin(udmamode, 2);
543 reg_val = via_modes[0];
545 else if (chiptype == 0x74411022 || /* AMD 768 */
546 chiptype == 0x74111022) { /* AMD 766 */
547 udmamode = imin(udmamode, 5);
548 reg_val = via_modes[4];
551 else if (chiptype == 0x74091022) { /* AMD 756 */
552 udmamode = imin(udmamode, 4);
553 reg_val = via_modes[4];
556 else if (chiptype == 0x01bc10de) { /* nVIDIA */
557 udmamode = imin(udmamode, 5);
558 reg_val = via_modes[4];
565 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
566 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
568 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
569 (error) ? "failed" : "success", chip);
571 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
572 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
577 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
578 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
580 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
581 (error) ? "failed" : "success", chip);
583 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
584 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
589 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
590 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
592 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
593 (error) ? "failed" : "success", chip);
595 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
596 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
601 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
602 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
604 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
605 (error) ? "failed" : "success", chip);
607 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
608 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
612 if (wdmamode >= 2 && apiomode >= 4) {
613 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
614 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
616 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
617 (error) ? "failed" : "success", chip);
619 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
620 pci_write_config(parent, 0x4b - devno, 0x31, 1);
621 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
626 /* we could set PIO mode timings, but we assume the BIOS did that */
629 case 0x55131039: /* SiS 5591 */
630 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
631 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
632 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
633 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
634 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
635 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
636 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
637 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
638 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
639 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
640 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
641 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
642 int8_t reg = 0x40 + (devno << 1);
643 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
646 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
647 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
649 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
650 (error) ? "failed" : "success");
652 pci_write_config(parent, reg, val | 0x8000, 2);
653 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
658 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
659 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
661 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
662 (error) ? "failed" : "success");
664 pci_write_config(parent, reg, val | 0x9000, 2);
665 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
670 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
671 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
673 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
674 (error) ? "failed" : "success");
676 pci_write_config(parent, reg, val | 0xb000, 2);
677 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
681 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
682 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
683 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
684 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
685 int8_t reg = 0x40 + (devno << 1);
686 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
689 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
690 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
692 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
693 (error) ? "failed" : "success");
695 pci_write_config(parent, reg, val | 0x9000, 2);
696 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
701 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
702 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
704 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
705 (error) ? "failed" : "success");
707 pci_write_config(parent, reg, val | 0xa000, 2);
708 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
712 } else if (udmamode >= 2 && chiprev > 0xc1) {
713 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
714 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
716 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
717 (error) ? "failed" : "success");
719 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
720 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
724 if (wdmamode >=2 && apiomode >= 4) {
725 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
726 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
728 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
729 (error) ? "failed" : "success");
731 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
732 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
736 /* we could set PIO mode timings, but we assume the BIOS did that */
739 case 0x06801095: /* Sil 0680 ATA133 controller */
741 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
742 u_int8_t uval = pci_read_config(parent, ureg, 1);
743 u_int8_t mreg = channel ? 0x84 : 0x80;
744 u_int8_t mask = device ? 0x30 : 0x03;
745 u_int8_t mode = pci_read_config(parent, mreg, 1);
747 /* enable UDMA mode */
748 pci_write_config(parent, mreg,
749 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
751 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
752 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
754 ata_prtdev(atadev, "%s setting UDMA6 on Sil chip\n",
755 (error) ? "failed" : "success");
757 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1);
758 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
763 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
764 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
766 ata_prtdev(atadev, "%s setting UDMA5 on Sil chip\n",
767 (error) ? "failed" : "success");
769 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1);
770 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
775 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
776 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
778 ata_prtdev(atadev, "%s setting UDMA4 on Sil chip\n",
779 (error) ? "failed" : "success");
781 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1);
782 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
787 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
788 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
790 ata_prtdev(atadev, "%s setting UDMA2 on Sil chip\n",
791 (error) ? "failed" : "success");
793 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1);
794 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
799 /* disable UDMA mode and enable WDMA mode */
800 pci_write_config(parent, mreg,
801 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
802 if (wdmamode >= 2 && apiomode >= 4) {
803 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
804 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
806 ata_prtdev(atadev, "%s setting WDMA2 on Sil chip\n",
807 (error) ? "failed" : "success");
809 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
810 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
815 /* restore PIO mode */
816 pci_write_config(parent, mreg, mode, 1);
818 /* we could set PIO mode timings, but we assume the BIOS did that */
821 case 0x06491095: /* CMD 649 ATA100 controller */
825 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
826 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
828 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
829 (error) ? "failed" : "success");
831 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
832 umode &= ~(device ? 0xca : 0x35);
833 umode |= (device ? 0x0a : 0x05);
834 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
835 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
841 case 0x06481095: /* CMD 648 ATA66 controller */
845 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
846 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
848 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
849 (error) ? "failed" : "success");
851 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
852 umode &= ~(device ? 0xca : 0x35);
853 umode |= (device ? 0x4a : 0x15);
854 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
855 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
862 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
863 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
865 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
866 (error) ? "failed" : "success");
868 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
869 umode &= ~(device ? 0xca : 0x35);
870 umode |= (device ? 0x42 : 0x11);
871 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
872 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
876 /* make sure eventual UDMA mode from the BIOS is disabled */
877 pci_write_config(parent, channel ? 0x7b : 0x73,
878 pci_read_config(parent, channel ? 0x7b : 0x73, 1) &
879 ~(device ? 0xca : 0x53), 1);
882 case 0x06461095: /* CMD 646 ATA controller */
883 if (wdmamode >= 2 && apiomode >= 4) {
884 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
885 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
887 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
888 error ? "failed" : "success");
890 int32_t offset = (devno < 3) ? (devno << 1) : 7;
892 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
893 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
897 /* we could set PIO mode timings, but we assume the BIOS did that */
900 case 0xc6931080: /* Cypress 82c693 ATA controller */
901 if (wdmamode >= 2 && apiomode >= 4) {
902 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
903 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
905 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
906 error ? "failed" : "success");
908 pci_write_config(atadev->channel->dev,
909 channel ? 0x4e:0x4c, 0x2020, 2);
910 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
914 /* we could set PIO mode timings, but we assume the BIOS did that */
917 case 0x01021078: /* Cyrix 5530 ATA33 controller */
918 atadev->channel->alignment = 0xf;
920 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
921 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
923 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
924 (error) ? "failed" : "success");
926 cyrix_timing(atadev, devno, ATA_UDMA2);
927 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
931 if (wdmamode >= 2 && apiomode >= 4) {
932 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
933 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
935 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
936 (error) ? "failed" : "success");
938 cyrix_timing(atadev, devno, ATA_WDMA2);
939 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
943 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
944 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
947 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
948 (error) ? "failed" : "success",
949 ata_mode2str(ATA_PIO0 + apiomode));
950 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
951 atadev->mode = ATA_PIO0 + apiomode;
954 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
955 if (udmamode >= 5 && chiprev >= 0x92) {
956 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
957 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
959 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
960 (error) ? "failed" : "success");
964 pci_write_config(parent, 0x54,
965 pci_read_config(parent, 0x54, 1) |
967 reg56 = pci_read_config(parent, 0x56, 2);
968 reg56 &= ~(0xf << (devno * 4));
969 reg56 |= (0x5 << (devno * 4));
970 pci_write_config(parent, 0x56, reg56, 2);
971 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
976 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
977 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
979 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
980 (error) ? "failed" : "success");
984 pci_write_config(parent, 0x54,
985 pci_read_config(parent, 0x54, 1) |
987 reg56 = pci_read_config(parent, 0x56, 2);
988 reg56 &= ~(0xf << (devno * 4));
989 reg56 |= (0x4 << (devno * 4));
990 pci_write_config(parent, 0x56, reg56, 2);
991 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
997 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
999 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1000 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1002 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1003 (error) ? "failed" : "success");
1007 pci_write_config(parent, 0x54,
1008 pci_read_config(parent, 0x54, 1) |
1009 (0x01 << devno), 1);
1010 reg56 = pci_read_config(parent, 0x56, 2);
1011 reg56 &= ~(0xf << (devno * 4));
1012 reg56 |= (0x2 << (devno * 4));
1013 pci_write_config(parent, 0x56, reg56, 2);
1014 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1018 if (wdmamode >= 2 && apiomode >= 4) {
1019 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1020 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1022 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1023 (error) ? "failed" : "success");
1025 int offset = devno ^ 0x01;
1026 int word44 = pci_read_config(parent, 0x44, 4);
1028 pci_write_config(parent, 0x54,
1029 pci_read_config(parent, 0x54, 1) &
1030 ~(0x01 << devno), 1);
1031 word44 &= ~(0xff << (offset << 8));
1032 word44 |= (0x20 << (offset << 8));
1033 pci_write_config(parent, 0x44, 0x20, 4);
1034 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1038 /* we could set PIO mode timings, but we assume the BIOS did that */
1041 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1042 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1043 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1044 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1045 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1046 if (udmamode >= 6 &&
1047 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1048 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1049 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1051 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1052 (error) ? "failed" : "success");
1054 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1060 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1061 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1062 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1063 if (udmamode >= 5 &&
1064 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1065 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1066 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1068 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1069 (error) ? "failed" : "success");
1071 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1075 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1076 if (udmamode >= 4 &&
1077 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1078 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1079 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1081 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1082 (error) ? "failed" : "success");
1084 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1088 if (udmamode >= 2) {
1089 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1090 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1092 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1093 (error) ? "failed" : "success");
1095 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1099 if (wdmamode >= 2 && apiomode >= 4) {
1100 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1101 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1103 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1104 (error) ? "failed" : "success");
1106 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1112 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1113 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1114 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1115 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) {
1116 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1117 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1119 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1120 (error) ? "failed" : "success");
1122 promise_timing(atadev, devno, ATA_UDMA5);
1123 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1129 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1130 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1131 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1132 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) {
1133 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1134 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1136 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1137 (error) ? "failed" : "success");
1139 promise_timing(atadev, devno, ATA_UDMA4);
1140 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1146 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1147 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1148 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1149 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1151 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1152 (error) ? "failed" : "success");
1154 promise_timing(atadev, devno, ATA_UDMA2);
1155 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1159 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1160 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1161 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1163 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1164 (error) ? "failed" : "success");
1166 promise_timing(atadev, devno, ATA_WDMA2);
1167 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1171 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1172 ATA_PIO0 + apiomode,
1173 ATA_C_F_SETXFER, ATA_WAIT_READY);
1175 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1176 (error) ? "failed" : "success",
1177 (apiomode >= 0) ? apiomode : 0);
1178 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1179 atadev->mode = ATA_PIO0 + apiomode;
1182 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1183 case 0x00051103: /* HighPoint HPT372 controllers */
1184 case 0x00081103: /* HighPoint HPT374 controllers */
1185 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1186 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1187 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1188 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1189 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1190 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1192 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1193 (error) ? "failed" : "success");
1195 hpt_timing(atadev, devno, ATA_UDMA6);
1196 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1200 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1201 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1202 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1203 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1204 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1205 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1207 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1208 (error) ? "failed" : "success");
1210 hpt_timing(atadev, devno, ATA_UDMA5);
1211 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1215 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1216 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1217 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1219 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1220 (error) ? "failed" : "success");
1222 hpt_timing(atadev, devno, ATA_UDMA4);
1223 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1227 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1228 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1229 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1231 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1232 (error) ? "failed" : "success");
1234 hpt_timing(atadev, devno, ATA_UDMA2);
1235 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1239 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1240 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1241 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1243 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1244 (error) ? "failed" : "success");
1246 hpt_timing(atadev, devno, ATA_WDMA2);
1247 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1251 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1252 ATA_PIO0 + apiomode,
1253 ATA_C_F_SETXFER, ATA_WAIT_READY);
1255 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1256 (error) ? "failed" : "success",
1257 (apiomode >= 0) ? apiomode : 0);
1258 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1259 atadev->mode = ATA_PIO0 + apiomode;
1262 case 0x000116ca: /* Cenatek Rocket Drive controller */
1263 if (wdmamode >= 0 &&
1264 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1265 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1266 ata_dmacreate(atadev, apiomode, ATA_DMA);
1268 atadev->mode = ATA_PIO;
1271 default: /* unknown controller chip */
1272 /* better not try generic DMA on ATAPI devices it almost never works */
1273 if (ATAPI_DEVICE(atadev))
1276 /* if controller says its setup for DMA take the easy way out */
1277 /* the downside is we dont know what DMA mode we are in */
1278 if ((udmamode >= 0 || wdmamode >= 2) &&
1279 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1280 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1281 ata_dmacreate(atadev, apiomode, ATA_DMA);
1285 /* well, we have no support for this, but try anyways */
1286 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1287 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1288 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1290 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1291 (error) ? "failed" : "success");
1293 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1298 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1299 ATA_C_F_SETXFER, ATA_WAIT_READY);
1301 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1302 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1304 atadev->mode = ATA_PIO0 + apiomode;
1307 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1308 atadev->mode = ATA_PIO;
1312 struct ata_dmasetup_data_cb_args {
1313 struct ata_dmaentry *dmatab;
1318 ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1320 struct ata_dmasetup_data_cb_args *cba =
1321 (struct ata_dmasetup_data_cb_args *)xsc;
1323 u_int32_t lastcount;
1330 for (i = 0; i < nsegs; i++) {
1332 * A maximum segment size was specified for bus_dma_tag_create, but
1333 * some busdma code does not seem to honor this, so fix up if needed.
1335 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) {
1336 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt);
1337 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff;
1338 cba->dmatab[j].count = htole32(lastcount);
1341 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT);
1345 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1347 struct ata_channel *ch = atadev->channel;
1349 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1350 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1355 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1362 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1364 struct ata_channel *ch = atadev->channel;
1365 struct ata_dmastate *ds = &atadev->dmastate;
1366 struct ata_dmasetup_data_cb_args cba;
1368 if (ds->flags & ATA_DS_ACTIVE)
1369 panic("ata_dmasetup: transfer active on this device!");
1371 cba.dmatab = ds->dmatab;
1372 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE);
1373 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count,
1374 ata_dmasetupd_cb, &cba, 0) || cba.error)
1377 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE);
1378 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD :
1379 BUS_DMASYNC_PREWRITE);
1381 ch->flags |= ATA_DMA_ACTIVE;
1382 ds->flags = ATA_DS_ACTIVE;
1384 ds->flags |= ATA_DS_READ;
1386 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab);
1387 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1388 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1389 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1390 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1391 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1392 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1397 ata_dmadone(struct ata_device *atadev)
1399 struct ata_channel *ch;
1400 struct ata_dmastate *ds;
1403 ch = atadev->channel;
1404 ds = &atadev->dmastate;
1405 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ?
1406 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1407 bus_dmamap_unload(ds->ddmatag, ds->ddmamap);
1409 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1410 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1411 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1412 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1413 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1414 ch->flags &= ~ATA_DMA_ACTIVE;
1416 return (error & ATA_BMSTAT_MASK);
1420 ata_dmastatus(struct ata_channel *ch)
1422 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1426 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1428 u_int32_t reg20 = 0x0000e132;
1429 u_int32_t reg24 = 0x00017771;
1432 case ATA_PIO0: reg20 = 0x0000e132; break;
1433 case ATA_PIO1: reg20 = 0x00018121; break;
1434 case ATA_PIO2: reg20 = 0x00024020; break;
1435 case ATA_PIO3: reg20 = 0x00032010; break;
1436 case ATA_PIO4: reg20 = 0x00040010; break;
1437 case ATA_WDMA2: reg24 = 0x00002020; break;
1438 case ATA_UDMA2: reg24 = 0x00911030; break;
1440 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1441 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1445 promise_timing(struct ata_device *atadev, int devno, int mode)
1447 u_int32_t timing = 0;
1448 /* XXX: Endianess */
1449 struct promise_timing {
1451 u_int8_t prefetch:1;
1462 u_int8_t reserved:8;
1463 } *t = (struct promise_timing*)&timing;
1465 t->iordy = 1; t->iordyp = 1;
1466 if (mode >= ATA_DMA) {
1467 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1470 switch (atadev->channel->chiptype) {
1471 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1474 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1475 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1476 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1477 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1478 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1479 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1480 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1484 case 0x0d38105a: /* Promise Fasttrak 66 */
1485 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1486 case 0x0d30105a: /* Promise OEM ATA 100 */
1487 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1490 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1491 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1492 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1493 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1494 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1495 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1496 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1497 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1498 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1502 pci_write_config(device_get_parent(atadev->channel->dev),
1503 0x60 + (devno << 2), timing, 4);
1507 hpt_timing(struct ata_device *atadev, int devno, int mode)
1509 device_t parent = device_get_parent(atadev->channel->dev);
1510 u_int32_t chiptype = atadev->channel->chiptype;
1511 int chiprev = pci_get_revid(parent);
1514 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1515 switch (mode) { /* HPT374 */
1516 case ATA_PIO0: timing = 0x0ac1f48a; break;
1517 case ATA_PIO1: timing = 0x0ac1f465; break;
1518 case ATA_PIO2: timing = 0x0a81f454; break;
1519 case ATA_PIO3: timing = 0x0a81f443; break;
1520 case ATA_PIO4: timing = 0x0a81f442; break;
1521 case ATA_WDMA2: timing = 0x22808242; break;
1522 case ATA_UDMA2: timing = 0x120c8242; break;
1523 case ATA_UDMA4: timing = 0x12ac8242; break;
1524 case ATA_UDMA5: timing = 0x12848242; break;
1525 case ATA_UDMA6: timing = 0x12808242; break;
1526 default: timing = 0x0d029d5e;
1529 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1530 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1531 switch (mode) { /* HPT372 */
1532 case ATA_PIO0: timing = 0x0d029d5e; break;
1533 case ATA_PIO1: timing = 0x0d029d26; break;
1534 case ATA_PIO2: timing = 0x0c829ca6; break;
1535 case ATA_PIO3: timing = 0x0c829c84; break;
1536 case ATA_PIO4: timing = 0x0c829c62; break;
1537 case ATA_WDMA2: timing = 0x2c829262; break;
1538 case ATA_UDMA2: timing = 0x1c91dc62; break;
1539 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1540 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1541 case ATA_UDMA6: timing = 0x1c81dc62; break;
1542 default: timing = 0x0d029d5e;
1545 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1546 switch (mode) { /* HPT370 */
1547 case ATA_PIO0: timing = 0x06914e57; break;
1548 case ATA_PIO1: timing = 0x06914e43; break;
1549 case ATA_PIO2: timing = 0x06514e33; break;
1550 case ATA_PIO3: timing = 0x06514e22; break;
1551 case ATA_PIO4: timing = 0x06514e21; break;
1552 case ATA_WDMA2: timing = 0x26514e21; break;
1553 case ATA_UDMA2: timing = 0x16494e31; break;
1554 case ATA_UDMA4: timing = 0x16454e31; break;
1555 case ATA_UDMA5: timing = 0x16454e31; break;
1556 default: timing = 0x06514e57;
1558 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1560 else { /* HPT36[68] */
1561 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1562 case 0x85: /* 25Mhz */
1564 case ATA_PIO0: timing = 0x40d08585; break;
1565 case ATA_PIO1: timing = 0x40d08572; break;
1566 case ATA_PIO2: timing = 0x40ca8542; break;
1567 case ATA_PIO3: timing = 0x40ca8532; break;
1568 case ATA_PIO4: timing = 0x40ca8521; break;
1569 case ATA_WDMA2: timing = 0x20ca8521; break;
1570 case ATA_UDMA2: timing = 0x10cf8521; break;
1571 case ATA_UDMA4: timing = 0x10c98521; break;
1572 default: timing = 0x01208585;
1576 case 0xa7: /* 33MHz */
1578 case ATA_PIO0: timing = 0x40d0a7aa; break;
1579 case ATA_PIO1: timing = 0x40d0a7a3; break;
1580 case ATA_PIO2: timing = 0x40d0a753; break;
1581 case ATA_PIO3: timing = 0x40c8a742; break;
1582 case ATA_PIO4: timing = 0x40c8a731; break;
1583 case ATA_WDMA2: timing = 0x20c8a731; break;
1584 case ATA_UDMA2: timing = 0x10caa731; break;
1585 case ATA_UDMA4: timing = 0x10c9a731; break;
1586 default: timing = 0x0120a7a7;
1589 case 0xd9: /* 40Mhz */
1591 case ATA_PIO0: timing = 0x4018d9d9; break;
1592 case ATA_PIO1: timing = 0x4010d9c7; break;
1593 case ATA_PIO2: timing = 0x4010d997; break;
1594 case ATA_PIO3: timing = 0x4010d974; break;
1595 case ATA_PIO4: timing = 0x4008d963; break;
1596 case ATA_WDMA2: timing = 0x2008d943; break;
1597 case ATA_UDMA2: timing = 0x100bd943; break;
1598 case ATA_UDMA4: timing = 0x100fd943; break;
1599 default: timing = 0x0120d9d9;
1603 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1607 hpt_cable80(struct ata_device *atadev)
1609 device_t parent = device_get_parent(atadev->channel->dev);
1610 u_int8_t reg, val, res;
1612 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) {
1613 reg = atadev->channel->unit ? 0x57 : 0x53;
1614 val = pci_read_config(parent, reg, 1);
1615 pci_write_config(parent, reg, val | 0x80, 1);
1619 val = pci_read_config(parent, reg, 1);
1620 pci_write_config(parent, reg, val & 0xfe, 1);
1622 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2);
1623 pci_write_config(parent, reg, val, 1);