2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/endian.h>
39 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ata/ata-all.h>
47 #include <dev/ata/ata-pci.h>
54 #include <cam/cam_ccb.h>
57 static int ata_generic_status(device_t dev);
58 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t);
59 static void ata_pio_read(struct ata_request *, int);
60 static void ata_pio_write(struct ata_request *, int);
61 static void ata_tf_read(struct ata_request *);
62 static void ata_tf_write(struct ata_request *);
65 * low level ATA functions
68 ata_generic_hw(device_t dev)
70 struct ata_channel *ch = device_get_softc(dev);
72 ch->hw.begin_transaction = ata_begin_transaction;
73 ch->hw.end_transaction = ata_end_transaction;
74 ch->hw.status = ata_generic_status;
75 ch->hw.softreset = NULL;
76 ch->hw.command = ata_generic_command;
77 ch->hw.tf_read = ata_tf_read;
78 ch->hw.tf_write = ata_tf_write;
79 ch->hw.pm_read = NULL;
80 ch->hw.pm_write = NULL;
83 /* must be called with ATA channel locked and state_mtx held */
85 ata_begin_transaction(struct ata_request *request)
87 struct ata_channel *ch = device_get_softc(request->parent);
90 ATA_DEBUG_RQ(request, "begin transaction");
92 /* disable ATAPI DMA writes if HW doesn't support it */
93 if ((ch->flags & ATA_NO_ATAPI_DMA) &&
94 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI)
95 request->flags &= ~ATA_R_DMA;
96 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
97 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
98 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
99 request->flags &= ~ATA_R_DMA;
101 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
102 /* ATA PIO data transfer and control commands */
105 /* record command direction here as our request might be gone later */
106 int write = (request->flags & ATA_R_WRITE);
109 if (ch->hw.command(request)) {
110 device_printf(request->parent, "error issuing %s command\n",
111 ata_cmd2str(request));
112 request->result = EIO;
116 /* device reset doesn't interrupt */
117 if (request->u.ata.command == ATA_DEVICE_RESET) {
118 int timeout = 1000000;
121 request->status = ATA_IDX_INB(ch, ATA_STATUS);
122 } while (request->status & ATA_S_BUSY && timeout--);
123 if (request->status & ATA_S_ERROR)
124 request->error = ATA_IDX_INB(ch, ATA_ERROR);
125 ch->hw.tf_read(request);
129 /* if write command output the data */
131 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
132 device_printf(request->parent,
133 "timeout waiting for write DRQ\n");
134 request->result = EIO;
137 ata_pio_write(request, request->transfersize);
142 /* ATA DMA data transfer commands */
144 /* check sanity, setup SG list and DMA engine */
145 if ((error = ch->dma.load(request, NULL, &dummy))) {
146 device_printf(request->parent, "setting up DMA failed\n");
147 request->result = error;
151 /* start DMA engine if necessary */
152 if ((ch->flags & ATA_DMA_BEFORE_CMD) &&
153 ch->dma.start && ch->dma.start(request)) {
154 device_printf(request->parent, "error starting DMA\n");
155 request->result = EIO;
160 if (ch->hw.command(request)) {
161 device_printf(request->parent, "error issuing %s command\n",
162 ata_cmd2str(request));
163 request->result = EIO;
167 /* start DMA engine */
168 if (!(ch->flags & ATA_DMA_BEFORE_CMD) &&
169 ch->dma.start && ch->dma.start(request)) {
170 device_printf(request->parent, "error starting DMA\n");
171 request->result = EIO;
176 /* ATAPI PIO commands */
178 /* is this just a POLL DSC command ? */
179 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
180 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
182 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
183 request->result = EBUSY;
187 /* start ATAPI operation */
188 if (ch->hw.command(request)) {
189 device_printf(request->parent, "error issuing ATA PACKET command\n");
190 request->result = EIO;
195 /* ATAPI DMA commands */
196 case ATA_R_ATAPI|ATA_R_DMA:
197 /* is this just a POLL DSC command ? */
198 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
199 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
201 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
202 request->result = EBUSY;
206 /* check sanity, setup SG list and DMA engine */
207 if ((error = ch->dma.load(request, NULL, &dummy))) {
208 device_printf(request->parent, "setting up DMA failed\n");
209 request->result = error;
213 /* start ATAPI operation */
214 if (ch->hw.command(request)) {
215 device_printf(request->parent, "error issuing ATA PACKET command\n");
216 request->result = EIO;
220 /* start DMA engine */
221 if (ch->dma.start && ch->dma.start(request)) {
222 request->result = EIO;
228 printf("ata_begin_transaction OOPS!!!\n");
231 if (ch->dma.unload) {
232 ch->dma.unload(request);
234 return ATA_OP_FINISHED;
237 callout_reset(&request->callout, request->timeout * hz,
238 ata_timeout, request);
239 return ATA_OP_CONTINUES;
242 /* must be called with ATA channel locked and state_mtx held */
244 ata_end_transaction(struct ata_request *request)
246 struct ata_channel *ch = device_get_softc(request->parent);
249 ATA_DEBUG_RQ(request, "end transaction");
251 /* clear interrupt and get status */
252 request->status = ATA_IDX_INB(ch, ATA_STATUS);
254 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
255 /* ATA PIO data transfer and control commands */
258 /* on timeouts we have no data or anything so just return */
259 if (request->flags & ATA_R_TIMEOUT)
262 /* Read back registers to the request struct. */
263 if ((request->status & ATA_S_ERROR) ||
264 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
265 ch->hw.tf_read(request);
268 /* if we got an error we are done with the HW */
269 if (request->status & ATA_S_ERROR) {
270 request->error = ATA_IDX_INB(ch, ATA_ERROR);
274 /* are we moving data ? */
275 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
276 /* if read data get it */
277 if (request->flags & ATA_R_READ) {
278 int flags = ATA_S_DRQ;
280 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
281 flags |= ATA_S_READY;
282 if (ata_wait(ch, request->unit, flags) < 0) {
283 device_printf(request->parent,
284 "timeout waiting for read DRQ\n");
285 request->result = EIO;
288 ata_pio_read(request, request->transfersize);
291 /* update how far we've gotten */
292 request->donecount += request->transfersize;
294 /* do we need a scoop more ? */
295 if (request->bytecount > request->donecount) {
296 /* set this transfer size according to HW capabilities */
297 request->transfersize =
298 min((request->bytecount - request->donecount),
299 request->transfersize);
301 /* if data write command, output the data */
302 if (request->flags & ATA_R_WRITE) {
303 /* if we get an error here we are done with the HW */
304 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
305 device_printf(request->parent,
306 "timeout waiting for write DRQ\n");
307 request->status = ATA_IDX_INB(ch, ATA_STATUS);
311 /* output data and return waiting for new interrupt */
312 ata_pio_write(request, request->transfersize);
316 /* if data read command, return & wait for interrupt */
317 if (request->flags & ATA_R_READ)
324 /* ATA DMA data transfer commands */
327 /* stop DMA engine and get status */
329 request->dma->status = ch->dma.stop(request);
331 /* did we get error or data */
332 if (request->status & ATA_S_ERROR)
333 request->error = ATA_IDX_INB(ch, ATA_ERROR);
334 else if (request->dma->status & ATA_BMSTAT_ERROR)
335 request->status |= ATA_S_ERROR;
336 else if (!(request->flags & ATA_R_TIMEOUT))
337 request->donecount = request->bytecount;
339 /* Read back registers to the request struct. */
340 if ((request->status & ATA_S_ERROR) ||
341 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
342 ch->hw.tf_read(request);
345 /* release SG list etc */
346 ch->dma.unload(request);
351 /* ATAPI PIO commands */
353 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
355 /* on timeouts we have no data or anything so just return */
356 if (request->flags & ATA_R_TIMEOUT)
359 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
360 (request->status & ATA_S_DRQ)) {
362 /* this seems to be needed for some (slow) devices */
365 if (!(request->status & ATA_S_DRQ)) {
366 device_printf(request->parent, "command interrupt without DRQ\n");
367 request->status = ATA_S_ERROR;
370 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
371 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
372 /* return wait for interrupt */
376 if (request->flags & ATA_R_READ) {
377 request->status = ATA_S_ERROR;
378 device_printf(request->parent,
379 "%s trying to write on read buffer\n",
380 ata_cmd2str(request));
383 ata_pio_write(request, length);
384 request->donecount += length;
386 /* set next transfer size according to HW capabilities */
387 request->transfersize = min((request->bytecount-request->donecount),
388 request->transfersize);
389 /* return wait for interrupt */
393 if (request->flags & ATA_R_WRITE) {
394 request->status = ATA_S_ERROR;
395 device_printf(request->parent,
396 "%s trying to read on write buffer\n",
397 ata_cmd2str(request));
400 ata_pio_read(request, length);
401 request->donecount += length;
403 /* set next transfer size according to HW capabilities */
404 request->transfersize = min((request->bytecount-request->donecount),
405 request->transfersize);
406 /* return wait for interrupt */
409 case ATAPI_P_DONEDRQ:
410 device_printf(request->parent,
411 "WARNING - %s DONEDRQ non conformant device\n",
412 ata_cmd2str(request));
413 if (request->flags & ATA_R_READ) {
414 ata_pio_read(request, length);
415 request->donecount += length;
417 else if (request->flags & ATA_R_WRITE) {
418 ata_pio_write(request, length);
419 request->donecount += length;
422 request->status = ATA_S_ERROR;
427 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
428 request->error = ATA_IDX_INB(ch, ATA_ERROR);
432 device_printf(request->parent, "unknown transfer phase\n");
433 request->status = ATA_S_ERROR;
439 /* ATAPI DMA commands */
440 case ATA_R_ATAPI|ATA_R_DMA:
442 /* stop DMA engine and get status */
444 request->dma->status = ch->dma.stop(request);
446 /* did we get error or data */
447 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
448 request->error = ATA_IDX_INB(ch, ATA_ERROR);
449 else if (request->dma->status & ATA_BMSTAT_ERROR)
450 request->status |= ATA_S_ERROR;
451 else if (!(request->flags & ATA_R_TIMEOUT))
452 request->donecount = request->bytecount;
454 /* release SG list etc */
455 ch->dma.unload(request);
461 printf("ata_end_transaction OOPS!!\n");
464 callout_stop(&request->callout);
465 return ATA_OP_FINISHED;
468 return ATA_OP_CONTINUES;
471 /* must be called with ATA channel locked and state_mtx held */
473 ata_generic_reset(device_t dev)
475 struct ata_channel *ch = device_get_softc(dev);
477 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
478 u_int8_t err = 0, lsb = 0, msb = 0;
479 int mask = 0, timeout;
481 /* do we have any signs of ATA/ATAPI HW being present ? */
482 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
484 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
485 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
491 /* in some setups we dont want to test for a slave */
492 if (!(ch->flags & ATA_NO_SLAVE)) {
493 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
495 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
496 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
504 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
505 mask, ostat0, ostat1);
507 /* if nothing showed up there is no need to get any further */
508 /* XXX SOS is that too strong?, we just might lose devices here */
513 /* reset (both) devices on this channel */
514 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
516 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
518 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
520 ATA_IDX_INB(ch, ATA_ERROR);
522 /* wait for BUSY to go inactive */
523 for (timeout = 0; timeout < 310; timeout++) {
524 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
525 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
527 if (ch->flags & ATA_STATUS_IS_LONG)
528 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
530 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
531 err = ATA_IDX_INB(ch, ATA_ERROR);
532 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
533 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
536 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
537 stat0, err, lsb, msb);
538 if (stat0 == err && lsb == err && msb == err &&
539 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
541 if (!(stat0 & ATA_S_BUSY)) {
542 if ((err & 0x7f) == ATA_E_ILI) {
543 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
544 ch->devices |= ATA_ATAPI_MASTER;
546 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) {
547 ch->devices |= ATA_ATA_MASTER;
550 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
556 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
557 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
558 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
560 if (ch->flags & ATA_STATUS_IS_LONG)
561 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
563 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
564 err = ATA_IDX_INB(ch, ATA_ERROR);
565 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
566 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
569 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
570 stat1, err, lsb, msb);
571 if (stat1 == err && lsb == err && msb == err &&
572 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
574 if (!(stat1 & ATA_S_BUSY)) {
575 if ((err & 0x7f) == ATA_E_ILI) {
576 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
577 ch->devices |= ATA_ATAPI_SLAVE;
579 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) {
580 ch->devices |= ATA_ATA_SLAVE;
583 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
589 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 &&
590 timeout > ((mask == 0x03) ? 20 : 10)) {
591 if ((mask & 0x01) && stat0 == 0xff)
593 if ((mask & 0x02) && stat1 == 0xff)
596 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) &&
597 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY)))
603 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
604 stat0, stat1, ch->devices);
607 /* must be called with ATA channel locked and state_mtx held */
609 ata_generic_status(device_t dev)
611 struct ata_channel *ch = device_get_softc(dev);
613 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
615 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
622 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask)
629 /* wait at max 1 second for device to get !BUSY */
630 while (timeout < 1000000) {
631 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
633 /* if drive fails status, reselect the drive and try again */
634 if (status == 0xff) {
635 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit));
642 if (!(status & ATA_S_BUSY))
645 if (timeout > 1000) {
654 if (timeout >= 1000000)
657 return (status & ATA_S_ERROR);
661 /* wait 50 msec for bits wanted */
664 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
665 if ((status & mask) == mask)
666 return (status & ATA_S_ERROR);
673 ata_generic_command(struct ata_request *request)
675 struct ata_channel *ch = device_get_softc(request->parent);
678 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit));
680 /* ready to issue command ? */
681 if (ata_wait(ch, request->unit, 0) < 0) {
682 device_printf(request->parent, "timeout waiting to issue command\n");
683 request->flags |= ATA_R_TIMEOUT;
687 /* enable interrupt */
688 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
690 if (request->flags & ATA_R_ATAPI) {
694 /* issue packet command to controller */
695 if (request->flags & ATA_R_DMA) {
696 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
697 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
698 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
701 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
702 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
703 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
705 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
707 /* command interrupt device ? just return and wait for interrupt */
708 if (request->flags & ATA_R_ATAPI_INTR)
711 /* command processed ? */
712 res = ata_wait(ch, request->unit, 0);
715 device_printf(request->parent,
716 "timeout waiting for PACKET command\n");
717 request->flags |= ATA_R_TIMEOUT;
721 /* wait for ready to write ATAPI command block */
723 int reason = ATA_IDX_INB(ch, ATA_IREASON);
724 int status = ATA_IDX_INB(ch, ATA_STATUS);
726 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
727 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
732 device_printf(request->parent,
733 "timeout waiting for ATAPI ready\n");
734 request->flags |= ATA_R_TIMEOUT;
738 /* this seems to be needed for some (slow) devices */
741 /* output command block */
742 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
743 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
746 ch->hw.tf_write(request);
748 /* issue command to controller */
749 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
755 ata_tf_read(struct ata_request *request)
757 struct ata_channel *ch = device_get_softc(request->parent);
759 if (request->flags & ATA_R_48BIT) {
760 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
761 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
763 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
764 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
765 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
767 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
768 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
769 request->u.ata.lba |=
770 (ATA_IDX_INB(ch, ATA_SECTOR) |
771 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
772 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
775 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
776 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
777 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
778 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
779 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
784 ata_tf_write(struct ata_request *request)
786 struct ata_channel *ch = device_get_softc(request->parent);
788 if (request->flags & ATA_R_48BIT) {
789 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
790 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
791 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
792 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
793 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
794 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
795 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
796 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
797 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
798 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
799 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
802 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
803 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
804 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
805 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
806 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
807 ATA_IDX_OUTB(ch, ATA_DRIVE,
808 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
809 ((request->u.ata.lba >> 24) & 0x0f));
814 ata_pio_read(struct ata_request *request, int length)
816 struct ata_channel *ch = device_get_softc(request->parent);
820 int todo, done, off, moff, resid, size, i;
821 uint8_t buf[2] __aligned(2);
823 todo = min(request->transfersize, length);
824 page = done = resid = 0;
825 while (done < todo) {
828 /* Prepare data address and limit size (if not sequential). */
829 off = request->donecount + done;
830 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 ||
831 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
832 addr = (uint8_t *)request->data + off;
833 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) {
834 bio = (struct bio *)request->data;
835 if ((bio->bio_flags & BIO_UNMAPPED) == 0) {
836 addr = (uint8_t *)bio->bio_data + off;
838 moff = bio->bio_ma_offset + off;
839 page = pmap_quick_enter_page(
840 bio->bio_ma[moff / PAGE_SIZE]);
842 size = min(size, PAGE_SIZE - moff);
843 addr = (void *)(page + moff);
846 panic("ata_pio_read: Unsupported CAM data type %x\n",
847 (request->ccb->ccb_h.flags & CAM_DATA_MASK));
849 /* We may have extra byte already read but not stored. */
857 /* Process main part of data. */
859 if (__predict_false((ch->flags & ATA_USE_16BIT) ||
860 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) {
861 #ifndef __NO_STRICT_ALIGNMENT
862 if (__predict_false((uintptr_t)addr % 2)) {
863 for (i = 0; i + 1 < size; i += 2) {
865 ATA_IDX_INW_STRM(ch, ATA_DATA);
867 addr[i + 1] = buf[1];
871 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr,
874 /* If we have extra byte of data, leave it for later. */
877 ATA_IDX_INW_STRM(ch, ATA_DATA);
878 addr[size - 1] = buf[0];
881 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / 4);
884 pmap_quick_remove_page(page);
891 device_printf(request->parent,
892 "WARNING - %s read data overrun %d > %d\n",
893 ata_cmd2str(request), length, done);
894 for (i = done + resid; i < length; i += 2)
895 ATA_IDX_INW(ch, ATA_DATA);
900 ata_pio_write(struct ata_request *request, int length)
902 struct ata_channel *ch = device_get_softc(request->parent);
906 int todo, done, off, moff, resid, size, i;
907 uint8_t buf[2] __aligned(2);
909 todo = min(request->transfersize, length);
910 page = done = resid = 0;
911 while (done < todo) {
914 /* Prepare data address and limit size (if not sequential). */
915 off = request->donecount + done;
916 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 ||
917 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
918 addr = (uint8_t *)request->data + off;
919 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) {
920 bio = (struct bio *)request->data;
921 if ((bio->bio_flags & BIO_UNMAPPED) == 0) {
922 addr = (uint8_t *)bio->bio_data + off;
924 moff = bio->bio_ma_offset + off;
925 page = pmap_quick_enter_page(
926 bio->bio_ma[moff / PAGE_SIZE]);
928 size = min(size, PAGE_SIZE - moff);
929 addr = (void *)(page + moff);
932 panic("ata_pio_write: Unsupported CAM data type %x\n",
933 (request->ccb->ccb_h.flags & CAM_DATA_MASK));
935 /* We may have extra byte to be written first. */
938 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
944 /* Process main part of data. */
946 if (__predict_false((ch->flags & ATA_USE_16BIT) ||
947 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) {
948 #ifndef __NO_STRICT_ALIGNMENT
949 if (__predict_false((uintptr_t)addr % 2)) {
950 for (i = 0; i + 1 < size; i += 2) {
952 buf[1] = addr[i + 1];
953 ATA_IDX_OUTW_STRM(ch, ATA_DATA,
958 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr,
961 /* If we have extra byte of data, save it for later. */
963 buf[0] = addr[size - 1];
965 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
966 (void*)addr, size / sizeof(int32_t));
969 pmap_quick_remove_page(page);
975 /* We may have extra byte of data to be written. Pad it with zero. */
978 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
982 device_printf(request->parent,
983 "WARNING - %s write data underrun %d > %d\n",
984 ata_cmd2str(request), length, done);
985 for (i = done + resid; i < length; i += 2)
986 ATA_IDX_OUTW(ch, ATA_DATA, 0);