2 * Copyright (c) 1998 - 2005 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/endian.h>
39 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ata/ata-all.h>
47 #include <dev/ata/ata-pci.h>
51 static int ata_begin_transaction(struct ata_request *);
52 static int ata_end_transaction(struct ata_request *);
53 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
54 static void ata_pio_read(struct ata_request *, int);
55 static void ata_pio_write(struct ata_request *, int);
58 * low level ATA functions
61 ata_generic_hw(device_t dev)
63 struct ata_channel *ch = device_get_softc(dev);
65 ch->hw.begin_transaction = ata_begin_transaction;
66 ch->hw.end_transaction = ata_end_transaction;
67 ch->hw.command = ata_generic_command;
70 /* must be called with ATA channel locked and state_mtx held */
72 ata_begin_transaction(struct ata_request *request)
74 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
75 struct ata_device *atadev = device_get_softc(request->dev);
78 ATA_DEBUG_RQ(request, "begin transaction");
80 /* disable ATAPI DMA writes if HW doesn't support it */
81 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
82 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
83 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
84 request->flags &= ~ATA_R_DMA;
86 /* check for 48 bit access and convert if needed */
87 ata_modify_if_48bit(request);
89 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
91 /* ATA PIO data transfer and control commands */
94 /* record command direction here as our request might be gone later */
95 int write = (request->flags & ATA_R_WRITE);
98 if (ch->hw.command(request)) {
99 device_printf(request->dev, "error issuing %s command\n",
100 ata_cmd2str(request));
101 request->result = EIO;
105 /* device reset doesn't interrupt */
106 if (request->u.ata.command == ATA_DEVICE_RESET) {
107 int timeout = 1000000;
110 request->status = ATA_IDX_INB(ch, ATA_STATUS);
111 } while (request->status & ATA_S_BUSY && timeout--);
112 if (request->status & ATA_S_ERROR)
113 request->error = ATA_IDX_INB(ch, ATA_ERROR);
117 /* if write command output the data */
119 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
120 device_printf(request->dev,
121 "timeout waiting for write DRQ\n");
122 request->result = EIO;
125 ata_pio_write(request, request->transfersize);
130 /* ATA DMA data transfer commands */
132 /* check sanity, setup SG list and DMA engine */
133 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
134 request->flags & ATA_R_READ, ch->dma->sg,
136 device_printf(request->dev, "setting up DMA failed\n");
137 request->result = error;
142 if (ch->hw.command(request)) {
143 device_printf(request->dev, "error issuing %s command\n",
144 ata_cmd2str(request));
145 request->result = EIO;
149 /* start DMA engine */
150 if (ch->dma->start && ch->dma->start(request->dev)) {
151 device_printf(request->dev, "error starting DMA\n");
152 request->result = EIO;
157 /* ATAPI PIO commands */
159 /* is this just a POLL DSC command ? */
160 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
161 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
163 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
164 request->result = EBUSY;
168 /* start ATAPI operation */
169 if (ch->hw.command(request)) {
170 device_printf(request->dev, "error issuing ATA PACKET command\n");
171 request->result = EIO;
176 /* ATAPI DMA commands */
177 case ATA_R_ATAPI|ATA_R_DMA:
178 /* is this just a POLL DSC command ? */
179 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
180 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
182 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
183 request->result = EBUSY;
187 /* check sanity, setup SG list and DMA engine */
188 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
189 request->flags & ATA_R_READ, ch->dma->sg,
191 device_printf(request->dev, "setting up DMA failed\n");
192 request->result = error;
196 /* start ATAPI operation */
197 if (ch->hw.command(request)) {
198 device_printf(request->dev, "error issuing ATA PACKET command\n");
199 request->result = EIO;
203 /* start DMA engine */
204 if (ch->dma->start && ch->dma->start(request->dev)) {
205 request->result = EIO;
211 printf("ata_begin_transaction OOPS!!!\n");
214 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
215 ch->dma->unload(ch->dev);
216 return ATA_OP_FINISHED;
219 callout_reset(&request->callout, request->timeout * hz,
220 (timeout_t*)ata_timeout, request);
221 return ATA_OP_CONTINUES;
224 /* must be called with ATA channel locked and state_mtx held */
226 ata_end_transaction(struct ata_request *request)
228 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
229 struct ata_device *atadev = device_get_softc(request->dev);
232 ATA_DEBUG_RQ(request, "end transaction");
234 /* clear interrupt and get status */
235 request->status = ATA_IDX_INB(ch, ATA_STATUS);
237 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
239 /* ATA PIO data transfer and control commands */
242 /* on timeouts we have no data or anything so just return */
243 if (request->flags & ATA_R_TIMEOUT)
246 /* on control commands read back registers to the request struct */
247 if (request->flags & ATA_R_CONTROL) {
248 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
249 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
250 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
252 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
253 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
254 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
256 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
257 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
258 request->u.ata.lba |=
259 (ATA_IDX_INB(ch, ATA_SECTOR) |
260 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
261 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
264 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
265 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
266 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
267 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
268 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
272 /* if we got an error we are done with the HW */
273 if (request->status & ATA_S_ERROR) {
274 request->error = ATA_IDX_INB(ch, ATA_ERROR);
278 /* are we moving data ? */
279 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
281 /* if read data get it */
282 if (request->flags & ATA_R_READ) {
283 int flags = ATA_S_DRQ;
285 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
286 flags |= ATA_S_READY;
287 if (ata_wait(ch, atadev, flags) < 0) {
288 device_printf(request->dev,
289 "timeout waiting for read DRQ\n");
290 request->result = EIO;
293 ata_pio_read(request, request->transfersize);
296 /* update how far we've gotten */
297 request->donecount += request->transfersize;
299 /* do we need a scoop more ? */
300 if (request->bytecount > request->donecount) {
302 /* set this transfer size according to HW capabilities */
303 request->transfersize =
304 min((request->bytecount - request->donecount),
305 request->transfersize);
307 /* if data write command, output the data */
308 if (request->flags & ATA_R_WRITE) {
310 /* if we get an error here we are done with the HW */
311 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
312 device_printf(request->dev,
313 "timeout waiting for write DRQ\n");
314 request->status = ATA_IDX_INB(ch, ATA_STATUS);
318 /* output data and return waiting for new interrupt */
319 ata_pio_write(request, request->transfersize);
323 /* if data read command, return & wait for interrupt */
324 if (request->flags & ATA_R_READ)
331 /* ATA DMA data transfer commands */
334 /* stop DMA engine and get status */
336 request->dmastat = ch->dma->stop(request->dev);
338 /* did we get error or data */
339 if (request->status & ATA_S_ERROR)
340 request->error = ATA_IDX_INB(ch, ATA_ERROR);
341 else if (request->dmastat & ATA_BMSTAT_ERROR)
342 request->status |= ATA_S_ERROR;
343 else if (!(request->flags & ATA_R_TIMEOUT))
344 request->donecount = request->bytecount;
346 /* release SG list etc */
347 ch->dma->unload(ch->dev);
352 /* ATAPI PIO commands */
354 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
356 /* on timeouts we have no data or anything so just return */
357 if (request->flags & ATA_R_TIMEOUT)
360 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
361 (request->status & ATA_S_DRQ)) {
364 /* this seems to be needed for some (slow) devices */
367 if (!(request->status & ATA_S_DRQ)) {
368 device_printf(request->dev, "command interrupt without DRQ\n");
369 request->status = ATA_S_ERROR;
372 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
373 (atadev->param.config &
374 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
375 /* return wait for interrupt */
379 if (request->flags & ATA_R_READ) {
380 request->status = ATA_S_ERROR;
381 device_printf(request->dev,
382 "%s trying to write on read buffer\n",
383 ata_cmd2str(request));
387 ata_pio_write(request, length);
388 request->donecount += length;
390 /* set next transfer size according to HW capabilities */
391 request->transfersize = min((request->bytecount-request->donecount),
392 request->transfersize);
393 /* return wait for interrupt */
397 if (request->flags & ATA_R_WRITE) {
398 request->status = ATA_S_ERROR;
399 device_printf(request->dev,
400 "%s trying to read on write buffer\n",
401 ata_cmd2str(request));
404 ata_pio_read(request, length);
405 request->donecount += length;
407 /* set next transfer size according to HW capabilities */
408 request->transfersize = min((request->bytecount-request->donecount),
409 request->transfersize);
410 /* return wait for interrupt */
413 case ATAPI_P_DONEDRQ:
414 device_printf(request->dev,
415 "WARNING - %s DONEDRQ non conformant device\n",
416 ata_cmd2str(request));
417 if (request->flags & ATA_R_READ) {
418 ata_pio_read(request, length);
419 request->donecount += length;
421 else if (request->flags & ATA_R_WRITE) {
422 ata_pio_write(request, length);
423 request->donecount += length;
426 request->status = ATA_S_ERROR;
431 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
432 request->error = ATA_IDX_INB(ch, ATA_ERROR);
436 device_printf(request->dev, "unknown transfer phase\n");
437 request->status = ATA_S_ERROR;
443 /* ATAPI DMA commands */
444 case ATA_R_ATAPI|ATA_R_DMA:
446 /* stop DMA engine and get status */
448 request->dmastat = ch->dma->stop(request->dev);
450 /* did we get error or data */
451 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
452 request->error = ATA_IDX_INB(ch, ATA_ERROR);
453 else if (request->dmastat & ATA_BMSTAT_ERROR)
454 request->status |= ATA_S_ERROR;
455 else if (!(request->flags & ATA_R_TIMEOUT))
456 request->donecount = request->bytecount;
458 /* release SG list etc */
459 ch->dma->unload(ch->dev);
465 printf("ata_end_transaction OOPS!!\n");
468 callout_stop(&request->callout);
469 return ATA_OP_FINISHED;
472 return ATA_OP_CONTINUES;
475 /* must be called with ATA channel locked */
477 ata_generic_reset(device_t dev)
479 struct ata_channel *ch = device_get_softc(dev);
481 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
482 u_int8_t err = 0, lsb = 0, msb = 0;
483 int mask = 0, timeout;
485 /* do we have any signs of ATA/ATAPI HW being present ? */
486 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
488 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
489 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
494 /* in some setups we dont want to test for a slave */
495 if (!(ch->flags & ATA_NO_SLAVE)) {
496 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
498 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
499 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
506 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
507 mask, ostat0, ostat1);
509 /* if nothing showed up there is no need to get any further */
510 /* XXX SOS is that too strong?, we just might loose devices here */
515 /* reset (both) devices on this channel */
516 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
518 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
520 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
522 ATA_IDX_INB(ch, ATA_ERROR);
524 /* wait for BUSY to go inactive */
525 for (timeout = 0; timeout < 310; timeout++) {
526 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
527 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
529 err = ATA_IDX_INB(ch, ATA_ERROR);
530 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
531 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
532 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
535 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
536 stat0, err, lsb, msb);
537 if (stat0 == err && lsb == err && msb == err &&
538 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
540 if (!(stat0 & ATA_S_BUSY)) {
541 if ((err & 0x7f) == ATA_E_ILI) {
542 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
543 ch->devices |= ATA_ATAPI_MASTER;
545 else if (stat0 & ATA_S_READY) {
546 ch->devices |= ATA_ATA_MASTER;
549 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
555 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
556 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
557 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
559 err = ATA_IDX_INB(ch, ATA_ERROR);
560 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
561 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
562 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
565 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
566 stat1, err, lsb, msb);
567 if (stat1 == err && lsb == err && msb == err &&
568 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
570 if (!(stat1 & ATA_S_BUSY)) {
571 if ((err & 0x7f) == ATA_E_ILI) {
572 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
573 ch->devices |= ATA_ATAPI_SLAVE;
575 else if (stat1 & ATA_S_READY) {
576 ch->devices |= ATA_ATA_SLAVE;
579 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
585 if (mask == 0x00) /* nothing to wait for */
587 if (mask == 0x01) /* wait for master only */
588 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
590 if (mask == 0x02) /* wait for slave only */
591 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
593 if (mask == 0x03) { /* wait for both master & slave */
594 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
596 if ((stat0 == 0xff) && (timeout > 20))
598 if ((stat1 == 0xff) && (timeout > 20))
605 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
606 stat0, stat1, ch->devices,
607 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
611 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
618 /* wait at max 1 second for device to get !BUSY */
619 while (timeout < 1000000) {
620 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
622 /* if drive fails status, reselect the drive and try again */
623 if (status == 0xff) {
624 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
631 if (!(status & ATA_S_BUSY))
634 if (timeout > 1000) {
643 if (timeout >= 1000000)
646 return (status & ATA_S_ERROR);
650 /* wait 50 msec for bits wanted */
653 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
654 if ((status & mask) == mask)
655 return (status & ATA_S_ERROR);
662 ata_generic_command(struct ata_request *request)
664 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
665 struct ata_device *atadev = device_get_softc(request->dev);
668 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
670 /* ready to issue command ? */
671 if (ata_wait(ch, atadev, 0) < 0) {
672 device_printf(request->dev, "timeout waiting to issue command\n");
676 /* enable interrupt */
677 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
679 if (request->flags & ATA_R_ATAPI) {
682 /* issue packet command to controller */
683 if (request->flags & ATA_R_DMA) {
684 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
685 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
686 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
689 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
690 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
691 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
693 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
695 /* command interrupt device ? just return and wait for interrupt */
696 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
699 /* wait for ready to write ATAPI command block */
701 int reason = ATA_IDX_INB(ch, ATA_IREASON);
702 int status = ATA_IDX_INB(ch, ATA_STATUS);
704 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
705 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
710 device_printf(request->dev,"timeout waiting for ATAPI ready\n");
711 request->result = EIO;
715 /* this seems to be needed for some (slow) devices */
718 /* output command block */
719 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
720 (atadev->param.config & ATA_PROTO_MASK) ==
721 ATA_PROTO_ATAPI_12 ? 6 : 8);
724 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
725 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
726 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
727 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
728 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
729 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
730 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
731 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
732 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
733 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
734 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
735 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
738 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
739 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
740 if (atadev->flags & ATA_D_USE_CHS) {
743 if (atadev->param.atavalid & ATA_FLAG_54_58) {
744 heads = atadev->param.current_heads;
745 sectors = atadev->param.current_sectors;
748 heads = atadev->param.heads;
749 sectors = atadev->param.sectors;
751 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
752 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
753 (request->u.ata.lba / (sectors * heads)));
754 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
755 (request->u.ata.lba / (sectors * heads)) >> 8);
756 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
757 (((request->u.ata.lba% (sectors * heads)) /
761 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
762 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
763 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
764 ATA_IDX_OUTB(ch, ATA_DRIVE,
765 ATA_D_IBM | ATA_D_LBA | atadev->unit |
766 ((request->u.ata.lba >> 24) & 0x0f));
770 /* issue command to controller */
771 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
778 ata_pio_read(struct ata_request *request, int length)
780 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
781 int size = min(request->transfersize, length);
784 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
785 ATA_IDX_INSW_STRM(ch, ATA_DATA,
786 (void*)((uintptr_t)request->data+request->donecount),
787 size / sizeof(int16_t));
789 ATA_IDX_INSL_STRM(ch, ATA_DATA,
790 (void*)((uintptr_t)request->data+request->donecount),
791 size / sizeof(int32_t));
793 if (request->transfersize < length) {
794 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
795 ata_cmd2str(request), length, request->transfersize);
796 for (resid = request->transfersize; resid < length;
797 resid += sizeof(int16_t))
798 ATA_IDX_INW(ch, ATA_DATA);
803 ata_pio_write(struct ata_request *request, int length)
805 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
806 int size = min(request->transfersize, length);
809 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
810 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
811 (void*)((uintptr_t)request->data+request->donecount),
812 size / sizeof(int16_t));
814 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
815 (void*)((uintptr_t)request->data+request->donecount),
816 size / sizeof(int32_t));
818 if (request->transfersize < length) {
819 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
820 ata_cmd2str(request), length, request->transfersize);
821 for (resid = request->transfersize; resid < length;
822 resid += sizeof(int16_t))
823 ATA_IDX_OUTW(ch, ATA_DATA, 0);