2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/endian.h>
39 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ata/ata-all.h>
47 #include <dev/ata/ata-pci.h>
54 #include <cam/cam_ccb.h>
57 static int ata_generic_status(device_t dev);
58 static int ata_wait(struct ata_channel *ch, int unit, u_int8_t);
59 static void ata_pio_read(struct ata_request *, int);
60 static void ata_pio_write(struct ata_request *, int);
61 static void ata_tf_read(struct ata_request *);
62 static void ata_tf_write(struct ata_request *);
65 * low level ATA functions
68 ata_generic_hw(device_t dev)
70 struct ata_channel *ch = device_get_softc(dev);
72 ch->hw.begin_transaction = ata_begin_transaction;
73 ch->hw.end_transaction = ata_end_transaction;
74 ch->hw.status = ata_generic_status;
75 ch->hw.softreset = NULL;
76 ch->hw.command = ata_generic_command;
77 ch->hw.tf_read = ata_tf_read;
78 ch->hw.tf_write = ata_tf_write;
79 ch->hw.pm_read = NULL;
80 ch->hw.pm_write = NULL;
83 /* must be called with ATA channel locked and state_mtx held */
85 ata_begin_transaction(struct ata_request *request)
87 struct ata_channel *ch = device_get_softc(request->parent);
90 ATA_DEBUG_RQ(request, "begin transaction");
92 /* disable ATAPI DMA writes if HW doesn't support it */
93 if ((ch->flags & ATA_NO_ATAPI_DMA) &&
94 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI)
95 request->flags &= ~ATA_R_DMA;
96 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
97 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
98 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
99 request->flags &= ~ATA_R_DMA;
101 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
103 /* ATA PIO data transfer and control commands */
106 /* record command direction here as our request might be gone later */
107 int write = (request->flags & ATA_R_WRITE);
110 if (ch->hw.command(request)) {
111 device_printf(request->parent, "error issuing %s command\n",
112 ata_cmd2str(request));
113 request->result = EIO;
117 /* device reset doesn't interrupt */
118 if (request->u.ata.command == ATA_DEVICE_RESET) {
120 int timeout = 1000000;
123 request->status = ATA_IDX_INB(ch, ATA_STATUS);
124 } while (request->status & ATA_S_BUSY && timeout--);
125 if (request->status & ATA_S_ERROR)
126 request->error = ATA_IDX_INB(ch, ATA_ERROR);
127 ch->hw.tf_read(request);
131 /* if write command output the data */
133 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
134 device_printf(request->parent,
135 "timeout waiting for write DRQ\n");
136 request->result = EIO;
139 ata_pio_write(request, request->transfersize);
144 /* ATA DMA data transfer commands */
146 /* check sanity, setup SG list and DMA engine */
147 if ((error = ch->dma.load(request, NULL, &dummy))) {
148 device_printf(request->parent, "setting up DMA failed\n");
149 request->result = error;
153 /* start DMA engine if necessary */
154 if ((ch->flags & ATA_DMA_BEFORE_CMD) &&
155 ch->dma.start && ch->dma.start(request)) {
156 device_printf(request->parent, "error starting DMA\n");
157 request->result = EIO;
162 if (ch->hw.command(request)) {
163 device_printf(request->parent, "error issuing %s command\n",
164 ata_cmd2str(request));
165 request->result = EIO;
169 /* start DMA engine */
170 if (!(ch->flags & ATA_DMA_BEFORE_CMD) &&
171 ch->dma.start && ch->dma.start(request)) {
172 device_printf(request->parent, "error starting DMA\n");
173 request->result = EIO;
178 /* ATAPI PIO commands */
180 /* is this just a POLL DSC command ? */
181 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
182 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
184 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
185 request->result = EBUSY;
189 /* start ATAPI operation */
190 if (ch->hw.command(request)) {
191 device_printf(request->parent, "error issuing ATA PACKET command\n");
192 request->result = EIO;
197 /* ATAPI DMA commands */
198 case ATA_R_ATAPI|ATA_R_DMA:
199 /* is this just a POLL DSC command ? */
200 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
201 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit));
203 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
204 request->result = EBUSY;
208 /* check sanity, setup SG list and DMA engine */
209 if ((error = ch->dma.load(request, NULL, &dummy))) {
210 device_printf(request->parent, "setting up DMA failed\n");
211 request->result = error;
215 /* start ATAPI operation */
216 if (ch->hw.command(request)) {
217 device_printf(request->parent, "error issuing ATA PACKET command\n");
218 request->result = EIO;
222 /* start DMA engine */
223 if (ch->dma.start && ch->dma.start(request)) {
224 request->result = EIO;
230 printf("ata_begin_transaction OOPS!!!\n");
233 if (ch->dma.unload) {
234 ch->dma.unload(request);
236 return ATA_OP_FINISHED;
239 callout_reset(&request->callout, request->timeout * hz,
240 ata_timeout, request);
241 return ATA_OP_CONTINUES;
244 /* must be called with ATA channel locked and state_mtx held */
246 ata_end_transaction(struct ata_request *request)
248 struct ata_channel *ch = device_get_softc(request->parent);
251 ATA_DEBUG_RQ(request, "end transaction");
253 /* clear interrupt and get status */
254 request->status = ATA_IDX_INB(ch, ATA_STATUS);
256 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
258 /* ATA PIO data transfer and control commands */
261 /* on timeouts we have no data or anything so just return */
262 if (request->flags & ATA_R_TIMEOUT)
265 /* Read back registers to the request struct. */
266 if ((request->status & ATA_S_ERROR) ||
267 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
268 ch->hw.tf_read(request);
271 /* if we got an error we are done with the HW */
272 if (request->status & ATA_S_ERROR) {
273 request->error = ATA_IDX_INB(ch, ATA_ERROR);
277 /* are we moving data ? */
278 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
280 /* if read data get it */
281 if (request->flags & ATA_R_READ) {
282 int flags = ATA_S_DRQ;
284 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
285 flags |= ATA_S_READY;
286 if (ata_wait(ch, request->unit, flags) < 0) {
287 device_printf(request->parent,
288 "timeout waiting for read DRQ\n");
289 request->result = EIO;
292 ata_pio_read(request, request->transfersize);
295 /* update how far we've gotten */
296 request->donecount += request->transfersize;
298 /* do we need a scoop more ? */
299 if (request->bytecount > request->donecount) {
301 /* set this transfer size according to HW capabilities */
302 request->transfersize =
303 min((request->bytecount - request->donecount),
304 request->transfersize);
306 /* if data write command, output the data */
307 if (request->flags & ATA_R_WRITE) {
309 /* if we get an error here we are done with the HW */
310 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) {
311 device_printf(request->parent,
312 "timeout waiting for write DRQ\n");
313 request->status = ATA_IDX_INB(ch, ATA_STATUS);
317 /* output data and return waiting for new interrupt */
318 ata_pio_write(request, request->transfersize);
322 /* if data read command, return & wait for interrupt */
323 if (request->flags & ATA_R_READ)
330 /* ATA DMA data transfer commands */
333 /* stop DMA engine and get status */
335 request->dma->status = ch->dma.stop(request);
337 /* did we get error or data */
338 if (request->status & ATA_S_ERROR)
339 request->error = ATA_IDX_INB(ch, ATA_ERROR);
340 else if (request->dma->status & ATA_BMSTAT_ERROR)
341 request->status |= ATA_S_ERROR;
342 else if (!(request->flags & ATA_R_TIMEOUT))
343 request->donecount = request->bytecount;
345 /* Read back registers to the request struct. */
346 if ((request->status & ATA_S_ERROR) ||
347 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) {
348 ch->hw.tf_read(request);
351 /* release SG list etc */
352 ch->dma.unload(request);
357 /* ATAPI PIO commands */
359 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
361 /* on timeouts we have no data or anything so just return */
362 if (request->flags & ATA_R_TIMEOUT)
365 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
366 (request->status & ATA_S_DRQ)) {
369 /* this seems to be needed for some (slow) devices */
372 if (!(request->status & ATA_S_DRQ)) {
373 device_printf(request->parent, "command interrupt without DRQ\n");
374 request->status = ATA_S_ERROR;
377 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
378 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
379 /* return wait for interrupt */
383 if (request->flags & ATA_R_READ) {
384 request->status = ATA_S_ERROR;
385 device_printf(request->parent,
386 "%s trying to write on read buffer\n",
387 ata_cmd2str(request));
390 ata_pio_write(request, length);
391 request->donecount += length;
393 /* set next transfer size according to HW capabilities */
394 request->transfersize = min((request->bytecount-request->donecount),
395 request->transfersize);
396 /* return wait for interrupt */
400 if (request->flags & ATA_R_WRITE) {
401 request->status = ATA_S_ERROR;
402 device_printf(request->parent,
403 "%s trying to read on write buffer\n",
404 ata_cmd2str(request));
407 ata_pio_read(request, length);
408 request->donecount += length;
410 /* set next transfer size according to HW capabilities */
411 request->transfersize = min((request->bytecount-request->donecount),
412 request->transfersize);
413 /* return wait for interrupt */
416 case ATAPI_P_DONEDRQ:
417 device_printf(request->parent,
418 "WARNING - %s DONEDRQ non conformant device\n",
419 ata_cmd2str(request));
420 if (request->flags & ATA_R_READ) {
421 ata_pio_read(request, length);
422 request->donecount += length;
424 else if (request->flags & ATA_R_WRITE) {
425 ata_pio_write(request, length);
426 request->donecount += length;
429 request->status = ATA_S_ERROR;
434 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
435 request->error = ATA_IDX_INB(ch, ATA_ERROR);
439 device_printf(request->parent, "unknown transfer phase\n");
440 request->status = ATA_S_ERROR;
446 /* ATAPI DMA commands */
447 case ATA_R_ATAPI|ATA_R_DMA:
449 /* stop DMA engine and get status */
451 request->dma->status = ch->dma.stop(request);
453 /* did we get error or data */
454 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
455 request->error = ATA_IDX_INB(ch, ATA_ERROR);
456 else if (request->dma->status & ATA_BMSTAT_ERROR)
457 request->status |= ATA_S_ERROR;
458 else if (!(request->flags & ATA_R_TIMEOUT))
459 request->donecount = request->bytecount;
461 /* release SG list etc */
462 ch->dma.unload(request);
468 printf("ata_end_transaction OOPS!!\n");
471 callout_stop(&request->callout);
472 return ATA_OP_FINISHED;
475 return ATA_OP_CONTINUES;
478 /* must be called with ATA channel locked and state_mtx held */
480 ata_generic_reset(device_t dev)
482 struct ata_channel *ch = device_get_softc(dev);
484 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
485 u_int8_t err = 0, lsb = 0, msb = 0;
486 int mask = 0, timeout;
488 /* do we have any signs of ATA/ATAPI HW being present ? */
489 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
491 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
492 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
498 /* in some setups we dont want to test for a slave */
499 if (!(ch->flags & ATA_NO_SLAVE)) {
500 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
502 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
503 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) &&
511 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
512 mask, ostat0, ostat1);
514 /* if nothing showed up there is no need to get any further */
515 /* XXX SOS is that too strong?, we just might lose devices here */
520 /* reset (both) devices on this channel */
521 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
523 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
525 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
527 ATA_IDX_INB(ch, ATA_ERROR);
529 /* wait for BUSY to go inactive */
530 for (timeout = 0; timeout < 310; timeout++) {
531 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
532 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
534 if (ch->flags & ATA_STATUS_IS_LONG)
535 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
537 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
538 err = ATA_IDX_INB(ch, ATA_ERROR);
539 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
540 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
543 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
544 stat0, err, lsb, msb);
545 if (stat0 == err && lsb == err && msb == err &&
546 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
548 if (!(stat0 & ATA_S_BUSY)) {
549 if ((err & 0x7f) == ATA_E_ILI) {
550 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
551 ch->devices |= ATA_ATAPI_MASTER;
553 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) {
554 ch->devices |= ATA_ATA_MASTER;
557 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
563 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
564 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
565 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
567 if (ch->flags & ATA_STATUS_IS_LONG)
568 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff;
570 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
571 err = ATA_IDX_INB(ch, ATA_ERROR);
572 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
573 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
576 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
577 stat1, err, lsb, msb);
578 if (stat1 == err && lsb == err && msb == err &&
579 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
581 if (!(stat1 & ATA_S_BUSY)) {
582 if ((err & 0x7f) == ATA_E_ILI) {
583 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
584 ch->devices |= ATA_ATAPI_SLAVE;
586 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) {
587 ch->devices |= ATA_ATA_SLAVE;
590 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
596 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 &&
597 timeout > ((mask == 0x03) ? 20 : 10)) {
598 if ((mask & 0x01) && stat0 == 0xff)
600 if ((mask & 0x02) && stat1 == 0xff)
603 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) &&
604 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY)))
610 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
611 stat0, stat1, ch->devices);
614 /* must be called with ATA channel locked and state_mtx held */
616 ata_generic_status(device_t dev)
618 struct ata_channel *ch = device_get_softc(dev);
620 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
622 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
629 ata_wait(struct ata_channel *ch, int unit, u_int8_t mask)
636 /* wait at max 1 second for device to get !BUSY */
637 while (timeout < 1000000) {
638 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
640 /* if drive fails status, reselect the drive and try again */
641 if (status == 0xff) {
642 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit));
649 if (!(status & ATA_S_BUSY))
652 if (timeout > 1000) {
661 if (timeout >= 1000000)
664 return (status & ATA_S_ERROR);
668 /* wait 50 msec for bits wanted */
671 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
672 if ((status & mask) == mask)
673 return (status & ATA_S_ERROR);
680 ata_generic_command(struct ata_request *request)
682 struct ata_channel *ch = device_get_softc(request->parent);
685 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit));
687 /* ready to issue command ? */
688 if (ata_wait(ch, request->unit, 0) < 0) {
689 device_printf(request->parent, "timeout waiting to issue command\n");
690 request->flags |= ATA_R_TIMEOUT;
694 /* enable interrupt */
695 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
697 if (request->flags & ATA_R_ATAPI) {
701 /* issue packet command to controller */
702 if (request->flags & ATA_R_DMA) {
703 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
704 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
705 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
708 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
709 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
710 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
712 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
714 /* command interrupt device ? just return and wait for interrupt */
715 if (request->flags & ATA_R_ATAPI_INTR)
718 /* command processed ? */
719 res = ata_wait(ch, request->unit, 0);
722 device_printf(request->parent,
723 "timeout waiting for PACKET command\n");
724 request->flags |= ATA_R_TIMEOUT;
728 /* wait for ready to write ATAPI command block */
730 int reason = ATA_IDX_INB(ch, ATA_IREASON);
731 int status = ATA_IDX_INB(ch, ATA_STATUS);
733 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
734 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
739 device_printf(request->parent,
740 "timeout waiting for ATAPI ready\n");
741 request->flags |= ATA_R_TIMEOUT;
745 /* this seems to be needed for some (slow) devices */
748 /* output command block */
749 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
750 (request->flags & ATA_R_ATAPI16) ? 8 : 6);
753 ch->hw.tf_write(request);
755 /* issue command to controller */
756 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
762 ata_tf_read(struct ata_request *request)
764 struct ata_channel *ch = device_get_softc(request->parent);
766 if (request->flags & ATA_R_48BIT) {
767 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
768 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
770 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
771 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
772 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
774 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
775 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
776 request->u.ata.lba |=
777 (ATA_IDX_INB(ch, ATA_SECTOR) |
778 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
779 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
782 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
783 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
784 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
785 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
786 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
791 ata_tf_write(struct ata_request *request)
793 struct ata_channel *ch = device_get_softc(request->parent);
795 if (request->flags & ATA_R_48BIT) {
796 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
797 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
798 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
799 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
800 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
801 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
802 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
803 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
804 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
805 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
806 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
809 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
810 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
811 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
812 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
813 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
814 ATA_IDX_OUTB(ch, ATA_DRIVE,
815 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
816 ((request->u.ata.lba >> 24) & 0x0f));
821 ata_pio_read(struct ata_request *request, int length)
823 struct ata_channel *ch = device_get_softc(request->parent);
827 int todo, done, off, moff, resid, size, i;
828 uint8_t buf[2] __aligned(2);
830 todo = min(request->transfersize, length);
831 page = done = resid = 0;
832 while (done < todo) {
835 /* Prepare data address and limit size (if not sequential). */
836 off = request->donecount + done;
837 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 ||
838 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
839 addr = (uint8_t *)request->data + off;
840 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) {
841 bio = (struct bio *)request->data;
842 if ((bio->bio_flags & BIO_UNMAPPED) == 0) {
843 addr = (uint8_t *)bio->bio_data + off;
845 moff = bio->bio_ma_offset + off;
846 page = pmap_quick_enter_page(
847 bio->bio_ma[moff / PAGE_SIZE]);
849 size = min(size, PAGE_SIZE - moff);
850 addr = (void *)(page + moff);
853 panic("ata_pio_read: Unsupported CAM data type %x\n",
854 (request->ccb->ccb_h.flags & CAM_DATA_MASK));
856 /* We may have extra byte already read but not stored. */
864 /* Process main part of data. */
866 if (__predict_false((ch->flags & ATA_USE_16BIT) ||
867 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) {
868 #ifndef __NO_STRICT_ALIGNMENT
869 if (__predict_false((uintptr_t)addr % 2)) {
870 for (i = 0; i + 1 < size; i += 2) {
872 ATA_IDX_INW_STRM(ch, ATA_DATA);
874 addr[i + 1] = buf[1];
878 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr,
881 /* If we have extra byte of data, leave it for later. */
884 ATA_IDX_INW_STRM(ch, ATA_DATA);
885 addr[size - 1] = buf[0];
888 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / 4);
891 pmap_quick_remove_page(page);
898 device_printf(request->parent,
899 "WARNING - %s read data overrun %d > %d\n",
900 ata_cmd2str(request), length, done);
901 for (i = done + resid; i < length; i += 2)
902 ATA_IDX_INW(ch, ATA_DATA);
907 ata_pio_write(struct ata_request *request, int length)
909 struct ata_channel *ch = device_get_softc(request->parent);
913 int todo, done, off, moff, resid, size, i;
914 uint8_t buf[2] __aligned(2);
916 todo = min(request->transfersize, length);
917 page = done = resid = 0;
918 while (done < todo) {
921 /* Prepare data address and limit size (if not sequential). */
922 off = request->donecount + done;
923 if ((request->flags & ATA_R_DATA_IN_CCB) == 0 ||
924 (request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
925 addr = (uint8_t *)request->data + off;
926 } else if ((request->ccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) {
927 bio = (struct bio *)request->data;
928 if ((bio->bio_flags & BIO_UNMAPPED) == 0) {
929 addr = (uint8_t *)bio->bio_data + off;
931 moff = bio->bio_ma_offset + off;
932 page = pmap_quick_enter_page(
933 bio->bio_ma[moff / PAGE_SIZE]);
935 size = min(size, PAGE_SIZE - moff);
936 addr = (void *)(page + moff);
939 panic("ata_pio_write: Unsupported CAM data type %x\n",
940 (request->ccb->ccb_h.flags & CAM_DATA_MASK));
942 /* We may have extra byte to be written first. */
945 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
951 /* Process main part of data. */
953 if (__predict_false((ch->flags & ATA_USE_16BIT) ||
954 (size % 4) != 0 || ((uintptr_t)addr % 4) != 0)) {
955 #ifndef __NO_STRICT_ALIGNMENT
956 if (__predict_false((uintptr_t)addr % 2)) {
957 for (i = 0; i + 1 < size; i += 2) {
959 buf[1] = addr[i + 1];
960 ATA_IDX_OUTW_STRM(ch, ATA_DATA,
965 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr,
968 /* If we have extra byte of data, save it for later. */
970 buf[0] = addr[size - 1];
972 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
973 (void*)addr, size / sizeof(int32_t));
976 pmap_quick_remove_page(page);
982 /* We may have extra byte of data to be written. Pad it with zero. */
985 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf);
989 device_printf(request->parent,
990 "WARNING - %s write data underrun %d > %d\n",
991 ata_cmd2str(request), length, done);
992 for (i = done + resid; i < length; i += 2)
993 ATA_IDX_OUTW(ch, ATA_DATA, 0);