2 * Copyright (c) 1998 - 2005 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/endian.h>
39 #include <sys/ctype.h>
42 #include <sys/taskqueue.h>
44 #include <machine/bus.h>
46 #include <dev/ata/ata-all.h>
47 #include <dev/ata/ata-pci.h>
51 static int ata_begin_transaction(struct ata_request *);
52 static int ata_end_transaction(struct ata_request *);
53 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
54 static void ata_pio_read(struct ata_request *, int);
55 static void ata_pio_write(struct ata_request *, int);
58 * low level ATA functions
61 ata_generic_hw(device_t dev)
63 struct ata_channel *ch = device_get_softc(dev);
65 ch->hw.begin_transaction = ata_begin_transaction;
66 ch->hw.end_transaction = ata_end_transaction;
67 ch->hw.command = ata_generic_command;
70 /* must be called with ATA channel locked and state_mtx held */
72 ata_begin_transaction(struct ata_request *request)
74 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
75 struct ata_device *atadev = device_get_softc(request->dev);
78 ATA_DEBUG_RQ(request, "begin transaction");
80 /* disable ATAPI DMA writes if HW doesn't support it */
81 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
82 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
83 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
84 request->flags &= ~ATA_R_DMA;
86 /* check for 48 bit access and convert if needed */
87 ata_modify_if_48bit(request);
89 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
91 /* ATA PIO data transfer and control commands */
94 /* record command direction here as our request might be gone later */
95 int write = (request->flags & ATA_R_WRITE);
98 if (ch->hw.command(request)) {
99 device_printf(request->dev, "error issueing %s command\n",
100 ata_cmd2str(request));
101 request->result = EIO;
105 /* device reset doesn't interrupt */
106 if (request->u.ata.command == ATA_DEVICE_RESET) {
107 int timeout = 1000000;
110 request->status = ATA_IDX_INB(ch, ATA_STATUS);
111 } while (request->status & ATA_S_BUSY && timeout--);
112 if (request->status & ATA_S_ERROR)
113 request->error = ATA_IDX_INB(ch, ATA_ERROR);
117 /* if write command output the data */
119 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
120 device_printf(request->dev,"timeout waiting for write DRQ");
121 request->result = EIO;
124 ata_pio_write(request, request->transfersize);
129 /* ATA DMA data transfer commands */
131 /* check sanity, setup SG list and DMA engine */
132 if (ch->dma->load(ch->dev, request->data, request->bytecount,
133 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) {
134 device_printf(request->dev, "setting up DMA failed\n");
135 request->result = EIO;
140 if (ch->hw.command(request)) {
141 device_printf(request->dev, "error issueing %s command\n",
142 ata_cmd2str(request));
143 request->result = EIO;
147 /* start DMA engine */
148 if (ch->dma->start && ch->dma->start(request->dev)) {
149 device_printf(request->dev, "error starting DMA\n");
150 request->result = EIO;
155 /* ATAPI PIO commands */
157 /* is this just a POLL DSC command ? */
158 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
159 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
161 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
162 request->result = EBUSY;
166 /* start ATAPI operation */
167 if (ch->hw.command(request)) {
168 device_printf(request->dev, "error issuing ATA PACKET command\n");
169 request->result = EIO;
174 /* ATAPI DMA commands */
175 case ATA_R_ATAPI|ATA_R_DMA:
176 /* is this just a POLL DSC command ? */
177 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
178 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
180 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
181 request->result = EBUSY;
185 /* check sanity, setup SG list and DMA engine */
186 if (ch->dma->load(ch->dev, request->data, request->bytecount,
187 request->flags & ATA_R_READ, ch->dma->sg, &dummy)) {
188 device_printf(request->dev, "setting up DMA failed\n");
189 request->result = EIO;
193 /* start ATAPI operation */
194 if (ch->hw.command(request)) {
195 device_printf(request->dev, "error issuing ATA PACKET command\n");
196 request->result = EIO;
200 /* start DMA engine */
201 if (ch->dma->start && ch->dma->start(request->dev)) {
202 request->result = EIO;
208 printf("ata_begin_transaction OOPS!!!\n");
211 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
212 ch->dma->unload(ch->dev);
213 return ATA_OP_FINISHED;
216 callout_reset(&request->callout, request->timeout * hz,
217 (timeout_t*)ata_timeout, request);
218 return ATA_OP_CONTINUES;
221 /* must be called with ATA channel locked and state_mtx held */
223 ata_end_transaction(struct ata_request *request)
225 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
226 struct ata_device *atadev = device_get_softc(request->dev);
229 ATA_DEBUG_RQ(request, "end transaction");
231 /* clear interrupt and get status */
232 request->status = ATA_IDX_INB(ch, ATA_STATUS);
234 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
236 /* ATA PIO data transfer and control commands */
239 /* on timeouts we have no data or anything so just return */
240 if (request->flags & ATA_R_TIMEOUT)
243 /* on control commands read back registers to the request struct */
244 if (request->flags & ATA_R_CONTROL) {
245 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
246 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
247 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
249 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
250 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
251 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
253 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
254 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
255 request->u.ata.lba |=
256 (ATA_IDX_INB(ch, ATA_SECTOR) |
257 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
258 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
261 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
262 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
263 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
264 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
265 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
269 /* if we got an error we are done with the HW */
270 if (request->status & ATA_S_ERROR) {
271 request->error = ATA_IDX_INB(ch, ATA_ERROR);
275 /* are we moving data ? */
276 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
278 /* if read data get it */
279 if (request->flags & ATA_R_READ) {
280 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
281 device_printf(request->dev, "timeout waiting for read DRQ");
282 request->result = EIO;
285 ata_pio_read(request, request->transfersize);
288 /* update how far we've gotten */
289 request->donecount += request->transfersize;
291 /* do we need a scoop more ? */
292 if (request->bytecount > request->donecount) {
294 /* set this transfer size according to HW capabilities */
295 request->transfersize =
296 min((request->bytecount - request->donecount),
297 request->transfersize);
299 /* if data write command, output the data */
300 if (request->flags & ATA_R_WRITE) {
302 /* if we get an error here we are done with the HW */
303 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
304 device_printf(request->dev,
305 "timeout waiting for write DRQ");
306 request->status = ATA_IDX_INB(ch, ATA_STATUS);
310 /* output data and return waiting for new interrupt */
311 ata_pio_write(request, request->transfersize);
315 /* if data read command, return & wait for interrupt */
316 if (request->flags & ATA_R_READ)
323 /* ATA DMA data transfer commands */
326 /* stop DMA engine and get status */
328 request->dmastat = ch->dma->stop(request->dev);
330 /* did we get error or data */
331 if (request->status & ATA_S_ERROR)
332 request->error = ATA_IDX_INB(ch, ATA_ERROR);
333 else if (request->dmastat & ATA_BMSTAT_ERROR)
334 request->status |= ATA_S_ERROR;
335 else if (!(request->flags & ATA_R_TIMEOUT))
336 request->donecount = request->bytecount;
338 /* release SG list etc */
339 ch->dma->unload(ch->dev);
344 /* ATAPI PIO commands */
346 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
348 /* on timeouts we have no data or anything so just return */
349 if (request->flags & ATA_R_TIMEOUT)
352 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
353 (request->status & ATA_S_DRQ)) {
356 /* this seems to be needed for some (slow) devices */
359 if (!(request->status & ATA_S_DRQ)) {
360 device_printf(request->dev, "command interrupt without DRQ\n");
361 request->status = ATA_S_ERROR;
364 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
365 (atadev->param.config &
366 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
367 /* return wait for interrupt */
371 if (request->flags & ATA_R_READ) {
372 request->status = ATA_S_ERROR;
373 device_printf(request->dev,
374 "%s trying to write on read buffer\n",
375 ata_cmd2str(request));
379 ata_pio_write(request, length);
380 request->donecount += length;
382 /* set next transfer size according to HW capabilities */
383 request->transfersize = min((request->bytecount-request->donecount),
384 request->transfersize);
385 /* return wait for interrupt */
389 if (request->flags & ATA_R_WRITE) {
390 request->status = ATA_S_ERROR;
391 device_printf(request->dev,
392 "%s trying to read on write buffer\n",
393 ata_cmd2str(request));
396 ata_pio_read(request, length);
397 request->donecount += length;
399 /* set next transfer size according to HW capabilities */
400 request->transfersize = min((request->bytecount-request->donecount),
401 request->transfersize);
402 /* return wait for interrupt */
405 case ATAPI_P_DONEDRQ:
406 device_printf(request->dev,
407 "WARNING - %s DONEDRQ non conformant device\n",
408 ata_cmd2str(request));
409 if (request->flags & ATA_R_READ) {
410 ata_pio_read(request, length);
411 request->donecount += length;
413 else if (request->flags & ATA_R_WRITE) {
414 ata_pio_write(request, length);
415 request->donecount += length;
418 request->status = ATA_S_ERROR;
423 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
424 request->error = ATA_IDX_INB(ch, ATA_ERROR);
428 device_printf(request->dev, "unknown transfer phase\n");
429 request->status = ATA_S_ERROR;
435 /* ATAPI DMA commands */
436 case ATA_R_ATAPI|ATA_R_DMA:
438 /* stop DMA engine and get status */
440 request->dmastat = ch->dma->stop(request->dev);
442 /* did we get error or data */
443 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
444 request->error = ATA_IDX_INB(ch, ATA_ERROR);
445 else if (request->dmastat & ATA_BMSTAT_ERROR)
446 request->status |= ATA_S_ERROR;
447 else if (!(request->flags & ATA_R_TIMEOUT))
448 request->donecount = request->bytecount;
450 /* release SG list etc */
451 ch->dma->unload(ch->dev);
457 printf("ata_end_transaction OOPS!!\n");
460 callout_stop(&request->callout);
461 return ATA_OP_FINISHED;
464 return ATA_OP_CONTINUES;
467 /* must be called with ATA channel locked */
469 ata_generic_reset(device_t dev)
471 struct ata_channel *ch = device_get_softc(dev);
473 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
474 u_int8_t err = 0, lsb = 0, msb = 0;
475 int mask = 0, timeout;
477 /* do we have any signs of ATA/ATAPI HW being present ? */
478 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
480 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
481 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
486 /* in some setups we dont want to test for a slave */
487 if (!(ch->flags & ATA_NO_SLAVE)) {
488 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
490 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
491 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
498 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
499 mask, ostat0, ostat1);
501 /* if nothing showed up there is no need to get any further */
502 /* XXX SOS is that too strong?, we just might loose devices here */
507 /* reset (both) devices on this channel */
508 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
510 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
512 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
514 ATA_IDX_INB(ch, ATA_ERROR);
516 /* wait for BUSY to go inactive */
517 for (timeout = 0; timeout < 310; timeout++) {
518 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
519 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
521 err = ATA_IDX_INB(ch, ATA_ERROR);
522 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
523 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
524 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
527 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
528 stat0, err, lsb, msb);
529 if (stat0 == err && lsb == err && msb == err &&
530 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
532 if (!(stat0 & ATA_S_BUSY)) {
533 if ((err & 0x7f) == ATA_E_ILI) {
534 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
535 ch->devices |= ATA_ATAPI_MASTER;
537 else if (stat0 & ATA_S_READY) {
538 ch->devices |= ATA_ATA_MASTER;
541 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
547 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
548 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
549 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
551 err = ATA_IDX_INB(ch, ATA_ERROR);
552 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
553 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
554 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
557 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
558 stat1, err, lsb, msb);
559 if (stat1 == err && lsb == err && msb == err &&
560 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
562 if (!(stat1 & ATA_S_BUSY)) {
563 if ((err & 0x7f) == ATA_E_ILI) {
564 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
565 ch->devices |= ATA_ATAPI_SLAVE;
567 else if (stat1 & ATA_S_READY) {
568 ch->devices |= ATA_ATA_SLAVE;
571 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
577 if (mask == 0x00) /* nothing to wait for */
579 if (mask == 0x01) /* wait for master only */
580 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
582 if (mask == 0x02) /* wait for slave only */
583 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
585 if (mask == 0x03) { /* wait for both master & slave */
586 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
588 if ((stat0 == 0xff) && (timeout > 20))
590 if ((stat1 == 0xff) && (timeout > 20))
597 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
598 stat0, stat1, ch->devices,
599 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
603 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
610 /* wait at max 1 second for device to get !BUSY */
611 while (timeout < 1000000) {
612 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
614 /* if drive fails status, reselect the drive and try again */
615 if (status == 0xff) {
616 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
623 if (!(status & ATA_S_BUSY))
626 if (timeout > 1000) {
635 if (timeout >= 1000000)
638 return (status & ATA_S_ERROR);
642 /* wait 50 msec for bits wanted */
645 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
646 if ((status & mask) == mask)
647 return (status & ATA_S_ERROR);
654 ata_generic_command(struct ata_request *request)
656 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
657 struct ata_device *atadev = device_get_softc(request->dev);
660 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
662 /* ready to issue command ? */
663 if (ata_wait(ch, atadev, 0) < 0) {
664 device_printf(request->dev, "timeout waiting to issue command\n");
668 /* enable interrupt */
669 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
671 if (request->flags & ATA_R_ATAPI) {
674 /* issue packet command to controller */
675 if (request->flags & ATA_R_DMA) {
676 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
677 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
678 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
681 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
682 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
683 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
685 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
687 /* command interrupt device ? just return and wait for interrupt */
688 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
691 /* wait for ready to write ATAPI command block */
693 int reason = ATA_IDX_INB(ch, ATA_IREASON);
694 int status = ATA_IDX_INB(ch, ATA_STATUS);
696 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
697 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
702 device_printf(request->dev,"timeout waiting for ATAPI ready\n");
703 request->result = EIO;
707 /* this seems to be needed for some (slow) devices */
710 /* output command block */
711 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
712 (atadev->param.config & ATA_PROTO_MASK) ==
713 ATA_PROTO_ATAPI_12 ? 6 : 8);
716 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
717 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
718 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
719 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
720 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
721 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
722 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
723 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
724 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
725 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
726 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
727 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
730 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
731 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
732 if (atadev->flags & ATA_D_USE_CHS) {
735 if (atadev->param.atavalid & ATA_FLAG_54_58) {
736 heads = atadev->param.current_heads;
737 sectors = atadev->param.current_sectors;
740 heads = atadev->param.heads;
741 sectors = atadev->param.sectors;
743 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
744 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
745 (request->u.ata.lba / (sectors * heads)));
746 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
747 (request->u.ata.lba / (sectors * heads)) >> 8);
748 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
749 (((request->u.ata.lba% (sectors * heads)) /
753 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
754 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
755 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
756 ATA_IDX_OUTB(ch, ATA_DRIVE,
757 ATA_D_IBM | ATA_D_LBA | atadev->unit |
758 ((request->u.ata.lba >> 24) & 0x0f));
762 /* issue command to controller */
763 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
770 ata_pio_read(struct ata_request *request, int length)
772 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
773 int size = min(request->transfersize, length);
776 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
777 ATA_IDX_INSW_STRM(ch, ATA_DATA,
778 (void*)((uintptr_t)request->data+request->donecount),
779 size / sizeof(int16_t));
781 ATA_IDX_INSL_STRM(ch, ATA_DATA,
782 (void*)((uintptr_t)request->data+request->donecount),
783 size / sizeof(int32_t));
785 if (request->transfersize < length) {
786 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
787 ata_cmd2str(request), length, request->transfersize);
788 for (resid = request->transfersize; resid < length;
789 resid += sizeof(int16_t))
790 ATA_IDX_INW(ch, ATA_DATA);
795 ata_pio_write(struct ata_request *request, int length)
797 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
798 int size = min(request->transfersize, length);
801 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
802 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
803 (void*)((uintptr_t)request->data+request->donecount),
804 size / sizeof(int16_t));
806 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
807 (void*)((uintptr_t)request->data+request->donecount),
808 size / sizeof(int32_t));
810 if (request->transfersize < length) {
811 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
812 ata_cmd2str(request), length, request->transfersize);
813 for (resid = request->transfersize; resid < length;
814 resid += sizeof(int16_t))
815 ATA_IDX_OUTW(ch, ATA_DATA, 0);