2 * Copyright (c) 1998 - 2007 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/endian.h>
37 #include <sys/ctype.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
49 static int ata_generic_status(device_t dev);
50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
51 static void ata_pio_read(struct ata_request *, int);
52 static void ata_pio_write(struct ata_request *, int);
55 * low level ATA functions
58 ata_generic_hw(device_t dev)
60 struct ata_channel *ch = device_get_softc(dev);
62 ch->hw.begin_transaction = ata_begin_transaction;
63 ch->hw.end_transaction = ata_end_transaction;
64 ch->hw.status = ata_generic_status;
65 ch->hw.command = ata_generic_command;
68 /* must be called with ATA channel locked and state_mtx held */
70 ata_begin_transaction(struct ata_request *request)
72 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
73 struct ata_device *atadev = device_get_softc(request->dev);
76 ATA_DEBUG_RQ(request, "begin transaction");
78 /* disable ATAPI DMA writes if HW doesn't support it */
79 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
80 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
81 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
82 request->flags &= ~ATA_R_DMA;
84 /* check for 48 bit access and convert if needed */
85 ata_modify_if_48bit(request);
87 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
89 /* ATA PIO data transfer and control commands */
92 /* record command direction here as our request might be gone later */
93 int write = (request->flags & ATA_R_WRITE);
96 if (ch->hw.command(request)) {
97 device_printf(request->dev, "error issuing %s command\n",
98 ata_cmd2str(request));
99 request->result = EIO;
103 /* device reset doesn't interrupt */
104 if (request->u.ata.command == ATA_DEVICE_RESET) {
106 int timeout = 1000000;
109 request->status = ATA_IDX_INB(ch, ATA_STATUS);
110 } while (request->status & ATA_S_BUSY && timeout--);
111 if (request->status & ATA_S_ERROR)
112 request->error = ATA_IDX_INB(ch, ATA_ERROR);
116 /* if write command output the data */
118 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
119 device_printf(request->dev,
120 "timeout waiting for write DRQ\n");
121 request->result = EIO;
124 ata_pio_write(request, request->transfersize);
129 /* ATA DMA data transfer commands */
131 /* check sanity, setup SG list and DMA engine */
132 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
133 request->flags & ATA_R_READ, ch->dma->sg,
135 device_printf(request->dev, "setting up DMA failed\n");
136 request->result = error;
141 if (ch->hw.command(request)) {
142 device_printf(request->dev, "error issuing %s command\n",
143 ata_cmd2str(request));
144 request->result = EIO;
148 /* start DMA engine */
149 if (ch->dma->start && ch->dma->start(request->dev)) {
150 device_printf(request->dev, "error starting DMA\n");
151 request->result = EIO;
156 /* ATAPI PIO commands */
158 /* is this just a POLL DSC command ? */
159 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
160 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
162 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
163 request->result = EBUSY;
167 /* start ATAPI operation */
168 if (ch->hw.command(request)) {
169 device_printf(request->dev, "error issuing ATA PACKET command\n");
170 request->result = EIO;
175 /* ATAPI DMA commands */
176 case ATA_R_ATAPI|ATA_R_DMA:
177 /* is this just a POLL DSC command ? */
178 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
179 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
181 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
182 request->result = EBUSY;
186 /* check sanity, setup SG list and DMA engine */
187 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
188 request->flags & ATA_R_READ, ch->dma->sg,
190 device_printf(request->dev, "setting up DMA failed\n");
191 request->result = error;
195 /* start ATAPI operation */
196 if (ch->hw.command(request)) {
197 device_printf(request->dev, "error issuing ATA PACKET command\n");
198 request->result = EIO;
202 /* start DMA engine */
203 if (ch->dma->start && ch->dma->start(request->dev)) {
204 request->result = EIO;
210 printf("ata_begin_transaction OOPS!!!\n");
213 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
214 ch->dma->unload(ch->dev);
215 return ATA_OP_FINISHED;
218 callout_reset(&request->callout, request->timeout * hz,
219 (timeout_t*)ata_timeout, request);
220 return ATA_OP_CONTINUES;
223 /* must be called with ATA channel locked and state_mtx held */
225 ata_end_transaction(struct ata_request *request)
227 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
228 struct ata_device *atadev = device_get_softc(request->dev);
231 ATA_DEBUG_RQ(request, "end transaction");
233 /* clear interrupt and get status */
234 request->status = ATA_IDX_INB(ch, ATA_STATUS);
236 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
238 /* ATA PIO data transfer and control commands */
241 /* on timeouts we have no data or anything so just return */
242 if (request->flags & ATA_R_TIMEOUT)
245 /* on control commands read back registers to the request struct */
246 if (request->flags & ATA_R_CONTROL) {
247 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
248 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
249 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
251 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
252 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
253 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
255 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
256 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
257 request->u.ata.lba |=
258 (ATA_IDX_INB(ch, ATA_SECTOR) |
259 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
260 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
263 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
264 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
265 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
266 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
267 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
271 /* if we got an error we are done with the HW */
272 if (request->status & ATA_S_ERROR) {
273 request->error = ATA_IDX_INB(ch, ATA_ERROR);
277 /* are we moving data ? */
278 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
280 /* if read data get it */
281 if (request->flags & ATA_R_READ) {
282 int flags = ATA_S_DRQ;
284 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
285 flags |= ATA_S_READY;
286 if (ata_wait(ch, atadev, flags) < 0) {
287 device_printf(request->dev,
288 "timeout waiting for read DRQ\n");
289 request->result = EIO;
292 ata_pio_read(request, request->transfersize);
295 /* update how far we've gotten */
296 request->donecount += request->transfersize;
298 /* do we need a scoop more ? */
299 if (request->bytecount > request->donecount) {
301 /* set this transfer size according to HW capabilities */
302 request->transfersize =
303 min((request->bytecount - request->donecount),
304 request->transfersize);
306 /* if data write command, output the data */
307 if (request->flags & ATA_R_WRITE) {
309 /* if we get an error here we are done with the HW */
310 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
311 device_printf(request->dev,
312 "timeout waiting for write DRQ\n");
313 request->status = ATA_IDX_INB(ch, ATA_STATUS);
317 /* output data and return waiting for new interrupt */
318 ata_pio_write(request, request->transfersize);
322 /* if data read command, return & wait for interrupt */
323 if (request->flags & ATA_R_READ)
330 /* ATA DMA data transfer commands */
333 /* stop DMA engine and get status */
335 request->dmastat = ch->dma->stop(request->dev);
337 /* did we get error or data */
338 if (request->status & ATA_S_ERROR)
339 request->error = ATA_IDX_INB(ch, ATA_ERROR);
340 else if (request->dmastat & ATA_BMSTAT_ERROR)
341 request->status |= ATA_S_ERROR;
342 else if (!(request->flags & ATA_R_TIMEOUT))
343 request->donecount = request->bytecount;
345 /* release SG list etc */
346 ch->dma->unload(ch->dev);
351 /* ATAPI PIO commands */
353 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
355 /* on timeouts we have no data or anything so just return */
356 if (request->flags & ATA_R_TIMEOUT)
359 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
360 (request->status & ATA_S_DRQ)) {
363 /* this seems to be needed for some (slow) devices */
366 if (!(request->status & ATA_S_DRQ)) {
367 device_printf(request->dev, "command interrupt without DRQ\n");
368 request->status = ATA_S_ERROR;
371 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
372 (atadev->param.config &
373 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
374 /* return wait for interrupt */
378 if (request->flags & ATA_R_READ) {
379 request->status = ATA_S_ERROR;
380 device_printf(request->dev,
381 "%s trying to write on read buffer\n",
382 ata_cmd2str(request));
386 ata_pio_write(request, length);
387 request->donecount += length;
389 /* set next transfer size according to HW capabilities */
390 request->transfersize = min((request->bytecount-request->donecount),
391 request->transfersize);
392 /* return wait for interrupt */
396 if (request->flags & ATA_R_WRITE) {
397 request->status = ATA_S_ERROR;
398 device_printf(request->dev,
399 "%s trying to read on write buffer\n",
400 ata_cmd2str(request));
403 ata_pio_read(request, length);
404 request->donecount += length;
406 /* set next transfer size according to HW capabilities */
407 request->transfersize = min((request->bytecount-request->donecount),
408 request->transfersize);
409 /* return wait for interrupt */
412 case ATAPI_P_DONEDRQ:
413 device_printf(request->dev,
414 "WARNING - %s DONEDRQ non conformant device\n",
415 ata_cmd2str(request));
416 if (request->flags & ATA_R_READ) {
417 ata_pio_read(request, length);
418 request->donecount += length;
420 else if (request->flags & ATA_R_WRITE) {
421 ata_pio_write(request, length);
422 request->donecount += length;
425 request->status = ATA_S_ERROR;
430 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
431 request->error = ATA_IDX_INB(ch, ATA_ERROR);
435 device_printf(request->dev, "unknown transfer phase\n");
436 request->status = ATA_S_ERROR;
442 /* ATAPI DMA commands */
443 case ATA_R_ATAPI|ATA_R_DMA:
445 /* stop DMA engine and get status */
447 request->dmastat = ch->dma->stop(request->dev);
449 /* did we get error or data */
450 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
451 request->error = ATA_IDX_INB(ch, ATA_ERROR);
452 else if (request->dmastat & ATA_BMSTAT_ERROR)
453 request->status |= ATA_S_ERROR;
454 else if (!(request->flags & ATA_R_TIMEOUT))
455 request->donecount = request->bytecount;
457 /* release SG list etc */
458 ch->dma->unload(ch->dev);
464 printf("ata_end_transaction OOPS!!\n");
467 callout_stop(&request->callout);
468 return ATA_OP_FINISHED;
471 return ATA_OP_CONTINUES;
474 /* must be called with ATA channel locked and state_mtx held */
476 ata_generic_reset(device_t dev)
478 struct ata_channel *ch = device_get_softc(dev);
480 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
481 u_int8_t err = 0, lsb = 0, msb = 0;
482 int mask = 0, timeout;
484 /* do we have any signs of ATA/ATAPI HW being present ? */
485 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
487 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
488 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
493 /* in some setups we dont want to test for a slave */
494 if (!(ch->flags & ATA_NO_SLAVE)) {
495 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
497 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
498 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
505 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
506 mask, ostat0, ostat1);
508 /* if nothing showed up there is no need to get any further */
509 /* XXX SOS is that too strong?, we just might loose devices here */
514 /* reset (both) devices on this channel */
515 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
517 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
519 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
521 ATA_IDX_INB(ch, ATA_ERROR);
523 /* wait for BUSY to go inactive */
524 for (timeout = 0; timeout < 310; timeout++) {
525 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
526 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
528 err = ATA_IDX_INB(ch, ATA_ERROR);
529 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
530 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
531 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
534 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
535 stat0, err, lsb, msb);
536 if (stat0 == err && lsb == err && msb == err &&
537 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
539 if (!(stat0 & ATA_S_BUSY)) {
540 if ((err & 0x7f) == ATA_E_ILI) {
541 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
542 ch->devices |= ATA_ATAPI_MASTER;
544 else if (stat0 & ATA_S_READY) {
545 ch->devices |= ATA_ATA_MASTER;
548 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
554 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
555 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
556 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
558 err = ATA_IDX_INB(ch, ATA_ERROR);
559 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
560 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
561 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
564 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
565 stat1, err, lsb, msb);
566 if (stat1 == err && lsb == err && msb == err &&
567 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
569 if (!(stat1 & ATA_S_BUSY)) {
570 if ((err & 0x7f) == ATA_E_ILI) {
571 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
572 ch->devices |= ATA_ATAPI_SLAVE;
574 else if (stat1 & ATA_S_READY) {
575 ch->devices |= ATA_ATA_SLAVE;
578 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
584 if (mask == 0x00) /* nothing to wait for */
586 if (mask == 0x01) /* wait for master only */
587 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
589 if (mask == 0x02) /* wait for slave only */
590 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
592 if (mask == 0x03) { /* wait for both master & slave */
593 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
595 if ((stat0 == 0xff) && (timeout > 20))
597 if ((stat1 == 0xff) && (timeout > 20))
604 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
605 stat0, stat1, ch->devices,
606 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
609 /* must be called with ATA channel locked and state_mtx held */
611 ata_generic_status(device_t dev)
613 struct ata_channel *ch = device_get_softc(dev);
615 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
617 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
624 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
631 /* wait at max 1 second for device to get !BUSY */
632 while (timeout < 1000000) {
633 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
635 /* if drive fails status, reselect the drive and try again */
636 if (status == 0xff) {
637 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
644 if (!(status & ATA_S_BUSY))
647 if (timeout > 1000) {
656 if (timeout >= 1000000)
659 return (status & ATA_S_ERROR);
663 /* wait 50 msec for bits wanted */
666 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
667 if ((status & mask) == mask)
668 return (status & ATA_S_ERROR);
675 ata_generic_command(struct ata_request *request)
677 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
678 struct ata_device *atadev = device_get_softc(request->dev);
681 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
683 /* ready to issue command ? */
684 if (ata_wait(ch, atadev, 0) < 0) {
685 device_printf(request->dev, "timeout waiting to issue command\n");
689 /* enable interrupt */
690 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
692 if (request->flags & ATA_R_ATAPI) {
695 /* issue packet command to controller */
696 if (request->flags & ATA_R_DMA) {
697 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
698 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
699 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
702 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
703 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
704 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
706 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
708 /* command interrupt device ? just return and wait for interrupt */
709 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
712 /* wait for ready to write ATAPI command block */
714 int reason = ATA_IDX_INB(ch, ATA_IREASON);
715 int status = ATA_IDX_INB(ch, ATA_STATUS);
717 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
718 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
723 device_printf(request->dev, "timeout waiting for ATAPI ready\n");
724 request->result = EIO;
728 /* this seems to be needed for some (slow) devices */
731 /* output command block */
732 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
733 (atadev->param.config & ATA_PROTO_MASK) ==
734 ATA_PROTO_ATAPI_12 ? 6 : 8);
737 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
738 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
739 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
740 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
741 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
742 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
743 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
744 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
745 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
746 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
747 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
748 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
751 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
752 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
753 if (atadev->flags & ATA_D_USE_CHS) {
756 if (atadev->param.atavalid & ATA_FLAG_54_58) {
757 heads = atadev->param.current_heads;
758 sectors = atadev->param.current_sectors;
761 heads = atadev->param.heads;
762 sectors = atadev->param.sectors;
764 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
765 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
766 (request->u.ata.lba / (sectors * heads)));
767 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
768 (request->u.ata.lba / (sectors * heads)) >> 8);
769 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
770 (((request->u.ata.lba% (sectors * heads)) /
774 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
775 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
776 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
777 ATA_IDX_OUTB(ch, ATA_DRIVE,
778 ATA_D_IBM | ATA_D_LBA | atadev->unit |
779 ((request->u.ata.lba >> 24) & 0x0f));
783 /* issue command to controller */
784 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
791 ata_pio_read(struct ata_request *request, int length)
793 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
794 int size = min(request->transfersize, length);
797 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
798 ATA_IDX_INSW_STRM(ch, ATA_DATA,
799 (void*)((uintptr_t)request->data+request->donecount),
800 size / sizeof(int16_t));
802 ATA_IDX_INSL_STRM(ch, ATA_DATA,
803 (void*)((uintptr_t)request->data+request->donecount),
804 size / sizeof(int32_t));
806 if (request->transfersize < length) {
807 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
808 ata_cmd2str(request), length, request->transfersize);
809 for (resid = request->transfersize; resid < length;
810 resid += sizeof(int16_t))
811 ATA_IDX_INW(ch, ATA_DATA);
816 ata_pio_write(struct ata_request *request, int length)
818 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
819 int size = min(request->transfersize, length);
822 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
823 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
824 (void*)((uintptr_t)request->data+request->donecount),
825 size / sizeof(int16_t));
827 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
828 (void*)((uintptr_t)request->data+request->donecount),
829 size / sizeof(int32_t));
831 if (request->transfersize < length) {
832 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
833 ata_cmd2str(request), length, request->transfersize);
834 for (resid = request->transfersize; resid < length;
835 resid += sizeof(int16_t))
836 ATA_IDX_OUTW(ch, ATA_DATA, 0);